Commit | Line | Data |
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3de42dc0 XZ |
1 | /* |
2 | * irq_comm.c: Common API for in kernel interrupt controller | |
3 | * Copyright (c) 2007, Intel Corporation. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., 59 Temple | |
16 | * Place - Suite 330, Boston, MA 02111-1307 USA. | |
17 | * Authors: | |
18 | * Yaozu (Eddie) Dong <Eddie.dong@intel.com> | |
19 | * | |
9611c187 | 20 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
3de42dc0 XZ |
21 | */ |
22 | ||
23 | #include <linux/kvm_host.h> | |
5a0e3ad6 | 24 | #include <linux/slab.h> |
c7c9c56c | 25 | #include <linux/export.h> |
b2d09103 IM |
26 | #include <linux/rculist.h> |
27 | ||
229456fc | 28 | #include <trace/events/kvm.h> |
79950e10 | 29 | |
79950e10 | 30 | #include <asm/msidef.h> |
79950e10 | 31 | |
3de42dc0 XZ |
32 | #include "irq.h" |
33 | ||
34 | #include "ioapic.h" | |
35 | ||
d1ebdbf9 JS |
36 | #include "lapic.h" |
37 | ||
5c919412 | 38 | #include "hyperv.h" |
52004014 | 39 | #include "x86.h" |
5c919412 | 40 | |
4925663a | 41 | static int kvm_set_pic_irq(struct kvm_kernel_irq_routing_entry *e, |
aa2fbe6d YZ |
42 | struct kvm *kvm, int irq_source_id, int level, |
43 | bool line_status) | |
399ec807 | 44 | { |
90bca052 | 45 | struct kvm_pic *pic = kvm->arch.vpic; |
1a577b72 | 46 | return kvm_pic_set_irq(pic, e->irqchip.pin, irq_source_id, level); |
399ec807 AK |
47 | } |
48 | ||
4925663a | 49 | static int kvm_set_ioapic_irq(struct kvm_kernel_irq_routing_entry *e, |
aa2fbe6d YZ |
50 | struct kvm *kvm, int irq_source_id, int level, |
51 | bool line_status) | |
399ec807 | 52 | { |
1a6e4a8c | 53 | struct kvm_ioapic *ioapic = kvm->arch.vioapic; |
aa2fbe6d YZ |
54 | return kvm_ioapic_set_irq(ioapic, e->irqchip.pin, irq_source_id, level, |
55 | line_status); | |
399ec807 AK |
56 | } |
57 | ||
58c2dde1 | 58 | int kvm_irq_delivery_to_apic(struct kvm *kvm, struct kvm_lapic *src, |
9e4aabe2 | 59 | struct kvm_lapic_irq *irq, struct dest_map *dest_map) |
58c2dde1 GN |
60 | { |
61 | int i, r = -1; | |
62 | struct kvm_vcpu *vcpu, *lowest = NULL; | |
52004014 FW |
63 | unsigned long dest_vcpu_bitmap[BITS_TO_LONGS(KVM_MAX_VCPUS)]; |
64 | unsigned int dest_vcpus = 0; | |
58c2dde1 GN |
65 | |
66 | if (irq->dest_mode == 0 && irq->dest_id == 0xff && | |
d1ebdbf9 | 67 | kvm_lowest_prio_delivery(irq)) { |
343f94fe | 68 | printk(KERN_INFO "kvm: apic: phys broadcast and lowest prio\n"); |
1e08ec4a GN |
69 | irq->delivery_mode = APIC_DM_FIXED; |
70 | } | |
71 | ||
b4f2225c | 72 | if (kvm_irq_delivery_to_apic_fast(kvm, src, irq, &r, dest_map)) |
1e08ec4a | 73 | return r; |
343f94fe | 74 | |
52004014 FW |
75 | memset(dest_vcpu_bitmap, 0, sizeof(dest_vcpu_bitmap)); |
76 | ||
988a2cae GN |
77 | kvm_for_each_vcpu(i, vcpu, kvm) { |
78 | if (!kvm_apic_present(vcpu)) | |
343f94fe GN |
79 | continue; |
80 | ||
58c2dde1 GN |
81 | if (!kvm_apic_match_dest(vcpu, src, irq->shorthand, |
82 | irq->dest_id, irq->dest_mode)) | |
343f94fe GN |
83 | continue; |
84 | ||
d1ebdbf9 | 85 | if (!kvm_lowest_prio_delivery(irq)) { |
58c2dde1 GN |
86 | if (r < 0) |
87 | r = 0; | |
b4f2225c | 88 | r += kvm_apic_set_irq(vcpu, irq, dest_map); |
aefd18f0 | 89 | } else if (kvm_lapic_enabled(vcpu)) { |
52004014 FW |
90 | if (!kvm_vector_hashing_enabled()) { |
91 | if (!lowest) | |
92 | lowest = vcpu; | |
93 | else if (kvm_apic_compare_prio(vcpu, lowest) < 0) | |
94 | lowest = vcpu; | |
95 | } else { | |
96 | __set_bit(i, dest_vcpu_bitmap); | |
97 | dest_vcpus++; | |
98 | } | |
e1035715 | 99 | } |
343f94fe GN |
100 | } |
101 | ||
52004014 FW |
102 | if (dest_vcpus != 0) { |
103 | int idx = kvm_vector_to_index(irq->vector, dest_vcpus, | |
104 | dest_vcpu_bitmap, KVM_MAX_VCPUS); | |
105 | ||
106 | lowest = kvm_get_vcpu(kvm, idx); | |
107 | } | |
108 | ||
58c2dde1 | 109 | if (lowest) |
b4f2225c | 110 | r = kvm_apic_set_irq(lowest, irq, dest_map); |
58c2dde1 GN |
111 | |
112 | return r; | |
116191b6 SY |
113 | } |
114 | ||
37131313 | 115 | void kvm_set_msi_irq(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e, |
d84f1e07 | 116 | struct kvm_lapic_irq *irq) |
01f21880 | 117 | { |
37131313 RK |
118 | trace_kvm_msi_set_irq(e->msi.address_lo | (kvm->arch.x2apic_format ? |
119 | (u64)e->msi.address_hi << 32 : 0), | |
120 | e->msi.data); | |
01f21880 MT |
121 | |
122 | irq->dest_id = (e->msi.address_lo & | |
123 | MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT; | |
37131313 RK |
124 | if (kvm->arch.x2apic_format) |
125 | irq->dest_id |= MSI_ADDR_EXT_DEST_ID(e->msi.address_hi); | |
01f21880 MT |
126 | irq->vector = (e->msi.data & |
127 | MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT; | |
128 | irq->dest_mode = (1 << MSI_ADDR_DEST_MODE_SHIFT) & e->msi.address_lo; | |
129 | irq->trig_mode = (1 << MSI_DATA_TRIGGER_SHIFT) & e->msi.data; | |
130 | irq->delivery_mode = e->msi.data & 0x700; | |
93bbf0b8 JS |
131 | irq->msi_redir_hint = ((e->msi.address_lo |
132 | & MSI_ADDR_REDIRECTION_LOWPRI) > 0); | |
01f21880 MT |
133 | irq->level = 1; |
134 | irq->shorthand = 0; | |
01f21880 | 135 | } |
d84f1e07 | 136 | EXPORT_SYMBOL_GPL(kvm_set_msi_irq); |
01f21880 | 137 | |
37131313 RK |
138 | static inline bool kvm_msi_route_invalid(struct kvm *kvm, |
139 | struct kvm_kernel_irq_routing_entry *e) | |
140 | { | |
141 | return kvm->arch.x2apic_format && (e->msi.address_hi & 0xff); | |
142 | } | |
143 | ||
bd2b53b2 | 144 | int kvm_set_msi(struct kvm_kernel_irq_routing_entry *e, |
aa2fbe6d | 145 | struct kvm *kvm, int irq_source_id, int level, bool line_status) |
79950e10 | 146 | { |
58c2dde1 | 147 | struct kvm_lapic_irq irq; |
79950e10 | 148 | |
37131313 RK |
149 | if (kvm_msi_route_invalid(kvm, e)) |
150 | return -EINVAL; | |
151 | ||
1a6e4a8c GN |
152 | if (!level) |
153 | return -1; | |
154 | ||
37131313 | 155 | kvm_set_msi_irq(kvm, e, &irq); |
116191b6 | 156 | |
b4f2225c | 157 | return kvm_irq_delivery_to_apic(kvm, NULL, &irq, NULL); |
79950e10 SY |
158 | } |
159 | ||
01f21880 | 160 | |
a2b07739 PB |
161 | static int kvm_hv_set_sint(struct kvm_kernel_irq_routing_entry *e, |
162 | struct kvm *kvm, int irq_source_id, int level, | |
163 | bool line_status) | |
164 | { | |
165 | if (!level) | |
166 | return -1; | |
167 | ||
168 | return kvm_hv_synic_set_irq(kvm, e->hv_sint.vcpu, e->hv_sint.sint); | |
169 | } | |
170 | ||
b97e6de9 PB |
171 | int kvm_arch_set_irq_inatomic(struct kvm_kernel_irq_routing_entry *e, |
172 | struct kvm *kvm, int irq_source_id, int level, | |
173 | bool line_status) | |
01f21880 MT |
174 | { |
175 | struct kvm_lapic_irq irq; | |
176 | int r; | |
177 | ||
a2b07739 PB |
178 | switch (e->type) { |
179 | case KVM_IRQ_ROUTING_HV_SINT: | |
180 | return kvm_hv_set_sint(e, kvm, irq_source_id, level, | |
181 | line_status); | |
b97e6de9 | 182 | |
a2b07739 PB |
183 | case KVM_IRQ_ROUTING_MSI: |
184 | if (kvm_msi_route_invalid(kvm, e)) | |
185 | return -EINVAL; | |
37131313 | 186 | |
a2b07739 | 187 | kvm_set_msi_irq(kvm, e, &irq); |
01f21880 | 188 | |
a2b07739 PB |
189 | if (kvm_irq_delivery_to_apic_fast(kvm, NULL, &irq, &r, NULL)) |
190 | return r; | |
191 | break; | |
192 | ||
193 | default: | |
194 | break; | |
195 | } | |
196 | ||
197 | return -EWOULDBLOCK; | |
01f21880 MT |
198 | } |
199 | ||
5550af4d SY |
200 | int kvm_request_irq_source_id(struct kvm *kvm) |
201 | { | |
202 | unsigned long *bitmap = &kvm->arch.irq_sources_bitmap; | |
fa40a821 MT |
203 | int irq_source_id; |
204 | ||
205 | mutex_lock(&kvm->irq_lock); | |
cd5a2685 | 206 | irq_source_id = find_first_zero_bit(bitmap, BITS_PER_LONG); |
61552367 | 207 | |
cd5a2685 | 208 | if (irq_source_id >= BITS_PER_LONG) { |
5550af4d | 209 | printk(KERN_WARNING "kvm: exhaust allocatable IRQ sources!\n"); |
0c6ddceb JS |
210 | irq_source_id = -EFAULT; |
211 | goto unlock; | |
61552367 MM |
212 | } |
213 | ||
214 | ASSERT(irq_source_id != KVM_USERSPACE_IRQ_SOURCE_ID); | |
7a84428a | 215 | ASSERT(irq_source_id != KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID); |
61552367 | 216 | set_bit(irq_source_id, bitmap); |
0c6ddceb | 217 | unlock: |
fa40a821 | 218 | mutex_unlock(&kvm->irq_lock); |
61552367 | 219 | |
5550af4d SY |
220 | return irq_source_id; |
221 | } | |
222 | ||
223 | void kvm_free_irq_source_id(struct kvm *kvm, int irq_source_id) | |
224 | { | |
61552367 | 225 | ASSERT(irq_source_id != KVM_USERSPACE_IRQ_SOURCE_ID); |
7a84428a | 226 | ASSERT(irq_source_id != KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID); |
61552367 | 227 | |
fa40a821 | 228 | mutex_lock(&kvm->irq_lock); |
61552367 | 229 | if (irq_source_id < 0 || |
cd5a2685 | 230 | irq_source_id >= BITS_PER_LONG) { |
5550af4d | 231 | printk(KERN_ERR "kvm: IRQ source ID out of range!\n"); |
0c6ddceb | 232 | goto unlock; |
5550af4d | 233 | } |
e50212bb | 234 | clear_bit(irq_source_id, &kvm->arch.irq_sources_bitmap); |
900ab14c | 235 | if (!irqchip_kernel(kvm)) |
e50212bb MT |
236 | goto unlock; |
237 | ||
1a577b72 | 238 | kvm_ioapic_clear_all(kvm->arch.vioapic, irq_source_id); |
90bca052 | 239 | kvm_pic_clear_all(kvm->arch.vpic, irq_source_id); |
0c6ddceb | 240 | unlock: |
fa40a821 | 241 | mutex_unlock(&kvm->irq_lock); |
5550af4d | 242 | } |
75858a84 AK |
243 | |
244 | void kvm_register_irq_mask_notifier(struct kvm *kvm, int irq, | |
245 | struct kvm_irq_mask_notifier *kimn) | |
246 | { | |
fa40a821 | 247 | mutex_lock(&kvm->irq_lock); |
75858a84 | 248 | kimn->irq = irq; |
6ef768fa | 249 | hlist_add_head_rcu(&kimn->link, &kvm->arch.mask_notifier_list); |
fa40a821 | 250 | mutex_unlock(&kvm->irq_lock); |
75858a84 AK |
251 | } |
252 | ||
253 | void kvm_unregister_irq_mask_notifier(struct kvm *kvm, int irq, | |
254 | struct kvm_irq_mask_notifier *kimn) | |
255 | { | |
fa40a821 | 256 | mutex_lock(&kvm->irq_lock); |
280aa177 | 257 | hlist_del_rcu(&kimn->link); |
fa40a821 | 258 | mutex_unlock(&kvm->irq_lock); |
719d93cd | 259 | synchronize_srcu(&kvm->irq_srcu); |
75858a84 AK |
260 | } |
261 | ||
4a994358 GN |
262 | void kvm_fire_mask_notifiers(struct kvm *kvm, unsigned irqchip, unsigned pin, |
263 | bool mask) | |
75858a84 AK |
264 | { |
265 | struct kvm_irq_mask_notifier *kimn; | |
719d93cd | 266 | int idx, gsi; |
75858a84 | 267 | |
719d93cd | 268 | idx = srcu_read_lock(&kvm->irq_srcu); |
9957c86d | 269 | gsi = kvm_irq_map_chip_pin(kvm, irqchip, pin); |
4a994358 | 270 | if (gsi != -1) |
6ef768fa | 271 | hlist_for_each_entry_rcu(kimn, &kvm->arch.mask_notifier_list, link) |
4a994358 GN |
272 | if (kimn->irq == gsi) |
273 | kimn->func(kimn, mask); | |
719d93cd | 274 | srcu_read_unlock(&kvm->irq_srcu, idx); |
75858a84 AK |
275 | } |
276 | ||
5c0aea0e DH |
277 | bool kvm_arch_can_set_irq_routing(struct kvm *kvm) |
278 | { | |
279 | return irqchip_in_kernel(kvm); | |
280 | } | |
281 | ||
c63cf538 RK |
282 | int kvm_set_routing_entry(struct kvm *kvm, |
283 | struct kvm_kernel_irq_routing_entry *e, | |
e8cde093 | 284 | const struct kvm_irq_routing_entry *ue) |
399ec807 | 285 | { |
5c0aea0e DH |
286 | /* We can't check irqchip_in_kernel() here as some callers are |
287 | * currently inititalizing the irqchip. Other callers should therefore | |
288 | * check kvm_arch_can_set_irq_routing() before calling this function. | |
289 | */ | |
399ec807 AK |
290 | switch (ue->type) { |
291 | case KVM_IRQ_ROUTING_IRQCHIP: | |
8bf463f3 | 292 | if (irqchip_split(kvm)) |
43ae312c | 293 | return -EINVAL; |
445ee82d | 294 | e->irqchip.pin = ue->u.irqchip.pin; |
399ec807 | 295 | switch (ue->u.irqchip.irqchip) { |
399ec807 | 296 | case KVM_IRQCHIP_PIC_SLAVE: |
445ee82d | 297 | e->irqchip.pin += PIC_NUM_PINS / 2; |
e5dc4877 RK |
298 | /* fall through */ |
299 | case KVM_IRQCHIP_PIC_MASTER: | |
445ee82d | 300 | if (ue->u.irqchip.pin >= PIC_NUM_PINS / 2) |
43ae312c | 301 | return -EINVAL; |
4925663a | 302 | e->set = kvm_set_pic_irq; |
399ec807 AK |
303 | break; |
304 | case KVM_IRQCHIP_IOAPIC: | |
445ee82d | 305 | if (ue->u.irqchip.pin >= KVM_IOAPIC_NUM_PINS) |
43ae312c | 306 | return -EINVAL; |
efbc100c | 307 | e->set = kvm_set_ioapic_irq; |
399ec807 AK |
308 | break; |
309 | default: | |
43ae312c | 310 | return -EINVAL; |
399ec807 AK |
311 | } |
312 | e->irqchip.irqchip = ue->u.irqchip.irqchip; | |
399ec807 | 313 | break; |
79950e10 SY |
314 | case KVM_IRQ_ROUTING_MSI: |
315 | e->set = kvm_set_msi; | |
316 | e->msi.address_lo = ue->u.msi.address_lo; | |
317 | e->msi.address_hi = ue->u.msi.address_hi; | |
318 | e->msi.data = ue->u.msi.data; | |
37131313 RK |
319 | |
320 | if (kvm_msi_route_invalid(kvm, e)) | |
43ae312c | 321 | return -EINVAL; |
79950e10 | 322 | break; |
5c919412 AS |
323 | case KVM_IRQ_ROUTING_HV_SINT: |
324 | e->set = kvm_hv_set_sint; | |
325 | e->hv_sint.vcpu = ue->u.hv_sint.vcpu; | |
326 | e->hv_sint.sint = ue->u.hv_sint.sint; | |
327 | break; | |
399ec807 | 328 | default: |
43ae312c | 329 | return -EINVAL; |
399ec807 | 330 | } |
46e624b9 | 331 | |
43ae312c | 332 | return 0; |
399ec807 AK |
333 | } |
334 | ||
8feb4a04 FW |
335 | bool kvm_intr_is_single_vcpu(struct kvm *kvm, struct kvm_lapic_irq *irq, |
336 | struct kvm_vcpu **dest_vcpu) | |
337 | { | |
338 | int i, r = 0; | |
339 | struct kvm_vcpu *vcpu; | |
340 | ||
341 | if (kvm_intr_is_single_vcpu_fast(kvm, irq, dest_vcpu)) | |
342 | return true; | |
343 | ||
344 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
345 | if (!kvm_apic_present(vcpu)) | |
346 | continue; | |
347 | ||
348 | if (!kvm_apic_match_dest(vcpu, NULL, irq->shorthand, | |
349 | irq->dest_id, irq->dest_mode)) | |
350 | continue; | |
351 | ||
352 | if (++r == 2) | |
353 | return false; | |
354 | ||
355 | *dest_vcpu = vcpu; | |
356 | } | |
357 | ||
358 | return r == 1; | |
359 | } | |
360 | EXPORT_SYMBOL_GPL(kvm_intr_is_single_vcpu); | |
361 | ||
399ec807 AK |
362 | #define IOAPIC_ROUTING_ENTRY(irq) \ |
363 | { .gsi = irq, .type = KVM_IRQ_ROUTING_IRQCHIP, \ | |
25f97ff4 | 364 | .u.irqchip = { .irqchip = KVM_IRQCHIP_IOAPIC, .pin = (irq) } } |
399ec807 AK |
365 | #define ROUTING_ENTRY1(irq) IOAPIC_ROUTING_ENTRY(irq) |
366 | ||
3bf58e9a | 367 | #define PIC_ROUTING_ENTRY(irq) \ |
399ec807 | 368 | { .gsi = irq, .type = KVM_IRQ_ROUTING_IRQCHIP, \ |
25f97ff4 | 369 | .u.irqchip = { .irqchip = SELECT_PIC(irq), .pin = (irq) % 8 } } |
3bf58e9a | 370 | #define ROUTING_ENTRY2(irq) \ |
399ec807 | 371 | IOAPIC_ROUTING_ENTRY(irq), PIC_ROUTING_ENTRY(irq) |
399ec807 AK |
372 | |
373 | static const struct kvm_irq_routing_entry default_routing[] = { | |
374 | ROUTING_ENTRY2(0), ROUTING_ENTRY2(1), | |
375 | ROUTING_ENTRY2(2), ROUTING_ENTRY2(3), | |
376 | ROUTING_ENTRY2(4), ROUTING_ENTRY2(5), | |
377 | ROUTING_ENTRY2(6), ROUTING_ENTRY2(7), | |
378 | ROUTING_ENTRY2(8), ROUTING_ENTRY2(9), | |
379 | ROUTING_ENTRY2(10), ROUTING_ENTRY2(11), | |
380 | ROUTING_ENTRY2(12), ROUTING_ENTRY2(13), | |
381 | ROUTING_ENTRY2(14), ROUTING_ENTRY2(15), | |
382 | ROUTING_ENTRY1(16), ROUTING_ENTRY1(17), | |
383 | ROUTING_ENTRY1(18), ROUTING_ENTRY1(19), | |
384 | ROUTING_ENTRY1(20), ROUTING_ENTRY1(21), | |
385 | ROUTING_ENTRY1(22), ROUTING_ENTRY1(23), | |
399ec807 AK |
386 | }; |
387 | ||
388 | int kvm_setup_default_irq_routing(struct kvm *kvm) | |
389 | { | |
390 | return kvm_set_irq_routing(kvm, default_routing, | |
391 | ARRAY_SIZE(default_routing), 0); | |
392 | } | |
49df6397 SR |
393 | |
394 | static const struct kvm_irq_routing_entry empty_routing[] = {}; | |
395 | ||
396 | int kvm_setup_empty_irq_routing(struct kvm *kvm) | |
397 | { | |
398 | return kvm_set_irq_routing(kvm, empty_routing, 0, 0); | |
399 | } | |
b053b2ae | 400 | |
abdb080f | 401 | void kvm_arch_post_irq_routing_update(struct kvm *kvm) |
b053b2ae | 402 | { |
826da321 | 403 | if (!irqchip_split(kvm)) |
b053b2ae SR |
404 | return; |
405 | kvm_make_scan_ioapic_request(kvm); | |
406 | } | |
407 | ||
6308630b AS |
408 | void kvm_scan_ioapic_routes(struct kvm_vcpu *vcpu, |
409 | ulong *ioapic_handled_vectors) | |
b053b2ae SR |
410 | { |
411 | struct kvm *kvm = vcpu->kvm; | |
412 | struct kvm_kernel_irq_routing_entry *entry; | |
413 | struct kvm_irq_routing_table *table; | |
414 | u32 i, nr_ioapic_pins; | |
415 | int idx; | |
416 | ||
b053b2ae SR |
417 | idx = srcu_read_lock(&kvm->irq_srcu); |
418 | table = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu); | |
419 | nr_ioapic_pins = min_t(u32, table->nr_rt_entries, | |
420 | kvm->arch.nr_reserved_ioapic_pins); | |
421 | for (i = 0; i < nr_ioapic_pins; ++i) { | |
422 | hlist_for_each_entry(entry, &table->map[i], link) { | |
3159d36a | 423 | struct kvm_lapic_irq irq; |
b053b2ae SR |
424 | |
425 | if (entry->type != KVM_IRQ_ROUTING_MSI) | |
426 | continue; | |
3159d36a | 427 | |
37131313 | 428 | kvm_set_msi_irq(vcpu->kvm, entry, &irq); |
3159d36a RK |
429 | |
430 | if (irq.level && kvm_apic_match_dest(vcpu, NULL, 0, | |
431 | irq.dest_id, irq.dest_mode)) | |
432 | __set_bit(irq.vector, ioapic_handled_vectors); | |
b053b2ae SR |
433 | } |
434 | } | |
435 | srcu_read_unlock(&kvm->irq_srcu, idx); | |
436 | } | |
5c919412 | 437 | |
5c919412 AS |
438 | void kvm_arch_irq_routing_update(struct kvm *kvm) |
439 | { | |
440 | kvm_hv_irq_routing_update(kvm); | |
441 | } |