Commit | Line | Data |
---|---|---|
3de42dc0 XZ |
1 | /* |
2 | * irq_comm.c: Common API for in kernel interrupt controller | |
3 | * Copyright (c) 2007, Intel Corporation. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., 59 Temple | |
16 | * Place - Suite 330, Boston, MA 02111-1307 USA. | |
17 | * Authors: | |
18 | * Yaozu (Eddie) Dong <Eddie.dong@intel.com> | |
19 | * | |
9611c187 | 20 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
3de42dc0 XZ |
21 | */ |
22 | ||
23 | #include <linux/kvm_host.h> | |
5a0e3ad6 | 24 | #include <linux/slab.h> |
c7c9c56c | 25 | #include <linux/export.h> |
229456fc | 26 | #include <trace/events/kvm.h> |
79950e10 | 27 | |
79950e10 | 28 | #include <asm/msidef.h> |
79950e10 | 29 | |
3de42dc0 XZ |
30 | #include "irq.h" |
31 | ||
32 | #include "ioapic.h" | |
33 | ||
d1ebdbf9 JS |
34 | #include "lapic.h" |
35 | ||
5c919412 | 36 | #include "hyperv.h" |
52004014 | 37 | #include "x86.h" |
5c919412 | 38 | |
4925663a | 39 | static int kvm_set_pic_irq(struct kvm_kernel_irq_routing_entry *e, |
aa2fbe6d YZ |
40 | struct kvm *kvm, int irq_source_id, int level, |
41 | bool line_status) | |
399ec807 | 42 | { |
1a6e4a8c | 43 | struct kvm_pic *pic = pic_irqchip(kvm); |
1a577b72 | 44 | return kvm_pic_set_irq(pic, e->irqchip.pin, irq_source_id, level); |
399ec807 AK |
45 | } |
46 | ||
4925663a | 47 | static int kvm_set_ioapic_irq(struct kvm_kernel_irq_routing_entry *e, |
aa2fbe6d YZ |
48 | struct kvm *kvm, int irq_source_id, int level, |
49 | bool line_status) | |
399ec807 | 50 | { |
1a6e4a8c | 51 | struct kvm_ioapic *ioapic = kvm->arch.vioapic; |
aa2fbe6d YZ |
52 | return kvm_ioapic_set_irq(ioapic, e->irqchip.pin, irq_source_id, level, |
53 | line_status); | |
399ec807 AK |
54 | } |
55 | ||
58c2dde1 | 56 | int kvm_irq_delivery_to_apic(struct kvm *kvm, struct kvm_lapic *src, |
9e4aabe2 | 57 | struct kvm_lapic_irq *irq, struct dest_map *dest_map) |
58c2dde1 GN |
58 | { |
59 | int i, r = -1; | |
60 | struct kvm_vcpu *vcpu, *lowest = NULL; | |
52004014 FW |
61 | unsigned long dest_vcpu_bitmap[BITS_TO_LONGS(KVM_MAX_VCPUS)]; |
62 | unsigned int dest_vcpus = 0; | |
58c2dde1 GN |
63 | |
64 | if (irq->dest_mode == 0 && irq->dest_id == 0xff && | |
d1ebdbf9 | 65 | kvm_lowest_prio_delivery(irq)) { |
343f94fe | 66 | printk(KERN_INFO "kvm: apic: phys broadcast and lowest prio\n"); |
1e08ec4a GN |
67 | irq->delivery_mode = APIC_DM_FIXED; |
68 | } | |
69 | ||
b4f2225c | 70 | if (kvm_irq_delivery_to_apic_fast(kvm, src, irq, &r, dest_map)) |
1e08ec4a | 71 | return r; |
343f94fe | 72 | |
52004014 FW |
73 | memset(dest_vcpu_bitmap, 0, sizeof(dest_vcpu_bitmap)); |
74 | ||
988a2cae GN |
75 | kvm_for_each_vcpu(i, vcpu, kvm) { |
76 | if (!kvm_apic_present(vcpu)) | |
343f94fe GN |
77 | continue; |
78 | ||
58c2dde1 GN |
79 | if (!kvm_apic_match_dest(vcpu, src, irq->shorthand, |
80 | irq->dest_id, irq->dest_mode)) | |
343f94fe GN |
81 | continue; |
82 | ||
d1ebdbf9 | 83 | if (!kvm_lowest_prio_delivery(irq)) { |
58c2dde1 GN |
84 | if (r < 0) |
85 | r = 0; | |
b4f2225c | 86 | r += kvm_apic_set_irq(vcpu, irq, dest_map); |
aefd18f0 | 87 | } else if (kvm_lapic_enabled(vcpu)) { |
52004014 FW |
88 | if (!kvm_vector_hashing_enabled()) { |
89 | if (!lowest) | |
90 | lowest = vcpu; | |
91 | else if (kvm_apic_compare_prio(vcpu, lowest) < 0) | |
92 | lowest = vcpu; | |
93 | } else { | |
94 | __set_bit(i, dest_vcpu_bitmap); | |
95 | dest_vcpus++; | |
96 | } | |
e1035715 | 97 | } |
343f94fe GN |
98 | } |
99 | ||
52004014 FW |
100 | if (dest_vcpus != 0) { |
101 | int idx = kvm_vector_to_index(irq->vector, dest_vcpus, | |
102 | dest_vcpu_bitmap, KVM_MAX_VCPUS); | |
103 | ||
104 | lowest = kvm_get_vcpu(kvm, idx); | |
105 | } | |
106 | ||
58c2dde1 | 107 | if (lowest) |
b4f2225c | 108 | r = kvm_apic_set_irq(lowest, irq, dest_map); |
58c2dde1 GN |
109 | |
110 | return r; | |
116191b6 SY |
111 | } |
112 | ||
37131313 | 113 | void kvm_set_msi_irq(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e, |
d84f1e07 | 114 | struct kvm_lapic_irq *irq) |
01f21880 | 115 | { |
37131313 RK |
116 | trace_kvm_msi_set_irq(e->msi.address_lo | (kvm->arch.x2apic_format ? |
117 | (u64)e->msi.address_hi << 32 : 0), | |
118 | e->msi.data); | |
01f21880 MT |
119 | |
120 | irq->dest_id = (e->msi.address_lo & | |
121 | MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT; | |
37131313 RK |
122 | if (kvm->arch.x2apic_format) |
123 | irq->dest_id |= MSI_ADDR_EXT_DEST_ID(e->msi.address_hi); | |
01f21880 MT |
124 | irq->vector = (e->msi.data & |
125 | MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT; | |
126 | irq->dest_mode = (1 << MSI_ADDR_DEST_MODE_SHIFT) & e->msi.address_lo; | |
127 | irq->trig_mode = (1 << MSI_DATA_TRIGGER_SHIFT) & e->msi.data; | |
128 | irq->delivery_mode = e->msi.data & 0x700; | |
93bbf0b8 JS |
129 | irq->msi_redir_hint = ((e->msi.address_lo |
130 | & MSI_ADDR_REDIRECTION_LOWPRI) > 0); | |
01f21880 MT |
131 | irq->level = 1; |
132 | irq->shorthand = 0; | |
01f21880 | 133 | } |
d84f1e07 | 134 | EXPORT_SYMBOL_GPL(kvm_set_msi_irq); |
01f21880 | 135 | |
37131313 RK |
136 | static inline bool kvm_msi_route_invalid(struct kvm *kvm, |
137 | struct kvm_kernel_irq_routing_entry *e) | |
138 | { | |
139 | return kvm->arch.x2apic_format && (e->msi.address_hi & 0xff); | |
140 | } | |
141 | ||
bd2b53b2 | 142 | int kvm_set_msi(struct kvm_kernel_irq_routing_entry *e, |
aa2fbe6d | 143 | struct kvm *kvm, int irq_source_id, int level, bool line_status) |
79950e10 | 144 | { |
58c2dde1 | 145 | struct kvm_lapic_irq irq; |
79950e10 | 146 | |
37131313 RK |
147 | if (kvm_msi_route_invalid(kvm, e)) |
148 | return -EINVAL; | |
149 | ||
1a6e4a8c GN |
150 | if (!level) |
151 | return -1; | |
152 | ||
37131313 | 153 | kvm_set_msi_irq(kvm, e, &irq); |
116191b6 | 154 | |
b4f2225c | 155 | return kvm_irq_delivery_to_apic(kvm, NULL, &irq, NULL); |
79950e10 SY |
156 | } |
157 | ||
01f21880 | 158 | |
b97e6de9 PB |
159 | int kvm_arch_set_irq_inatomic(struct kvm_kernel_irq_routing_entry *e, |
160 | struct kvm *kvm, int irq_source_id, int level, | |
161 | bool line_status) | |
01f21880 MT |
162 | { |
163 | struct kvm_lapic_irq irq; | |
164 | int r; | |
165 | ||
b97e6de9 PB |
166 | if (unlikely(e->type != KVM_IRQ_ROUTING_MSI)) |
167 | return -EWOULDBLOCK; | |
168 | ||
37131313 RK |
169 | if (kvm_msi_route_invalid(kvm, e)) |
170 | return -EINVAL; | |
171 | ||
172 | kvm_set_msi_irq(kvm, e, &irq); | |
01f21880 | 173 | |
b4f2225c | 174 | if (kvm_irq_delivery_to_apic_fast(kvm, NULL, &irq, &r, NULL)) |
01f21880 MT |
175 | return r; |
176 | else | |
177 | return -EWOULDBLOCK; | |
178 | } | |
179 | ||
5550af4d SY |
180 | int kvm_request_irq_source_id(struct kvm *kvm) |
181 | { | |
182 | unsigned long *bitmap = &kvm->arch.irq_sources_bitmap; | |
fa40a821 MT |
183 | int irq_source_id; |
184 | ||
185 | mutex_lock(&kvm->irq_lock); | |
cd5a2685 | 186 | irq_source_id = find_first_zero_bit(bitmap, BITS_PER_LONG); |
61552367 | 187 | |
cd5a2685 | 188 | if (irq_source_id >= BITS_PER_LONG) { |
5550af4d | 189 | printk(KERN_WARNING "kvm: exhaust allocatable IRQ sources!\n"); |
0c6ddceb JS |
190 | irq_source_id = -EFAULT; |
191 | goto unlock; | |
61552367 MM |
192 | } |
193 | ||
194 | ASSERT(irq_source_id != KVM_USERSPACE_IRQ_SOURCE_ID); | |
7a84428a | 195 | ASSERT(irq_source_id != KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID); |
61552367 | 196 | set_bit(irq_source_id, bitmap); |
0c6ddceb | 197 | unlock: |
fa40a821 | 198 | mutex_unlock(&kvm->irq_lock); |
61552367 | 199 | |
5550af4d SY |
200 | return irq_source_id; |
201 | } | |
202 | ||
203 | void kvm_free_irq_source_id(struct kvm *kvm, int irq_source_id) | |
204 | { | |
61552367 | 205 | ASSERT(irq_source_id != KVM_USERSPACE_IRQ_SOURCE_ID); |
7a84428a | 206 | ASSERT(irq_source_id != KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID); |
61552367 | 207 | |
fa40a821 | 208 | mutex_lock(&kvm->irq_lock); |
61552367 | 209 | if (irq_source_id < 0 || |
cd5a2685 | 210 | irq_source_id >= BITS_PER_LONG) { |
5550af4d | 211 | printk(KERN_ERR "kvm: IRQ source ID out of range!\n"); |
0c6ddceb | 212 | goto unlock; |
5550af4d | 213 | } |
e50212bb | 214 | clear_bit(irq_source_id, &kvm->arch.irq_sources_bitmap); |
49df6397 | 215 | if (!ioapic_in_kernel(kvm)) |
e50212bb MT |
216 | goto unlock; |
217 | ||
1a577b72 | 218 | kvm_ioapic_clear_all(kvm->arch.vioapic, irq_source_id); |
1a577b72 | 219 | kvm_pic_clear_all(pic_irqchip(kvm), irq_source_id); |
0c6ddceb | 220 | unlock: |
fa40a821 | 221 | mutex_unlock(&kvm->irq_lock); |
5550af4d | 222 | } |
75858a84 AK |
223 | |
224 | void kvm_register_irq_mask_notifier(struct kvm *kvm, int irq, | |
225 | struct kvm_irq_mask_notifier *kimn) | |
226 | { | |
fa40a821 | 227 | mutex_lock(&kvm->irq_lock); |
75858a84 | 228 | kimn->irq = irq; |
6ef768fa | 229 | hlist_add_head_rcu(&kimn->link, &kvm->arch.mask_notifier_list); |
fa40a821 | 230 | mutex_unlock(&kvm->irq_lock); |
75858a84 AK |
231 | } |
232 | ||
233 | void kvm_unregister_irq_mask_notifier(struct kvm *kvm, int irq, | |
234 | struct kvm_irq_mask_notifier *kimn) | |
235 | { | |
fa40a821 | 236 | mutex_lock(&kvm->irq_lock); |
280aa177 | 237 | hlist_del_rcu(&kimn->link); |
fa40a821 | 238 | mutex_unlock(&kvm->irq_lock); |
719d93cd | 239 | synchronize_srcu(&kvm->irq_srcu); |
75858a84 AK |
240 | } |
241 | ||
4a994358 GN |
242 | void kvm_fire_mask_notifiers(struct kvm *kvm, unsigned irqchip, unsigned pin, |
243 | bool mask) | |
75858a84 AK |
244 | { |
245 | struct kvm_irq_mask_notifier *kimn; | |
719d93cd | 246 | int idx, gsi; |
75858a84 | 247 | |
719d93cd | 248 | idx = srcu_read_lock(&kvm->irq_srcu); |
9957c86d | 249 | gsi = kvm_irq_map_chip_pin(kvm, irqchip, pin); |
4a994358 | 250 | if (gsi != -1) |
6ef768fa | 251 | hlist_for_each_entry_rcu(kimn, &kvm->arch.mask_notifier_list, link) |
4a994358 GN |
252 | if (kimn->irq == gsi) |
253 | kimn->func(kimn, mask); | |
719d93cd | 254 | srcu_read_unlock(&kvm->irq_srcu, idx); |
75858a84 AK |
255 | } |
256 | ||
5c919412 AS |
257 | static int kvm_hv_set_sint(struct kvm_kernel_irq_routing_entry *e, |
258 | struct kvm *kvm, int irq_source_id, int level, | |
259 | bool line_status) | |
260 | { | |
261 | if (!level) | |
262 | return -1; | |
263 | ||
264 | return kvm_hv_synic_set_irq(kvm, e->hv_sint.vcpu, e->hv_sint.sint); | |
265 | } | |
266 | ||
c63cf538 RK |
267 | int kvm_set_routing_entry(struct kvm *kvm, |
268 | struct kvm_kernel_irq_routing_entry *e, | |
e8cde093 | 269 | const struct kvm_irq_routing_entry *ue) |
399ec807 AK |
270 | { |
271 | int r = -EINVAL; | |
272 | int delta; | |
d72118ce | 273 | unsigned max_pin; |
46e624b9 | 274 | |
399ec807 AK |
275 | switch (ue->type) { |
276 | case KVM_IRQ_ROUTING_IRQCHIP: | |
277 | delta = 0; | |
278 | switch (ue->u.irqchip.irqchip) { | |
279 | case KVM_IRQCHIP_PIC_MASTER: | |
280 | e->set = kvm_set_pic_irq; | |
93b6547e | 281 | max_pin = PIC_NUM_PINS; |
399ec807 AK |
282 | break; |
283 | case KVM_IRQCHIP_PIC_SLAVE: | |
4925663a | 284 | e->set = kvm_set_pic_irq; |
93b6547e | 285 | max_pin = PIC_NUM_PINS; |
399ec807 AK |
286 | delta = 8; |
287 | break; | |
288 | case KVM_IRQCHIP_IOAPIC: | |
d72118ce | 289 | max_pin = KVM_IOAPIC_NUM_PINS; |
efbc100c | 290 | e->set = kvm_set_ioapic_irq; |
399ec807 AK |
291 | break; |
292 | default: | |
293 | goto out; | |
294 | } | |
295 | e->irqchip.irqchip = ue->u.irqchip.irqchip; | |
296 | e->irqchip.pin = ue->u.irqchip.pin + delta; | |
d72118ce | 297 | if (e->irqchip.pin >= max_pin) |
3e71f88b | 298 | goto out; |
399ec807 | 299 | break; |
79950e10 SY |
300 | case KVM_IRQ_ROUTING_MSI: |
301 | e->set = kvm_set_msi; | |
302 | e->msi.address_lo = ue->u.msi.address_lo; | |
303 | e->msi.address_hi = ue->u.msi.address_hi; | |
304 | e->msi.data = ue->u.msi.data; | |
37131313 RK |
305 | |
306 | if (kvm_msi_route_invalid(kvm, e)) | |
307 | goto out; | |
79950e10 | 308 | break; |
5c919412 AS |
309 | case KVM_IRQ_ROUTING_HV_SINT: |
310 | e->set = kvm_hv_set_sint; | |
311 | e->hv_sint.vcpu = ue->u.hv_sint.vcpu; | |
312 | e->hv_sint.sint = ue->u.hv_sint.sint; | |
313 | break; | |
399ec807 AK |
314 | default: |
315 | goto out; | |
316 | } | |
46e624b9 | 317 | |
399ec807 AK |
318 | r = 0; |
319 | out: | |
320 | return r; | |
321 | } | |
322 | ||
8feb4a04 FW |
323 | bool kvm_intr_is_single_vcpu(struct kvm *kvm, struct kvm_lapic_irq *irq, |
324 | struct kvm_vcpu **dest_vcpu) | |
325 | { | |
326 | int i, r = 0; | |
327 | struct kvm_vcpu *vcpu; | |
328 | ||
329 | if (kvm_intr_is_single_vcpu_fast(kvm, irq, dest_vcpu)) | |
330 | return true; | |
331 | ||
332 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
333 | if (!kvm_apic_present(vcpu)) | |
334 | continue; | |
335 | ||
336 | if (!kvm_apic_match_dest(vcpu, NULL, irq->shorthand, | |
337 | irq->dest_id, irq->dest_mode)) | |
338 | continue; | |
339 | ||
340 | if (++r == 2) | |
341 | return false; | |
342 | ||
343 | *dest_vcpu = vcpu; | |
344 | } | |
345 | ||
346 | return r == 1; | |
347 | } | |
348 | EXPORT_SYMBOL_GPL(kvm_intr_is_single_vcpu); | |
349 | ||
399ec807 AK |
350 | #define IOAPIC_ROUTING_ENTRY(irq) \ |
351 | { .gsi = irq, .type = KVM_IRQ_ROUTING_IRQCHIP, \ | |
25f97ff4 | 352 | .u.irqchip = { .irqchip = KVM_IRQCHIP_IOAPIC, .pin = (irq) } } |
399ec807 AK |
353 | #define ROUTING_ENTRY1(irq) IOAPIC_ROUTING_ENTRY(irq) |
354 | ||
3bf58e9a | 355 | #define PIC_ROUTING_ENTRY(irq) \ |
399ec807 | 356 | { .gsi = irq, .type = KVM_IRQ_ROUTING_IRQCHIP, \ |
25f97ff4 | 357 | .u.irqchip = { .irqchip = SELECT_PIC(irq), .pin = (irq) % 8 } } |
3bf58e9a | 358 | #define ROUTING_ENTRY2(irq) \ |
399ec807 | 359 | IOAPIC_ROUTING_ENTRY(irq), PIC_ROUTING_ENTRY(irq) |
399ec807 AK |
360 | |
361 | static const struct kvm_irq_routing_entry default_routing[] = { | |
362 | ROUTING_ENTRY2(0), ROUTING_ENTRY2(1), | |
363 | ROUTING_ENTRY2(2), ROUTING_ENTRY2(3), | |
364 | ROUTING_ENTRY2(4), ROUTING_ENTRY2(5), | |
365 | ROUTING_ENTRY2(6), ROUTING_ENTRY2(7), | |
366 | ROUTING_ENTRY2(8), ROUTING_ENTRY2(9), | |
367 | ROUTING_ENTRY2(10), ROUTING_ENTRY2(11), | |
368 | ROUTING_ENTRY2(12), ROUTING_ENTRY2(13), | |
369 | ROUTING_ENTRY2(14), ROUTING_ENTRY2(15), | |
370 | ROUTING_ENTRY1(16), ROUTING_ENTRY1(17), | |
371 | ROUTING_ENTRY1(18), ROUTING_ENTRY1(19), | |
372 | ROUTING_ENTRY1(20), ROUTING_ENTRY1(21), | |
373 | ROUTING_ENTRY1(22), ROUTING_ENTRY1(23), | |
399ec807 AK |
374 | }; |
375 | ||
376 | int kvm_setup_default_irq_routing(struct kvm *kvm) | |
377 | { | |
378 | return kvm_set_irq_routing(kvm, default_routing, | |
379 | ARRAY_SIZE(default_routing), 0); | |
380 | } | |
49df6397 SR |
381 | |
382 | static const struct kvm_irq_routing_entry empty_routing[] = {}; | |
383 | ||
384 | int kvm_setup_empty_irq_routing(struct kvm *kvm) | |
385 | { | |
386 | return kvm_set_irq_routing(kvm, empty_routing, 0, 0); | |
387 | } | |
b053b2ae | 388 | |
abdb080f | 389 | void kvm_arch_post_irq_routing_update(struct kvm *kvm) |
b053b2ae SR |
390 | { |
391 | if (ioapic_in_kernel(kvm) || !irqchip_in_kernel(kvm)) | |
392 | return; | |
393 | kvm_make_scan_ioapic_request(kvm); | |
394 | } | |
395 | ||
6308630b AS |
396 | void kvm_scan_ioapic_routes(struct kvm_vcpu *vcpu, |
397 | ulong *ioapic_handled_vectors) | |
b053b2ae SR |
398 | { |
399 | struct kvm *kvm = vcpu->kvm; | |
400 | struct kvm_kernel_irq_routing_entry *entry; | |
401 | struct kvm_irq_routing_table *table; | |
402 | u32 i, nr_ioapic_pins; | |
403 | int idx; | |
404 | ||
b053b2ae SR |
405 | idx = srcu_read_lock(&kvm->irq_srcu); |
406 | table = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu); | |
407 | nr_ioapic_pins = min_t(u32, table->nr_rt_entries, | |
408 | kvm->arch.nr_reserved_ioapic_pins); | |
409 | for (i = 0; i < nr_ioapic_pins; ++i) { | |
410 | hlist_for_each_entry(entry, &table->map[i], link) { | |
3159d36a | 411 | struct kvm_lapic_irq irq; |
b053b2ae SR |
412 | |
413 | if (entry->type != KVM_IRQ_ROUTING_MSI) | |
414 | continue; | |
3159d36a | 415 | |
37131313 | 416 | kvm_set_msi_irq(vcpu->kvm, entry, &irq); |
3159d36a RK |
417 | |
418 | if (irq.level && kvm_apic_match_dest(vcpu, NULL, 0, | |
419 | irq.dest_id, irq.dest_mode)) | |
420 | __set_bit(irq.vector, ioapic_handled_vectors); | |
b053b2ae SR |
421 | } |
422 | } | |
423 | srcu_read_unlock(&kvm->irq_srcu, idx); | |
424 | } | |
5c919412 AS |
425 | |
426 | int kvm_arch_set_irq(struct kvm_kernel_irq_routing_entry *irq, struct kvm *kvm, | |
427 | int irq_source_id, int level, bool line_status) | |
428 | { | |
429 | switch (irq->type) { | |
430 | case KVM_IRQ_ROUTING_HV_SINT: | |
431 | return kvm_hv_set_sint(irq, kvm, irq_source_id, level, | |
432 | line_status); | |
433 | default: | |
434 | return -EWOULDBLOCK; | |
435 | } | |
436 | } | |
437 | ||
438 | void kvm_arch_irq_routing_update(struct kvm *kvm) | |
439 | { | |
440 | kvm_hv_irq_routing_update(kvm); | |
441 | } |