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85f455f7 ED |
1 | /* |
2 | * irq.h: in kernel interrupt controller related definitions | |
3 | * Copyright (c) 2007, Intel Corporation. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., 59 Temple | |
16 | * Place - Suite 330, Boston, MA 02111-1307 USA. | |
17 | * Authors: | |
18 | * Yaozu (Eddie) Dong <Eddie.dong@intel.com> | |
19 | * | |
20 | */ | |
21 | ||
22 | #ifndef __IRQ_H | |
23 | #define __IRQ_H | |
24 | ||
e01a1b57 HB |
25 | #include <linux/mm_types.h> |
26 | #include <linux/hrtimer.h> | |
edf88417 | 27 | #include <linux/kvm_host.h> |
82470196 | 28 | |
e2174021 | 29 | #include "iodev.h" |
82470196 ZX |
30 | #include "ioapic.h" |
31 | #include "lapic.h" | |
85f455f7 | 32 | |
c65bbfa1 BAY |
33 | #define PIC_NUM_PINS 16 |
34 | ||
e01a1b57 HB |
35 | struct kvm; |
36 | struct kvm_vcpu; | |
37 | ||
85f455f7 ED |
38 | typedef void irq_request_func(void *opaque, int level); |
39 | ||
85f455f7 ED |
40 | struct kvm_kpic_state { |
41 | u8 last_irr; /* edge detection */ | |
42 | u8 irr; /* interrupt request register */ | |
43 | u8 imr; /* interrupt mask register */ | |
44 | u8 isr; /* interrupt service register */ | |
45 | u8 priority_add; /* highest irq priority */ | |
46 | u8 irq_base; | |
47 | u8 read_reg_select; | |
48 | u8 poll; | |
49 | u8 special_mask; | |
50 | u8 init_state; | |
51 | u8 auto_eoi; | |
52 | u8 rotate_on_auto_eoi; | |
53 | u8 special_fully_nested_mode; | |
54 | u8 init4; /* true if 4 byte init */ | |
55 | u8 elcr; /* PIIX edge/trigger selection */ | |
56 | u8 elcr_mask; | |
57 | struct kvm_pic *pics_state; | |
58 | }; | |
59 | ||
60 | struct kvm_pic { | |
61 | struct kvm_kpic_state pics[2]; /* 0 is master pic, 1 is slave pic */ | |
62 | irq_request_func *irq_request; | |
63 | void *irq_request_opaque; | |
64 | int output; /* intr from master PIC */ | |
65 | struct kvm_io_device dev; | |
66 | }; | |
67 | ||
68 | struct kvm_pic *kvm_create_pic(struct kvm *kvm); | |
69 | void kvm_pic_set_irq(void *opaque, int irq, int level); | |
70 | int kvm_pic_read_irq(struct kvm_pic *s); | |
6ceb9d79 | 71 | void kvm_pic_update_irq(struct kvm_pic *s); |
85f455f7 | 72 | |
682c59a3 ZX |
73 | static inline struct kvm_pic *pic_irqchip(struct kvm *kvm) |
74 | { | |
d7deeeb0 | 75 | return kvm->arch.vpic; |
682c59a3 ZX |
76 | } |
77 | ||
682c59a3 ZX |
78 | static inline int irqchip_in_kernel(struct kvm *kvm) |
79 | { | |
80 | return pic_irqchip(kvm) != NULL; | |
81 | } | |
82 | ||
2fcceae1 | 83 | void kvm_pic_reset(struct kvm_kpic_state *s); |
8be5453f | 84 | |
867767a3 | 85 | void kvm_set_irq(struct kvm *kvm, int irq, int level); |
564f1537 AK |
86 | void kvm_notify_acked_irq(struct kvm *kvm, unsigned gsi); |
87 | void kvm_register_irq_ack_notifier(struct kvm *kvm, | |
88 | struct kvm_irq_ack_notifier *kian); | |
89 | void kvm_unregister_irq_ack_notifier(struct kvm *kvm, | |
90 | struct kvm_irq_ack_notifier *kian); | |
867767a3 | 91 | |
1b9778da ED |
92 | void kvm_timer_intr_post(struct kvm_vcpu *vcpu, int vec); |
93 | void kvm_inject_pending_timer_irqs(struct kvm_vcpu *vcpu); | |
94 | void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu); | |
2f52d58c | 95 | void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu); |
2f599714 MT |
96 | void __kvm_migrate_pit_timer(struct kvm_vcpu *vcpu); |
97 | void __kvm_migrate_timers(struct kvm_vcpu *vcpu); | |
97222cc8 | 98 | |
3d80840d MT |
99 | int pit_has_pending_timer(struct kvm_vcpu *vcpu); |
100 | int apic_has_pending_timer(struct kvm_vcpu *vcpu); | |
101 | ||
85f455f7 | 102 | #endif |