[linux-2.6-block.git] / arch / x86 / kvm / ioapic.c

/*
 *  Copyright (C) 2001  MandrakeSoft S.A.
 *  Copyright 2010 Red Hat, Inc. and/or its affiliates.
 *
 *    MandrakeSoft S.A.
 *    43, rue d'Aboukir
 *    75002 Paris - France
 *    http://www.linux-mandrake.com/
 *    http://www.mandrakesoft.com/
 *
 *  This library is free software; you can redistribute it and/or
 *  modify it under the terms of the GNU Lesser General Public
 *  License as published by the Free Software Foundation; either
 *  version 2 of the License, or (at your option) any later version.
 *
 *  This library is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 *  Lesser General Public License for more details.
 *
 *  You should have received a copy of the GNU Lesser General Public
 *  License along with this library; if not, write to the Free Software
 *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 *
 *  Yunhong Jiang <yunhong.jiang@intel.com>
 *  Yaozu (Eddie) Dong <eddie.dong@intel.com>
 *  Based on Xen 3.1 code.
 */

#include <linux/kvm_host.h>
#include <linux/kvm.h>
#include <linux/mm.h>
#include <linux/highmem.h>
#include <linux/smp.h>
#include <linux/hrtimer.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/export.h>
#include <asm/processor.h>
#include <asm/page.h>
#include <asm/current.h>
#include <trace/events/kvm.h>

#include "ioapic.h"
#include "lapic.h"
#include "irq.h"

#if 0
#define ioapic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg)
#else
#define ioapic_debug(fmt, arg...)
#endif
static int ioapic_service(struct kvm_ioapic *vioapic, int irq,
		bool line_status);

static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic,
					  unsigned long addr,
					  unsigned long length)
{
	unsigned long result = 0;

	switch (ioapic->ioregsel) {
	case IOAPIC_REG_VERSION:
		result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16)
			  | (IOAPIC_VERSION_ID & 0xff));
		break;

	case IOAPIC_REG_APIC_ID:
	case IOAPIC_REG_ARB_ID:
		result = ((ioapic->id & 0xf) << 24);
		break;

	default:
		{
			u32 redir_index = (ioapic->ioregsel - 0x10) >> 1;
			u64 redir_content;

			if (redir_index < IOAPIC_NUM_PINS)
				redir_content =
					ioapic->redirtbl[redir_index].bits;
			else
				redir_content = ~0ULL;

			result = (ioapic->ioregsel & 0x1) ?
			    (redir_content >> 32) & 0xffffffff :
			    redir_content & 0xffffffff;
			break;
		}
	}

	return result;
}

static void rtc_irq_eoi_tracking_reset(struct kvm_ioapic *ioapic)
{
	ioapic->rtc_status.pending_eoi = 0;
	bitmap_zero(ioapic->rtc_status.dest_map.map, KVM_MAX_VCPUS);
}

static void kvm_rtc_eoi_tracking_restore_all(struct kvm_ioapic *ioapic);

static void rtc_status_pending_eoi_check_valid(struct kvm_ioapic *ioapic)
{
	if (WARN_ON(ioapic->rtc_status.pending_eoi < 0))
		kvm_rtc_eoi_tracking_restore_all(ioapic);
}

static void __rtc_irq_eoi_tracking_restore_one(struct kvm_vcpu *vcpu)
{
	bool new_val, old_val;
	struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic;
	union kvm_ioapic_redirect_entry *e;

	e = &ioapic->redirtbl[RTC_GSI];
	if (!kvm_apic_match_dest(vcpu, NULL, 0,	e->fields.dest_id,
				e->fields.dest_mode))
		return;

	new_val = kvm_apic_pending_eoi(vcpu, e->fields.vector);
	old_val = test_bit(vcpu->vcpu_id, ioapic->rtc_status.dest_map.map);

	if (new_val == old_val)
		return;

	if (new_val) {
		__set_bit(vcpu->vcpu_id, ioapic->rtc_status.dest_map.map);
		ioapic->rtc_status.pending_eoi++;
	} else {
		__clear_bit(vcpu->vcpu_id, ioapic->rtc_status.dest_map.map);
		ioapic->rtc_status.pending_eoi--;
		rtc_status_pending_eoi_check_valid(ioapic);
	}
}

void kvm_rtc_eoi_tracking_restore_one(struct kvm_vcpu *vcpu)
{
	struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic;

	spin_lock(&ioapic->lock);
	__rtc_irq_eoi_tracking_restore_one(vcpu);
	spin_unlock(&ioapic->lock);
}

static void kvm_rtc_eoi_tracking_restore_all(struct kvm_ioapic *ioapic)
{
	struct kvm_vcpu *vcpu;
	int i;

	if (RTC_GSI >= IOAPIC_NUM_PINS)
		return;

	rtc_irq_eoi_tracking_reset(ioapic);
	kvm_for_each_vcpu(i, vcpu, ioapic->kvm)
	    __rtc_irq_eoi_tracking_restore_one(vcpu);
}

static void rtc_irq_eoi(struct kvm_ioapic *ioapic, struct kvm_vcpu *vcpu)
{
	if (test_and_clear_bit(vcpu->vcpu_id,
			       ioapic->rtc_status.dest_map.map)) {
		--ioapic->rtc_status.pending_eoi;
		rtc_status_pending_eoi_check_valid(ioapic);
	}
}

static bool rtc_irq_check_coalesced(struct kvm_ioapic *ioapic)
{
	if (ioapic->rtc_status.pending_eoi > 0)
		return true; /* coalesced */

	return false;
}

static int ioapic_set_irq(struct kvm_ioapic *ioapic, unsigned int irq,
		int irq_level, bool line_status)
{
	union kvm_ioapic_redirect_entry entry;
	u32 mask = 1 << irq;
	u32 old_irr;
	int edge, ret;

	entry = ioapic->redirtbl[irq];
	edge = (entry.fields.trig_mode == IOAPIC_EDGE_TRIG);

	if (!irq_level) {
		ioapic->irr &= ~mask;
		ret = 1;
		goto out;
	}

	/*
	 * Return 0 for coalesced interrupts; for edge-triggered interrupts,
	 * this only happens if a previous edge has not been delivered due
	 * do masking.  For level interrupts, the remote_irr field tells
	 * us if the interrupt is waiting for an EOI.
	 *
	 * RTC is special: it is edge-triggered, but userspace likes to know
	 * if it has been already ack-ed via EOI because coalesced RTC
	 * interrupts lead to time drift in Windows guests.  So we track
	 * EOI manually for the RTC interrupt.
	 */
	if (irq == RTC_GSI && line_status &&
		rtc_irq_check_coalesced(ioapic)) {
		ret = 0;
		goto out;
	}

	old_irr = ioapic->irr;
	ioapic->irr |= mask;
	if (edge)
		ioapic->irr_delivered &= ~mask;
	if ((edge && old_irr == ioapic->irr) ||
	    (!edge && entry.fields.remote_irr)) {
		ret = 0;
		goto out;
	}

	ret = ioapic_service(ioapic, irq, line_status);

out:
	trace_kvm_ioapic_set_irq(entry.bits, irq, ret == 0);
	return ret;
}

static void kvm_ioapic_inject_all(struct kvm_ioapic *ioapic, unsigned long irr)
{
	u32 idx;

	rtc_irq_eoi_tracking_reset(ioapic);
	for_each_set_bit(idx, &irr, IOAPIC_NUM_PINS)
		ioapic_set_irq(ioapic, idx, 1, true);

	kvm_rtc_eoi_tracking_restore_all(ioapic);
}


void kvm_ioapic_scan_entry(struct kvm_vcpu *vcpu, ulong *ioapic_handled_vectors)
{
	struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic;
	union kvm_ioapic_redirect_entry *e;
	int index;

	spin_lock(&ioapic->lock);
	for (index = 0; index < IOAPIC_NUM_PINS; index++) {
		e = &ioapic->redirtbl[index];
		if (e->fields.trig_mode == IOAPIC_LEVEL_TRIG ||
		    kvm_irq_has_notifier(ioapic->kvm, KVM_IRQCHIP_IOAPIC, index) ||
		    index == RTC_GSI) {
			if (kvm_apic_match_dest(vcpu, NULL, 0,
			             e->fields.dest_id, e->fields.dest_mode) ||
			    (e->fields.trig_mode == IOAPIC_EDGE_TRIG &&
			     kvm_apic_pending_eoi(vcpu, e->fields.vector)))
				__set_bit(e->fields.vector,
					  ioapic_handled_vectors);
		}
	}
	spin_unlock(&ioapic->lock);
}

void kvm_vcpu_request_scan_ioapic(struct kvm *kvm)
{
	struct kvm_ioapic *ioapic = kvm->arch.vioapic;

	if (!ioapic)
		return;
	kvm_make_scan_ioapic_request(kvm);
}

static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
{
	unsigned index;
	bool mask_before, mask_after;
	union kvm_ioapic_redirect_entry *e;

	switch (ioapic->ioregsel) {
	case IOAPIC_REG_VERSION:
		/* Writes are ignored. */
		break;

	case IOAPIC_REG_APIC_ID:
		ioapic->id = (val >> 24) & 0xf;
		break;

	case IOAPIC_REG_ARB_ID:
		break;

	default:
		index = (ioapic->ioregsel - 0x10) >> 1;

		ioapic_debug("change redir index %x val %x\n", index, val);
		if (index >= IOAPIC_NUM_PINS)
			return;
		e = &ioapic->redirtbl[index];
		mask_before = e->fields.mask;
		if (ioapic->ioregsel & 1) {
			e->bits &= 0xffffffff;
			e->bits |= (u64) val << 32;
		} else {
			e->bits &= ~0xffffffffULL;
			e->bits |= (u32) val;
			e->fields.remote_irr = 0;
		}
		mask_after = e->fields.mask;
		if (mask_before != mask_after)
			kvm_fire_mask_notifiers(ioapic->kvm, KVM_IRQCHIP_IOAPIC, index, mask_after);
		if (e->fields.trig_mode == IOAPIC_LEVEL_TRIG
		    && ioapic->irr & (1 << index))
			ioapic_service(ioapic, index, false);
		kvm_vcpu_request_scan_ioapic(ioapic->kvm);
		break;
	}
}

static int ioapic_service(struct kvm_ioapic *ioapic, int irq, bool line_status)
{
	union kvm_ioapic_redirect_entry *entry = &ioapic->redirtbl[irq];
	struct kvm_lapic_irq irqe;
	int ret;

	if (entry->fields.mask)
		return -1;

	ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x "
		     "vector=%x trig_mode=%x\n",
		     entry->fields.dest_id, entry->fields.dest_mode,
		     entry->fields.delivery_mode, entry->fields.vector,
		     entry->fields.trig_mode);

	irqe.dest_id = entry->fields.dest_id;
	irqe.vector = entry->fields.vector;
	irqe.dest_mode = entry->fields.dest_mode;
	irqe.trig_mode = entry->fields.trig_mode;
	irqe.delivery_mode = entry->fields.delivery_mode << 8;
	irqe.level = 1;
	irqe.shorthand = 0;
	irqe.msi_redir_hint = false;

	if (irqe.trig_mode == IOAPIC_EDGE_TRIG)
		ioapic->irr_delivered |= 1 << irq;

	if (irq == RTC_GSI && line_status) {
		/*
		 * pending_eoi cannot ever become negative (see
		 * rtc_status_pending_eoi_check_valid) and the caller
		 * ensures that it is only called if it is >= zero, namely
		 * if rtc_irq_check_coalesced returns false).
		 */
		BUG_ON(ioapic->rtc_status.pending_eoi != 0);
		ret = kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe,
					       &ioapic->rtc_status.dest_map);
		ioapic->rtc_status.pending_eoi = (ret < 0 ? 0 : ret);
	} else
		ret = kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe, NULL);

	if (ret && irqe.trig_mode == IOAPIC_LEVEL_TRIG)
		entry->fields.remote_irr = 1;

	return ret;
}

int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int irq_source_id,
		       int level, bool line_status)
{
	int ret, irq_level;

	BUG_ON(irq < 0 || irq >= IOAPIC_NUM_PINS);

	spin_lock(&ioapic->lock);
	irq_level = __kvm_irq_line_state(&ioapic->irq_states[irq],
					 irq_source_id, level);
	ret = ioapic_set_irq(ioapic, irq, irq_level, line_status);

	spin_unlock(&ioapic->lock);

	return ret;
}

void kvm_ioapic_clear_all(struct kvm_ioapic *ioapic, int irq_source_id)
{
	int i;

	spin_lock(&ioapic->lock);
	for (i = 0; i < KVM_IOAPIC_NUM_PINS; i++)
		__clear_bit(irq_source_id, &ioapic->irq_states[i]);
	spin_unlock(&ioapic->lock);
}

static void kvm_ioapic_eoi_inject_work(struct work_struct *work)
{
	int i;
	struct kvm_ioapic *ioapic = container_of(work, struct kvm_ioapic,
						 eoi_inject.work);
	spin_lock(&ioapic->lock);
	for (i = 0; i < IOAPIC_NUM_PINS; i++) {
		union kvm_ioapic_redirect_entry *ent = &ioapic->redirtbl[i];

		if (ent->fields.trig_mode != IOAPIC_LEVEL_TRIG)
			continue;

		if (ioapic->irr & (1 << i) && !ent->fields.remote_irr)
			ioapic_service(ioapic, i, false);
	}
	spin_unlock(&ioapic->lock);
}

#define IOAPIC_SUCCESSIVE_IRQ_MAX_COUNT 10000

static void __kvm_ioapic_update_eoi(struct kvm_vcpu *vcpu,
			struct kvm_ioapic *ioapic, int vector, int trigger_mode)
{
	int i;
	struct kvm_lapic *apic = vcpu->arch.apic;

	for (i = 0; i < IOAPIC_NUM_PINS; i++) {
		union kvm_ioapic_redirect_entry *ent = &ioapic->redirtbl[i];

		if (ent->fields.vector != vector)
			continue;

		if (i == RTC_GSI)
			rtc_irq_eoi(ioapic, vcpu);
		/*
		 * We are dropping lock while calling ack notifiers because ack
		 * notifier callbacks for assigned devices call into IOAPIC
		 * recursively. Since remote_irr is cleared only after call
		 * to notifiers if the same vector will be delivered while lock
		 * is dropped it will be put into irr and will be delivered
		 * after ack notifier returns.
		 */
		spin_unlock(&ioapic->lock);
		kvm_notify_acked_irq(ioapic->kvm, KVM_IRQCHIP_IOAPIC, i);
		spin_lock(&ioapic->lock);

		if (trigger_mode != IOAPIC_LEVEL_TRIG ||
		    kvm_apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI)
			continue;

		ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG);
		ent->fields.remote_irr = 0;
		if (!ent->fields.mask && (ioapic->irr & (1 << i))) {
			++ioapic->irq_eoi[i];
			if (ioapic->irq_eoi[i] == IOAPIC_SUCCESSIVE_IRQ_MAX_COUNT) {
				/*
				 * Real hardware does not deliver the interrupt
				 * immediately during eoi broadcast, and this
				 * lets a buggy guest make slow progress
				 * even if it does not correctly handle a
				 * level-triggered interrupt.  Emulate this
				 * behavior if we detect an interrupt storm.
				 */
				schedule_delayed_work(&ioapic->eoi_inject, HZ / 100);
				ioapic->irq_eoi[i] = 0;
				trace_kvm_ioapic_delayed_eoi_inj(ent->bits);
			} else {
				ioapic_service(ioapic, i, false);
			}
		} else {
			ioapic->irq_eoi[i] = 0;
		}
	}
}

void kvm_ioapic_update_eoi(struct kvm_vcpu *vcpu, int vector, int trigger_mode)
{
	struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic;

	spin_lock(&ioapic->lock);
	__kvm_ioapic_update_eoi(vcpu, ioapic, vector, trigger_mode);
	spin_unlock(&ioapic->lock);
}

static inline struct kvm_ioapic *to_ioapic(struct kvm_io_device *dev)
{
	return container_of(dev, struct kvm_ioapic, dev);
}

static inline int ioapic_in_range(struct kvm_ioapic *ioapic, gpa_t addr)
{
	return ((addr >= ioapic->base_address &&
		 (addr < ioapic->base_address + IOAPIC_MEM_LENGTH)));
}

static int ioapic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
				gpa_t addr, int len, void *val)
{
	struct kvm_ioapic *ioapic = to_ioapic(this);
	u32 result;
	if (!ioapic_in_range(ioapic, addr))
		return -EOPNOTSUPP;

	ioapic_debug("addr %lx\n", (unsigned long)addr);
	ASSERT(!(addr & 0xf));	/* check alignment */

	addr &= 0xff;
	spin_lock(&ioapic->lock);
	switch (addr) {
	case IOAPIC_REG_SELECT:
		result = ioapic->ioregsel;
		break;

	case IOAPIC_REG_WINDOW:
		result = ioapic_read_indirect(ioapic, addr, len);
		break;

	default:
		result = 0;
		break;
	}
	spin_unlock(&ioapic->lock);

	switch (len) {
	case 8:
		*(u64 *) val = result;
		break;
	case 1:
	case 2:
	case 4:
		memcpy(val, (char *)&result, len);
		break;
	default:
		printk(KERN_WARNING "ioapic: wrong length %d\n", len);
	}
	return 0;
}

static int ioapic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
				 gpa_t addr, int len, const void *val)
{
	struct kvm_ioapic *ioapic = to_ioapic(this);
	u32 data;
	if (!ioapic_in_range(ioapic, addr))
		return -EOPNOTSUPP;

	ioapic_debug("ioapic_mmio_write addr=%p len=%d val=%p\n",
		     (void*)addr, len, val);
	ASSERT(!(addr & 0xf));	/* check alignment */

	switch (len) {
	case 8:
	case 4:
		data = *(u32 *) val;
		break;
	case 2:
		data = *(u16 *) val;
		break;
	case 1:
		data = *(u8  *) val;
		break;
	default:
		printk(KERN_WARNING "ioapic: Unsupported size %d\n", len);
		return 0;
	}

	addr &= 0xff;
	spin_lock(&ioapic->lock);
	switch (addr) {
	case IOAPIC_REG_SELECT:
		ioapic->ioregsel = data & 0xFF; /* 8-bit register */
		break;

	case IOAPIC_REG_WINDOW:
		ioapic_write_indirect(ioapic, data);
		break;

	default:
		break;
	}
	spin_unlock(&ioapic->lock);
	return 0;
}

static void kvm_ioapic_reset(struct kvm_ioapic *ioapic)
{
	int i;

	cancel_delayed_work_sync(&ioapic->eoi_inject);
	for (i = 0; i < IOAPIC_NUM_PINS; i++)
		ioapic->redirtbl[i].fields.mask = 1;
	ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
	ioapic->ioregsel = 0;
	ioapic->irr = 0;
	ioapic->irr_delivered = 0;
	ioapic->id = 0;
	memset(ioapic->irq_eoi, 0x00, IOAPIC_NUM_PINS);
	rtc_irq_eoi_tracking_reset(ioapic);
}

static const struct kvm_io_device_ops ioapic_mmio_ops = {
	.read     = ioapic_mmio_read,
	.write    = ioapic_mmio_write,
};

int kvm_ioapic_init(struct kvm *kvm)
{
	struct kvm_ioapic *ioapic;
	int ret;

	ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL);
	if (!ioapic)
		return -ENOMEM;
	spin_lock_init(&ioapic->lock);
	INIT_DELAYED_WORK(&ioapic->eoi_inject, kvm_ioapic_eoi_inject_work);
	kvm->arch.vioapic = ioapic;
	kvm_ioapic_reset(ioapic);
	kvm_iodevice_init(&ioapic->dev, &ioapic_mmio_ops);
	ioapic->kvm = kvm;
	mutex_lock(&kvm->slots_lock);
	ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, ioapic->base_address,
				      IOAPIC_MEM_LENGTH, &ioapic->dev);
	mutex_unlock(&kvm->slots_lock);
	if (ret < 0) {
		kvm->arch.vioapic = NULL;
		kfree(ioapic);
		return ret;
	}

	kvm_vcpu_request_scan_ioapic(kvm);
	return ret;
}

void kvm_ioapic_destroy(struct kvm *kvm)
{
	struct kvm_ioapic *ioapic = kvm->arch.vioapic;

	cancel_delayed_work_sync(&ioapic->eoi_inject);
	kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS, &ioapic->dev);
	kvm->arch.vioapic = NULL;
	kfree(ioapic);
}

int kvm_get_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state)
{
	struct kvm_ioapic *ioapic = ioapic_irqchip(kvm);
	if (!ioapic)
		return -EINVAL;

	spin_lock(&ioapic->lock);
	memcpy(state, ioapic, sizeof(struct kvm_ioapic_state));
	state->irr &= ~ioapic->irr_delivered;
	spin_unlock(&ioapic->lock);
	return 0;
}

int kvm_set_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state)
{
	struct kvm_ioapic *ioapic = ioapic_irqchip(kvm);
	if (!ioapic)
		return -EINVAL;

	spin_lock(&ioapic->lock);
	memcpy(ioapic, state, sizeof(struct kvm_ioapic_state));
	ioapic->irr = 0;
	ioapic->irr_delivered = 0;
	kvm_vcpu_request_scan_ioapic(kvm);
	kvm_ioapic_inject_all(ioapic, state->irr);
	spin_unlock(&ioapic->lock);
	return 0;
}
Commit	Line	Data
1fd4f2a5 ED	1	/*
1fd4f2a5 ED	2	* Copyright (C) 2001 MandrakeSoft S.A.
221d059d	3	* Copyright 2010 Red Hat, Inc. and/or its affiliates.
1fd4f2a5 ED	4	*
	5	* MandrakeSoft S.A.
	6	* 43, rue d'Aboukir
	7	* 75002 Paris - France
	8	* http://www.linux-mandrake.com/
	9	* http://www.mandrakesoft.com/
	10	*
	11	* This library is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU Lesser General Public
	13	* License as published by the Free Software Foundation; either
	14	* version 2 of the License, or (at your option) any later version.
	15	*
	16	* This library is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	19	* Lesser General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU Lesser General Public
	22	* License along with this library; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	24	*
	25	* Yunhong Jiang <yunhong.jiang@intel.com>
	26	* Yaozu (Eddie) Dong <eddie.dong@intel.com>
	27	* Based on Xen 3.1 code.
	28	*/
	29
edf88417	30	#include <linux/kvm_host.h>
1fd4f2a5 ED	31	#include <linux/kvm.h>
	32	#include <linux/mm.h>
	33	#include <linux/highmem.h>
	34	#include <linux/smp.h>
	35	#include <linux/hrtimer.h>
	36	#include <linux/io.h>
5a0e3ad6	37	#include <linux/slab.h>
c7c9c56c	38	#include <linux/export.h>
1fd4f2a5	39	#include <asm/processor.h>
1fd4f2a5 ED	40	#include <asm/page.h>
1fd4f2a5 ED	41	#include <asm/current.h>
1000ff8d	42	#include <trace/events/kvm.h>
82470196 ZX	43
	44	#include "ioapic.h"
	45	#include "lapic.h"
f5244726	46	#include "irq.h"
82470196	47
e25e3ed5 LV	48	#if 0
	49	#define ioapic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg)
	50	#else
1fd4f2a5	51	#define ioapic_debug(fmt, arg...)
e25e3ed5	52	#endif
0b10a1c8	53	static int ioapic_service(struct kvm_ioapic *vioapic, int irq,
aa2fbe6d	54	bool line_status);
1fd4f2a5 ED	55
	56	static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic,
	57	unsigned long addr,
	58	unsigned long length)
	59	{
	60	unsigned long result = 0;
	61
	62	switch (ioapic->ioregsel) {
	63	case IOAPIC_REG_VERSION:
	64	result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16)
	65	\| (IOAPIC_VERSION_ID & 0xff));
	66	break;
	67
	68	case IOAPIC_REG_APIC_ID:
	69	case IOAPIC_REG_ARB_ID:
	70	result = ((ioapic->id & 0xf) << 24);
	71	break;
	72
	73	default:
	74	{
	75	u32 redir_index = (ioapic->ioregsel - 0x10) >> 1;
	76	u64 redir_content;
	77
a2c118bf AH	78	if (redir_index < IOAPIC_NUM_PINS)
	79	redir_content =
	80	ioapic->redirtbl[redir_index].bits;
	81	else
	82	redir_content = ~0ULL;
1fd4f2a5	83
1fd4f2a5 ED	84	result = (ioapic->ioregsel & 0x1) ?
	85	(redir_content >> 32) & 0xffffffff :
	86	redir_content & 0xffffffff;
	87	break;
	88	}
	89	}
	90
	91	return result;
	92	}
	93
10606919 YZ	94	static void rtc_irq_eoi_tracking_reset(struct kvm_ioapic *ioapic)
	95	{
	96	ioapic->rtc_status.pending_eoi = 0;
9e4aabe2	97	bitmap_zero(ioapic->rtc_status.dest_map.map, KVM_MAX_VCPUS);
10606919 YZ	98	}
10606919 YZ	99
4009b249 PB	100	static void kvm_rtc_eoi_tracking_restore_all(struct kvm_ioapic *ioapic);
	101
	102	static void rtc_status_pending_eoi_check_valid(struct kvm_ioapic *ioapic)
	103	{
	104	if (WARN_ON(ioapic->rtc_status.pending_eoi < 0))
	105	kvm_rtc_eoi_tracking_restore_all(ioapic);
	106	}
	107
10606919 YZ	108	static void __rtc_irq_eoi_tracking_restore_one(struct kvm_vcpu *vcpu)
	109	{
	110	bool new_val, old_val;
	111	struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic;
	112	union kvm_ioapic_redirect_entry *e;
	113
	114	e = &ioapic->redirtbl[RTC_GSI];
	115	if (!kvm_apic_match_dest(vcpu, NULL, 0, e->fields.dest_id,
	116	e->fields.dest_mode))
	117	return;
	118
	119	new_val = kvm_apic_pending_eoi(vcpu, e->fields.vector);
9e4aabe2	120	old_val = test_bit(vcpu->vcpu_id, ioapic->rtc_status.dest_map.map);
10606919 YZ	121
	122	if (new_val == old_val)
	123	return;
	124
	125	if (new_val) {
9e4aabe2	126	__set_bit(vcpu->vcpu_id, ioapic->rtc_status.dest_map.map);
10606919 YZ	127	ioapic->rtc_status.pending_eoi++;
10606919 YZ	128	} else {
9e4aabe2	129	__clear_bit(vcpu->vcpu_id, ioapic->rtc_status.dest_map.map);
10606919	130	ioapic->rtc_status.pending_eoi--;
4009b249	131	rtc_status_pending_eoi_check_valid(ioapic);
10606919	132	}
10606919 YZ	133	}
	134
	135	void kvm_rtc_eoi_tracking_restore_one(struct kvm_vcpu *vcpu)
	136	{
	137	struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic;
	138
	139	spin_lock(&ioapic->lock);
	140	__rtc_irq_eoi_tracking_restore_one(vcpu);
	141	spin_unlock(&ioapic->lock);
	142	}
	143
	144	static void kvm_rtc_eoi_tracking_restore_all(struct kvm_ioapic *ioapic)
	145	{
	146	struct kvm_vcpu *vcpu;
	147	int i;
	148
	149	if (RTC_GSI >= IOAPIC_NUM_PINS)
	150	return;
	151
	152	rtc_irq_eoi_tracking_reset(ioapic);
	153	kvm_for_each_vcpu(i, vcpu, ioapic->kvm)
	154	__rtc_irq_eoi_tracking_restore_one(vcpu);
	155	}
	156
2c2bf011 YZ	157	static void rtc_irq_eoi(struct kvm_ioapic ioapic, struct kvm_vcpu vcpu)
2c2bf011 YZ	158	{
9e4aabe2 JR	159	if (test_and_clear_bit(vcpu->vcpu_id,
9e4aabe2 JR	160	ioapic->rtc_status.dest_map.map)) {
2c2bf011	161	--ioapic->rtc_status.pending_eoi;
4009b249 PB	162	rtc_status_pending_eoi_check_valid(ioapic);
4009b249 PB	163	}
2c2bf011 YZ	164	}
	165
	166	static bool rtc_irq_check_coalesced(struct kvm_ioapic *ioapic)
	167	{
	168	if (ioapic->rtc_status.pending_eoi > 0)
	169	return true; /* coalesced */
	170
	171	return false;
	172	}
	173
44847dea PB	174	static int ioapic_set_irq(struct kvm_ioapic *ioapic, unsigned int irq,
	175	int irq_level, bool line_status)
	176	{
	177	union kvm_ioapic_redirect_entry entry;
	178	u32 mask = 1 << irq;
	179	u32 old_irr;
	180	int edge, ret;
	181
	182	entry = ioapic->redirtbl[irq];
	183	edge = (entry.fields.trig_mode == IOAPIC_EDGE_TRIG);
	184
	185	if (!irq_level) {
	186	ioapic->irr &= ~mask;
	187	ret = 1;
	188	goto out;
	189	}
	190
	191	/*
	192	* Return 0 for coalesced interrupts; for edge-triggered interrupts,
	193	* this only happens if a previous edge has not been delivered due
	194	* do masking. For level interrupts, the remote_irr field tells
	195	* us if the interrupt is waiting for an EOI.
	196	*
	197	* RTC is special: it is edge-triggered, but userspace likes to know
	198	* if it has been already ack-ed via EOI because coalesced RTC
	199	* interrupts lead to time drift in Windows guests. So we track
	200	* EOI manually for the RTC interrupt.
	201	*/
	202	if (irq == RTC_GSI && line_status &&
	203	rtc_irq_check_coalesced(ioapic)) {
	204	ret = 0;
	205	goto out;
	206	}
	207
	208	old_irr = ioapic->irr;
	209	ioapic->irr \|= mask;
5bda6eed WV	210	if (edge)
5bda6eed WV	211	ioapic->irr_delivered &= ~mask;
44847dea PB	212	if ((edge && old_irr == ioapic->irr) \|\|
	213	(!edge && entry.fields.remote_irr)) {
	214	ret = 0;
	215	goto out;
	216	}
	217
	218	ret = ioapic_service(ioapic, irq, line_status);
	219
	220	out:
	221	trace_kvm_ioapic_set_irq(entry.bits, irq, ret == 0);
	222	return ret;
	223	}
	224
673f7b42 PB	225	static void kvm_ioapic_inject_all(struct kvm_ioapic *ioapic, unsigned long irr)
	226	{
	227	u32 idx;
	228
	229	rtc_irq_eoi_tracking_reset(ioapic);
	230	for_each_set_bit(idx, &irr, IOAPIC_NUM_PINS)
	231	ioapic_set_irq(ioapic, idx, 1, true);
	232
	233	kvm_rtc_eoi_tracking_restore_all(ioapic);
	234	}
	235
	236
6308630b	237	void kvm_ioapic_scan_entry(struct kvm_vcpu vcpu, ulong ioapic_handled_vectors)
c7c9c56c YZ	238	{
	239	struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic;
	240	union kvm_ioapic_redirect_entry *e;
c7c9c56c YZ	241	int index;
	242
	243	spin_lock(&ioapic->lock);
c7c9c56c YZ	244	for (index = 0; index < IOAPIC_NUM_PINS; index++) {
c7c9c56c YZ	245	e = &ioapic->redirtbl[index];
0f6c0a74 PB	246	if (e->fields.trig_mode == IOAPIC_LEVEL_TRIG \|\|
	247	kvm_irq_has_notifier(ioapic->kvm, KVM_IRQCHIP_IOAPIC, index) \|\|
	248	index == RTC_GSI) {
44944d4d	249	if (kvm_apic_match_dest(vcpu, NULL, 0,
db2bdcbb RK	250	e->fields.dest_id, e->fields.dest_mode) \|\|
	251	(e->fields.trig_mode == IOAPIC_EDGE_TRIG &&
	252	kvm_apic_pending_eoi(vcpu, e->fields.vector)))
cf9e65b7	253	__set_bit(e->fields.vector,
6308630b	254	ioapic_handled_vectors);
c7c9c56c YZ	255	}
	256	}
	257	spin_unlock(&ioapic->lock);
	258	}
c7c9c56c	259
3d81bc7e	260	void kvm_vcpu_request_scan_ioapic(struct kvm *kvm)
c7c9c56c YZ	261	{
	262	struct kvm_ioapic *ioapic = kvm->arch.vioapic;
	263
3d81bc7e	264	if (!ioapic)
c7c9c56c	265	return;
3d81bc7e	266	kvm_make_scan_ioapic_request(kvm);
c7c9c56c YZ	267	}
c7c9c56c YZ	268
1fd4f2a5 ED	269	static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
	270	{
	271	unsigned index;
75858a84	272	bool mask_before, mask_after;
70f93dae	273	union kvm_ioapic_redirect_entry *e;
1fd4f2a5 ED	274
	275	switch (ioapic->ioregsel) {
	276	case IOAPIC_REG_VERSION:
	277	/* Writes are ignored. */
	278	break;
	279
	280	case IOAPIC_REG_APIC_ID:
	281	ioapic->id = (val >> 24) & 0xf;
	282	break;
	283
	284	case IOAPIC_REG_ARB_ID:
	285	break;
	286
	287	default:
	288	index = (ioapic->ioregsel - 0x10) >> 1;
	289
e25e3ed5	290	ioapic_debug("change redir index %x val %x\n", index, val);
1fd4f2a5 ED	291	if (index >= IOAPIC_NUM_PINS)
1fd4f2a5 ED	292	return;
70f93dae GN	293	e = &ioapic->redirtbl[index];
70f93dae GN	294	mask_before = e->fields.mask;
1fd4f2a5	295	if (ioapic->ioregsel & 1) {
70f93dae GN	296	e->bits &= 0xffffffff;
70f93dae GN	297	e->bits \|= (u64) val << 32;
1fd4f2a5	298	} else {
70f93dae GN	299	e->bits &= ~0xffffffffULL;
	300	e->bits \|= (u32) val;
	301	e->fields.remote_irr = 0;
1fd4f2a5	302	}
70f93dae	303	mask_after = e->fields.mask;
75858a84	304	if (mask_before != mask_after)
4a994358	305	kvm_fire_mask_notifiers(ioapic->kvm, KVM_IRQCHIP_IOAPIC, index, mask_after);
70f93dae	306	if (e->fields.trig_mode == IOAPIC_LEVEL_TRIG
b4a2f5e7	307	&& ioapic->irr & (1 << index))
aa2fbe6d	308	ioapic_service(ioapic, index, false);
3d81bc7e	309	kvm_vcpu_request_scan_ioapic(ioapic->kvm);
1fd4f2a5 ED	310	break;
	311	}
	312	}
	313
0b10a1c8	314	static int ioapic_service(struct kvm_ioapic *ioapic, int irq, bool line_status)
a53c17d2	315	{
58c2dde1 GN	316	union kvm_ioapic_redirect_entry *entry = &ioapic->redirtbl[irq];
58c2dde1 GN	317	struct kvm_lapic_irq irqe;
2c2bf011	318	int ret;
a53c17d2	319
0b10a1c8 PB	320	if (entry->fields.mask)
	321	return -1;
	322
a53c17d2 GN	323	ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x "
a53c17d2 GN	324	"vector=%x trig_mode=%x\n",
a38f84ca	325	entry->fields.dest_id, entry->fields.dest_mode,
58c2dde1 GN	326	entry->fields.delivery_mode, entry->fields.vector,
	327	entry->fields.trig_mode);
	328
	329	irqe.dest_id = entry->fields.dest_id;
	330	irqe.vector = entry->fields.vector;
	331	irqe.dest_mode = entry->fields.dest_mode;
	332	irqe.trig_mode = entry->fields.trig_mode;
	333	irqe.delivery_mode = entry->fields.delivery_mode << 8;
	334	irqe.level = 1;
	335	irqe.shorthand = 0;
93bbf0b8	336	irqe.msi_redir_hint = false;
a53c17d2	337
0bc830b0	338	if (irqe.trig_mode == IOAPIC_EDGE_TRIG)
5bda6eed	339	ioapic->irr_delivered \|= 1 << irq;
0bc830b0	340
2c2bf011	341	if (irq == RTC_GSI && line_status) {
4009b249 PB	342	/*
	343	* pending_eoi cannot ever become negative (see
	344	* rtc_status_pending_eoi_check_valid) and the caller
	345	* ensures that it is only called if it is >= zero, namely
	346	* if rtc_irq_check_coalesced returns false).
	347	*/
2c2bf011 YZ	348	BUG_ON(ioapic->rtc_status.pending_eoi != 0);
2c2bf011 YZ	349	ret = kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe,
9e4aabe2	350	&ioapic->rtc_status.dest_map);
5678de3f	351	ioapic->rtc_status.pending_eoi = (ret < 0 ? 0 : ret);
2c2bf011 YZ	352	} else
	353	ret = kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe, NULL);
	354
0b10a1c8 PB	355	if (ret && irqe.trig_mode == IOAPIC_LEVEL_TRIG)
	356	entry->fields.remote_irr = 1;
	357
2c2bf011	358	return ret;
a53c17d2 GN	359	}
a53c17d2 GN	360
1a577b72	361	int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int irq_source_id,
aa2fbe6d	362	int level, bool line_status)
1fd4f2a5	363	{
28a6fdab MT	364	int ret, irq_level;
	365
	366	BUG_ON(irq < 0 \|\| irq >= IOAPIC_NUM_PINS);
1fd4f2a5	367
46a47b1e	368	spin_lock(&ioapic->lock);
28a6fdab MT	369	irq_level = __kvm_irq_line_state(&ioapic->irq_states[irq],
28a6fdab MT	370	irq_source_id, level);
44847dea	371	ret = ioapic_set_irq(ioapic, irq, irq_level, line_status);
2c2bf011	372
46a47b1e	373	spin_unlock(&ioapic->lock);
eba0226b	374
4925663a	375	return ret;
1fd4f2a5 ED	376	}
1fd4f2a5 ED	377
1a577b72 MT	378	void kvm_ioapic_clear_all(struct kvm_ioapic *ioapic, int irq_source_id)
	379	{
	380	int i;
	381
	382	spin_lock(&ioapic->lock);
	383	for (i = 0; i < KVM_IOAPIC_NUM_PINS; i++)
	384	__clear_bit(irq_source_id, &ioapic->irq_states[i]);
	385	spin_unlock(&ioapic->lock);
	386	}
	387
184564ef ZH	388	static void kvm_ioapic_eoi_inject_work(struct work_struct *work)
	389	{
	390	int i;
	391	struct kvm_ioapic *ioapic = container_of(work, struct kvm_ioapic,
	392	eoi_inject.work);
	393	spin_lock(&ioapic->lock);
	394	for (i = 0; i < IOAPIC_NUM_PINS; i++) {
	395	union kvm_ioapic_redirect_entry *ent = &ioapic->redirtbl[i];
	396
	397	if (ent->fields.trig_mode != IOAPIC_LEVEL_TRIG)
	398	continue;
	399
	400	if (ioapic->irr & (1 << i) && !ent->fields.remote_irr)
	401	ioapic_service(ioapic, i, false);
	402	}
	403	spin_unlock(&ioapic->lock);
	404	}
	405
	406	#define IOAPIC_SUCCESSIVE_IRQ_MAX_COUNT 10000
	407
1fcc7890 YZ	408	static void __kvm_ioapic_update_eoi(struct kvm_vcpu *vcpu,
1fcc7890 YZ	409	struct kvm_ioapic *ioapic, int vector, int trigger_mode)
1fd4f2a5	410	{
eba0226b	411	int i;
c806a6ad	412	struct kvm_lapic *apic = vcpu->arch.apic;
eba0226b GN	413
	414	for (i = 0; i < IOAPIC_NUM_PINS; i++) {
	415	union kvm_ioapic_redirect_entry *ent = &ioapic->redirtbl[i];
1fd4f2a5	416
eba0226b GN	417	if (ent->fields.vector != vector)
eba0226b GN	418	continue;
1fd4f2a5	419
2c2bf011 YZ	420	if (i == RTC_GSI)
2c2bf011 YZ	421	rtc_irq_eoi(ioapic, vcpu);
eba0226b GN	422	/*
	423	* We are dropping lock while calling ack notifiers because ack
	424	* notifier callbacks for assigned devices call into IOAPIC
	425	* recursively. Since remote_irr is cleared only after call
	426	* to notifiers if the same vector will be delivered while lock
	427	* is dropped it will be put into irr and will be delivered
	428	* after ack notifier returns.
	429	*/
46a47b1e	430	spin_unlock(&ioapic->lock);
eba0226b	431	kvm_notify_acked_irq(ioapic->kvm, KVM_IRQCHIP_IOAPIC, i);
46a47b1e	432	spin_lock(&ioapic->lock);
eba0226b	433
c806a6ad RK	434	if (trigger_mode != IOAPIC_LEVEL_TRIG \|\|
c806a6ad RK	435	kvm_apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI)
eba0226b	436	continue;
f5244726	437
f5244726 MT	438	ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG);
f5244726 MT	439	ent->fields.remote_irr = 0;
184564ef ZH	440	if (!ent->fields.mask && (ioapic->irr & (1 << i))) {
	441	++ioapic->irq_eoi[i];
	442	if (ioapic->irq_eoi[i] == IOAPIC_SUCCESSIVE_IRQ_MAX_COUNT) {
	443	/*
	444	* Real hardware does not deliver the interrupt
	445	* immediately during eoi broadcast, and this
	446	* lets a buggy guest make slow progress
	447	* even if it does not correctly handle a
	448	* level-triggered interrupt. Emulate this
	449	* behavior if we detect an interrupt storm.
	450	*/
	451	schedule_delayed_work(&ioapic->eoi_inject, HZ / 100);
	452	ioapic->irq_eoi[i] = 0;
	453	trace_kvm_ioapic_delayed_eoi_inj(ent->bits);
	454	} else {
	455	ioapic_service(ioapic, i, false);
	456	}
	457	} else {
	458	ioapic->irq_eoi[i] = 0;
	459	}
f5244726	460	}
1fd4f2a5 ED	461	}
1fd4f2a5 ED	462
1fcc7890	463	void kvm_ioapic_update_eoi(struct kvm_vcpu *vcpu, int vector, int trigger_mode)
4fa6b9c5	464	{
1fcc7890	465	struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic;
4fa6b9c5	466
46a47b1e	467	spin_lock(&ioapic->lock);
1fcc7890	468	__kvm_ioapic_update_eoi(vcpu, ioapic, vector, trigger_mode);
46a47b1e	469	spin_unlock(&ioapic->lock);
4fa6b9c5 AK	470	}
4fa6b9c5 AK	471
d76685c4 GH	472	static inline struct kvm_ioapic to_ioapic(struct kvm_io_device dev)
	473	{
	474	return container_of(dev, struct kvm_ioapic, dev);
	475	}
	476
bda9020e	477	static inline int ioapic_in_range(struct kvm_ioapic *ioapic, gpa_t addr)
1fd4f2a5	478	{
1fd4f2a5 ED	479	return ((addr >= ioapic->base_address &&
	480	(addr < ioapic->base_address + IOAPIC_MEM_LENGTH)));
	481	}
	482
e32edf4f NN	483	static int ioapic_mmio_read(struct kvm_vcpu vcpu, struct kvm_io_device this,
e32edf4f NN	484	gpa_t addr, int len, void *val)
1fd4f2a5	485	{
d76685c4	486	struct kvm_ioapic *ioapic = to_ioapic(this);
1fd4f2a5	487	u32 result;
bda9020e MT	488	if (!ioapic_in_range(ioapic, addr))
bda9020e MT	489	return -EOPNOTSUPP;
1fd4f2a5	490
e25e3ed5	491	ioapic_debug("addr %lx\n", (unsigned long)addr);
1fd4f2a5 ED	492	ASSERT(!(addr & 0xf)); /* check alignment */
	493
	494	addr &= 0xff;
46a47b1e	495	spin_lock(&ioapic->lock);
1fd4f2a5 ED	496	switch (addr) {
	497	case IOAPIC_REG_SELECT:
	498	result = ioapic->ioregsel;
	499	break;
	500
	501	case IOAPIC_REG_WINDOW:
	502	result = ioapic_read_indirect(ioapic, addr, len);
	503	break;
	504
	505	default:
	506	result = 0;
	507	break;
	508	}
46a47b1e	509	spin_unlock(&ioapic->lock);
eba0226b	510
1fd4f2a5 ED	511	switch (len) {
	512	case 8:
	513	(u64 ) val = result;
	514	break;
	515	case 1:
	516	case 2:
	517	case 4:
	518	memcpy(val, (char *)&result, len);
	519	break;
	520	default:
	521	printk(KERN_WARNING "ioapic: wrong length %d\n", len);
	522	}
bda9020e	523	return 0;
1fd4f2a5 ED	524	}
1fd4f2a5 ED	525
e32edf4f NN	526	static int ioapic_mmio_write(struct kvm_vcpu vcpu, struct kvm_io_device this,
e32edf4f NN	527	gpa_t addr, int len, const void *val)
1fd4f2a5	528	{
d76685c4	529	struct kvm_ioapic *ioapic = to_ioapic(this);
1fd4f2a5	530	u32 data;
bda9020e MT	531	if (!ioapic_in_range(ioapic, addr))
bda9020e MT	532	return -EOPNOTSUPP;
1fd4f2a5	533
e25e3ed5 LV	534	ioapic_debug("ioapic_mmio_write addr=%p len=%d val=%p\n",
e25e3ed5 LV	535	(void*)addr, len, val);
1fd4f2a5	536	ASSERT(!(addr & 0xf)); /* check alignment */
60eead79	537
d77fe635 JS	538	switch (len) {
	539	case 8:
	540	case 4:
1fd4f2a5	541	data = (u32 ) val;
d77fe635 JS	542	break;
	543	case 2:
	544	data = (u16 ) val;
	545	break;
	546	case 1:
	547	data = (u8 ) val;
	548	break;
	549	default:
1fd4f2a5	550	printk(KERN_WARNING "ioapic: Unsupported size %d\n", len);
eba0226b	551	return 0;
1fd4f2a5 ED	552	}
	553
	554	addr &= 0xff;
46a47b1e	555	spin_lock(&ioapic->lock);
1fd4f2a5 ED	556	switch (addr) {
1fd4f2a5 ED	557	case IOAPIC_REG_SELECT:
d77fe635	558	ioapic->ioregsel = data & 0xFF; /* 8-bit register */
1fd4f2a5 ED	559	break;
	560
	561	case IOAPIC_REG_WINDOW:
	562	ioapic_write_indirect(ioapic, data);
	563	break;
	564
	565	default:
	566	break;
	567	}
46a47b1e	568	spin_unlock(&ioapic->lock);
bda9020e	569	return 0;
1fd4f2a5 ED	570	}
1fd4f2a5 ED	571
7940876e	572	static void kvm_ioapic_reset(struct kvm_ioapic *ioapic)
8c392696 ED	573	{
	574	int i;
	575
184564ef	576	cancel_delayed_work_sync(&ioapic->eoi_inject);
8c392696 ED	577	for (i = 0; i < IOAPIC_NUM_PINS; i++)
	578	ioapic->redirtbl[i].fields.mask = 1;
	579	ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
	580	ioapic->ioregsel = 0;
	581	ioapic->irr = 0;
5bda6eed	582	ioapic->irr_delivered = 0;
8c392696	583	ioapic->id = 0;
184564ef	584	memset(ioapic->irq_eoi, 0x00, IOAPIC_NUM_PINS);
10606919	585	rtc_irq_eoi_tracking_reset(ioapic);
8c392696 ED	586	}
8c392696 ED	587
d76685c4 GH	588	static const struct kvm_io_device_ops ioapic_mmio_ops = {
	589	.read = ioapic_mmio_read,
	590	.write = ioapic_mmio_write,
d76685c4 GH	591	};
d76685c4 GH	592
1fd4f2a5 ED	593	int kvm_ioapic_init(struct kvm *kvm)
	594	{
	595	struct kvm_ioapic *ioapic;
090b7aff	596	int ret;
1fd4f2a5 ED	597
	598	ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL);
	599	if (!ioapic)
	600	return -ENOMEM;
46a47b1e	601	spin_lock_init(&ioapic->lock);
184564ef	602	INIT_DELAYED_WORK(&ioapic->eoi_inject, kvm_ioapic_eoi_inject_work);
d7deeeb0	603	kvm->arch.vioapic = ioapic;
8c392696	604	kvm_ioapic_reset(ioapic);
d76685c4	605	kvm_iodevice_init(&ioapic->dev, &ioapic_mmio_ops);
1fd4f2a5	606	ioapic->kvm = kvm;
79fac95e	607	mutex_lock(&kvm->slots_lock);
743eeb0b SL	608	ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, ioapic->base_address,
743eeb0b SL	609	IOAPIC_MEM_LENGTH, &ioapic->dev);
79fac95e	610	mutex_unlock(&kvm->slots_lock);
1ae77bad WY	611	if (ret < 0) {
1ae77bad WY	612	kvm->arch.vioapic = NULL;
090b7aff	613	kfree(ioapic);
3bb345f3	614	return ret;
1ae77bad	615	}
090b7aff	616
3bb345f3	617	kvm_vcpu_request_scan_ioapic(kvm);
090b7aff	618	return ret;
1fd4f2a5	619	}
75858a84	620
72bb2fcd WY	621	void kvm_ioapic_destroy(struct kvm *kvm)
	622	{
	623	struct kvm_ioapic *ioapic = kvm->arch.vioapic;
	624
184564ef	625	cancel_delayed_work_sync(&ioapic->eoi_inject);
d90e3a35 JL	626	kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS, &ioapic->dev);
	627	kvm->arch.vioapic = NULL;
	628	kfree(ioapic);
72bb2fcd WY	629	}
72bb2fcd WY	630
eba0226b GN	631	int kvm_get_ioapic(struct kvm kvm, struct kvm_ioapic_state state)
	632	{
	633	struct kvm_ioapic *ioapic = ioapic_irqchip(kvm);
	634	if (!ioapic)
	635	return -EINVAL;
	636
46a47b1e	637	spin_lock(&ioapic->lock);
eba0226b	638	memcpy(state, ioapic, sizeof(struct kvm_ioapic_state));
5bda6eed	639	state->irr &= ~ioapic->irr_delivered;
46a47b1e	640	spin_unlock(&ioapic->lock);
eba0226b GN	641	return 0;
	642	}
	643
	644	int kvm_set_ioapic(struct kvm kvm, struct kvm_ioapic_state state)
	645	{
	646	struct kvm_ioapic *ioapic = ioapic_irqchip(kvm);
	647	if (!ioapic)
	648	return -EINVAL;
	649
46a47b1e	650	spin_lock(&ioapic->lock);
eba0226b	651	memcpy(ioapic, state, sizeof(struct kvm_ioapic_state));
673f7b42	652	ioapic->irr = 0;
5bda6eed	653	ioapic->irr_delivered = 0;
3d81bc7e	654	kvm_vcpu_request_scan_ioapic(kvm);
673f7b42	655	kvm_ioapic_inject_all(ioapic, state->irr);
46a47b1e	656	spin_unlock(&ioapic->lock);
eba0226b GN	657	return 0;
eba0226b GN	658	}