Commit | Line | Data |
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1fd4f2a5 ED |
1 | /* |
2 | * Copyright (C) 2001 MandrakeSoft S.A. | |
221d059d | 3 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
1fd4f2a5 ED |
4 | * |
5 | * MandrakeSoft S.A. | |
6 | * 43, rue d'Aboukir | |
7 | * 75002 Paris - France | |
8 | * http://www.linux-mandrake.com/ | |
9 | * http://www.mandrakesoft.com/ | |
10 | * | |
11 | * This library is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU Lesser General Public | |
13 | * License as published by the Free Software Foundation; either | |
14 | * version 2 of the License, or (at your option) any later version. | |
15 | * | |
16 | * This library is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
19 | * Lesser General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU Lesser General Public | |
22 | * License along with this library; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
24 | * | |
25 | * Yunhong Jiang <yunhong.jiang@intel.com> | |
26 | * Yaozu (Eddie) Dong <eddie.dong@intel.com> | |
27 | * Based on Xen 3.1 code. | |
28 | */ | |
8d20bd63 | 29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
1fd4f2a5 | 30 | |
edf88417 | 31 | #include <linux/kvm_host.h> |
1fd4f2a5 ED |
32 | #include <linux/kvm.h> |
33 | #include <linux/mm.h> | |
34 | #include <linux/highmem.h> | |
35 | #include <linux/smp.h> | |
36 | #include <linux/hrtimer.h> | |
37 | #include <linux/io.h> | |
5a0e3ad6 | 38 | #include <linux/slab.h> |
c7c9c56c | 39 | #include <linux/export.h> |
8c86405f | 40 | #include <linux/nospec.h> |
1fd4f2a5 | 41 | #include <asm/processor.h> |
1fd4f2a5 ED |
42 | #include <asm/page.h> |
43 | #include <asm/current.h> | |
1000ff8d | 44 | #include <trace/events/kvm.h> |
82470196 ZX |
45 | |
46 | #include "ioapic.h" | |
47 | #include "lapic.h" | |
f5244726 | 48 | #include "irq.h" |
82470196 | 49 | |
0b10a1c8 | 50 | static int ioapic_service(struct kvm_ioapic *vioapic, int irq, |
aa2fbe6d | 51 | bool line_status); |
1fd4f2a5 | 52 | |
f458d039 SS |
53 | static void kvm_ioapic_update_eoi_one(struct kvm_vcpu *vcpu, |
54 | struct kvm_ioapic *ioapic, | |
55 | int trigger_mode, | |
56 | int pin); | |
57 | ||
019024e5 | 58 | static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic) |
1fd4f2a5 ED |
59 | { |
60 | unsigned long result = 0; | |
61 | ||
62 | switch (ioapic->ioregsel) { | |
63 | case IOAPIC_REG_VERSION: | |
64 | result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16) | |
65 | | (IOAPIC_VERSION_ID & 0xff)); | |
66 | break; | |
67 | ||
68 | case IOAPIC_REG_APIC_ID: | |
69 | case IOAPIC_REG_ARB_ID: | |
70 | result = ((ioapic->id & 0xf) << 24); | |
71 | break; | |
72 | ||
73 | default: | |
74 | { | |
75 | u32 redir_index = (ioapic->ioregsel - 0x10) >> 1; | |
8c86405f | 76 | u64 redir_content = ~0ULL; |
1fd4f2a5 | 77 | |
8c86405f MP |
78 | if (redir_index < IOAPIC_NUM_PINS) { |
79 | u32 index = array_index_nospec( | |
80 | redir_index, IOAPIC_NUM_PINS); | |
81 | ||
82 | redir_content = ioapic->redirtbl[index].bits; | |
83 | } | |
1fd4f2a5 | 84 | |
1fd4f2a5 ED |
85 | result = (ioapic->ioregsel & 0x1) ? |
86 | (redir_content >> 32) & 0xffffffff : | |
87 | redir_content & 0xffffffff; | |
88 | break; | |
89 | } | |
90 | } | |
91 | ||
92 | return result; | |
93 | } | |
94 | ||
10606919 YZ |
95 | static void rtc_irq_eoi_tracking_reset(struct kvm_ioapic *ioapic) |
96 | { | |
97 | ioapic->rtc_status.pending_eoi = 0; | |
a1c42dde | 98 | bitmap_zero(ioapic->rtc_status.dest_map.map, KVM_MAX_VCPU_IDS); |
10606919 YZ |
99 | } |
100 | ||
4009b249 PB |
101 | static void kvm_rtc_eoi_tracking_restore_all(struct kvm_ioapic *ioapic); |
102 | ||
103 | static void rtc_status_pending_eoi_check_valid(struct kvm_ioapic *ioapic) | |
104 | { | |
105 | if (WARN_ON(ioapic->rtc_status.pending_eoi < 0)) | |
106 | kvm_rtc_eoi_tracking_restore_all(ioapic); | |
107 | } | |
108 | ||
10606919 YZ |
109 | static void __rtc_irq_eoi_tracking_restore_one(struct kvm_vcpu *vcpu) |
110 | { | |
111 | bool new_val, old_val; | |
112 | struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic; | |
b0eaf450 | 113 | struct dest_map *dest_map = &ioapic->rtc_status.dest_map; |
10606919 YZ |
114 | union kvm_ioapic_redirect_entry *e; |
115 | ||
116 | e = &ioapic->redirtbl[RTC_GSI]; | |
5c69d5c1 PX |
117 | if (!kvm_apic_match_dest(vcpu, NULL, APIC_DEST_NOSHORT, |
118 | e->fields.dest_id, | |
119 | kvm_lapic_irq_dest_mode(!!e->fields.dest_mode))) | |
10606919 YZ |
120 | return; |
121 | ||
122 | new_val = kvm_apic_pending_eoi(vcpu, e->fields.vector); | |
b0eaf450 | 123 | old_val = test_bit(vcpu->vcpu_id, dest_map->map); |
10606919 YZ |
124 | |
125 | if (new_val == old_val) | |
126 | return; | |
127 | ||
128 | if (new_val) { | |
b0eaf450 PB |
129 | __set_bit(vcpu->vcpu_id, dest_map->map); |
130 | dest_map->vectors[vcpu->vcpu_id] = e->fields.vector; | |
10606919 YZ |
131 | ioapic->rtc_status.pending_eoi++; |
132 | } else { | |
b0eaf450 | 133 | __clear_bit(vcpu->vcpu_id, dest_map->map); |
10606919 | 134 | ioapic->rtc_status.pending_eoi--; |
4009b249 | 135 | rtc_status_pending_eoi_check_valid(ioapic); |
10606919 | 136 | } |
10606919 YZ |
137 | } |
138 | ||
139 | void kvm_rtc_eoi_tracking_restore_one(struct kvm_vcpu *vcpu) | |
140 | { | |
141 | struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic; | |
142 | ||
143 | spin_lock(&ioapic->lock); | |
144 | __rtc_irq_eoi_tracking_restore_one(vcpu); | |
145 | spin_unlock(&ioapic->lock); | |
146 | } | |
147 | ||
148 | static void kvm_rtc_eoi_tracking_restore_all(struct kvm_ioapic *ioapic) | |
149 | { | |
150 | struct kvm_vcpu *vcpu; | |
46808a4c | 151 | unsigned long i; |
10606919 YZ |
152 | |
153 | if (RTC_GSI >= IOAPIC_NUM_PINS) | |
154 | return; | |
155 | ||
156 | rtc_irq_eoi_tracking_reset(ioapic); | |
157 | kvm_for_each_vcpu(i, vcpu, ioapic->kvm) | |
158 | __rtc_irq_eoi_tracking_restore_one(vcpu); | |
159 | } | |
160 | ||
1ec2405c SS |
161 | static void rtc_irq_eoi(struct kvm_ioapic *ioapic, struct kvm_vcpu *vcpu, |
162 | int vector) | |
2c2bf011 | 163 | { |
1ec2405c SS |
164 | struct dest_map *dest_map = &ioapic->rtc_status.dest_map; |
165 | ||
166 | /* RTC special handling */ | |
167 | if (test_bit(vcpu->vcpu_id, dest_map->map) && | |
168 | (vector == dest_map->vectors[vcpu->vcpu_id]) && | |
169 | (test_and_clear_bit(vcpu->vcpu_id, | |
170 | ioapic->rtc_status.dest_map.map))) { | |
2c2bf011 | 171 | --ioapic->rtc_status.pending_eoi; |
4009b249 PB |
172 | rtc_status_pending_eoi_check_valid(ioapic); |
173 | } | |
2c2bf011 YZ |
174 | } |
175 | ||
176 | static bool rtc_irq_check_coalesced(struct kvm_ioapic *ioapic) | |
177 | { | |
178 | if (ioapic->rtc_status.pending_eoi > 0) | |
179 | return true; /* coalesced */ | |
180 | ||
181 | return false; | |
182 | } | |
183 | ||
f458d039 SS |
184 | static void ioapic_lazy_update_eoi(struct kvm_ioapic *ioapic, int irq) |
185 | { | |
46808a4c | 186 | unsigned long i; |
f458d039 SS |
187 | struct kvm_vcpu *vcpu; |
188 | union kvm_ioapic_redirect_entry *entry = &ioapic->redirtbl[irq]; | |
189 | ||
190 | kvm_for_each_vcpu(i, vcpu, ioapic->kvm) { | |
191 | if (!kvm_apic_match_dest(vcpu, NULL, APIC_DEST_NOSHORT, | |
192 | entry->fields.dest_id, | |
193 | entry->fields.dest_mode) || | |
194 | kvm_apic_pending_eoi(vcpu, entry->fields.vector)) | |
195 | continue; | |
196 | ||
197 | /* | |
198 | * If no longer has pending EOI in LAPICs, update | |
77377064 | 199 | * EOI for this vector. |
f458d039 SS |
200 | */ |
201 | rtc_irq_eoi(ioapic, vcpu, entry->fields.vector); | |
f458d039 SS |
202 | break; |
203 | } | |
204 | } | |
205 | ||
44847dea PB |
206 | static int ioapic_set_irq(struct kvm_ioapic *ioapic, unsigned int irq, |
207 | int irq_level, bool line_status) | |
208 | { | |
209 | union kvm_ioapic_redirect_entry entry; | |
210 | u32 mask = 1 << irq; | |
211 | u32 old_irr; | |
212 | int edge, ret; | |
213 | ||
214 | entry = ioapic->redirtbl[irq]; | |
215 | edge = (entry.fields.trig_mode == IOAPIC_EDGE_TRIG); | |
216 | ||
217 | if (!irq_level) { | |
218 | ioapic->irr &= ~mask; | |
219 | ret = 1; | |
220 | goto out; | |
221 | } | |
222 | ||
f458d039 | 223 | /* |
8be8f932 PB |
224 | * AMD SVM AVIC accelerate EOI write iff the interrupt is edge |
225 | * triggered, in which case the in-kernel IOAPIC will not be able | |
226 | * to receive the EOI. In this case, we do a lazy update of the | |
227 | * pending EOI when trying to set IOAPIC irq. | |
f458d039 | 228 | */ |
8be8f932 | 229 | if (edge && kvm_apicv_activated(ioapic->kvm)) |
f458d039 SS |
230 | ioapic_lazy_update_eoi(ioapic, irq); |
231 | ||
44847dea PB |
232 | /* |
233 | * Return 0 for coalesced interrupts; for edge-triggered interrupts, | |
234 | * this only happens if a previous edge has not been delivered due | |
00116795 | 235 | * to masking. For level interrupts, the remote_irr field tells |
44847dea PB |
236 | * us if the interrupt is waiting for an EOI. |
237 | * | |
238 | * RTC is special: it is edge-triggered, but userspace likes to know | |
239 | * if it has been already ack-ed via EOI because coalesced RTC | |
240 | * interrupts lead to time drift in Windows guests. So we track | |
241 | * EOI manually for the RTC interrupt. | |
242 | */ | |
243 | if (irq == RTC_GSI && line_status && | |
244 | rtc_irq_check_coalesced(ioapic)) { | |
245 | ret = 0; | |
246 | goto out; | |
247 | } | |
248 | ||
249 | old_irr = ioapic->irr; | |
250 | ioapic->irr |= mask; | |
7d225368 | 251 | if (edge) { |
5bda6eed | 252 | ioapic->irr_delivered &= ~mask; |
7d225368 NL |
253 | if (old_irr == ioapic->irr) { |
254 | ret = 0; | |
255 | goto out; | |
256 | } | |
44847dea PB |
257 | } |
258 | ||
259 | ret = ioapic_service(ioapic, irq, line_status); | |
260 | ||
261 | out: | |
262 | trace_kvm_ioapic_set_irq(entry.bits, irq, ret == 0); | |
263 | return ret; | |
264 | } | |
265 | ||
673f7b42 PB |
266 | static void kvm_ioapic_inject_all(struct kvm_ioapic *ioapic, unsigned long irr) |
267 | { | |
268 | u32 idx; | |
269 | ||
270 | rtc_irq_eoi_tracking_reset(ioapic); | |
271 | for_each_set_bit(idx, &irr, IOAPIC_NUM_PINS) | |
272 | ioapic_set_irq(ioapic, idx, 1, true); | |
273 | ||
274 | kvm_rtc_eoi_tracking_restore_all(ioapic); | |
275 | } | |
276 | ||
277 | ||
6308630b | 278 | void kvm_ioapic_scan_entry(struct kvm_vcpu *vcpu, ulong *ioapic_handled_vectors) |
c7c9c56c YZ |
279 | { |
280 | struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic; | |
4d99ba89 | 281 | struct dest_map *dest_map = &ioapic->rtc_status.dest_map; |
c7c9c56c | 282 | union kvm_ioapic_redirect_entry *e; |
c7c9c56c YZ |
283 | int index; |
284 | ||
285 | spin_lock(&ioapic->lock); | |
4d99ba89 JR |
286 | |
287 | /* Make sure we see any missing RTC EOI */ | |
288 | if (test_bit(vcpu->vcpu_id, dest_map->map)) | |
289 | __set_bit(dest_map->vectors[vcpu->vcpu_id], | |
290 | ioapic_handled_vectors); | |
291 | ||
c7c9c56c YZ |
292 | for (index = 0; index < IOAPIC_NUM_PINS; index++) { |
293 | e = &ioapic->redirtbl[index]; | |
0f6c0a74 PB |
294 | if (e->fields.trig_mode == IOAPIC_LEVEL_TRIG || |
295 | kvm_irq_has_notifier(ioapic->kvm, KVM_IRQCHIP_IOAPIC, index) || | |
296 | index == RTC_GSI) { | |
5c69d5c1 PX |
297 | u16 dm = kvm_lapic_irq_dest_mode(!!e->fields.dest_mode); |
298 | ||
299 | if (kvm_apic_match_dest(vcpu, NULL, APIC_DEST_NOSHORT, | |
300 | e->fields.dest_id, dm) || | |
0fc5a36d | 301 | kvm_apic_pending_eoi(vcpu, e->fields.vector)) |
cf9e65b7 | 302 | __set_bit(e->fields.vector, |
6308630b | 303 | ioapic_handled_vectors); |
c7c9c56c YZ |
304 | } |
305 | } | |
306 | spin_unlock(&ioapic->lock); | |
307 | } | |
c7c9c56c | 308 | |
993225ad | 309 | void kvm_arch_post_irq_ack_notifier_list_update(struct kvm *kvm) |
c7c9c56c | 310 | { |
0bceb15a | 311 | if (!ioapic_in_kernel(kvm)) |
c7c9c56c | 312 | return; |
3d81bc7e | 313 | kvm_make_scan_ioapic_request(kvm); |
c7c9c56c YZ |
314 | } |
315 | ||
1fd4f2a5 ED |
316 | static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val) |
317 | { | |
318 | unsigned index; | |
75858a84 | 319 | bool mask_before, mask_after; |
70f93dae | 320 | union kvm_ioapic_redirect_entry *e; |
7ee30bc1 | 321 | int old_remote_irr, old_delivery_status, old_dest_id, old_dest_mode; |
2f9b68f5 | 322 | DECLARE_BITMAP(vcpu_bitmap, KVM_MAX_VCPUS); |
1fd4f2a5 ED |
323 | |
324 | switch (ioapic->ioregsel) { | |
325 | case IOAPIC_REG_VERSION: | |
326 | /* Writes are ignored. */ | |
327 | break; | |
328 | ||
329 | case IOAPIC_REG_APIC_ID: | |
330 | ioapic->id = (val >> 24) & 0xf; | |
331 | break; | |
332 | ||
333 | case IOAPIC_REG_ARB_ID: | |
334 | break; | |
335 | ||
336 | default: | |
337 | index = (ioapic->ioregsel - 0x10) >> 1; | |
338 | ||
1fd4f2a5 ED |
339 | if (index >= IOAPIC_NUM_PINS) |
340 | return; | |
67056455 | 341 | index = array_index_nospec(index, IOAPIC_NUM_PINS); |
70f93dae GN |
342 | e = &ioapic->redirtbl[index]; |
343 | mask_before = e->fields.mask; | |
b200dded NL |
344 | /* Preserve read-only fields */ |
345 | old_remote_irr = e->fields.remote_irr; | |
346 | old_delivery_status = e->fields.delivery_status; | |
7ee30bc1 NNL |
347 | old_dest_id = e->fields.dest_id; |
348 | old_dest_mode = e->fields.dest_mode; | |
1fd4f2a5 | 349 | if (ioapic->ioregsel & 1) { |
70f93dae GN |
350 | e->bits &= 0xffffffff; |
351 | e->bits |= (u64) val << 32; | |
1fd4f2a5 | 352 | } else { |
70f93dae GN |
353 | e->bits &= ~0xffffffffULL; |
354 | e->bits |= (u32) val; | |
1fd4f2a5 | 355 | } |
b200dded NL |
356 | e->fields.remote_irr = old_remote_irr; |
357 | e->fields.delivery_status = old_delivery_status; | |
a8bfec29 NL |
358 | |
359 | /* | |
360 | * Some OSes (Linux, Xen) assume that Remote IRR bit will | |
361 | * be cleared by IOAPIC hardware when the entry is configured | |
362 | * as edge-triggered. This behavior is used to simulate an | |
363 | * explicit EOI on IOAPICs that don't have the EOI register. | |
364 | */ | |
365 | if (e->fields.trig_mode == IOAPIC_EDGE_TRIG) | |
366 | e->fields.remote_irr = 0; | |
367 | ||
70f93dae | 368 | mask_after = e->fields.mask; |
75858a84 | 369 | if (mask_before != mask_after) |
4a994358 | 370 | kvm_fire_mask_notifiers(ioapic->kvm, KVM_IRQCHIP_IOAPIC, index, mask_after); |
fef8f2b9 DM |
371 | if (e->fields.trig_mode == IOAPIC_LEVEL_TRIG && |
372 | ioapic->irr & (1 << index) && !e->fields.mask && !e->fields.remote_irr) { | |
373 | /* | |
374 | * Pending status in irr may be outdated: the IRQ line may have | |
375 | * already been deasserted by a device while the IRQ was masked. | |
376 | * This occurs, for instance, if the interrupt is handled in a | |
377 | * Linux guest as a oneshot interrupt (IRQF_ONESHOT). In this | |
378 | * case the guest acknowledges the interrupt to the device in | |
379 | * its threaded irq handler, i.e. after the EOI but before | |
380 | * unmasking, so at the time of unmasking the IRQ line is | |
381 | * already down but our pending irr bit is still set. In such | |
382 | * cases, injecting this pending interrupt to the guest is | |
383 | * buggy: the guest will receive an extra unwanted interrupt. | |
384 | * | |
385 | * So we need to check here if the IRQ is actually still pending. | |
386 | * As we are generally not able to probe the IRQ line status | |
387 | * directly, we do it through irqfd resampler. Namely, we clear | |
388 | * the pending status and notify the resampler that this interrupt | |
389 | * is done, without actually injecting it into the guest. If the | |
390 | * IRQ line is actually already deasserted, we are done. If it is | |
391 | * still asserted, a new interrupt will be shortly triggered | |
392 | * through irqfd and injected into the guest. | |
393 | * | |
394 | * If, however, it's not possible to resample (no irqfd resampler | |
395 | * registered for this irq), then unconditionally inject this | |
396 | * pending interrupt into the guest, so the guest will not miss | |
397 | * an interrupt, although may get an extra unwanted interrupt. | |
398 | */ | |
399 | if (kvm_notify_irqfd_resampler(ioapic->kvm, KVM_IRQCHIP_IOAPIC, index)) | |
400 | ioapic->irr &= ~(1 << index); | |
401 | else | |
402 | ioapic_service(ioapic, index, false); | |
403 | } | |
7ee30bc1 NNL |
404 | if (e->fields.delivery_mode == APIC_DM_FIXED) { |
405 | struct kvm_lapic_irq irq; | |
406 | ||
7ee30bc1 NNL |
407 | irq.vector = e->fields.vector; |
408 | irq.delivery_mode = e->fields.delivery_mode << 8; | |
c96001c5 PX |
409 | irq.dest_mode = |
410 | kvm_lapic_irq_dest_mode(!!e->fields.dest_mode); | |
0c22056f NNL |
411 | irq.level = false; |
412 | irq.trig_mode = e->fields.trig_mode; | |
413 | irq.shorthand = APIC_DEST_NOSHORT; | |
414 | irq.dest_id = e->fields.dest_id; | |
415 | irq.msi_redir_hint = false; | |
2f9b68f5 | 416 | bitmap_zero(vcpu_bitmap, KVM_MAX_VCPUS); |
7ee30bc1 | 417 | kvm_bitmap_or_dest_vcpus(ioapic->kvm, &irq, |
2f9b68f5 | 418 | vcpu_bitmap); |
7ee30bc1 NNL |
419 | if (old_dest_mode != e->fields.dest_mode || |
420 | old_dest_id != e->fields.dest_id) { | |
421 | /* | |
422 | * Update vcpu_bitmap with vcpus specified in | |
423 | * the previous request as well. This is done to | |
424 | * keep ioapic_handled_vectors synchronized. | |
425 | */ | |
426 | irq.dest_id = old_dest_id; | |
c96001c5 PX |
427 | irq.dest_mode = |
428 | kvm_lapic_irq_dest_mode( | |
429 | !!e->fields.dest_mode); | |
7ee30bc1 | 430 | kvm_bitmap_or_dest_vcpus(ioapic->kvm, &irq, |
2f9b68f5 | 431 | vcpu_bitmap); |
7ee30bc1 NNL |
432 | } |
433 | kvm_make_scan_ioapic_request_mask(ioapic->kvm, | |
2f9b68f5 | 434 | vcpu_bitmap); |
7ee30bc1 NNL |
435 | } else { |
436 | kvm_make_scan_ioapic_request(ioapic->kvm); | |
437 | } | |
1fd4f2a5 ED |
438 | break; |
439 | } | |
440 | } | |
441 | ||
0b10a1c8 | 442 | static int ioapic_service(struct kvm_ioapic *ioapic, int irq, bool line_status) |
a53c17d2 | 443 | { |
58c2dde1 GN |
444 | union kvm_ioapic_redirect_entry *entry = &ioapic->redirtbl[irq]; |
445 | struct kvm_lapic_irq irqe; | |
2c2bf011 | 446 | int ret; |
a53c17d2 | 447 | |
da3fe7bd NL |
448 | if (entry->fields.mask || |
449 | (entry->fields.trig_mode == IOAPIC_LEVEL_TRIG && | |
450 | entry->fields.remote_irr)) | |
0b10a1c8 PB |
451 | return -1; |
452 | ||
58c2dde1 GN |
453 | irqe.dest_id = entry->fields.dest_id; |
454 | irqe.vector = entry->fields.vector; | |
c96001c5 | 455 | irqe.dest_mode = kvm_lapic_irq_dest_mode(!!entry->fields.dest_mode); |
58c2dde1 GN |
456 | irqe.trig_mode = entry->fields.trig_mode; |
457 | irqe.delivery_mode = entry->fields.delivery_mode << 8; | |
458 | irqe.level = 1; | |
150a84fe | 459 | irqe.shorthand = APIC_DEST_NOSHORT; |
93bbf0b8 | 460 | irqe.msi_redir_hint = false; |
a53c17d2 | 461 | |
0bc830b0 | 462 | if (irqe.trig_mode == IOAPIC_EDGE_TRIG) |
5bda6eed | 463 | ioapic->irr_delivered |= 1 << irq; |
0bc830b0 | 464 | |
2c2bf011 | 465 | if (irq == RTC_GSI && line_status) { |
4009b249 PB |
466 | /* |
467 | * pending_eoi cannot ever become negative (see | |
468 | * rtc_status_pending_eoi_check_valid) and the caller | |
469 | * ensures that it is only called if it is >= zero, namely | |
470 | * if rtc_irq_check_coalesced returns false). | |
471 | */ | |
2c2bf011 YZ |
472 | BUG_ON(ioapic->rtc_status.pending_eoi != 0); |
473 | ret = kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe, | |
9e4aabe2 | 474 | &ioapic->rtc_status.dest_map); |
5678de3f | 475 | ioapic->rtc_status.pending_eoi = (ret < 0 ? 0 : ret); |
2c2bf011 YZ |
476 | } else |
477 | ret = kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe, NULL); | |
478 | ||
0b10a1c8 PB |
479 | if (ret && irqe.trig_mode == IOAPIC_LEVEL_TRIG) |
480 | entry->fields.remote_irr = 1; | |
481 | ||
2c2bf011 | 482 | return ret; |
a53c17d2 GN |
483 | } |
484 | ||
1a577b72 | 485 | int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int irq_source_id, |
aa2fbe6d | 486 | int level, bool line_status) |
1fd4f2a5 | 487 | { |
28a6fdab MT |
488 | int ret, irq_level; |
489 | ||
490 | BUG_ON(irq < 0 || irq >= IOAPIC_NUM_PINS); | |
1fd4f2a5 | 491 | |
46a47b1e | 492 | spin_lock(&ioapic->lock); |
28a6fdab MT |
493 | irq_level = __kvm_irq_line_state(&ioapic->irq_states[irq], |
494 | irq_source_id, level); | |
44847dea | 495 | ret = ioapic_set_irq(ioapic, irq, irq_level, line_status); |
2c2bf011 | 496 | |
46a47b1e | 497 | spin_unlock(&ioapic->lock); |
eba0226b | 498 | |
4925663a | 499 | return ret; |
1fd4f2a5 ED |
500 | } |
501 | ||
1a577b72 MT |
502 | void kvm_ioapic_clear_all(struct kvm_ioapic *ioapic, int irq_source_id) |
503 | { | |
504 | int i; | |
505 | ||
506 | spin_lock(&ioapic->lock); | |
507 | for (i = 0; i < KVM_IOAPIC_NUM_PINS; i++) | |
508 | __clear_bit(irq_source_id, &ioapic->irq_states[i]); | |
509 | spin_unlock(&ioapic->lock); | |
510 | } | |
511 | ||
184564ef ZH |
512 | static void kvm_ioapic_eoi_inject_work(struct work_struct *work) |
513 | { | |
514 | int i; | |
515 | struct kvm_ioapic *ioapic = container_of(work, struct kvm_ioapic, | |
516 | eoi_inject.work); | |
517 | spin_lock(&ioapic->lock); | |
518 | for (i = 0; i < IOAPIC_NUM_PINS; i++) { | |
519 | union kvm_ioapic_redirect_entry *ent = &ioapic->redirtbl[i]; | |
520 | ||
521 | if (ent->fields.trig_mode != IOAPIC_LEVEL_TRIG) | |
522 | continue; | |
523 | ||
524 | if (ioapic->irr & (1 << i) && !ent->fields.remote_irr) | |
525 | ioapic_service(ioapic, i, false); | |
526 | } | |
527 | spin_unlock(&ioapic->lock); | |
528 | } | |
529 | ||
530 | #define IOAPIC_SUCCESSIVE_IRQ_MAX_COUNT 10000 | |
1ec2405c SS |
531 | static void kvm_ioapic_update_eoi_one(struct kvm_vcpu *vcpu, |
532 | struct kvm_ioapic *ioapic, | |
533 | int trigger_mode, | |
534 | int pin) | |
1fd4f2a5 | 535 | { |
c806a6ad | 536 | struct kvm_lapic *apic = vcpu->arch.apic; |
1ec2405c | 537 | union kvm_ioapic_redirect_entry *ent = &ioapic->redirtbl[pin]; |
eba0226b | 538 | |
1ec2405c SS |
539 | /* |
540 | * We are dropping lock while calling ack notifiers because ack | |
541 | * notifier callbacks for assigned devices call into IOAPIC | |
542 | * recursively. Since remote_irr is cleared only after call | |
543 | * to notifiers if the same vector will be delivered while lock | |
544 | * is dropped it will be put into irr and will be delivered | |
545 | * after ack notifier returns. | |
546 | */ | |
547 | spin_unlock(&ioapic->lock); | |
548 | kvm_notify_acked_irq(ioapic->kvm, KVM_IRQCHIP_IOAPIC, pin); | |
549 | spin_lock(&ioapic->lock); | |
eba0226b | 550 | |
1ec2405c SS |
551 | if (trigger_mode != IOAPIC_LEVEL_TRIG || |
552 | kvm_lapic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI) | |
553 | return; | |
f5244726 | 554 | |
1ec2405c SS |
555 | ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG); |
556 | ent->fields.remote_irr = 0; | |
557 | if (!ent->fields.mask && (ioapic->irr & (1 << pin))) { | |
558 | ++ioapic->irq_eoi[pin]; | |
559 | if (ioapic->irq_eoi[pin] == IOAPIC_SUCCESSIVE_IRQ_MAX_COUNT) { | |
560 | /* | |
561 | * Real hardware does not deliver the interrupt | |
562 | * immediately during eoi broadcast, and this | |
563 | * lets a buggy guest make slow progress | |
564 | * even if it does not correctly handle a | |
565 | * level-triggered interrupt. Emulate this | |
566 | * behavior if we detect an interrupt storm. | |
567 | */ | |
568 | schedule_delayed_work(&ioapic->eoi_inject, HZ / 100); | |
569 | ioapic->irq_eoi[pin] = 0; | |
570 | trace_kvm_ioapic_delayed_eoi_inj(ent->bits); | |
184564ef | 571 | } else { |
1ec2405c | 572 | ioapic_service(ioapic, pin, false); |
184564ef | 573 | } |
1ec2405c SS |
574 | } else { |
575 | ioapic->irq_eoi[pin] = 0; | |
f5244726 | 576 | } |
1fd4f2a5 ED |
577 | } |
578 | ||
1fcc7890 | 579 | void kvm_ioapic_update_eoi(struct kvm_vcpu *vcpu, int vector, int trigger_mode) |
4fa6b9c5 | 580 | { |
1ec2405c | 581 | int i; |
1fcc7890 | 582 | struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic; |
4fa6b9c5 | 583 | |
46a47b1e | 584 | spin_lock(&ioapic->lock); |
1ec2405c SS |
585 | rtc_irq_eoi(ioapic, vcpu, vector); |
586 | for (i = 0; i < IOAPIC_NUM_PINS; i++) { | |
587 | union kvm_ioapic_redirect_entry *ent = &ioapic->redirtbl[i]; | |
588 | ||
589 | if (ent->fields.vector != vector) | |
590 | continue; | |
591 | kvm_ioapic_update_eoi_one(vcpu, ioapic, trigger_mode, i); | |
592 | } | |
46a47b1e | 593 | spin_unlock(&ioapic->lock); |
4fa6b9c5 AK |
594 | } |
595 | ||
d76685c4 GH |
596 | static inline struct kvm_ioapic *to_ioapic(struct kvm_io_device *dev) |
597 | { | |
598 | return container_of(dev, struct kvm_ioapic, dev); | |
599 | } | |
600 | ||
bda9020e | 601 | static inline int ioapic_in_range(struct kvm_ioapic *ioapic, gpa_t addr) |
1fd4f2a5 | 602 | { |
1fd4f2a5 ED |
603 | return ((addr >= ioapic->base_address && |
604 | (addr < ioapic->base_address + IOAPIC_MEM_LENGTH))); | |
605 | } | |
606 | ||
e32edf4f NN |
607 | static int ioapic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this, |
608 | gpa_t addr, int len, void *val) | |
1fd4f2a5 | 609 | { |
d76685c4 | 610 | struct kvm_ioapic *ioapic = to_ioapic(this); |
1fd4f2a5 | 611 | u32 result; |
bda9020e MT |
612 | if (!ioapic_in_range(ioapic, addr)) |
613 | return -EOPNOTSUPP; | |
1fd4f2a5 | 614 | |
1fd4f2a5 ED |
615 | ASSERT(!(addr & 0xf)); /* check alignment */ |
616 | ||
617 | addr &= 0xff; | |
46a47b1e | 618 | spin_lock(&ioapic->lock); |
1fd4f2a5 ED |
619 | switch (addr) { |
620 | case IOAPIC_REG_SELECT: | |
621 | result = ioapic->ioregsel; | |
622 | break; | |
623 | ||
624 | case IOAPIC_REG_WINDOW: | |
019024e5 | 625 | result = ioapic_read_indirect(ioapic); |
1fd4f2a5 ED |
626 | break; |
627 | ||
628 | default: | |
629 | result = 0; | |
630 | break; | |
631 | } | |
46a47b1e | 632 | spin_unlock(&ioapic->lock); |
eba0226b | 633 | |
1fd4f2a5 ED |
634 | switch (len) { |
635 | case 8: | |
636 | *(u64 *) val = result; | |
637 | break; | |
638 | case 1: | |
639 | case 2: | |
640 | case 4: | |
641 | memcpy(val, (char *)&result, len); | |
642 | break; | |
643 | default: | |
644 | printk(KERN_WARNING "ioapic: wrong length %d\n", len); | |
645 | } | |
bda9020e | 646 | return 0; |
1fd4f2a5 ED |
647 | } |
648 | ||
e32edf4f NN |
649 | static int ioapic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this, |
650 | gpa_t addr, int len, const void *val) | |
1fd4f2a5 | 651 | { |
d76685c4 | 652 | struct kvm_ioapic *ioapic = to_ioapic(this); |
1fd4f2a5 | 653 | u32 data; |
bda9020e MT |
654 | if (!ioapic_in_range(ioapic, addr)) |
655 | return -EOPNOTSUPP; | |
1fd4f2a5 | 656 | |
1fd4f2a5 | 657 | ASSERT(!(addr & 0xf)); /* check alignment */ |
60eead79 | 658 | |
d77fe635 JS |
659 | switch (len) { |
660 | case 8: | |
661 | case 4: | |
1fd4f2a5 | 662 | data = *(u32 *) val; |
d77fe635 JS |
663 | break; |
664 | case 2: | |
665 | data = *(u16 *) val; | |
666 | break; | |
667 | case 1: | |
668 | data = *(u8 *) val; | |
669 | break; | |
670 | default: | |
1fd4f2a5 | 671 | printk(KERN_WARNING "ioapic: Unsupported size %d\n", len); |
eba0226b | 672 | return 0; |
1fd4f2a5 ED |
673 | } |
674 | ||
675 | addr &= 0xff; | |
46a47b1e | 676 | spin_lock(&ioapic->lock); |
1fd4f2a5 ED |
677 | switch (addr) { |
678 | case IOAPIC_REG_SELECT: | |
d77fe635 | 679 | ioapic->ioregsel = data & 0xFF; /* 8-bit register */ |
1fd4f2a5 ED |
680 | break; |
681 | ||
682 | case IOAPIC_REG_WINDOW: | |
683 | ioapic_write_indirect(ioapic, data); | |
684 | break; | |
685 | ||
686 | default: | |
687 | break; | |
688 | } | |
46a47b1e | 689 | spin_unlock(&ioapic->lock); |
bda9020e | 690 | return 0; |
1fd4f2a5 ED |
691 | } |
692 | ||
7940876e | 693 | static void kvm_ioapic_reset(struct kvm_ioapic *ioapic) |
8c392696 ED |
694 | { |
695 | int i; | |
696 | ||
184564ef | 697 | cancel_delayed_work_sync(&ioapic->eoi_inject); |
8c392696 ED |
698 | for (i = 0; i < IOAPIC_NUM_PINS; i++) |
699 | ioapic->redirtbl[i].fields.mask = 1; | |
700 | ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS; | |
701 | ioapic->ioregsel = 0; | |
702 | ioapic->irr = 0; | |
5bda6eed | 703 | ioapic->irr_delivered = 0; |
8c392696 | 704 | ioapic->id = 0; |
8678654e | 705 | memset(ioapic->irq_eoi, 0x00, sizeof(ioapic->irq_eoi)); |
10606919 | 706 | rtc_irq_eoi_tracking_reset(ioapic); |
8c392696 ED |
707 | } |
708 | ||
d76685c4 GH |
709 | static const struct kvm_io_device_ops ioapic_mmio_ops = { |
710 | .read = ioapic_mmio_read, | |
711 | .write = ioapic_mmio_write, | |
d76685c4 GH |
712 | }; |
713 | ||
1fd4f2a5 ED |
714 | int kvm_ioapic_init(struct kvm *kvm) |
715 | { | |
716 | struct kvm_ioapic *ioapic; | |
090b7aff | 717 | int ret; |
1fd4f2a5 | 718 | |
254272ce | 719 | ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL_ACCOUNT); |
1fd4f2a5 ED |
720 | if (!ioapic) |
721 | return -ENOMEM; | |
46a47b1e | 722 | spin_lock_init(&ioapic->lock); |
184564ef | 723 | INIT_DELAYED_WORK(&ioapic->eoi_inject, kvm_ioapic_eoi_inject_work); |
d7deeeb0 | 724 | kvm->arch.vioapic = ioapic; |
8c392696 | 725 | kvm_ioapic_reset(ioapic); |
d76685c4 | 726 | kvm_iodevice_init(&ioapic->dev, &ioapic_mmio_ops); |
1fd4f2a5 | 727 | ioapic->kvm = kvm; |
79fac95e | 728 | mutex_lock(&kvm->slots_lock); |
743eeb0b SL |
729 | ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, ioapic->base_address, |
730 | IOAPIC_MEM_LENGTH, &ioapic->dev); | |
79fac95e | 731 | mutex_unlock(&kvm->slots_lock); |
1ae77bad WY |
732 | if (ret < 0) { |
733 | kvm->arch.vioapic = NULL; | |
090b7aff | 734 | kfree(ioapic); |
1ae77bad | 735 | } |
090b7aff GH |
736 | |
737 | return ret; | |
1fd4f2a5 | 738 | } |
75858a84 | 739 | |
72bb2fcd WY |
740 | void kvm_ioapic_destroy(struct kvm *kvm) |
741 | { | |
742 | struct kvm_ioapic *ioapic = kvm->arch.vioapic; | |
743 | ||
950712eb PX |
744 | if (!ioapic) |
745 | return; | |
746 | ||
184564ef | 747 | cancel_delayed_work_sync(&ioapic->eoi_inject); |
49f520b9 | 748 | mutex_lock(&kvm->slots_lock); |
d90e3a35 | 749 | kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS, &ioapic->dev); |
49f520b9 | 750 | mutex_unlock(&kvm->slots_lock); |
d90e3a35 JL |
751 | kvm->arch.vioapic = NULL; |
752 | kfree(ioapic); | |
72bb2fcd WY |
753 | } |
754 | ||
33392b49 | 755 | void kvm_get_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state) |
eba0226b | 756 | { |
0191e92d | 757 | struct kvm_ioapic *ioapic = kvm->arch.vioapic; |
eba0226b | 758 | |
46a47b1e | 759 | spin_lock(&ioapic->lock); |
eba0226b | 760 | memcpy(state, ioapic, sizeof(struct kvm_ioapic_state)); |
5bda6eed | 761 | state->irr &= ~ioapic->irr_delivered; |
46a47b1e | 762 | spin_unlock(&ioapic->lock); |
eba0226b GN |
763 | } |
764 | ||
33392b49 | 765 | void kvm_set_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state) |
eba0226b | 766 | { |
0191e92d | 767 | struct kvm_ioapic *ioapic = kvm->arch.vioapic; |
eba0226b | 768 | |
46a47b1e | 769 | spin_lock(&ioapic->lock); |
eba0226b | 770 | memcpy(ioapic, state, sizeof(struct kvm_ioapic_state)); |
673f7b42 | 771 | ioapic->irr = 0; |
5bda6eed | 772 | ioapic->irr_delivered = 0; |
ca8ab3f8 | 773 | kvm_make_scan_ioapic_request(kvm); |
673f7b42 | 774 | kvm_ioapic_inject_all(ioapic, state->irr); |
46a47b1e | 775 | spin_unlock(&ioapic->lock); |
eba0226b | 776 | } |