[linux-2.6-block.git] / arch / x86 / kvm / i8259.c

/*
 * 8259 interrupt controller emulation
 *
 * Copyright (c) 2003-2004 Fabrice Bellard
 * Copyright (c) 2007 Intel Corporation
 * Copyright 2009 Red Hat, Inc. and/or its affilates.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 * Authors:
 *   Yaozu (Eddie) Dong <Eddie.dong@intel.com>
 *   Port from Qemu.
 */
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/bitops.h>
#include "irq.h"

#include <linux/kvm_host.h>
#include "trace.h"

static void pic_irq_request(struct kvm *kvm, int level);

static void pic_lock(struct kvm_pic *s)
	__acquires(&s->lock)
{
	raw_spin_lock(&s->lock);
}

static void pic_unlock(struct kvm_pic *s)
	__releases(&s->lock)
{
	bool wakeup = s->wakeup_needed;
	struct kvm_vcpu *vcpu, *found = NULL;
	int i;

	s->wakeup_needed = false;

	raw_spin_unlock(&s->lock);

	if (wakeup) {
		kvm_for_each_vcpu(i, vcpu, s->kvm) {
			if (kvm_apic_accept_pic_intr(vcpu)) {
				found = vcpu;
				break;
			}
		}

		if (!found)
			found = s->kvm->bsp_vcpu;

		if (!found)
			return;

		kvm_make_request(KVM_REQ_EVENT, found);
		kvm_vcpu_kick(found);
	}
}

static void pic_clear_isr(struct kvm_kpic_state *s, int irq)
{
	s->isr &= ~(1 << irq);
	s->isr_ack |= (1 << irq);
	if (s != &s->pics_state->pics[0])
		irq += 8;
	/*
	 * We are dropping lock while calling ack notifiers since ack
	 * notifier callbacks for assigned devices call into PIC recursively.
	 * Other interrupt may be delivered to PIC while lock is dropped but
	 * it should be safe since PIC state is already updated at this stage.
	 */
	pic_unlock(s->pics_state);
	kvm_notify_acked_irq(s->pics_state->kvm, SELECT_PIC(irq), irq);
	pic_lock(s->pics_state);
}

void kvm_pic_clear_isr_ack(struct kvm *kvm)
{
	struct kvm_pic *s = pic_irqchip(kvm);

	pic_lock(s);
	s->pics[0].isr_ack = 0xff;
	s->pics[1].isr_ack = 0xff;
	pic_unlock(s);
}

/*
 * set irq level. If an edge is detected, then the IRR is set to 1
 */
static inline int pic_set_irq1(struct kvm_kpic_state *s, int irq, int level)
{
	int mask, ret = 1;
	mask = 1 << irq;
	if (s->elcr & mask)	/* level triggered */
		if (level) {
			ret = !(s->irr & mask);
			s->irr |= mask;
			s->last_irr |= mask;
		} else {
			s->irr &= ~mask;
			s->last_irr &= ~mask;
		}
	else	/* edge triggered */
		if (level) {
			if ((s->last_irr & mask) == 0) {
				ret = !(s->irr & mask);
				s->irr |= mask;
			}
			s->last_irr |= mask;
		} else
			s->last_irr &= ~mask;

	return (s->imr & mask) ? -1 : ret;
}

/*
 * return the highest priority found in mask (highest = smallest
 * number). Return 8 if no irq
 */
static inline int get_priority(struct kvm_kpic_state *s, int mask)
{
	int priority;
	if (mask == 0)
		return 8;
	priority = 0;
	while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
		priority++;
	return priority;
}

/*
 * return the pic wanted interrupt. return -1 if none
 */
static int pic_get_irq(struct kvm_kpic_state *s)
{
	int mask, cur_priority, priority;

	mask = s->irr & ~s->imr;
	priority = get_priority(s, mask);
	if (priority == 8)
		return -1;
	/*
	 * compute current priority. If special fully nested mode on the
	 * master, the IRQ coming from the slave is not taken into account
	 * for the priority computation.
	 */
	mask = s->isr;
	if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
		mask &= ~(1 << 2);
	cur_priority = get_priority(s, mask);
	if (priority < cur_priority)
		/*
		 * higher priority found: an irq should be generated
		 */
		return (priority + s->priority_add) & 7;
	else
		return -1;
}

/*
 * raise irq to CPU if necessary. must be called every time the active
 * irq may change
 */
static void pic_update_irq(struct kvm_pic *s)
{
	int irq2, irq;

	irq2 = pic_get_irq(&s->pics[1]);
	if (irq2 >= 0) {
		/*
		 * if irq request by slave pic, signal master PIC
		 */
		pic_set_irq1(&s->pics[0], 2, 1);
		pic_set_irq1(&s->pics[0], 2, 0);
	}
	irq = pic_get_irq(&s->pics[0]);
	pic_irq_request(s->kvm, irq >= 0);
}

void kvm_pic_update_irq(struct kvm_pic *s)
{
	pic_lock(s);
	pic_update_irq(s);
	pic_unlock(s);
}

int kvm_pic_set_irq(void *opaque, int irq, int level)
{
	struct kvm_pic *s = opaque;
	int ret = -1;

	pic_lock(s);
	if (irq >= 0 && irq < PIC_NUM_PINS) {
		ret = pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
		pic_update_irq(s);
		trace_kvm_pic_set_irq(irq >> 3, irq & 7, s->pics[irq >> 3].elcr,
				      s->pics[irq >> 3].imr, ret == 0);
	}
	pic_unlock(s);

	return ret;
}

/*
 * acknowledge interrupt 'irq'
 */
static inline void pic_intack(struct kvm_kpic_state *s, int irq)
{
	s->isr |= 1 << irq;
	/*
	 * We don't clear a level sensitive interrupt here
	 */
	if (!(s->elcr & (1 << irq)))
		s->irr &= ~(1 << irq);

	if (s->auto_eoi) {
		if (s->rotate_on_auto_eoi)
			s->priority_add = (irq + 1) & 7;
		pic_clear_isr(s, irq);
	}

}

int kvm_pic_read_irq(struct kvm *kvm)
{
	int irq, irq2, intno;
	struct kvm_pic *s = pic_irqchip(kvm);

	pic_lock(s);
	irq = pic_get_irq(&s->pics[0]);
	if (irq >= 0) {
		pic_intack(&s->pics[0], irq);
		if (irq == 2) {
			irq2 = pic_get_irq(&s->pics[1]);
			if (irq2 >= 0)
				pic_intack(&s->pics[1], irq2);
			else
				/*
				 * spurious IRQ on slave controller
				 */
				irq2 = 7;
			intno = s->pics[1].irq_base + irq2;
			irq = irq2 + 8;
		} else
			intno = s->pics[0].irq_base + irq;
	} else {
		/*
		 * spurious IRQ on host controller
		 */
		irq = 7;
		intno = s->pics[0].irq_base + irq;
	}
	pic_update_irq(s);
	pic_unlock(s);

	return intno;
}

void kvm_pic_reset(struct kvm_kpic_state *s)
{
	int irq;
	struct kvm_vcpu *vcpu0 = s->pics_state->kvm->bsp_vcpu;
	u8 irr = s->irr, isr = s->imr;

	s->last_irr = 0;
	s->irr = 0;
	s->imr = 0;
	s->isr = 0;
	s->isr_ack = 0xff;
	s->priority_add = 0;
	s->irq_base = 0;
	s->read_reg_select = 0;
	s->poll = 0;
	s->special_mask = 0;
	s->init_state = 0;
	s->auto_eoi = 0;
	s->rotate_on_auto_eoi = 0;
	s->special_fully_nested_mode = 0;
	s->init4 = 0;

	for (irq = 0; irq < PIC_NUM_PINS/2; irq++) {
		if (vcpu0 && kvm_apic_accept_pic_intr(vcpu0))
			if (irr & (1 << irq) || isr & (1 << irq)) {
				pic_clear_isr(s, irq);
			}
	}
}

static void pic_ioport_write(void *opaque, u32 addr, u32 val)
{
	struct kvm_kpic_state *s = opaque;
	int priority, cmd, irq;

	addr &= 1;
	if (addr == 0) {
		if (val & 0x10) {
			s->init4 = val & 1;
			s->last_irr = 0;
			s->imr = 0;
			s->priority_add = 0;
			s->special_mask = 0;
			s->read_reg_select = 0;
			if (!s->init4) {
				s->special_fully_nested_mode = 0;
				s->auto_eoi = 0;
			}
			s->init_state = 1;
			if (val & 0x02)
				printk(KERN_ERR "single mode not supported");
			if (val & 0x08)
				printk(KERN_ERR
				       "level sensitive irq not supported");
		} else if (val & 0x08) {
			if (val & 0x04)
				s->poll = 1;
			if (val & 0x02)
				s->read_reg_select = val & 1;
			if (val & 0x40)
				s->special_mask = (val >> 5) & 1;
		} else {
			cmd = val >> 5;
			switch (cmd) {
			case 0:
			case 4:
				s->rotate_on_auto_eoi = cmd >> 2;
				break;
			case 1:	/* end of interrupt */
			case 5:
				priority = get_priority(s, s->isr);
				if (priority != 8) {
					irq = (priority + s->priority_add) & 7;
					if (cmd == 5)
						s->priority_add = (irq + 1) & 7;
					pic_clear_isr(s, irq);
					pic_update_irq(s->pics_state);
				}
				break;
			case 3:
				irq = val & 7;
				pic_clear_isr(s, irq);
				pic_update_irq(s->pics_state);
				break;
			case 6:
				s->priority_add = (val + 1) & 7;
				pic_update_irq(s->pics_state);
				break;
			case 7:
				irq = val & 7;
				s->priority_add = (irq + 1) & 7;
				pic_clear_isr(s, irq);
				pic_update_irq(s->pics_state);
				break;
			default:
				break;	/* no operation */
			}
		}
	} else
		switch (s->init_state) {
		case 0: { /* normal mode */
			u8 imr_diff = s->imr ^ val,
				off = (s == &s->pics_state->pics[0]) ? 0 : 8;
			s->imr = val;
			for (irq = 0; irq < PIC_NUM_PINS/2; irq++)
				if (imr_diff & (1 << irq))
					kvm_fire_mask_notifiers(
						s->pics_state->kvm,
						SELECT_PIC(irq + off),
						irq + off,
						!!(s->imr & (1 << irq)));
			pic_update_irq(s->pics_state);
			break;
		}
		case 1:
			s->irq_base = val & 0xf8;
			s->init_state = 2;
			break;
		case 2:
			if (s->init4)
				s->init_state = 3;
			else
				s->init_state = 0;
			break;
		case 3:
			s->special_fully_nested_mode = (val >> 4) & 1;
			s->auto_eoi = (val >> 1) & 1;
			s->init_state = 0;
			break;
		}
}

static u32 pic_poll_read(struct kvm_kpic_state *s, u32 addr1)
{
	int ret;

	ret = pic_get_irq(s);
	if (ret >= 0) {
		if (addr1 >> 7) {
			s->pics_state->pics[0].isr &= ~(1 << 2);
			s->pics_state->pics[0].irr &= ~(1 << 2);
		}
		s->irr &= ~(1 << ret);
		pic_clear_isr(s, ret);
		if (addr1 >> 7 || ret != 2)
			pic_update_irq(s->pics_state);
	} else {
		ret = 0x07;
		pic_update_irq(s->pics_state);
	}

	return ret;
}

static u32 pic_ioport_read(void *opaque, u32 addr1)
{
	struct kvm_kpic_state *s = opaque;
	unsigned int addr;
	int ret;

	addr = addr1;
	addr &= 1;
	if (s->poll) {
		ret = pic_poll_read(s, addr1);
		s->poll = 0;
	} else
		if (addr == 0)
			if (s->read_reg_select)
				ret = s->isr;
			else
				ret = s->irr;
		else
			ret = s->imr;
	return ret;
}

static void elcr_ioport_write(void *opaque, u32 addr, u32 val)
{
	struct kvm_kpic_state *s = opaque;
	s->elcr = val & s->elcr_mask;
}

static u32 elcr_ioport_read(void *opaque, u32 addr1)
{
	struct kvm_kpic_state *s = opaque;
	return s->elcr;
}

static int picdev_in_range(gpa_t addr)
{
	switch (addr) {
	case 0x20:
	case 0x21:
	case 0xa0:
	case 0xa1:
	case 0x4d0:
	case 0x4d1:
		return 1;
	default:
		return 0;
	}
}

static inline struct kvm_pic *to_pic(struct kvm_io_device *dev)
{
	return container_of(dev, struct kvm_pic, dev);
}

static int picdev_write(struct kvm_io_device *this,
			 gpa_t addr, int len, const void *val)
{
	struct kvm_pic *s = to_pic(this);
	unsigned char data = *(unsigned char *)val;
	if (!picdev_in_range(addr))
		return -EOPNOTSUPP;

	if (len != 1) {
		if (printk_ratelimit())
			printk(KERN_ERR "PIC: non byte write\n");
		return 0;
	}
	pic_lock(s);
	switch (addr) {
	case 0x20:
	case 0x21:
	case 0xa0:
	case 0xa1:
		pic_ioport_write(&s->pics[addr >> 7], addr, data);
		break;
	case 0x4d0:
	case 0x4d1:
		elcr_ioport_write(&s->pics[addr & 1], addr, data);
		break;
	}
	pic_unlock(s);
	return 0;
}

static int picdev_read(struct kvm_io_device *this,
		       gpa_t addr, int len, void *val)
{
	struct kvm_pic *s = to_pic(this);
	unsigned char data = 0;
	if (!picdev_in_range(addr))
		return -EOPNOTSUPP;

	if (len != 1) {
		if (printk_ratelimit())
			printk(KERN_ERR "PIC: non byte read\n");
		return 0;
	}
	pic_lock(s);
	switch (addr) {
	case 0x20:
	case 0x21:
	case 0xa0:
	case 0xa1:
		data = pic_ioport_read(&s->pics[addr >> 7], addr);
		break;
	case 0x4d0:
	case 0x4d1:
		data = elcr_ioport_read(&s->pics[addr & 1], addr);
		break;
	}
	*(unsigned char *)val = data;
	pic_unlock(s);
	return 0;
}

/*
 * callback when PIC0 irq status changed
 */
static void pic_irq_request(struct kvm *kvm, int level)
{
	struct kvm_vcpu *vcpu = kvm->bsp_vcpu;
	struct kvm_pic *s = pic_irqchip(kvm);
	int irq = pic_get_irq(&s->pics[0]);

	s->output = level;
	if (vcpu && level && (s->pics[0].isr_ack & (1 << irq))) {
		s->pics[0].isr_ack &= ~(1 << irq);
		s->wakeup_needed = true;
	}
}

static const struct kvm_io_device_ops picdev_ops = {
	.read     = picdev_read,
	.write    = picdev_write,
};

struct kvm_pic *kvm_create_pic(struct kvm *kvm)
{
	struct kvm_pic *s;
	int ret;

	s = kzalloc(sizeof(struct kvm_pic), GFP_KERNEL);
	if (!s)
		return NULL;
	raw_spin_lock_init(&s->lock);
	s->kvm = kvm;
	s->pics[0].elcr_mask = 0xf8;
	s->pics[1].elcr_mask = 0xde;
	s->pics[0].pics_state = s;
	s->pics[1].pics_state = s;

	/*
	 * Initialize PIO device
	 */
	kvm_iodevice_init(&s->dev, &picdev_ops);
	mutex_lock(&kvm->slots_lock);
	ret = kvm_io_bus_register_dev(kvm, KVM_PIO_BUS, &s->dev);
	mutex_unlock(&kvm->slots_lock);
	if (ret < 0) {
		kfree(s);
		return NULL;
	}

	return s;
}

void kvm_destroy_pic(struct kvm *kvm)
{
	struct kvm_pic *vpic = kvm->arch.vpic;

	if (vpic) {
		kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, &vpic->dev);
		kvm->arch.vpic = NULL;
		kfree(vpic);
	}
}
Commit	Line	Data
85f455f7 ED	1	/*
	2	* 8259 interrupt controller emulation
	3	*
	4	* Copyright (c) 2003-2004 Fabrice Bellard
	5	* Copyright (c) 2007 Intel Corporation
221d059d	6	* Copyright 2009 Red Hat, Inc. and/or its affilates.
85f455f7 ED	7	*
	8	* Permission is hereby granted, free of charge, to any person obtaining a copy
	9	* of this software and associated documentation files (the "Software"), to deal
	10	* in the Software without restriction, including without limitation the rights
	11	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	12	* copies of the Software, and to permit persons to whom the Software is
	13	* furnished to do so, subject to the following conditions:
	14	*
	15	* The above copyright notice and this permission notice shall be included in
	16	* all copies or substantial portions of the Software.
	17	*
	18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	19	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	20	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	21	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	22	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	23	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	24	* THE SOFTWARE.
	25	* Authors:
	26	* Yaozu (Eddie) Dong <Eddie.dong@intel.com>
	27	* Port from Qemu.
	28	*/
	29	#include <linux/mm.h>
5a0e3ad6	30	#include <linux/slab.h>
3f353858	31	#include <linux/bitops.h>
85f455f7	32	#include "irq.h"
edf88417 AK	33
edf88417 AK	34	#include <linux/kvm_host.h>
1000ff8d	35	#include "trace.h"
85f455f7	36
073d4613 AK	37	static void pic_irq_request(struct kvm *kvm, int level);
073d4613 AK	38
50a085bd JK	39	static void pic_lock(struct kvm_pic *s)
	40	__acquires(&s->lock)
	41	{
	42	raw_spin_lock(&s->lock);
	43	}
	44
	45	static void pic_unlock(struct kvm_pic *s)
	46	__releases(&s->lock)
	47	{
	48	bool wakeup = s->wakeup_needed;
529df65e CL	49	struct kvm_vcpu vcpu, found = NULL;
529df65e CL	50	int i;
50a085bd JK	51
	52	s->wakeup_needed = false;
	53
	54	raw_spin_unlock(&s->lock);
	55
	56	if (wakeup) {
529df65e CL	57	kvm_for_each_vcpu(i, vcpu, s->kvm) {
	58	if (kvm_apic_accept_pic_intr(vcpu)) {
	59	found = vcpu;
	60	break;
	61	}
	62	}
	63
	64	if (!found)
	65	found = s->kvm->bsp_vcpu;
	66
ae0635b3 AK	67	if (!found)
	68	return;
	69
3842d135	70	kvm_make_request(KVM_REQ_EVENT, found);
529df65e	71	kvm_vcpu_kick(found);
50a085bd JK	72	}
	73	}
	74
7edd0ce0 AK	75	static void pic_clear_isr(struct kvm_kpic_state *s, int irq)
	76	{
	77	s->isr &= ~(1 << irq);
e4825800	78	s->isr_ack \|= (1 << irq);
938396a2 GN	79	if (s != &s->pics_state->pics[0])
938396a2 GN	80	irq += 8;
eba0226b GN	81	/*
	82	* We are dropping lock while calling ack notifiers since ack
	83	* notifier callbacks for assigned devices call into PIC recursively.
	84	* Other interrupt may be delivered to PIC while lock is dropped but
	85	* it should be safe since PIC state is already updated at this stage.
	86	*/
50a085bd	87	pic_unlock(s->pics_state);
938396a2	88	kvm_notify_acked_irq(s->pics_state->kvm, SELECT_PIC(irq), irq);
50a085bd	89	pic_lock(s->pics_state);
e4825800 MT	90	}
	91
	92	void kvm_pic_clear_isr_ack(struct kvm *kvm)
	93	{
	94	struct kvm_pic *s = pic_irqchip(kvm);
fa8273e9	95
50a085bd	96	pic_lock(s);
e4825800 MT	97	s->pics[0].isr_ack = 0xff;
e4825800 MT	98	s->pics[1].isr_ack = 0xff;
50a085bd	99	pic_unlock(s);
7edd0ce0 AK	100	}
7edd0ce0 AK	101
85f455f7 ED	102	/*
	103	* set irq level. If an edge is detected, then the IRR is set to 1
	104	*/
4925663a	105	static inline int pic_set_irq1(struct kvm_kpic_state *s, int irq, int level)
85f455f7	106	{
4925663a	107	int mask, ret = 1;
85f455f7 ED	108	mask = 1 << irq;
	109	if (s->elcr & mask) /* level triggered */
	110	if (level) {
4925663a	111	ret = !(s->irr & mask);
85f455f7 ED	112	s->irr \|= mask;
	113	s->last_irr \|= mask;
	114	} else {
	115	s->irr &= ~mask;
	116	s->last_irr &= ~mask;
	117	}
	118	else /* edge triggered */
	119	if (level) {
4925663a GN	120	if ((s->last_irr & mask) == 0) {
4925663a GN	121	ret = !(s->irr & mask);
85f455f7	122	s->irr \|= mask;
4925663a	123	}
85f455f7 ED	124	s->last_irr \|= mask;
	125	} else
	126	s->last_irr &= ~mask;
4925663a GN	127
4925663a GN	128	return (s->imr & mask) ? -1 : ret;
85f455f7 ED	129	}
	130
	131	/*
	132	* return the highest priority found in mask (highest = smallest
	133	* number). Return 8 if no irq
	134	*/
	135	static inline int get_priority(struct kvm_kpic_state *s, int mask)
	136	{
	137	int priority;
	138	if (mask == 0)
	139	return 8;
	140	priority = 0;
	141	while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
	142	priority++;
	143	return priority;
	144	}
	145
	146	/*
	147	* return the pic wanted interrupt. return -1 if none
	148	*/
	149	static int pic_get_irq(struct kvm_kpic_state *s)
	150	{
	151	int mask, cur_priority, priority;
	152
	153	mask = s->irr & ~s->imr;
	154	priority = get_priority(s, mask);
	155	if (priority == 8)
	156	return -1;
	157	/*
	158	* compute current priority. If special fully nested mode on the
	159	* master, the IRQ coming from the slave is not taken into account
	160	* for the priority computation.
	161	*/
	162	mask = s->isr;
	163	if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
	164	mask &= ~(1 << 2);
	165	cur_priority = get_priority(s, mask);
	166	if (priority < cur_priority)
	167	/*
	168	* higher priority found: an irq should be generated
	169	*/
	170	return (priority + s->priority_add) & 7;
	171	else
	172	return -1;
	173	}
	174
	175	/*
	176	* raise irq to CPU if necessary. must be called every time the active
	177	* irq may change
	178	*/
	179	static void pic_update_irq(struct kvm_pic *s)
	180	{
	181	int irq2, irq;
	182
	183	irq2 = pic_get_irq(&s->pics[1]);
	184	if (irq2 >= 0) {
	185	/*
	186	* if irq request by slave pic, signal master PIC
	187	*/
	188	pic_set_irq1(&s->pics[0], 2, 1);
	189	pic_set_irq1(&s->pics[0], 2, 0);
	190	}
	191	irq = pic_get_irq(&s->pics[0]);
36633f32	192	pic_irq_request(s->kvm, irq >= 0);
85f455f7 ED	193	}
85f455f7 ED	194
6ceb9d79 HQ	195	void kvm_pic_update_irq(struct kvm_pic *s)
6ceb9d79 HQ	196	{
50a085bd	197	pic_lock(s);
6ceb9d79	198	pic_update_irq(s);
50a085bd	199	pic_unlock(s);
6ceb9d79 HQ	200	}
6ceb9d79 HQ	201
4925663a	202	int kvm_pic_set_irq(void *opaque, int irq, int level)
85f455f7 ED	203	{
85f455f7 ED	204	struct kvm_pic *s = opaque;
4925663a	205	int ret = -1;
85f455f7	206
50a085bd	207	pic_lock(s);
c65bbfa1	208	if (irq >= 0 && irq < PIC_NUM_PINS) {
4925663a	209	ret = pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
c65bbfa1	210	pic_update_irq(s);
1000ff8d GN	211	trace_kvm_pic_set_irq(irq >> 3, irq & 7, s->pics[irq >> 3].elcr,
1000ff8d GN	212	s->pics[irq >> 3].imr, ret == 0);
c65bbfa1	213	}
50a085bd	214	pic_unlock(s);
4925663a GN	215
4925663a GN	216	return ret;
85f455f7 ED	217	}
	218
	219	/*
	220	* acknowledge interrupt 'irq'
	221	*/
	222	static inline void pic_intack(struct kvm_kpic_state *s, int irq)
	223	{
7edd0ce0	224	s->isr \|= 1 << irq;
85f455f7 ED	225	/*
	226	* We don't clear a level sensitive interrupt here
	227	*/
	228	if (!(s->elcr & (1 << irq)))
	229	s->irr &= ~(1 << irq);
eba0226b GN	230
	231	if (s->auto_eoi) {
	232	if (s->rotate_on_auto_eoi)
	233	s->priority_add = (irq + 1) & 7;
	234	pic_clear_isr(s, irq);
	235	}
	236
85f455f7 ED	237	}
85f455f7 ED	238
f5244726	239	int kvm_pic_read_irq(struct kvm *kvm)
85f455f7 ED	240	{
85f455f7 ED	241	int irq, irq2, intno;
f5244726	242	struct kvm_pic *s = pic_irqchip(kvm);
85f455f7	243
50a085bd	244	pic_lock(s);
85f455f7 ED	245	irq = pic_get_irq(&s->pics[0]);
	246	if (irq >= 0) {
	247	pic_intack(&s->pics[0], irq);
	248	if (irq == 2) {
	249	irq2 = pic_get_irq(&s->pics[1]);
	250	if (irq2 >= 0)
	251	pic_intack(&s->pics[1], irq2);
	252	else
	253	/*
	254	* spurious IRQ on slave controller
	255	*/
	256	irq2 = 7;
	257	intno = s->pics[1].irq_base + irq2;
	258	irq = irq2 + 8;
	259	} else
	260	intno = s->pics[0].irq_base + irq;
	261	} else {
	262	/*
	263	* spurious IRQ on host controller
	264	*/
	265	irq = 7;
	266	intno = s->pics[0].irq_base + irq;
	267	}
	268	pic_update_irq(s);
50a085bd	269	pic_unlock(s);
85f455f7 ED	270
	271	return intno;
	272	}
	273
2fcceae1	274	void kvm_pic_reset(struct kvm_kpic_state *s)
85f455f7	275	{
79c727d4	276	int irq;
073d4613	277	struct kvm_vcpu *vcpu0 = s->pics_state->kvm->bsp_vcpu;
79c727d4	278	u8 irr = s->irr, isr = s->imr;
f5244726	279
85f455f7 ED	280	s->last_irr = 0;
	281	s->irr = 0;
	282	s->imr = 0;
	283	s->isr = 0;
e4825800	284	s->isr_ack = 0xff;
85f455f7 ED	285	s->priority_add = 0;
	286	s->irq_base = 0;
	287	s->read_reg_select = 0;
	288	s->poll = 0;
	289	s->special_mask = 0;
	290	s->init_state = 0;
	291	s->auto_eoi = 0;
	292	s->rotate_on_auto_eoi = 0;
	293	s->special_fully_nested_mode = 0;
	294	s->init4 = 0;
79c727d4 GN	295
	296	for (irq = 0; irq < PIC_NUM_PINS/2; irq++) {
	297	if (vcpu0 && kvm_apic_accept_pic_intr(vcpu0))
	298	if (irr & (1 << irq) \|\| isr & (1 << irq)) {
	299	pic_clear_isr(s, irq);
	300	}
	301	}
85f455f7 ED	302	}
	303
	304	static void pic_ioport_write(void *opaque, u32 addr, u32 val)
	305	{
	306	struct kvm_kpic_state *s = opaque;
	307	int priority, cmd, irq;
	308
	309	addr &= 1;
	310	if (addr == 0) {
	311	if (val & 0x10) {
85f455f7	312	s->init4 = val & 1;
9ed049c3 AK	313	s->last_irr = 0;
	314	s->imr = 0;
	315	s->priority_add = 0;
	316	s->special_mask = 0;
	317	s->read_reg_select = 0;
	318	if (!s->init4) {
	319	s->special_fully_nested_mode = 0;
	320	s->auto_eoi = 0;
	321	}
	322	s->init_state = 1;
85f455f7 ED	323	if (val & 0x02)
	324	printk(KERN_ERR "single mode not supported");
	325	if (val & 0x08)
	326	printk(KERN_ERR
	327	"level sensitive irq not supported");
	328	} else if (val & 0x08) {
	329	if (val & 0x04)
	330	s->poll = 1;
	331	if (val & 0x02)
	332	s->read_reg_select = val & 1;
	333	if (val & 0x40)
	334	s->special_mask = (val >> 5) & 1;
	335	} else {
	336	cmd = val >> 5;
	337	switch (cmd) {
	338	case 0:
	339	case 4:
	340	s->rotate_on_auto_eoi = cmd >> 2;
	341	break;
	342	case 1: /* end of interrupt */
	343	case 5:
	344	priority = get_priority(s, s->isr);
	345	if (priority != 8) {
	346	irq = (priority + s->priority_add) & 7;
85f455f7 ED	347	if (cmd == 5)
85f455f7 ED	348	s->priority_add = (irq + 1) & 7;
eba0226b	349	pic_clear_isr(s, irq);
85f455f7 ED	350	pic_update_irq(s->pics_state);
	351	}
	352	break;
	353	case 3:
	354	irq = val & 7;
7edd0ce0	355	pic_clear_isr(s, irq);
85f455f7 ED	356	pic_update_irq(s->pics_state);
	357	break;
	358	case 6:
	359	s->priority_add = (val + 1) & 7;
	360	pic_update_irq(s->pics_state);
	361	break;
	362	case 7:
	363	irq = val & 7;
85f455f7	364	s->priority_add = (irq + 1) & 7;
7edd0ce0	365	pic_clear_isr(s, irq);
85f455f7 ED	366	pic_update_irq(s->pics_state);
	367	break;
	368	default:
	369	break; /* no operation */
	370	}
	371	}
	372	} else
	373	switch (s->init_state) {
9195c4da GN	374	case 0: { /* normal mode */
	375	u8 imr_diff = s->imr ^ val,
	376	off = (s == &s->pics_state->pics[0]) ? 0 : 8;
85f455f7	377	s->imr = val;
9195c4da GN	378	for (irq = 0; irq < PIC_NUM_PINS/2; irq++)
	379	if (imr_diff & (1 << irq))
	380	kvm_fire_mask_notifiers(
	381	s->pics_state->kvm,
	382	SELECT_PIC(irq + off),
	383	irq + off,
	384	!!(s->imr & (1 << irq)));
85f455f7 ED	385	pic_update_irq(s->pics_state);
85f455f7 ED	386	break;
9195c4da	387	}
85f455f7 ED	388	case 1:
	389	s->irq_base = val & 0xf8;
	390	s->init_state = 2;
	391	break;
	392	case 2:
	393	if (s->init4)
	394	s->init_state = 3;
	395	else
	396	s->init_state = 0;
	397	break;
	398	case 3:
	399	s->special_fully_nested_mode = (val >> 4) & 1;
	400	s->auto_eoi = (val >> 1) & 1;
	401	s->init_state = 0;
	402	break;
	403	}
	404	}
	405
	406	static u32 pic_poll_read(struct kvm_kpic_state *s, u32 addr1)
	407	{
	408	int ret;
	409
	410	ret = pic_get_irq(s);
	411	if (ret >= 0) {
	412	if (addr1 >> 7) {
	413	s->pics_state->pics[0].isr &= ~(1 << 2);
	414	s->pics_state->pics[0].irr &= ~(1 << 2);
	415	}
	416	s->irr &= ~(1 << ret);
7edd0ce0	417	pic_clear_isr(s, ret);
85f455f7 ED	418	if (addr1 >> 7 \|\| ret != 2)
	419	pic_update_irq(s->pics_state);
	420	} else {
	421	ret = 0x07;
	422	pic_update_irq(s->pics_state);
	423	}
	424
	425	return ret;
	426	}
	427
	428	static u32 pic_ioport_read(void *opaque, u32 addr1)
	429	{
	430	struct kvm_kpic_state *s = opaque;
	431	unsigned int addr;
	432	int ret;
	433
	434	addr = addr1;
	435	addr &= 1;
	436	if (s->poll) {
	437	ret = pic_poll_read(s, addr1);
	438	s->poll = 0;
	439	} else
	440	if (addr == 0)
	441	if (s->read_reg_select)
	442	ret = s->isr;
	443	else
	444	ret = s->irr;
	445	else
	446	ret = s->imr;
	447	return ret;
	448	}
	449
	450	static void elcr_ioport_write(void *opaque, u32 addr, u32 val)
	451	{
	452	struct kvm_kpic_state *s = opaque;
	453	s->elcr = val & s->elcr_mask;
	454	}
	455
	456	static u32 elcr_ioport_read(void *opaque, u32 addr1)
	457	{
	458	struct kvm_kpic_state *s = opaque;
	459	return s->elcr;
	460	}
	461
bda9020e	462	static int picdev_in_range(gpa_t addr)
85f455f7 ED	463	{
	464	switch (addr) {
	465	case 0x20:
	466	case 0x21:
	467	case 0xa0:
	468	case 0xa1:
	469	case 0x4d0:
	470	case 0x4d1:
	471	return 1;
	472	default:
	473	return 0;
	474	}
	475	}
	476
d76685c4 GH	477	static inline struct kvm_pic to_pic(struct kvm_io_device dev)
	478	{
	479	return container_of(dev, struct kvm_pic, dev);
	480	}
	481
bda9020e	482	static int picdev_write(struct kvm_io_device *this,
85f455f7 ED	483	gpa_t addr, int len, const void *val)
85f455f7 ED	484	{
d76685c4	485	struct kvm_pic *s = to_pic(this);
85f455f7	486	unsigned char data = (unsigned char )val;
bda9020e MT	487	if (!picdev_in_range(addr))
bda9020e MT	488	return -EOPNOTSUPP;
85f455f7 ED	489
	490	if (len != 1) {
	491	if (printk_ratelimit())
	492	printk(KERN_ERR "PIC: non byte write\n");
bda9020e	493	return 0;
85f455f7	494	}
50a085bd	495	pic_lock(s);
85f455f7 ED	496	switch (addr) {
	497	case 0x20:
	498	case 0x21:
	499	case 0xa0:
	500	case 0xa1:
	501	pic_ioport_write(&s->pics[addr >> 7], addr, data);
	502	break;
	503	case 0x4d0:
	504	case 0x4d1:
	505	elcr_ioport_write(&s->pics[addr & 1], addr, data);
	506	break;
	507	}
50a085bd	508	pic_unlock(s);
bda9020e	509	return 0;
85f455f7 ED	510	}
85f455f7 ED	511
bda9020e MT	512	static int picdev_read(struct kvm_io_device *this,
bda9020e MT	513	gpa_t addr, int len, void *val)
85f455f7	514	{
d76685c4	515	struct kvm_pic *s = to_pic(this);
85f455f7	516	unsigned char data = 0;
bda9020e MT	517	if (!picdev_in_range(addr))
bda9020e MT	518	return -EOPNOTSUPP;
85f455f7 ED	519
	520	if (len != 1) {
	521	if (printk_ratelimit())
	522	printk(KERN_ERR "PIC: non byte read\n");
bda9020e	523	return 0;
85f455f7	524	}
50a085bd	525	pic_lock(s);
85f455f7 ED	526	switch (addr) {
	527	case 0x20:
	528	case 0x21:
	529	case 0xa0:
	530	case 0xa1:
	531	data = pic_ioport_read(&s->pics[addr >> 7], addr);
	532	break;
	533	case 0x4d0:
	534	case 0x4d1:
	535	data = elcr_ioport_read(&s->pics[addr & 1], addr);
	536	break;
	537	}
	538	(unsigned char )val = data;
50a085bd	539	pic_unlock(s);
bda9020e	540	return 0;
85f455f7 ED	541	}
	542
	543	/*
	544	* callback when PIC0 irq status changed
	545	*/
073d4613	546	static void pic_irq_request(struct kvm *kvm, int level)
85f455f7	547	{
c5af89b6	548	struct kvm_vcpu *vcpu = kvm->bsp_vcpu;
e4825800 MT	549	struct kvm_pic *s = pic_irqchip(kvm);
e4825800 MT	550	int irq = pic_get_irq(&s->pics[0]);
85f455f7	551
e4825800 MT	552	s->output = level;
	553	if (vcpu && level && (s->pics[0].isr_ack & (1 << irq))) {
	554	s->pics[0].isr_ack &= ~(1 << irq);
50a085bd	555	s->wakeup_needed = true;
e4825800	556	}
85f455f7 ED	557	}
85f455f7 ED	558
d76685c4 GH	559	static const struct kvm_io_device_ops picdev_ops = {
	560	.read = picdev_read,
	561	.write = picdev_write,
d76685c4 GH	562	};
d76685c4 GH	563
85f455f7 ED	564	struct kvm_pic kvm_create_pic(struct kvm kvm)
	565	{
	566	struct kvm_pic *s;
090b7aff GH	567	int ret;
090b7aff GH	568
85f455f7 ED	569	s = kzalloc(sizeof(struct kvm_pic), GFP_KERNEL);
	570	if (!s)
	571	return NULL;
fa8273e9	572	raw_spin_lock_init(&s->lock);
3f353858	573	s->kvm = kvm;
85f455f7 ED	574	s->pics[0].elcr_mask = 0xf8;
85f455f7 ED	575	s->pics[1].elcr_mask = 0xde;
85f455f7 ED	576	s->pics[0].pics_state = s;
	577	s->pics[1].pics_state = s;
	578
	579	/*
	580	* Initialize PIO device
	581	*/
d76685c4	582	kvm_iodevice_init(&s->dev, &picdev_ops);
79fac95e	583	mutex_lock(&kvm->slots_lock);
e93f8a0f	584	ret = kvm_io_bus_register_dev(kvm, KVM_PIO_BUS, &s->dev);
79fac95e	585	mutex_unlock(&kvm->slots_lock);
090b7aff GH	586	if (ret < 0) {
	587	kfree(s);
	588	return NULL;
	589	}
	590
85f455f7 ED	591	return s;
85f455f7 ED	592	}
72bb2fcd WY	593
	594	void kvm_destroy_pic(struct kvm *kvm)
	595	{
	596	struct kvm_pic *vpic = kvm->arch.vpic;
	597
	598	if (vpic) {
	599	kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, &vpic->dev);
	600	kvm->arch.vpic = NULL;
	601	kfree(vpic);
	602	}
	603	}