Commit | Line | Data |
---|---|---|
85f455f7 ED |
1 | /* |
2 | * 8259 interrupt controller emulation | |
3 | * | |
4 | * Copyright (c) 2003-2004 Fabrice Bellard | |
5 | * Copyright (c) 2007 Intel Corporation | |
6 | * | |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | * Authors: | |
25 | * Yaozu (Eddie) Dong <Eddie.dong@intel.com> | |
26 | * Port from Qemu. | |
27 | */ | |
28 | #include <linux/mm.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
3f353858 | 30 | #include <linux/bitops.h> |
85f455f7 | 31 | #include "irq.h" |
edf88417 AK |
32 | |
33 | #include <linux/kvm_host.h> | |
1000ff8d | 34 | #include "trace.h" |
85f455f7 | 35 | |
50a085bd JK |
36 | static void pic_lock(struct kvm_pic *s) |
37 | __acquires(&s->lock) | |
38 | { | |
39 | raw_spin_lock(&s->lock); | |
40 | } | |
41 | ||
42 | static void pic_unlock(struct kvm_pic *s) | |
43 | __releases(&s->lock) | |
44 | { | |
45 | bool wakeup = s->wakeup_needed; | |
46 | struct kvm_vcpu *vcpu; | |
47 | ||
48 | s->wakeup_needed = false; | |
49 | ||
50 | raw_spin_unlock(&s->lock); | |
51 | ||
52 | if (wakeup) { | |
53 | vcpu = s->kvm->bsp_vcpu; | |
54 | if (vcpu) | |
55 | kvm_vcpu_kick(vcpu); | |
56 | } | |
57 | } | |
58 | ||
7edd0ce0 AK |
59 | static void pic_clear_isr(struct kvm_kpic_state *s, int irq) |
60 | { | |
61 | s->isr &= ~(1 << irq); | |
e4825800 | 62 | s->isr_ack |= (1 << irq); |
938396a2 GN |
63 | if (s != &s->pics_state->pics[0]) |
64 | irq += 8; | |
eba0226b GN |
65 | /* |
66 | * We are dropping lock while calling ack notifiers since ack | |
67 | * notifier callbacks for assigned devices call into PIC recursively. | |
68 | * Other interrupt may be delivered to PIC while lock is dropped but | |
69 | * it should be safe since PIC state is already updated at this stage. | |
70 | */ | |
50a085bd | 71 | pic_unlock(s->pics_state); |
938396a2 | 72 | kvm_notify_acked_irq(s->pics_state->kvm, SELECT_PIC(irq), irq); |
50a085bd | 73 | pic_lock(s->pics_state); |
e4825800 MT |
74 | } |
75 | ||
76 | void kvm_pic_clear_isr_ack(struct kvm *kvm) | |
77 | { | |
78 | struct kvm_pic *s = pic_irqchip(kvm); | |
fa8273e9 | 79 | |
50a085bd | 80 | pic_lock(s); |
e4825800 MT |
81 | s->pics[0].isr_ack = 0xff; |
82 | s->pics[1].isr_ack = 0xff; | |
50a085bd | 83 | pic_unlock(s); |
7edd0ce0 AK |
84 | } |
85 | ||
85f455f7 ED |
86 | /* |
87 | * set irq level. If an edge is detected, then the IRR is set to 1 | |
88 | */ | |
4925663a | 89 | static inline int pic_set_irq1(struct kvm_kpic_state *s, int irq, int level) |
85f455f7 | 90 | { |
4925663a | 91 | int mask, ret = 1; |
85f455f7 ED |
92 | mask = 1 << irq; |
93 | if (s->elcr & mask) /* level triggered */ | |
94 | if (level) { | |
4925663a | 95 | ret = !(s->irr & mask); |
85f455f7 ED |
96 | s->irr |= mask; |
97 | s->last_irr |= mask; | |
98 | } else { | |
99 | s->irr &= ~mask; | |
100 | s->last_irr &= ~mask; | |
101 | } | |
102 | else /* edge triggered */ | |
103 | if (level) { | |
4925663a GN |
104 | if ((s->last_irr & mask) == 0) { |
105 | ret = !(s->irr & mask); | |
85f455f7 | 106 | s->irr |= mask; |
4925663a | 107 | } |
85f455f7 ED |
108 | s->last_irr |= mask; |
109 | } else | |
110 | s->last_irr &= ~mask; | |
4925663a GN |
111 | |
112 | return (s->imr & mask) ? -1 : ret; | |
85f455f7 ED |
113 | } |
114 | ||
115 | /* | |
116 | * return the highest priority found in mask (highest = smallest | |
117 | * number). Return 8 if no irq | |
118 | */ | |
119 | static inline int get_priority(struct kvm_kpic_state *s, int mask) | |
120 | { | |
121 | int priority; | |
122 | if (mask == 0) | |
123 | return 8; | |
124 | priority = 0; | |
125 | while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0) | |
126 | priority++; | |
127 | return priority; | |
128 | } | |
129 | ||
130 | /* | |
131 | * return the pic wanted interrupt. return -1 if none | |
132 | */ | |
133 | static int pic_get_irq(struct kvm_kpic_state *s) | |
134 | { | |
135 | int mask, cur_priority, priority; | |
136 | ||
137 | mask = s->irr & ~s->imr; | |
138 | priority = get_priority(s, mask); | |
139 | if (priority == 8) | |
140 | return -1; | |
141 | /* | |
142 | * compute current priority. If special fully nested mode on the | |
143 | * master, the IRQ coming from the slave is not taken into account | |
144 | * for the priority computation. | |
145 | */ | |
146 | mask = s->isr; | |
147 | if (s->special_fully_nested_mode && s == &s->pics_state->pics[0]) | |
148 | mask &= ~(1 << 2); | |
149 | cur_priority = get_priority(s, mask); | |
150 | if (priority < cur_priority) | |
151 | /* | |
152 | * higher priority found: an irq should be generated | |
153 | */ | |
154 | return (priority + s->priority_add) & 7; | |
155 | else | |
156 | return -1; | |
157 | } | |
158 | ||
159 | /* | |
160 | * raise irq to CPU if necessary. must be called every time the active | |
161 | * irq may change | |
162 | */ | |
163 | static void pic_update_irq(struct kvm_pic *s) | |
164 | { | |
165 | int irq2, irq; | |
166 | ||
167 | irq2 = pic_get_irq(&s->pics[1]); | |
168 | if (irq2 >= 0) { | |
169 | /* | |
170 | * if irq request by slave pic, signal master PIC | |
171 | */ | |
172 | pic_set_irq1(&s->pics[0], 2, 1); | |
173 | pic_set_irq1(&s->pics[0], 2, 0); | |
174 | } | |
175 | irq = pic_get_irq(&s->pics[0]); | |
176 | if (irq >= 0) | |
177 | s->irq_request(s->irq_request_opaque, 1); | |
178 | else | |
179 | s->irq_request(s->irq_request_opaque, 0); | |
180 | } | |
181 | ||
6ceb9d79 HQ |
182 | void kvm_pic_update_irq(struct kvm_pic *s) |
183 | { | |
50a085bd | 184 | pic_lock(s); |
6ceb9d79 | 185 | pic_update_irq(s); |
50a085bd | 186 | pic_unlock(s); |
6ceb9d79 HQ |
187 | } |
188 | ||
4925663a | 189 | int kvm_pic_set_irq(void *opaque, int irq, int level) |
85f455f7 ED |
190 | { |
191 | struct kvm_pic *s = opaque; | |
4925663a | 192 | int ret = -1; |
85f455f7 | 193 | |
50a085bd | 194 | pic_lock(s); |
c65bbfa1 | 195 | if (irq >= 0 && irq < PIC_NUM_PINS) { |
4925663a | 196 | ret = pic_set_irq1(&s->pics[irq >> 3], irq & 7, level); |
c65bbfa1 | 197 | pic_update_irq(s); |
1000ff8d GN |
198 | trace_kvm_pic_set_irq(irq >> 3, irq & 7, s->pics[irq >> 3].elcr, |
199 | s->pics[irq >> 3].imr, ret == 0); | |
c65bbfa1 | 200 | } |
50a085bd | 201 | pic_unlock(s); |
4925663a GN |
202 | |
203 | return ret; | |
85f455f7 ED |
204 | } |
205 | ||
206 | /* | |
207 | * acknowledge interrupt 'irq' | |
208 | */ | |
209 | static inline void pic_intack(struct kvm_kpic_state *s, int irq) | |
210 | { | |
7edd0ce0 | 211 | s->isr |= 1 << irq; |
85f455f7 ED |
212 | /* |
213 | * We don't clear a level sensitive interrupt here | |
214 | */ | |
215 | if (!(s->elcr & (1 << irq))) | |
216 | s->irr &= ~(1 << irq); | |
eba0226b GN |
217 | |
218 | if (s->auto_eoi) { | |
219 | if (s->rotate_on_auto_eoi) | |
220 | s->priority_add = (irq + 1) & 7; | |
221 | pic_clear_isr(s, irq); | |
222 | } | |
223 | ||
85f455f7 ED |
224 | } |
225 | ||
f5244726 | 226 | int kvm_pic_read_irq(struct kvm *kvm) |
85f455f7 ED |
227 | { |
228 | int irq, irq2, intno; | |
f5244726 | 229 | struct kvm_pic *s = pic_irqchip(kvm); |
85f455f7 | 230 | |
50a085bd | 231 | pic_lock(s); |
85f455f7 ED |
232 | irq = pic_get_irq(&s->pics[0]); |
233 | if (irq >= 0) { | |
234 | pic_intack(&s->pics[0], irq); | |
235 | if (irq == 2) { | |
236 | irq2 = pic_get_irq(&s->pics[1]); | |
237 | if (irq2 >= 0) | |
238 | pic_intack(&s->pics[1], irq2); | |
239 | else | |
240 | /* | |
241 | * spurious IRQ on slave controller | |
242 | */ | |
243 | irq2 = 7; | |
244 | intno = s->pics[1].irq_base + irq2; | |
245 | irq = irq2 + 8; | |
246 | } else | |
247 | intno = s->pics[0].irq_base + irq; | |
248 | } else { | |
249 | /* | |
250 | * spurious IRQ on host controller | |
251 | */ | |
252 | irq = 7; | |
253 | intno = s->pics[0].irq_base + irq; | |
254 | } | |
255 | pic_update_irq(s); | |
50a085bd | 256 | pic_unlock(s); |
85f455f7 ED |
257 | |
258 | return intno; | |
259 | } | |
260 | ||
2fcceae1 | 261 | void kvm_pic_reset(struct kvm_kpic_state *s) |
85f455f7 | 262 | { |
79c727d4 | 263 | int irq; |
f5244726 | 264 | struct kvm *kvm = s->pics_state->irq_request_opaque; |
c5af89b6 | 265 | struct kvm_vcpu *vcpu0 = kvm->bsp_vcpu; |
79c727d4 | 266 | u8 irr = s->irr, isr = s->imr; |
f5244726 | 267 | |
85f455f7 ED |
268 | s->last_irr = 0; |
269 | s->irr = 0; | |
270 | s->imr = 0; | |
271 | s->isr = 0; | |
e4825800 | 272 | s->isr_ack = 0xff; |
85f455f7 ED |
273 | s->priority_add = 0; |
274 | s->irq_base = 0; | |
275 | s->read_reg_select = 0; | |
276 | s->poll = 0; | |
277 | s->special_mask = 0; | |
278 | s->init_state = 0; | |
279 | s->auto_eoi = 0; | |
280 | s->rotate_on_auto_eoi = 0; | |
281 | s->special_fully_nested_mode = 0; | |
282 | s->init4 = 0; | |
79c727d4 GN |
283 | |
284 | for (irq = 0; irq < PIC_NUM_PINS/2; irq++) { | |
285 | if (vcpu0 && kvm_apic_accept_pic_intr(vcpu0)) | |
286 | if (irr & (1 << irq) || isr & (1 << irq)) { | |
287 | pic_clear_isr(s, irq); | |
288 | } | |
289 | } | |
85f455f7 ED |
290 | } |
291 | ||
292 | static void pic_ioport_write(void *opaque, u32 addr, u32 val) | |
293 | { | |
294 | struct kvm_kpic_state *s = opaque; | |
295 | int priority, cmd, irq; | |
296 | ||
297 | addr &= 1; | |
298 | if (addr == 0) { | |
299 | if (val & 0x10) { | |
2fcceae1 | 300 | kvm_pic_reset(s); /* init */ |
85f455f7 ED |
301 | /* |
302 | * deassert a pending interrupt | |
303 | */ | |
304 | s->pics_state->irq_request(s->pics_state-> | |
305 | irq_request_opaque, 0); | |
306 | s->init_state = 1; | |
307 | s->init4 = val & 1; | |
308 | if (val & 0x02) | |
309 | printk(KERN_ERR "single mode not supported"); | |
310 | if (val & 0x08) | |
311 | printk(KERN_ERR | |
312 | "level sensitive irq not supported"); | |
313 | } else if (val & 0x08) { | |
314 | if (val & 0x04) | |
315 | s->poll = 1; | |
316 | if (val & 0x02) | |
317 | s->read_reg_select = val & 1; | |
318 | if (val & 0x40) | |
319 | s->special_mask = (val >> 5) & 1; | |
320 | } else { | |
321 | cmd = val >> 5; | |
322 | switch (cmd) { | |
323 | case 0: | |
324 | case 4: | |
325 | s->rotate_on_auto_eoi = cmd >> 2; | |
326 | break; | |
327 | case 1: /* end of interrupt */ | |
328 | case 5: | |
329 | priority = get_priority(s, s->isr); | |
330 | if (priority != 8) { | |
331 | irq = (priority + s->priority_add) & 7; | |
85f455f7 ED |
332 | if (cmd == 5) |
333 | s->priority_add = (irq + 1) & 7; | |
eba0226b | 334 | pic_clear_isr(s, irq); |
85f455f7 ED |
335 | pic_update_irq(s->pics_state); |
336 | } | |
337 | break; | |
338 | case 3: | |
339 | irq = val & 7; | |
7edd0ce0 | 340 | pic_clear_isr(s, irq); |
85f455f7 ED |
341 | pic_update_irq(s->pics_state); |
342 | break; | |
343 | case 6: | |
344 | s->priority_add = (val + 1) & 7; | |
345 | pic_update_irq(s->pics_state); | |
346 | break; | |
347 | case 7: | |
348 | irq = val & 7; | |
85f455f7 | 349 | s->priority_add = (irq + 1) & 7; |
7edd0ce0 | 350 | pic_clear_isr(s, irq); |
85f455f7 ED |
351 | pic_update_irq(s->pics_state); |
352 | break; | |
353 | default: | |
354 | break; /* no operation */ | |
355 | } | |
356 | } | |
357 | } else | |
358 | switch (s->init_state) { | |
359 | case 0: /* normal mode */ | |
360 | s->imr = val; | |
361 | pic_update_irq(s->pics_state); | |
362 | break; | |
363 | case 1: | |
364 | s->irq_base = val & 0xf8; | |
365 | s->init_state = 2; | |
366 | break; | |
367 | case 2: | |
368 | if (s->init4) | |
369 | s->init_state = 3; | |
370 | else | |
371 | s->init_state = 0; | |
372 | break; | |
373 | case 3: | |
374 | s->special_fully_nested_mode = (val >> 4) & 1; | |
375 | s->auto_eoi = (val >> 1) & 1; | |
376 | s->init_state = 0; | |
377 | break; | |
378 | } | |
379 | } | |
380 | ||
381 | static u32 pic_poll_read(struct kvm_kpic_state *s, u32 addr1) | |
382 | { | |
383 | int ret; | |
384 | ||
385 | ret = pic_get_irq(s); | |
386 | if (ret >= 0) { | |
387 | if (addr1 >> 7) { | |
388 | s->pics_state->pics[0].isr &= ~(1 << 2); | |
389 | s->pics_state->pics[0].irr &= ~(1 << 2); | |
390 | } | |
391 | s->irr &= ~(1 << ret); | |
7edd0ce0 | 392 | pic_clear_isr(s, ret); |
85f455f7 ED |
393 | if (addr1 >> 7 || ret != 2) |
394 | pic_update_irq(s->pics_state); | |
395 | } else { | |
396 | ret = 0x07; | |
397 | pic_update_irq(s->pics_state); | |
398 | } | |
399 | ||
400 | return ret; | |
401 | } | |
402 | ||
403 | static u32 pic_ioport_read(void *opaque, u32 addr1) | |
404 | { | |
405 | struct kvm_kpic_state *s = opaque; | |
406 | unsigned int addr; | |
407 | int ret; | |
408 | ||
409 | addr = addr1; | |
410 | addr &= 1; | |
411 | if (s->poll) { | |
412 | ret = pic_poll_read(s, addr1); | |
413 | s->poll = 0; | |
414 | } else | |
415 | if (addr == 0) | |
416 | if (s->read_reg_select) | |
417 | ret = s->isr; | |
418 | else | |
419 | ret = s->irr; | |
420 | else | |
421 | ret = s->imr; | |
422 | return ret; | |
423 | } | |
424 | ||
425 | static void elcr_ioport_write(void *opaque, u32 addr, u32 val) | |
426 | { | |
427 | struct kvm_kpic_state *s = opaque; | |
428 | s->elcr = val & s->elcr_mask; | |
429 | } | |
430 | ||
431 | static u32 elcr_ioport_read(void *opaque, u32 addr1) | |
432 | { | |
433 | struct kvm_kpic_state *s = opaque; | |
434 | return s->elcr; | |
435 | } | |
436 | ||
bda9020e | 437 | static int picdev_in_range(gpa_t addr) |
85f455f7 ED |
438 | { |
439 | switch (addr) { | |
440 | case 0x20: | |
441 | case 0x21: | |
442 | case 0xa0: | |
443 | case 0xa1: | |
444 | case 0x4d0: | |
445 | case 0x4d1: | |
446 | return 1; | |
447 | default: | |
448 | return 0; | |
449 | } | |
450 | } | |
451 | ||
d76685c4 GH |
452 | static inline struct kvm_pic *to_pic(struct kvm_io_device *dev) |
453 | { | |
454 | return container_of(dev, struct kvm_pic, dev); | |
455 | } | |
456 | ||
bda9020e | 457 | static int picdev_write(struct kvm_io_device *this, |
85f455f7 ED |
458 | gpa_t addr, int len, const void *val) |
459 | { | |
d76685c4 | 460 | struct kvm_pic *s = to_pic(this); |
85f455f7 | 461 | unsigned char data = *(unsigned char *)val; |
bda9020e MT |
462 | if (!picdev_in_range(addr)) |
463 | return -EOPNOTSUPP; | |
85f455f7 ED |
464 | |
465 | if (len != 1) { | |
466 | if (printk_ratelimit()) | |
467 | printk(KERN_ERR "PIC: non byte write\n"); | |
bda9020e | 468 | return 0; |
85f455f7 | 469 | } |
50a085bd | 470 | pic_lock(s); |
85f455f7 ED |
471 | switch (addr) { |
472 | case 0x20: | |
473 | case 0x21: | |
474 | case 0xa0: | |
475 | case 0xa1: | |
476 | pic_ioport_write(&s->pics[addr >> 7], addr, data); | |
477 | break; | |
478 | case 0x4d0: | |
479 | case 0x4d1: | |
480 | elcr_ioport_write(&s->pics[addr & 1], addr, data); | |
481 | break; | |
482 | } | |
50a085bd | 483 | pic_unlock(s); |
bda9020e | 484 | return 0; |
85f455f7 ED |
485 | } |
486 | ||
bda9020e MT |
487 | static int picdev_read(struct kvm_io_device *this, |
488 | gpa_t addr, int len, void *val) | |
85f455f7 | 489 | { |
d76685c4 | 490 | struct kvm_pic *s = to_pic(this); |
85f455f7 | 491 | unsigned char data = 0; |
bda9020e MT |
492 | if (!picdev_in_range(addr)) |
493 | return -EOPNOTSUPP; | |
85f455f7 ED |
494 | |
495 | if (len != 1) { | |
496 | if (printk_ratelimit()) | |
497 | printk(KERN_ERR "PIC: non byte read\n"); | |
bda9020e | 498 | return 0; |
85f455f7 | 499 | } |
50a085bd | 500 | pic_lock(s); |
85f455f7 ED |
501 | switch (addr) { |
502 | case 0x20: | |
503 | case 0x21: | |
504 | case 0xa0: | |
505 | case 0xa1: | |
506 | data = pic_ioport_read(&s->pics[addr >> 7], addr); | |
507 | break; | |
508 | case 0x4d0: | |
509 | case 0x4d1: | |
510 | data = elcr_ioport_read(&s->pics[addr & 1], addr); | |
511 | break; | |
512 | } | |
513 | *(unsigned char *)val = data; | |
50a085bd | 514 | pic_unlock(s); |
bda9020e | 515 | return 0; |
85f455f7 ED |
516 | } |
517 | ||
518 | /* | |
519 | * callback when PIC0 irq status changed | |
520 | */ | |
521 | static void pic_irq_request(void *opaque, int level) | |
522 | { | |
523 | struct kvm *kvm = opaque; | |
c5af89b6 | 524 | struct kvm_vcpu *vcpu = kvm->bsp_vcpu; |
e4825800 MT |
525 | struct kvm_pic *s = pic_irqchip(kvm); |
526 | int irq = pic_get_irq(&s->pics[0]); | |
85f455f7 | 527 | |
e4825800 MT |
528 | s->output = level; |
529 | if (vcpu && level && (s->pics[0].isr_ack & (1 << irq))) { | |
530 | s->pics[0].isr_ack &= ~(1 << irq); | |
50a085bd | 531 | s->wakeup_needed = true; |
e4825800 | 532 | } |
85f455f7 ED |
533 | } |
534 | ||
d76685c4 GH |
535 | static const struct kvm_io_device_ops picdev_ops = { |
536 | .read = picdev_read, | |
537 | .write = picdev_write, | |
d76685c4 GH |
538 | }; |
539 | ||
85f455f7 ED |
540 | struct kvm_pic *kvm_create_pic(struct kvm *kvm) |
541 | { | |
542 | struct kvm_pic *s; | |
090b7aff GH |
543 | int ret; |
544 | ||
85f455f7 ED |
545 | s = kzalloc(sizeof(struct kvm_pic), GFP_KERNEL); |
546 | if (!s) | |
547 | return NULL; | |
fa8273e9 | 548 | raw_spin_lock_init(&s->lock); |
3f353858 | 549 | s->kvm = kvm; |
85f455f7 ED |
550 | s->pics[0].elcr_mask = 0xf8; |
551 | s->pics[1].elcr_mask = 0xde; | |
552 | s->irq_request = pic_irq_request; | |
553 | s->irq_request_opaque = kvm; | |
554 | s->pics[0].pics_state = s; | |
555 | s->pics[1].pics_state = s; | |
556 | ||
557 | /* | |
558 | * Initialize PIO device | |
559 | */ | |
d76685c4 | 560 | kvm_iodevice_init(&s->dev, &picdev_ops); |
79fac95e | 561 | mutex_lock(&kvm->slots_lock); |
e93f8a0f | 562 | ret = kvm_io_bus_register_dev(kvm, KVM_PIO_BUS, &s->dev); |
79fac95e | 563 | mutex_unlock(&kvm->slots_lock); |
090b7aff GH |
564 | if (ret < 0) { |
565 | kfree(s); | |
566 | return NULL; | |
567 | } | |
568 | ||
85f455f7 ED |
569 | return s; |
570 | } | |
72bb2fcd WY |
571 | |
572 | void kvm_destroy_pic(struct kvm *kvm) | |
573 | { | |
574 | struct kvm_pic *vpic = kvm->arch.vpic; | |
575 | ||
576 | if (vpic) { | |
577 | kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, &vpic->dev); | |
578 | kvm->arch.vpic = NULL; | |
579 | kfree(vpic); | |
580 | } | |
581 | } |