[linux-2.6-block.git] / arch / x86 / kvm / i8254.c

/*
 * 8253/8254 interval timer emulation
 *
 * Copyright (c) 2003-2004 Fabrice Bellard
 * Copyright (c) 2006 Intel Corporation
 * Copyright (c) 2007 Keir Fraser, XenSource Inc
 * Copyright (c) 2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 *
 * Authors:
 *   Sheng Yang <sheng.yang@intel.com>
 *   Based on QEMU and Xen.
 */

#include <linux/kvm_host.h>

#include "irq.h"
#include "i8254.h"

#ifndef CONFIG_X86_64
#define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
#else
#define mod_64(x, y) ((x) % (y))
#endif

#define RW_STATE_LSB 1
#define RW_STATE_MSB 2
#define RW_STATE_WORD0 3
#define RW_STATE_WORD1 4

/* Compute with 96 bit intermediate result: (a*b)/c */
static u64 muldiv64(u64 a, u32 b, u32 c)
{
	union {
		u64 ll;
		struct {
			u32 low, high;
		} l;
	} u, res;
	u64 rl, rh;

	u.ll = a;
	rl = (u64)u.l.low * (u64)b;
	rh = (u64)u.l.high * (u64)b;
	rh += (rl >> 32);
	res.l.high = div64_u64(rh, c);
	res.l.low = div64_u64(((mod_64(rh, c) << 32) + (rl & 0xffffffff)), c);
	return res.ll;
}

static void pit_set_gate(struct kvm *kvm, int channel, u32 val)
{
	struct kvm_kpit_channel_state *c =
		&kvm->arch.vpit->pit_state.channels[channel];

	WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));

	switch (c->mode) {
	default:
	case 0:
	case 4:
		/* XXX: just disable/enable counting */
		break;
	case 1:
	case 2:
	case 3:
	case 5:
		/* Restart counting on rising edge. */
		if (c->gate < val)
			c->count_load_time = ktime_get();
		break;
	}

	c->gate = val;
}

static int pit_get_gate(struct kvm *kvm, int channel)
{
	WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));

	return kvm->arch.vpit->pit_state.channels[channel].gate;
}

static s64 __kpit_elapsed(struct kvm *kvm)
{
	s64 elapsed;
	ktime_t remaining;
	struct kvm_kpit_state *ps = &kvm->arch.vpit->pit_state;

	if (!ps->pit_timer.period)
		return 0;

	/*
	 * The Counter does not stop when it reaches zero. In
	 * Modes 0, 1, 4, and 5 the Counter ``wraps around'' to
	 * the highest count, either FFFF hex for binary counting
	 * or 9999 for BCD counting, and continues counting.
	 * Modes 2 and 3 are periodic; the Counter reloads
	 * itself with the initial count and continues counting
	 * from there.
	 */
	remaining = hrtimer_expires_remaining(&ps->pit_timer.timer);
	elapsed = ps->pit_timer.period - ktime_to_ns(remaining);
	elapsed = mod_64(elapsed, ps->pit_timer.period);

	return elapsed;
}

static s64 kpit_elapsed(struct kvm *kvm, struct kvm_kpit_channel_state *c,
			int channel)
{
	if (channel == 0)
		return __kpit_elapsed(kvm);

	return ktime_to_ns(ktime_sub(ktime_get(), c->count_load_time));
}

static int pit_get_count(struct kvm *kvm, int channel)
{
	struct kvm_kpit_channel_state *c =
		&kvm->arch.vpit->pit_state.channels[channel];
	s64 d, t;
	int counter;

	WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));

	t = kpit_elapsed(kvm, c, channel);
	d = muldiv64(t, KVM_PIT_FREQ, NSEC_PER_SEC);

	switch (c->mode) {
	case 0:
	case 1:
	case 4:
	case 5:
		counter = (c->count - d) & 0xffff;
		break;
	case 3:
		/* XXX: may be incorrect for odd counts */
		counter = c->count - (mod_64((2 * d), c->count));
		break;
	default:
		counter = c->count - mod_64(d, c->count);
		break;
	}
	return counter;
}

static int pit_get_out(struct kvm *kvm, int channel)
{
	struct kvm_kpit_channel_state *c =
		&kvm->arch.vpit->pit_state.channels[channel];
	s64 d, t;
	int out;

	WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));

	t = kpit_elapsed(kvm, c, channel);
	d = muldiv64(t, KVM_PIT_FREQ, NSEC_PER_SEC);

	switch (c->mode) {
	default:
	case 0:
		out = (d >= c->count);
		break;
	case 1:
		out = (d < c->count);
		break;
	case 2:
		out = ((mod_64(d, c->count) == 0) && (d != 0));
		break;
	case 3:
		out = (mod_64(d, c->count) < ((c->count + 1) >> 1));
		break;
	case 4:
	case 5:
		out = (d == c->count);
		break;
	}

	return out;
}

static void pit_latch_count(struct kvm *kvm, int channel)
{
	struct kvm_kpit_channel_state *c =
		&kvm->arch.vpit->pit_state.channels[channel];

	WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));

	if (!c->count_latched) {
		c->latched_count = pit_get_count(kvm, channel);
		c->count_latched = c->rw_mode;
	}
}

static void pit_latch_status(struct kvm *kvm, int channel)
{
	struct kvm_kpit_channel_state *c =
		&kvm->arch.vpit->pit_state.channels[channel];

	WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));

	if (!c->status_latched) {
		/* TODO: Return NULL COUNT (bit 6). */
		c->status = ((pit_get_out(kvm, channel) << 7) |
				(c->rw_mode << 4) |
				(c->mode << 1) |
				c->bcd);
		c->status_latched = 1;
	}
}

int pit_has_pending_timer(struct kvm_vcpu *vcpu)
{
	struct kvm_pit *pit = vcpu->kvm->arch.vpit;

	if (pit && vcpu->vcpu_id == 0 && pit->pit_state.irq_ack)
		return atomic_read(&pit->pit_state.pit_timer.pending);
	return 0;
}

static void kvm_pit_ack_irq(struct kvm_irq_ack_notifier *kian)
{
	struct kvm_kpit_state *ps = container_of(kian, struct kvm_kpit_state,
						 irq_ack_notifier);
	spin_lock(&ps->inject_lock);
	if (atomic_dec_return(&ps->pit_timer.pending) < 0)
		atomic_inc(&ps->pit_timer.pending);
	ps->irq_ack = 1;
	spin_unlock(&ps->inject_lock);
}

void __kvm_migrate_pit_timer(struct kvm_vcpu *vcpu)
{
	struct kvm_pit *pit = vcpu->kvm->arch.vpit;
	struct hrtimer *timer;

	if (vcpu->vcpu_id != 0 || !pit)
		return;

	timer = &pit->pit_state.pit_timer.timer;
	if (hrtimer_cancel(timer))
		hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
}

static void destroy_pit_timer(struct kvm_timer *pt)
{
	pr_debug("pit: execute del timer!\n");
	hrtimer_cancel(&pt->timer);
}

static bool kpit_is_periodic(struct kvm_timer *ktimer)
{
	struct kvm_kpit_state *ps = container_of(ktimer, struct kvm_kpit_state,
						 pit_timer);
	return ps->is_periodic;
}

static struct kvm_timer_ops kpit_ops = {
	.is_periodic = kpit_is_periodic,
};

static void create_pit_timer(struct kvm_kpit_state *ps, u32 val, int is_period)
{
	struct kvm_timer *pt = &ps->pit_timer;
	s64 interval;

	interval = muldiv64(val, NSEC_PER_SEC, KVM_PIT_FREQ);

	pr_debug("pit: create pit timer, interval is %llu nsec\n", interval);

	/* TODO The new value only affected after the retriggered */
	hrtimer_cancel(&pt->timer);
	pt->period = interval;
	ps->is_periodic = is_period;

	pt->timer.function = kvm_timer_fn;
	pt->t_ops = &kpit_ops;
	pt->kvm = ps->pit->kvm;
	pt->vcpu_id = 0;

	atomic_set(&pt->pending, 0);
	ps->irq_ack = 1;

	hrtimer_start(&pt->timer, ktime_add_ns(ktime_get(), interval),
		      HRTIMER_MODE_ABS);
}

static void pit_load_count(struct kvm *kvm, int channel, u32 val)
{
	struct kvm_kpit_state *ps = &kvm->arch.vpit->pit_state;

	WARN_ON(!mutex_is_locked(&ps->lock));

	pr_debug("pit: load_count val is %d, channel is %d\n", val, channel);

	/*
	 * The largest possible initial count is 0; this is equivalent
	 * to 216 for binary counting and 104 for BCD counting.
	 */
	if (val == 0)
		val = 0x10000;

	ps->channels[channel].count = val;

	if (channel != 0) {
		ps->channels[channel].count_load_time = ktime_get();
		return;
	}

	/* Two types of timer
	 * mode 1 is one shot, mode 2 is period, otherwise del timer */
	switch (ps->channels[0].mode) {
	case 0:
	case 1:
        /* FIXME: enhance mode 4 precision */
	case 4:
		create_pit_timer(ps, val, 0);
		break;
	case 2:
	case 3:
		create_pit_timer(ps, val, 1);
		break;
	default:
		destroy_pit_timer(&ps->pit_timer);
	}
}

void kvm_pit_load_count(struct kvm *kvm, int channel, u32 val)
{
	mutex_lock(&kvm->arch.vpit->pit_state.lock);
	pit_load_count(kvm, channel, val);
	mutex_unlock(&kvm->arch.vpit->pit_state.lock);
}

static void pit_ioport_write(struct kvm_io_device *this,
			     gpa_t addr, int len, const void *data)
{
	struct kvm_pit *pit = (struct kvm_pit *)this->private;
	struct kvm_kpit_state *pit_state = &pit->pit_state;
	struct kvm *kvm = pit->kvm;
	int channel, access;
	struct kvm_kpit_channel_state *s;
	u32 val = *(u32 *) data;

	val  &= 0xff;
	addr &= KVM_PIT_CHANNEL_MASK;

	mutex_lock(&pit_state->lock);

	if (val != 0)
		pr_debug("pit: write addr is 0x%x, len is %d, val is 0x%x\n",
			  (unsigned int)addr, len, val);

	if (addr == 3) {
		channel = val >> 6;
		if (channel == 3) {
			/* Read-Back Command. */
			for (channel = 0; channel < 3; channel++) {
				s = &pit_state->channels[channel];
				if (val & (2 << channel)) {
					if (!(val & 0x20))
						pit_latch_count(kvm, channel);
					if (!(val & 0x10))
						pit_latch_status(kvm, channel);
				}
			}
		} else {
			/* Select Counter <channel>. */
			s = &pit_state->channels[channel];
			access = (val >> 4) & KVM_PIT_CHANNEL_MASK;
			if (access == 0) {
				pit_latch_count(kvm, channel);
			} else {
				s->rw_mode = access;
				s->read_state = access;
				s->write_state = access;
				s->mode = (val >> 1) & 7;
				if (s->mode > 5)
					s->mode -= 4;
				s->bcd = val & 1;
			}
		}
	} else {
		/* Write Count. */
		s = &pit_state->channels[addr];
		switch (s->write_state) {
		default:
		case RW_STATE_LSB:
			pit_load_count(kvm, addr, val);
			break;
		case RW_STATE_MSB:
			pit_load_count(kvm, addr, val << 8);
			break;
		case RW_STATE_WORD0:
			s->write_latch = val;
			s->write_state = RW_STATE_WORD1;
			break;
		case RW_STATE_WORD1:
			pit_load_count(kvm, addr, s->write_latch | (val << 8));
			s->write_state = RW_STATE_WORD0;
			break;
		}
	}

	mutex_unlock(&pit_state->lock);
}

static void pit_ioport_read(struct kvm_io_device *this,
			    gpa_t addr, int len, void *data)
{
	struct kvm_pit *pit = (struct kvm_pit *)this->private;
	struct kvm_kpit_state *pit_state = &pit->pit_state;
	struct kvm *kvm = pit->kvm;
	int ret, count;
	struct kvm_kpit_channel_state *s;

	addr &= KVM_PIT_CHANNEL_MASK;
	s = &pit_state->channels[addr];

	mutex_lock(&pit_state->lock);

	if (s->status_latched) {
		s->status_latched = 0;
		ret = s->status;
	} else if (s->count_latched) {
		switch (s->count_latched) {
		default:
		case RW_STATE_LSB:
			ret = s->latched_count & 0xff;
			s->count_latched = 0;
			break;
		case RW_STATE_MSB:
			ret = s->latched_count >> 8;
			s->count_latched = 0;
			break;
		case RW_STATE_WORD0:
			ret = s->latched_count & 0xff;
			s->count_latched = RW_STATE_MSB;
			break;
		}
	} else {
		switch (s->read_state) {
		default:
		case RW_STATE_LSB:
			count = pit_get_count(kvm, addr);
			ret = count & 0xff;
			break;
		case RW_STATE_MSB:
			count = pit_get_count(kvm, addr);
			ret = (count >> 8) & 0xff;
			break;
		case RW_STATE_WORD0:
			count = pit_get_count(kvm, addr);
			ret = count & 0xff;
			s->read_state = RW_STATE_WORD1;
			break;
		case RW_STATE_WORD1:
			count = pit_get_count(kvm, addr);
			ret = (count >> 8) & 0xff;
			s->read_state = RW_STATE_WORD0;
			break;
		}
	}

	if (len > sizeof(ret))
		len = sizeof(ret);
	memcpy(data, (char *)&ret, len);

	mutex_unlock(&pit_state->lock);
}

static int pit_in_range(struct kvm_io_device *this, gpa_t addr,
			int len, int is_write)
{
	return ((addr >= KVM_PIT_BASE_ADDRESS) &&
		(addr < KVM_PIT_BASE_ADDRESS + KVM_PIT_MEM_LENGTH));
}

static void speaker_ioport_write(struct kvm_io_device *this,
				 gpa_t addr, int len, const void *data)
{
	struct kvm_pit *pit = (struct kvm_pit *)this->private;
	struct kvm_kpit_state *pit_state = &pit->pit_state;
	struct kvm *kvm = pit->kvm;
	u32 val = *(u32 *) data;

	mutex_lock(&pit_state->lock);
	pit_state->speaker_data_on = (val >> 1) & 1;
	pit_set_gate(kvm, 2, val & 1);
	mutex_unlock(&pit_state->lock);
}

static void speaker_ioport_read(struct kvm_io_device *this,
				gpa_t addr, int len, void *data)
{
	struct kvm_pit *pit = (struct kvm_pit *)this->private;
	struct kvm_kpit_state *pit_state = &pit->pit_state;
	struct kvm *kvm = pit->kvm;
	unsigned int refresh_clock;
	int ret;

	/* Refresh clock toggles at about 15us. We approximate as 2^14ns. */
	refresh_clock = ((unsigned int)ktime_to_ns(ktime_get()) >> 14) & 1;

	mutex_lock(&pit_state->lock);
	ret = ((pit_state->speaker_data_on << 1) | pit_get_gate(kvm, 2) |
		(pit_get_out(kvm, 2) << 5) | (refresh_clock << 4));
	if (len > sizeof(ret))
		len = sizeof(ret);
	memcpy(data, (char *)&ret, len);
	mutex_unlock(&pit_state->lock);
}

static int speaker_in_range(struct kvm_io_device *this, gpa_t addr,
			    int len, int is_write)
{
	return (addr == KVM_SPEAKER_BASE_ADDRESS);
}

void kvm_pit_reset(struct kvm_pit *pit)
{
	int i;
	struct kvm_kpit_channel_state *c;

	mutex_lock(&pit->pit_state.lock);
	for (i = 0; i < 3; i++) {
		c = &pit->pit_state.channels[i];
		c->mode = 0xff;
		c->gate = (i != 2);
		pit_load_count(pit->kvm, i, 0);
	}
	mutex_unlock(&pit->pit_state.lock);

	atomic_set(&pit->pit_state.pit_timer.pending, 0);
	pit->pit_state.irq_ack = 1;
}

static void pit_mask_notifer(struct kvm_irq_mask_notifier *kimn, bool mask)
{
	struct kvm_pit *pit = container_of(kimn, struct kvm_pit, mask_notifier);

	if (!mask) {
		atomic_set(&pit->pit_state.pit_timer.pending, 0);
		pit->pit_state.irq_ack = 1;
	}
}

struct kvm_pit *kvm_create_pit(struct kvm *kvm)
{
	struct kvm_pit *pit;
	struct kvm_kpit_state *pit_state;

	pit = kzalloc(sizeof(struct kvm_pit), GFP_KERNEL);
	if (!pit)
		return NULL;

	pit->irq_source_id = kvm_request_irq_source_id(kvm);
	if (pit->irq_source_id < 0) {
		kfree(pit);
		return NULL;
	}

	mutex_init(&pit->pit_state.lock);
	mutex_lock(&pit->pit_state.lock);
	spin_lock_init(&pit->pit_state.inject_lock);

	/* Initialize PIO device */
	pit->dev.read = pit_ioport_read;
	pit->dev.write = pit_ioport_write;
	pit->dev.in_range = pit_in_range;
	pit->dev.private = pit;
	kvm_io_bus_register_dev(&kvm->pio_bus, &pit->dev);

	pit->speaker_dev.read = speaker_ioport_read;
	pit->speaker_dev.write = speaker_ioport_write;
	pit->speaker_dev.in_range = speaker_in_range;
	pit->speaker_dev.private = pit;
	kvm_io_bus_register_dev(&kvm->pio_bus, &pit->speaker_dev);

	kvm->arch.vpit = pit;
	pit->kvm = kvm;

	pit_state = &pit->pit_state;
	pit_state->pit = pit;
	hrtimer_init(&pit_state->pit_timer.timer,
		     CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
	pit_state->irq_ack_notifier.gsi = 0;
	pit_state->irq_ack_notifier.irq_acked = kvm_pit_ack_irq;
	kvm_register_irq_ack_notifier(kvm, &pit_state->irq_ack_notifier);
	pit_state->pit_timer.reinject = true;
	mutex_unlock(&pit->pit_state.lock);

	kvm_pit_reset(pit);

	pit->mask_notifier.func = pit_mask_notifer;
	kvm_register_irq_mask_notifier(kvm, 0, &pit->mask_notifier);

	return pit;
}

void kvm_free_pit(struct kvm *kvm)
{
	struct hrtimer *timer;

	if (kvm->arch.vpit) {
		kvm_unregister_irq_mask_notifier(kvm, 0,
					       &kvm->arch.vpit->mask_notifier);
		mutex_lock(&kvm->arch.vpit->pit_state.lock);
		timer = &kvm->arch.vpit->pit_state.pit_timer.timer;
		hrtimer_cancel(timer);
		kvm_free_irq_source_id(kvm, kvm->arch.vpit->irq_source_id);
		mutex_unlock(&kvm->arch.vpit->pit_state.lock);
		kfree(kvm->arch.vpit);
	}
}

static void __inject_pit_timer_intr(struct kvm *kvm)
{
	struct kvm_vcpu *vcpu;
	int i;

	mutex_lock(&kvm->lock);
	kvm_set_irq(kvm, kvm->arch.vpit->irq_source_id, 0, 1);
	kvm_set_irq(kvm, kvm->arch.vpit->irq_source_id, 0, 0);
	mutex_unlock(&kvm->lock);

	/*
	 * Provides NMI watchdog support via Virtual Wire mode.
	 * The route is: PIT -> PIC -> LVT0 in NMI mode.
	 *
	 * Note: Our Virtual Wire implementation is simplified, only
	 * propagating PIT interrupts to all VCPUs when they have set
	 * LVT0 to NMI delivery. Other PIC interrupts are just sent to
	 * VCPU0, and only if its LVT0 is in EXTINT mode.
	 */
	if (kvm->arch.vapics_in_nmi_mode > 0)
		for (i = 0; i < KVM_MAX_VCPUS; ++i) {
			vcpu = kvm->vcpus[i];
			if (vcpu)
				kvm_apic_nmi_wd_deliver(vcpu);
		}
}

void kvm_inject_pit_timer_irqs(struct kvm_vcpu *vcpu)
{
	struct kvm_pit *pit = vcpu->kvm->arch.vpit;
	struct kvm *kvm = vcpu->kvm;
	struct kvm_kpit_state *ps;

	if (vcpu && pit) {
		int inject = 0;
		ps = &pit->pit_state;

		/* Try to inject pending interrupts when
		 * last one has been acked.
		 */
		spin_lock(&ps->inject_lock);
		if (atomic_read(&ps->pit_timer.pending) && ps->irq_ack) {
			ps->irq_ack = 0;
			inject = 1;
		}
		spin_unlock(&ps->inject_lock);
		if (inject)
			__inject_pit_timer_intr(kvm);
	}
}
Commit	Line	Data
7837699f SY	1	/*
	2	* 8253/8254 interval timer emulation
	3	*
	4	* Copyright (c) 2003-2004 Fabrice Bellard
	5	* Copyright (c) 2006 Intel Corporation
	6	* Copyright (c) 2007 Keir Fraser, XenSource Inc
	7	* Copyright (c) 2008 Intel Corporation
	8	*
	9	* Permission is hereby granted, free of charge, to any person obtaining a copy
	10	* of this software and associated documentation files (the "Software"), to deal
	11	* in the Software without restriction, including without limitation the rights
	12	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	13	* copies of the Software, and to permit persons to whom the Software is
	14	* furnished to do so, subject to the following conditions:
	15	*
	16	* The above copyright notice and this permission notice shall be included in
	17	* all copies or substantial portions of the Software.
	18	*
	19	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	20	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	21	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	22	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	23	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	24	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	25	* THE SOFTWARE.
	26	*
	27	* Authors:
	28	* Sheng Yang <sheng.yang@intel.com>
	29	* Based on QEMU and Xen.
	30	*/
	31
	32	#include <linux/kvm_host.h>
	33
	34	#include "irq.h"
	35	#include "i8254.h"
	36
	37	#ifndef CONFIG_X86_64
6f6d6a1a	38	#define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
7837699f SY	39	#else
	40	#define mod_64(x, y) ((x) % (y))
	41	#endif
	42
	43	#define RW_STATE_LSB 1
	44	#define RW_STATE_MSB 2
	45	#define RW_STATE_WORD0 3
	46	#define RW_STATE_WORD1 4
	47
	48	/* Compute with 96 bit intermediate result: (ab)/c /
	49	static u64 muldiv64(u64 a, u32 b, u32 c)
	50	{
	51	union {
	52	u64 ll;
	53	struct {
	54	u32 low, high;
	55	} l;
	56	} u, res;
	57	u64 rl, rh;
	58
	59	u.ll = a;
	60	rl = (u64)u.l.low * (u64)b;
	61	rh = (u64)u.l.high * (u64)b;
	62	rh += (rl >> 32);
6f6d6a1a RZ	63	res.l.high = div64_u64(rh, c);
6f6d6a1a RZ	64	res.l.low = div64_u64(((mod_64(rh, c) << 32) + (rl & 0xffffffff)), c);
7837699f SY	65	return res.ll;
	66	}
	67
	68	static void pit_set_gate(struct kvm *kvm, int channel, u32 val)
	69	{
	70	struct kvm_kpit_channel_state *c =
	71	&kvm->arch.vpit->pit_state.channels[channel];
	72
	73	WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
	74
	75	switch (c->mode) {
	76	default:
	77	case 0:
	78	case 4:
	79	/* XXX: just disable/enable counting */
	80	break;
	81	case 1:
	82	case 2:
	83	case 3:
	84	case 5:
	85	/* Restart counting on rising edge. */
	86	if (c->gate < val)
	87	c->count_load_time = ktime_get();
	88	break;
	89	}
	90
	91	c->gate = val;
	92	}
	93
8b2cf73c	94	static int pit_get_gate(struct kvm *kvm, int channel)
7837699f SY	95	{
	96	WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
	97
	98	return kvm->arch.vpit->pit_state.channels[channel].gate;
	99	}
	100
fd668423 MT	101	static s64 __kpit_elapsed(struct kvm *kvm)
	102	{
	103	s64 elapsed;
	104	ktime_t remaining;
	105	struct kvm_kpit_state *ps = &kvm->arch.vpit->pit_state;
	106
0ff77873 MT	107	if (!ps->pit_timer.period)
	108	return 0;
	109
ede2ccc5 MT	110	/*
	111	* The Counter does not stop when it reaches zero. In
	112	* Modes 0, 1, 4, and 5 the Counter ``wraps around'' to
	113	* the highest count, either FFFF hex for binary counting
	114	* or 9999 for BCD counting, and continues counting.
	115	* Modes 2 and 3 are periodic; the Counter reloads
	116	* itself with the initial count and continues counting
	117	* from there.
	118	*/
fd668423	119	remaining = hrtimer_expires_remaining(&ps->pit_timer.timer);
ede2ccc5 MT	120	elapsed = ps->pit_timer.period - ktime_to_ns(remaining);
ede2ccc5 MT	121	elapsed = mod_64(elapsed, ps->pit_timer.period);
fd668423 MT	122
	123	return elapsed;
	124	}
	125
	126	static s64 kpit_elapsed(struct kvm kvm, struct kvm_kpit_channel_state c,
	127	int channel)
	128	{
	129	if (channel == 0)
	130	return __kpit_elapsed(kvm);
	131
	132	return ktime_to_ns(ktime_sub(ktime_get(), c->count_load_time));
	133	}
	134
7837699f SY	135	static int pit_get_count(struct kvm *kvm, int channel)
	136	{
	137	struct kvm_kpit_channel_state *c =
	138	&kvm->arch.vpit->pit_state.channels[channel];
	139	s64 d, t;
	140	int counter;
	141
	142	WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
	143
fd668423	144	t = kpit_elapsed(kvm, c, channel);
7837699f SY	145	d = muldiv64(t, KVM_PIT_FREQ, NSEC_PER_SEC);
	146
	147	switch (c->mode) {
	148	case 0:
	149	case 1:
	150	case 4:
	151	case 5:
	152	counter = (c->count - d) & 0xffff;
	153	break;
	154	case 3:
	155	/* XXX: may be incorrect for odd counts */
	156	counter = c->count - (mod_64((2 * d), c->count));
	157	break;
	158	default:
	159	counter = c->count - mod_64(d, c->count);
	160	break;
	161	}
	162	return counter;
	163	}
	164
	165	static int pit_get_out(struct kvm *kvm, int channel)
	166	{
	167	struct kvm_kpit_channel_state *c =
	168	&kvm->arch.vpit->pit_state.channels[channel];
	169	s64 d, t;
	170	int out;
	171
	172	WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
	173
fd668423	174	t = kpit_elapsed(kvm, c, channel);
7837699f SY	175	d = muldiv64(t, KVM_PIT_FREQ, NSEC_PER_SEC);
	176
	177	switch (c->mode) {
	178	default:
	179	case 0:
	180	out = (d >= c->count);
	181	break;
	182	case 1:
	183	out = (d < c->count);
	184	break;
	185	case 2:
	186	out = ((mod_64(d, c->count) == 0) && (d != 0));
	187	break;
	188	case 3:
	189	out = (mod_64(d, c->count) < ((c->count + 1) >> 1));
	190	break;
	191	case 4:
	192	case 5:
	193	out = (d == c->count);
	194	break;
	195	}
	196
	197	return out;
	198	}
	199
	200	static void pit_latch_count(struct kvm *kvm, int channel)
	201	{
	202	struct kvm_kpit_channel_state *c =
	203	&kvm->arch.vpit->pit_state.channels[channel];
	204
	205	WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
	206
	207	if (!c->count_latched) {
	208	c->latched_count = pit_get_count(kvm, channel);
	209	c->count_latched = c->rw_mode;
	210	}
	211	}
	212
	213	static void pit_latch_status(struct kvm *kvm, int channel)
	214	{
	215	struct kvm_kpit_channel_state *c =
	216	&kvm->arch.vpit->pit_state.channels[channel];
	217
	218	WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
	219
	220	if (!c->status_latched) {
	221	/* TODO: Return NULL COUNT (bit 6). */
	222	c->status = ((pit_get_out(kvm, channel) << 7) \|
	223	(c->rw_mode << 4) \|
	224	(c->mode << 1) \|
	225	c->bcd);
	226	c->status_latched = 1;
	227	}
	228	}
	229
3d80840d MT	230	int pit_has_pending_timer(struct kvm_vcpu *vcpu)
	231	{
	232	struct kvm_pit *pit = vcpu->kvm->arch.vpit;
	233
3cf57fed	234	if (pit && vcpu->vcpu_id == 0 && pit->pit_state.irq_ack)
3d80840d	235	return atomic_read(&pit->pit_state.pit_timer.pending);
3d80840d MT	236	return 0;
	237	}
	238
ee032c99	239	static void kvm_pit_ack_irq(struct kvm_irq_ack_notifier *kian)
3cf57fed MT	240	{
	241	struct kvm_kpit_state *ps = container_of(kian, struct kvm_kpit_state,
	242	irq_ack_notifier);
	243	spin_lock(&ps->inject_lock);
	244	if (atomic_dec_return(&ps->pit_timer.pending) < 0)
dc7404ce	245	atomic_inc(&ps->pit_timer.pending);
3cf57fed MT	246	ps->irq_ack = 1;
	247	spin_unlock(&ps->inject_lock);
	248	}
	249
2f599714 MT	250	void __kvm_migrate_pit_timer(struct kvm_vcpu *vcpu)
	251	{
	252	struct kvm_pit *pit = vcpu->kvm->arch.vpit;
	253	struct hrtimer *timer;
	254
	255	if (vcpu->vcpu_id != 0 \|\| !pit)
	256	return;
	257
	258	timer = &pit->pit_state.pit_timer.timer;
	259	if (hrtimer_cancel(timer))
beb20d52	260	hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
2f599714 MT	261	}
2f599714 MT	262
d3c7b77d	263	static void destroy_pit_timer(struct kvm_timer *pt)
7837699f SY	264	{
	265	pr_debug("pit: execute del timer!\n");
	266	hrtimer_cancel(&pt->timer);
	267	}
	268
d3c7b77d MT	269	static bool kpit_is_periodic(struct kvm_timer *ktimer)
	270	{
	271	struct kvm_kpit_state *ps = container_of(ktimer, struct kvm_kpit_state,
	272	pit_timer);
	273	return ps->is_periodic;
	274	}
	275
386eb6e8	276	static struct kvm_timer_ops kpit_ops = {
d3c7b77d MT	277	.is_periodic = kpit_is_periodic,
	278	};
	279
3cf57fed	280	static void create_pit_timer(struct kvm_kpit_state *ps, u32 val, int is_period)
7837699f	281	{
d3c7b77d	282	struct kvm_timer *pt = &ps->pit_timer;
7837699f SY	283	s64 interval;
	284
	285	interval = muldiv64(val, NSEC_PER_SEC, KVM_PIT_FREQ);
	286
	287	pr_debug("pit: create pit timer, interval is %llu nsec\n", interval);
	288
	289	/* TODO The new value only affected after the retriggered */
	290	hrtimer_cancel(&pt->timer);
ede2ccc5	291	pt->period = interval;
d3c7b77d MT	292	ps->is_periodic = is_period;
	293
	294	pt->timer.function = kvm_timer_fn;
	295	pt->t_ops = &kpit_ops;
	296	pt->kvm = ps->pit->kvm;
	297	pt->vcpu_id = 0;
	298
7837699f	299	atomic_set(&pt->pending, 0);
3cf57fed	300	ps->irq_ack = 1;
7837699f SY	301
	302	hrtimer_start(&pt->timer, ktime_add_ns(ktime_get(), interval),
	303	HRTIMER_MODE_ABS);
	304	}
	305
	306	static void pit_load_count(struct kvm *kvm, int channel, u32 val)
	307	{
	308	struct kvm_kpit_state *ps = &kvm->arch.vpit->pit_state;
	309
	310	WARN_ON(!mutex_is_locked(&ps->lock));
	311
	312	pr_debug("pit: load_count val is %d, channel is %d\n", val, channel);
	313
	314	/*
ede2ccc5 MT	315	* The largest possible initial count is 0; this is equivalent
ede2ccc5 MT	316	* to 216 for binary counting and 104 for BCD counting.
7837699f SY	317	*/
	318	if (val == 0)
	319	val = 0x10000;
	320
7837699f SY	321	ps->channels[channel].count = val;
7837699f SY	322
fd668423 MT	323	if (channel != 0) {
fd668423 MT	324	ps->channels[channel].count_load_time = ktime_get();
7837699f	325	return;
fd668423	326	}
7837699f SY	327
	328	/* Two types of timer
	329	* mode 1 is one shot, mode 2 is period, otherwise del timer */
	330	switch (ps->channels[0].mode) {
ede2ccc5	331	case 0:
7837699f	332	case 1:
ece15bab MT	333	/* FIXME: enhance mode 4 precision */
ece15bab MT	334	case 4:
3cf57fed	335	create_pit_timer(ps, val, 0);
7837699f SY	336	break;
7837699f SY	337	case 2:
f6975545	338	case 3:
3cf57fed	339	create_pit_timer(ps, val, 1);
7837699f SY	340	break;
	341	default:
	342	destroy_pit_timer(&ps->pit_timer);
	343	}
	344	}
	345
e0f63cb9 SY	346	void kvm_pit_load_count(struct kvm *kvm, int channel, u32 val)
	347	{
	348	mutex_lock(&kvm->arch.vpit->pit_state.lock);
	349	pit_load_count(kvm, channel, val);
	350	mutex_unlock(&kvm->arch.vpit->pit_state.lock);
	351	}
	352
7837699f SY	353	static void pit_ioport_write(struct kvm_io_device *this,
	354	gpa_t addr, int len, const void *data)
	355	{
	356	struct kvm_pit pit = (struct kvm_pit )this->private;
	357	struct kvm_kpit_state *pit_state = &pit->pit_state;
	358	struct kvm *kvm = pit->kvm;
	359	int channel, access;
	360	struct kvm_kpit_channel_state *s;
	361	u32 val = (u32 ) data;
	362
	363	val &= 0xff;
	364	addr &= KVM_PIT_CHANNEL_MASK;
	365
	366	mutex_lock(&pit_state->lock);
	367
	368	if (val != 0)
	369	pr_debug("pit: write addr is 0x%x, len is %d, val is 0x%x\n",
	370	(unsigned int)addr, len, val);
	371
	372	if (addr == 3) {
	373	channel = val >> 6;
	374	if (channel == 3) {
	375	/* Read-Back Command. */
	376	for (channel = 0; channel < 3; channel++) {
	377	s = &pit_state->channels[channel];
	378	if (val & (2 << channel)) {
	379	if (!(val & 0x20))
	380	pit_latch_count(kvm, channel);
	381	if (!(val & 0x10))
	382	pit_latch_status(kvm, channel);
	383	}
	384	}
	385	} else {
	386	/* Select Counter <channel>. */
	387	s = &pit_state->channels[channel];
	388	access = (val >> 4) & KVM_PIT_CHANNEL_MASK;
	389	if (access == 0) {
	390	pit_latch_count(kvm, channel);
	391	} else {
	392	s->rw_mode = access;
	393	s->read_state = access;
	394	s->write_state = access;
	395	s->mode = (val >> 1) & 7;
	396	if (s->mode > 5)
	397	s->mode -= 4;
	398	s->bcd = val & 1;
	399	}
	400	}
	401	} else {
	402	/* Write Count. */
	403	s = &pit_state->channels[addr];
	404	switch (s->write_state) {
	405	default:
	406	case RW_STATE_LSB:
	407	pit_load_count(kvm, addr, val);
	408	break;
	409	case RW_STATE_MSB:
	410	pit_load_count(kvm, addr, val << 8);
	411	break;
	412	case RW_STATE_WORD0:
	413	s->write_latch = val;
	414	s->write_state = RW_STATE_WORD1;
	415	break;
	416	case RW_STATE_WORD1:
417	pit_load_count(kvm, addr, s->write_latch \| (val << 8));
418	s->write_state = RW_STATE_WORD0;
419	break;
420	}
421	}
422
423	mutex_unlock(&pit_state->lock);
424	}
425
426	static void pit_ioport_read(struct kvm_io_device *this,
427	gpa_t addr, int len, void *data)
428	{
429	struct kvm_pit pit = (struct kvm_pit )this->private;
430	struct kvm_kpit_state *pit_state = &pit->pit_state;
431	struct kvm *kvm = pit->kvm;
432	int ret, count;
433	struct kvm_kpit_channel_state *s;
434
435	addr &= KVM_PIT_CHANNEL_MASK;
436	s = &pit_state->channels[addr];
437
438	mutex_lock(&pit_state->lock);
439
440	if (s->status_latched) {
441	s->status_latched = 0;
442	ret = s->status;
443	} else if (s->count_latched) {
444	switch (s->count_latched) {
445	default:
446	case RW_STATE_LSB:
447	ret = s->latched_count & 0xff;
448	s->count_latched = 0;
449	break;
450	case RW_STATE_MSB:
451	ret = s->latched_count >> 8;
452	s->count_latched = 0;
453	break;
454	case RW_STATE_WORD0:
455	ret = s->latched_count & 0xff;
456	s->count_latched = RW_STATE_MSB;
457	break;
458	}
459	} else {
460	switch (s->read_state) {
461	default:
462	case RW_STATE_LSB:
463	count = pit_get_count(kvm, addr);
464	ret = count & 0xff;
465	break;
466	case RW_STATE_MSB:
467	count = pit_get_count(kvm, addr);
468	ret = (count >> 8) & 0xff;
469	break;
470	case RW_STATE_WORD0:
471	count = pit_get_count(kvm, addr);
472	ret = count & 0xff;
473	s->read_state = RW_STATE_WORD1;
474	break;
475	case RW_STATE_WORD1:
476	count = pit_get_count(kvm, addr);
477	ret = (count >> 8) & 0xff;
478	s->read_state = RW_STATE_WORD0;
479	break;
480	}
481	}
482
483	if (len > sizeof(ret))
484	len = sizeof(ret);
485	memcpy(data, (char *)&ret, len);
486
487	mutex_unlock(&pit_state->lock);
488	}
489
92760499 LV	490	static int pit_in_range(struct kvm_io_device *this, gpa_t addr,
92760499 LV	491	int len, int is_write)
7837699f SY	492	{
	493	return ((addr >= KVM_PIT_BASE_ADDRESS) &&
	494	(addr < KVM_PIT_BASE_ADDRESS + KVM_PIT_MEM_LENGTH));
	495	}
	496
	497	static void speaker_ioport_write(struct kvm_io_device *this,
	498	gpa_t addr, int len, const void *data)
	499	{
	500	struct kvm_pit pit = (struct kvm_pit )this->private;
	501	struct kvm_kpit_state *pit_state = &pit->pit_state;
	502	struct kvm *kvm = pit->kvm;
	503	u32 val = (u32 ) data;
	504
	505	mutex_lock(&pit_state->lock);
	506	pit_state->speaker_data_on = (val >> 1) & 1;
	507	pit_set_gate(kvm, 2, val & 1);
	508	mutex_unlock(&pit_state->lock);
	509	}
	510
	511	static void speaker_ioport_read(struct kvm_io_device *this,
	512	gpa_t addr, int len, void *data)
	513	{
	514	struct kvm_pit pit = (struct kvm_pit )this->private;
	515	struct kvm_kpit_state *pit_state = &pit->pit_state;
	516	struct kvm *kvm = pit->kvm;
	517	unsigned int refresh_clock;
	518	int ret;
	519
	520	/* Refresh clock toggles at about 15us. We approximate as 2^14ns. */
	521	refresh_clock = ((unsigned int)ktime_to_ns(ktime_get()) >> 14) & 1;
	522
	523	mutex_lock(&pit_state->lock);
	524	ret = ((pit_state->speaker_data_on << 1) \| pit_get_gate(kvm, 2) \|
	525	(pit_get_out(kvm, 2) << 5) \| (refresh_clock << 4));
	526	if (len > sizeof(ret))
	527	len = sizeof(ret);
	528	memcpy(data, (char *)&ret, len);
	529	mutex_unlock(&pit_state->lock);
	530	}
	531
92760499 LV	532	static int speaker_in_range(struct kvm_io_device *this, gpa_t addr,
92760499 LV	533	int len, int is_write)
7837699f SY	534	{
	535	return (addr == KVM_SPEAKER_BASE_ADDRESS);
	536	}
	537
308b0f23	538	void kvm_pit_reset(struct kvm_pit *pit)
7837699f SY	539	{
7837699f SY	540	int i;
308b0f23 SY	541	struct kvm_kpit_channel_state *c;
	542
	543	mutex_lock(&pit->pit_state.lock);
	544	for (i = 0; i < 3; i++) {
	545	c = &pit->pit_state.channels[i];
	546	c->mode = 0xff;
	547	c->gate = (i != 2);
	548	pit_load_count(pit->kvm, i, 0);
	549	}
	550	mutex_unlock(&pit->pit_state.lock);
	551
	552	atomic_set(&pit->pit_state.pit_timer.pending, 0);
3cf57fed	553	pit->pit_state.irq_ack = 1;
308b0f23 SY	554	}
308b0f23 SY	555
4780c659 AK	556	static void pit_mask_notifer(struct kvm_irq_mask_notifier *kimn, bool mask)
	557	{
	558	struct kvm_pit *pit = container_of(kimn, struct kvm_pit, mask_notifier);
	559
	560	if (!mask) {
	561	atomic_set(&pit->pit_state.pit_timer.pending, 0);
	562	pit->pit_state.irq_ack = 1;
	563	}
	564	}
	565
308b0f23 SY	566	struct kvm_pit kvm_create_pit(struct kvm kvm)
308b0f23 SY	567	{
7837699f SY	568	struct kvm_pit *pit;
7837699f SY	569	struct kvm_kpit_state *pit_state;
7837699f SY	570
	571	pit = kzalloc(sizeof(struct kvm_pit), GFP_KERNEL);
	572	if (!pit)
	573	return NULL;
	574
5550af4d	575	pit->irq_source_id = kvm_request_irq_source_id(kvm);
e17d1dc0 AK	576	if (pit->irq_source_id < 0) {
e17d1dc0 AK	577	kfree(pit);
5550af4d	578	return NULL;
e17d1dc0	579	}
5550af4d	580
7837699f SY	581	mutex_init(&pit->pit_state.lock);
7837699f SY	582	mutex_lock(&pit->pit_state.lock);
3cf57fed	583	spin_lock_init(&pit->pit_state.inject_lock);
7837699f SY	584
	585	/* Initialize PIO device */
	586	pit->dev.read = pit_ioport_read;
	587	pit->dev.write = pit_ioport_write;
	588	pit->dev.in_range = pit_in_range;
	589	pit->dev.private = pit;
	590	kvm_io_bus_register_dev(&kvm->pio_bus, &pit->dev);
	591
	592	pit->speaker_dev.read = speaker_ioport_read;
	593	pit->speaker_dev.write = speaker_ioport_write;
	594	pit->speaker_dev.in_range = speaker_in_range;
	595	pit->speaker_dev.private = pit;
	596	kvm_io_bus_register_dev(&kvm->pio_bus, &pit->speaker_dev);
	597
	598	kvm->arch.vpit = pit;
	599	pit->kvm = kvm;
	600
	601	pit_state = &pit->pit_state;
	602	pit_state->pit = pit;
	603	hrtimer_init(&pit_state->pit_timer.timer,
	604	CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
3cf57fed MT	605	pit_state->irq_ack_notifier.gsi = 0;
	606	pit_state->irq_ack_notifier.irq_acked = kvm_pit_ack_irq;
	607	kvm_register_irq_ack_notifier(kvm, &pit_state->irq_ack_notifier);
52d939a0	608	pit_state->pit_timer.reinject = true;
7837699f SY	609	mutex_unlock(&pit->pit_state.lock);
7837699f SY	610
308b0f23	611	kvm_pit_reset(pit);
7837699f	612
4780c659 AK	613	pit->mask_notifier.func = pit_mask_notifer;
	614	kvm_register_irq_mask_notifier(kvm, 0, &pit->mask_notifier);
	615
7837699f SY	616	return pit;
	617	}
	618
	619	void kvm_free_pit(struct kvm *kvm)
	620	{
	621	struct hrtimer *timer;
	622
	623	if (kvm->arch.vpit) {
4780c659 AK	624	kvm_unregister_irq_mask_notifier(kvm, 0,
4780c659 AK	625	&kvm->arch.vpit->mask_notifier);
7837699f SY	626	mutex_lock(&kvm->arch.vpit->pit_state.lock);
	627	timer = &kvm->arch.vpit->pit_state.pit_timer.timer;
	628	hrtimer_cancel(timer);
5550af4d	629	kvm_free_irq_source_id(kvm, kvm->arch.vpit->irq_source_id);
7837699f SY	630	mutex_unlock(&kvm->arch.vpit->pit_state.lock);
	631	kfree(kvm->arch.vpit);
	632	}
	633	}
	634
8b2cf73c	635	static void __inject_pit_timer_intr(struct kvm *kvm)
7837699f	636	{
23930f95 JK	637	struct kvm_vcpu *vcpu;
	638	int i;
	639
7837699f	640	mutex_lock(&kvm->lock);
5550af4d SY	641	kvm_set_irq(kvm, kvm->arch.vpit->irq_source_id, 0, 1);
5550af4d SY	642	kvm_set_irq(kvm, kvm->arch.vpit->irq_source_id, 0, 0);
7837699f	643	mutex_unlock(&kvm->lock);
23930f95 JK	644
23930f95 JK	645	/*
8fdb2351 JK	646	* Provides NMI watchdog support via Virtual Wire mode.
	647	* The route is: PIT -> PIC -> LVT0 in NMI mode.
	648	*
	649	* Note: Our Virtual Wire implementation is simplified, only
	650	* propagating PIT interrupts to all VCPUs when they have set
	651	* LVT0 to NMI delivery. Other PIC interrupts are just sent to
	652	* VCPU0, and only if its LVT0 is in EXTINT mode.
23930f95	653	*/
cc6e462c JK	654	if (kvm->arch.vapics_in_nmi_mode > 0)
	655	for (i = 0; i < KVM_MAX_VCPUS; ++i) {
	656	vcpu = kvm->vcpus[i];
	657	if (vcpu)
	658	kvm_apic_nmi_wd_deliver(vcpu);
	659	}
7837699f SY	660	}
	661
	662	void kvm_inject_pit_timer_irqs(struct kvm_vcpu *vcpu)
	663	{
	664	struct kvm_pit *pit = vcpu->kvm->arch.vpit;
	665	struct kvm *kvm = vcpu->kvm;
	666	struct kvm_kpit_state *ps;
	667
	668	if (vcpu && pit) {
3cf57fed	669	int inject = 0;
7837699f SY	670	ps = &pit->pit_state;
7837699f SY	671
3cf57fed MT	672	/* Try to inject pending interrupts when
	673	* last one has been acked.
	674	*/
	675	spin_lock(&ps->inject_lock);
	676	if (atomic_read(&ps->pit_timer.pending) && ps->irq_ack) {
	677	ps->irq_ack = 0;
	678	inject = 1;
7837699f	679	}
3cf57fed MT	680	spin_unlock(&ps->inject_lock);
	681	if (inject)
	682	__inject_pit_timer_intr(kvm);
7837699f SY	683	}
7837699f SY	684	}