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KVM: lapic: sync highest ISR to hardware apic on EOI
[linux-2.6-block.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
b7d491e7 27#include <linux/stringify.h>
6aa8b732 28
3eeb3288 29#include "x86.h"
38ba30ba 30#include "tss.h"
e99f0507 31
a9945549
AK		 32/*
33 * Operand types
34 */
b1ea50b2
AK		 35#define OpNone 0ull
36#define OpImplicit 1ull /* No generic decode */
37#define OpReg 2ull /* Register */
38#define OpMem 3ull /* Memory */
39#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
40#define OpDI 5ull /* ES:DI/EDI/RDI */
41#define OpMem64 6ull /* Memory, 64-bit */
42#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
43#define OpDX 8ull /* DX register */
4dd6a57d
AK		 44#define OpCL 9ull /* CL register (for shifts) */
45#define OpImmByte 10ull /* 8-bit sign extended immediate */
46#define OpOne 11ull /* Implied 1 */
5e2c6883 47#define OpImm 12ull /* Sign extended up to 32-bit immediate */
0fe59128
AK		 48#define OpMem16 13ull /* Memory operand (16-bit). */
49#define OpMem32 14ull /* Memory operand (32-bit). */
50#define OpImmU 15ull /* Immediate operand, zero extended */
51#define OpSI 16ull /* SI/ESI/RSI */
52#define OpImmFAddr 17ull /* Immediate far address */
53#define OpMemFAddr 18ull /* Far address in memory */
54#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 55#define OpES 20ull /* ES */
56#define OpCS 21ull /* CS */
57#define OpSS 22ull /* SS */
58#define OpDS 23ull /* DS */
59#define OpFS 24ull /* FS */
60#define OpGS 25ull /* GS */
28867cee 61#define OpMem8 26ull /* 8-bit zero extended memory operand */
5e2c6883 62#define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
7fa57952 63#define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */
820207c8
AK		 64#define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */
65#define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */
0fe59128
AK		 66
67#define OpBits 5 /* Width of operand field */
b1ea50b2 68#define OpMask ((1ull << OpBits) - 1)
a9945549 69
6aa8b732
AK		 70/*
71 * Opcode effective-address decode tables.
72 * Note that we only emulate instructions that have at least one memory
73 * operand (excluding implicit stack references). We assume that stack
74 * references and instruction fetches will never occur in special memory
75 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
76 * not be handled.
77 */
78
79/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 80#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 81/* Destination operand type. */
a9945549
AK		 82#define DstShift 1
83#define ImplicitOps (OpImplicit << DstShift)
84#define DstReg (OpReg << DstShift)
85#define DstMem (OpMem << DstShift)
86#define DstAcc (OpAcc << DstShift)
87#define DstDI (OpDI << DstShift)
88#define DstMem64 (OpMem64 << DstShift)
89#define DstImmUByte (OpImmUByte << DstShift)
90#define DstDX (OpDX << DstShift)
820207c8 91#define DstAccLo (OpAccLo << DstShift)
a9945549 92#define DstMask (OpMask << DstShift)
6aa8b732 93/* Source operand type. */
0fe59128
AK		 94#define SrcShift 6
95#define SrcNone (OpNone << SrcShift)
96#define SrcReg (OpReg << SrcShift)
97#define SrcMem (OpMem << SrcShift)
98#define SrcMem16 (OpMem16 << SrcShift)
99#define SrcMem32 (OpMem32 << SrcShift)
100#define SrcImm (OpImm << SrcShift)
101#define SrcImmByte (OpImmByte << SrcShift)
102#define SrcOne (OpOne << SrcShift)
103#define SrcImmUByte (OpImmUByte << SrcShift)
104#define SrcImmU (OpImmU << SrcShift)
105#define SrcSI (OpSI << SrcShift)
7fa57952 106#define SrcXLat (OpXLat << SrcShift)
0fe59128
AK		 107#define SrcImmFAddr (OpImmFAddr << SrcShift)
108#define SrcMemFAddr (OpMemFAddr << SrcShift)
109#define SrcAcc (OpAcc << SrcShift)
110#define SrcImmU16 (OpImmU16 << SrcShift)
5e2c6883 111#define SrcImm64 (OpImm64 << SrcShift)
0fe59128 112#define SrcDX (OpDX << SrcShift)
28867cee 113#define SrcMem8 (OpMem8 << SrcShift)
820207c8 114#define SrcAccHi (OpAccHi << SrcShift)
0fe59128 115#define SrcMask (OpMask << SrcShift)
221192bd
MT		 116#define BitOp (1<<11)
117#define MemAbs (1<<12) /* Memory operand is absolute displacement */
118#define String (1<<13) /* String instruction (rep capable) */
119#define Stack (1<<14) /* Stack instruction (push/pop) */
120#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
121#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
122#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
123#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
124#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
045a282c 125#define Escape (5<<15) /* Escape to coprocessor instruction */
221192bd 126#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 127/* Generic ModRM decode. */
128#define ModRM (1<<19)
129/* Destination is only written; never read. */
130#define Mov (1<<20)
d8769fed 131/* Misc flags */
8ea7d6ae 132#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
b51e974f 133#define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */
5a506b12 134#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 135#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 136#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 137#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 138#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 139#define No64 (1<<28)
d5ae7ce8 140#define PageTable (1 << 29) /* instruction used to write page table */
0b789eee 141#define NotImpl (1 << 30) /* instruction is not implemented */
0dc8d10f 142/* Source 2 operand type */
0b789eee 143#define Src2Shift (31)
4dd6a57d 144#define Src2None (OpNone << Src2Shift)
ab2c5ce6 145#define Src2Mem (OpMem << Src2Shift)
4dd6a57d
AK		 146#define Src2CL (OpCL << Src2Shift)
147#define Src2ImmByte (OpImmByte << Src2Shift)
148#define Src2One (OpOne << Src2Shift)
149#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 150#define Src2ES (OpES << Src2Shift)
151#define Src2CS (OpCS << Src2Shift)
152#define Src2SS (OpSS << Src2Shift)
153#define Src2DS (OpDS << Src2Shift)
154#define Src2FS (OpFS << Src2Shift)
155#define Src2GS (OpGS << Src2Shift)
4dd6a57d 156#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 157#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
1c11b376
AK		 158#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
159#define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
160#define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
e28bbd44 161#define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
b6744dc3 162#define NoWrite ((u64)1 << 45) /* No writeback */
fb32b1ed 163#define SrcWrite ((u64)1 << 46) /* Write back src operand */
6aa8b732 164
820207c8 165#define DstXacc (DstAccLo | SrcAccHi | SrcWrite)
6aa8b732 166
d0e53325
AK		 167#define X2(x...) x, x
168#define X3(x...) X2(x), x
169#define X4(x...) X2(x), X2(x)
170#define X5(x...) X4(x), x
171#define X6(x...) X4(x), X2(x)
172#define X7(x...) X4(x), X3(x)
173#define X8(x...) X4(x), X4(x)
174#define X16(x...) X8(x), X8(x)
83babbca 175
e28bbd44
AK		 176#define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
177#define FASTOP_SIZE 8
178
179/*
180 * fastop functions have a special calling convention:
181 *
017da7b6
AK		 182 * dst: rax (in/out)
183 * src: rdx (in/out)
e28bbd44
AK		 184 * src2: rcx (in)
185 * flags: rflags (in/out)
b8c0b6ae 186 * ex: rsi (in:fastop pointer, out:zero if exception)
e28bbd44
AK		 187 *
188 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
189 * different operand sizes can be reached by calculation, rather than a jump
190 * table (which would be bigger than the code).
191 *
192 * fastop functions are declared as taking a never-defined fastop parameter,
193 * so they can't be called from C directly.
194 */
195
196struct fastop;
197
d65b1dee 198struct opcode {
b1ea50b2
AK		 199 u64 flags : 56;
200 u64 intercept : 8;
120df890 201 union {
ef65c889 202 int (*execute)(struct x86_emulate_ctxt *ctxt);
fd0a0d82
MK		 203 const struct opcode *group;
204 const struct group_dual *gdual;
205 const struct gprefix *gprefix;
045a282c 206 const struct escape *esc;
e28bbd44 207 void (*fastop)(struct fastop *fake);
120df890 208 } u;
d09beabd 209 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 210};
211
212struct group_dual {
213 struct opcode mod012[8];
214 struct opcode mod3[8];
d65b1dee
AK		 215};
216
0d7cdee8
AK		 217struct gprefix {
218 struct opcode pfx_no;
219 struct opcode pfx_66;
220 struct opcode pfx_f2;
221 struct opcode pfx_f3;
222};
223
045a282c
GN		 224struct escape {
225 struct opcode op[8];
226 struct opcode high[64];
227};
228
6aa8b732 229/* EFLAGS bit definitions. */
d4c6a154
GN		 230#define EFLG_ID (1<<21)
231#define EFLG_VIP (1<<20)
232#define EFLG_VIF (1<<19)
233#define EFLG_AC (1<<18)
b1d86143
AP		 234#define EFLG_VM (1<<17)
235#define EFLG_RF (1<<16)
d4c6a154
GN		 236#define EFLG_IOPL (3<<12)
237#define EFLG_NT (1<<14)
6aa8b732
AK		 238#define EFLG_OF (1<<11)
239#define EFLG_DF (1<<10)
b1d86143 240#define EFLG_IF (1<<9)
d4c6a154 241#define EFLG_TF (1<<8)
6aa8b732
AK		 242#define EFLG_SF (1<<7)
243#define EFLG_ZF (1<<6)
244#define EFLG_AF (1<<4)
245#define EFLG_PF (1<<2)
246#define EFLG_CF (1<<0)
247
62bd430e
MG		 248#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
249#define EFLG_RESERVED_ONE_MASK 2
250
dd856efa
AK		 251static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
252{
253 if (!(ctxt->regs_valid & (1 << nr))) {
254 ctxt->regs_valid |= 1 << nr;
255 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
256 }
257 return ctxt->_regs[nr];
258}
259
260static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
261{
262 ctxt->regs_valid |= 1 << nr;
263 ctxt->regs_dirty |= 1 << nr;
264 return &ctxt->_regs[nr];
265}
266
267static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
268{
269 reg_read(ctxt, nr);
270 return reg_write(ctxt, nr);
271}
272
273static void writeback_registers(struct x86_emulate_ctxt *ctxt)
274{
275 unsigned reg;
276
277 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
278 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
279}
280
281static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
282{
283 ctxt->regs_dirty = 0;
284 ctxt->regs_valid = 0;
285}
286
6aa8b732
AK		 287/*
288 * These EFLAGS bits are restored from saved value during emulation, and
289 * any changes are written back to the saved value after emulation.
290 */
291#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
292
dda96d8f
AK		 293#ifdef CONFIG_X86_64
294#define ON64(x) x
295#else
296#define ON64(x)
297#endif
298
4d758349
AK		 299static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));
300
b7d491e7
AK		 301#define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t"
302#define FOP_RET "ret \n\t"
303
304#define FOP_START(op) \
305 extern void em_##op(struct fastop *fake); \
306 asm(".pushsection .text, \"ax\" \n\t" \
307 ".global em_" #op " \n\t" \
308 FOP_ALIGN \
309 "em_" #op ": \n\t"
310
311#define FOP_END \
312 ".popsection")
313
0bdea068
AK		 314#define FOPNOP() FOP_ALIGN FOP_RET
315
b7d491e7 316#define FOP1E(op, dst) \
b8c0b6ae
AK		 317 FOP_ALIGN "10: " #op " %" #dst " \n\t" FOP_RET
318
319#define FOP1EEX(op, dst) \
320 FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception)
b7d491e7
AK		 321
322#define FASTOP1(op) \
323 FOP_START(op) \
324 FOP1E(op##b, al) \
325 FOP1E(op##w, ax) \
326 FOP1E(op##l, eax) \
327 ON64(FOP1E(op##q, rax)) \
328 FOP_END
329
b9fa409b
AK		 330/* 1-operand, using src2 (for MUL/DIV r/m) */
331#define FASTOP1SRC2(op, name) \
332 FOP_START(name) \
333 FOP1E(op, cl) \
334 FOP1E(op, cx) \
335 FOP1E(op, ecx) \
336 ON64(FOP1E(op, rcx)) \
337 FOP_END
338
b8c0b6ae
AK		 339/* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */
340#define FASTOP1SRC2EX(op, name) \
341 FOP_START(name) \
342 FOP1EEX(op, cl) \
343 FOP1EEX(op, cx) \
344 FOP1EEX(op, ecx) \
345 ON64(FOP1EEX(op, rcx)) \
346 FOP_END
347
f7857f35
AK		 348#define FOP2E(op, dst, src) \
349 FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET
350
351#define FASTOP2(op) \
352 FOP_START(op) \
017da7b6
AK		 353 FOP2E(op##b, al, dl) \
354 FOP2E(op##w, ax, dx) \
355 FOP2E(op##l, eax, edx) \
356 ON64(FOP2E(op##q, rax, rdx)) \
f7857f35
AK		 357 FOP_END
358
11c363ba
AK		 359/* 2 operand, word only */
360#define FASTOP2W(op) \
361 FOP_START(op) \
362 FOPNOP() \
017da7b6
AK		 363 FOP2E(op##w, ax, dx) \
364 FOP2E(op##l, eax, edx) \
365 ON64(FOP2E(op##q, rax, rdx)) \
11c363ba
AK		 366 FOP_END
367
007a3b54
AK		 368/* 2 operand, src is CL */
369#define FASTOP2CL(op) \
370 FOP_START(op) \
371 FOP2E(op##b, al, cl) \
372 FOP2E(op##w, ax, cl) \
373 FOP2E(op##l, eax, cl) \
374 ON64(FOP2E(op##q, rax, cl)) \
375 FOP_END
376
0bdea068
AK		 377#define FOP3E(op, dst, src, src2) \
378 FOP_ALIGN #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET
379
380/* 3-operand, word-only, src2=cl */
381#define FASTOP3WCL(op) \
382 FOP_START(op) \
383 FOPNOP() \
017da7b6
AK		 384 FOP3E(op##w, ax, dx, cl) \
385 FOP3E(op##l, eax, edx, cl) \
386 ON64(FOP3E(op##q, rax, rdx, cl)) \
0bdea068
AK		 387 FOP_END
388
9ae9feba
AK		 389/* Special case for SETcc - 1 instruction per cc */
390#define FOP_SETCC(op) ".align 4; " #op " %al; ret \n\t"
391
b8c0b6ae
AK		 392asm(".global kvm_fastop_exception \n"
393 "kvm_fastop_exception: xor %esi, %esi; ret");
394
9ae9feba
AK		 395FOP_START(setcc)
396FOP_SETCC(seto)
397FOP_SETCC(setno)
398FOP_SETCC(setc)
399FOP_SETCC(setnc)
400FOP_SETCC(setz)
401FOP_SETCC(setnz)
402FOP_SETCC(setbe)
403FOP_SETCC(setnbe)
404FOP_SETCC(sets)
405FOP_SETCC(setns)
406FOP_SETCC(setp)
407FOP_SETCC(setnp)
408FOP_SETCC(setl)
409FOP_SETCC(setnl)
410FOP_SETCC(setle)
411FOP_SETCC(setnle)
412FOP_END;
413
326f578f
PB		 414FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET
415FOP_END;
416
8a76d7f2
JR		 417static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
418 enum x86_intercept intercept,
419 enum x86_intercept_stage stage)
420{
421 struct x86_instruction_info info = {
422 .intercept = intercept,
9dac77fa
AK		 423 .rep_prefix = ctxt->rep_prefix,
424 .modrm_mod = ctxt->modrm_mod,
425 .modrm_reg = ctxt->modrm_reg,
426 .modrm_rm = ctxt->modrm_rm,
427 .src_val = ctxt->src.val64,
428 .src_bytes = ctxt->src.bytes,
429 .dst_bytes = ctxt->dst.bytes,
430 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 431 .next_rip = ctxt->eip,
432 };
433
2953538e 434 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 435}
436
f47cfa31
AK		 437static void assign_masked(ulong *dest, ulong src, ulong mask)
438{
439 *dest = (*dest & ~mask) | (src & mask);
440}
441
9dac77fa 442static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 443{
9dac77fa 444 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 445}
446
f47cfa31
AK		 447static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
448{
449 u16 sel;
450 struct desc_struct ss;
451
452 if (ctxt->mode == X86EMUL_MODE_PROT64)
453 return ~0UL;
454 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
455 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
456}
457
612e89f0
AK		 458static int stack_size(struct x86_emulate_ctxt *ctxt)
459{
460 return (__fls(stack_mask(ctxt)) + 1) >> 3;
461}
462
6aa8b732 463/* Access/update address held in a register, based on addressing mode. */
e4706772 464static inline unsigned long
9dac77fa 465address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 466{
9dac77fa 467 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 468 return reg;
469 else
9dac77fa 470 return reg & ad_mask(ctxt);
e4706772
HH		 471}
472
473static inline unsigned long
9dac77fa 474register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 475{
9dac77fa 476 return address_mask(ctxt, reg);
e4706772
HH		 477}
478
5ad105e5
AK		 479static void masked_increment(ulong *reg, ulong mask, int inc)
480{
481 assign_masked(reg, *reg + inc, mask);
482}
483
7a957275 484static inline void
9dac77fa 485register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
7a957275 486{
5ad105e5
AK		 487 ulong mask;
488
9dac77fa 489 if (ctxt->ad_bytes == sizeof(unsigned long))
5ad105e5 490 mask = ~0UL;
7a957275 491 else
5ad105e5
AK		 492 mask = ad_mask(ctxt);
493 masked_increment(reg, mask, inc);
494}
495
496static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
497{
dd856efa 498 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
7a957275 499}
6aa8b732 500
9dac77fa 501static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
7a957275 502{
9dac77fa 503 register_address_increment(ctxt, &ctxt->_eip, rel);
7a957275 504}
098c937b 505
56697687
AK		 506static u32 desc_limit_scaled(struct desc_struct *desc)
507{
508 u32 limit = get_desc_limit(desc);
509
510 return desc->g ? (limit << 12) | 0xfff : limit;
511}
512
9dac77fa 513static void set_seg_override(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df 514{
9dac77fa
AK		 515 ctxt->has_seg_override = true;
516 ctxt->seg_override = seg;
7a5b56df
AK		 517}
518
7b105ca2 519static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 520{
521 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
522 return 0;
523
7b105ca2 524 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 525}
526
9dac77fa 527static unsigned seg_override(struct x86_emulate_ctxt *ctxt)
7a5b56df 528{
9dac77fa 529 if (!ctxt->has_seg_override)
7a5b56df
AK		 530 return 0;
531
9dac77fa 532 return ctxt->seg_override;
7a5b56df
AK		 533}
534
35d3d4a1
AK		 535static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
536 u32 error, bool valid)
54b8486f 537{
da9cb575
AK		 538 ctxt->exception.vector = vec;
539 ctxt->exception.error_code = error;
540 ctxt->exception.error_code_valid = valid;
35d3d4a1 541 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 542}
543
3b88e41a
JR		 544static int emulate_db(struct x86_emulate_ctxt *ctxt)
545{
546 return emulate_exception(ctxt, DB_VECTOR, 0, false);
547}
548
35d3d4a1 549static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 550{
35d3d4a1 551 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 552}
553
618ff15d
AK		 554static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
555{
556 return emulate_exception(ctxt, SS_VECTOR, err, true);
557}
558
35d3d4a1 559static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 560{
35d3d4a1 561 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 562}
563
35d3d4a1 564static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 565{
35d3d4a1 566 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 567}
568
34d1f490
AK		 569static int emulate_de(struct x86_emulate_ctxt *ctxt)
570{
35d3d4a1 571 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 572}
573
1253791d
AK		 574static int emulate_nm(struct x86_emulate_ctxt *ctxt)
575{
576 return emulate_exception(ctxt, NM_VECTOR, 0, false);
577}
578
1aa36616
AK		 579static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
580{
581 u16 selector;
582 struct desc_struct desc;
583
584 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
585 return selector;
586}
587
588static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
589 unsigned seg)
590{
591 u16 dummy;
592 u32 base3;
593 struct desc_struct desc;
594
595 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
596 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
597}
598
1c11b376
AK		 599/*
600 * x86 defines three classes of vector instructions: explicitly
601 * aligned, explicitly unaligned, and the rest, which change behaviour
602 * depending on whether they're AVX encoded or not.
603 *
604 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
605 * subject to the same check.
606 */
607static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
608{
609 if (likely(size < 16))
610 return false;
611
612 if (ctxt->d & Aligned)
613 return true;
614 else if (ctxt->d & Unaligned)
615 return false;
616 else if (ctxt->d & Avx)
617 return false;
618 else
619 return true;
620}
621
3d9b938e 622static int __linearize(struct x86_emulate_ctxt *ctxt,
52fd8b44 623 struct segmented_address addr,
3d9b938e 624 unsigned size, bool write, bool fetch,
52fd8b44
AK		 625 ulong *linear)
626{
618ff15d
AK		 627 struct desc_struct desc;
628 bool usable;
52fd8b44 629 ulong la;
618ff15d 630 u32 lim;
1aa36616 631 u16 sel;
3a78a4f4 632 unsigned cpl;
52fd8b44 633
7b105ca2 634 la = seg_base(ctxt, addr.seg) + addr.ea;
618ff15d 635 switch (ctxt->mode) {
618ff15d
AK		 636 case X86EMUL_MODE_PROT64:
637 if (((signed long)la << 16) >> 16 != la)
638 return emulate_gp(ctxt, 0);
639 break;
640 default:
1aa36616
AK		 641 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
642 addr.seg);
618ff15d
AK		 643 if (!usable)
644 goto bad;
58b7825b
GN		 645 /* code segment in protected mode or read-only data segment */
646 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
647 || !(desc.type & 2)) && write)
618ff15d
AK		 648 goto bad;
649 /* unreadable code segment */
3d9b938e 650 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 651 goto bad;
652 lim = desc_limit_scaled(&desc);
653 if ((desc.type & 8) || !(desc.type & 4)) {
654 /* expand-up segment */
655 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
656 goto bad;
657 } else {
fc058680 658 /* expand-down segment */
618ff15d
AK		 659 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
660 goto bad;
661 lim = desc.d ? 0xffffffff : 0xffff;
662 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
663 goto bad;
664 }
717746e3 665 cpl = ctxt->ops->cpl(ctxt);
618ff15d
AK		 666 if (!(desc.type & 8)) {
667 /* data segment */
668 if (cpl > desc.dpl)
669 goto bad;
670 } else if ((desc.type & 8) && !(desc.type & 4)) {
671 /* nonconforming code segment */
672 if (cpl != desc.dpl)
673 goto bad;
674 } else if ((desc.type & 8) && (desc.type & 4)) {
675 /* conforming code segment */
676 if (cpl < desc.dpl)
677 goto bad;
678 }
679 break;
680 }
9dac77fa 681 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
52fd8b44 682 la &= (u32)-1;
1c11b376
AK		 683 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
684 return emulate_gp(ctxt, 0);
52fd8b44
AK		 685 *linear = la;
686 return X86EMUL_CONTINUE;
618ff15d
AK		 687bad:
688 if (addr.seg == VCPU_SREG_SS)
0afbe2f8 689 return emulate_ss(ctxt, sel);
618ff15d 690 else
0afbe2f8 691 return emulate_gp(ctxt, sel);
52fd8b44
AK		 692}
693
3d9b938e
NE		 694static int linearize(struct x86_emulate_ctxt *ctxt,
695 struct segmented_address addr,
696 unsigned size, bool write,
697 ulong *linear)
698{
699 return __linearize(ctxt, addr, size, write, false, linear);
700}
701
702
3ca3ac4d
AK		 703static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
704 struct segmented_address addr,
705 void *data,
706 unsigned size)
707{
9fa088f4
AK		 708 int rc;
709 ulong linear;
710
83b8795a 711 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 712 if (rc != X86EMUL_CONTINUE)
713 return rc;
0f65dd70 714 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 715}
716
807941b1
TY		 717/*
718 * Fetch the next byte of the instruction being emulated which is pointed to
719 * by ctxt->_eip, then increment ctxt->_eip.
720 *
721 * Also prefetch the remaining bytes of the instruction without crossing page
722 * boundary if they are not in fetch_cache yet.
723 */
724static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest)
62266869 725{
9dac77fa 726 struct fetch_cache *fc = &ctxt->fetch;
62266869 727 int rc;
2fb53ad8 728 int size, cur_size;
62266869 729
807941b1 730 if (ctxt->_eip == fc->end) {
3d9b938e 731 unsigned long linear;
807941b1
TY		 732 struct segmented_address addr = { .seg = VCPU_SREG_CS,
733 .ea = ctxt->_eip };
2fb53ad8 734 cur_size = fc->end - fc->start;
807941b1
TY		 735 size = min(15UL - cur_size,
736 PAGE_SIZE - offset_in_page(ctxt->_eip));
3d9b938e 737 rc = __linearize(ctxt, addr, size, false, true, &linear);
7d88bb48 738 if (unlikely(rc != X86EMUL_CONTINUE))
3d9b938e 739 return rc;
ef5d75cc
TY		 740 rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size,
741 size, &ctxt->exception);
7d88bb48 742 if (unlikely(rc != X86EMUL_CONTINUE))
62266869 743 return rc;
2fb53ad8 744 fc->end += size;
62266869 745 }
807941b1
TY		 746 *dest = fc->data[ctxt->_eip - fc->start];
747 ctxt->_eip++;
3e2815e9 748 return X86EMUL_CONTINUE;
62266869
AK		 749}
750
751static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
807941b1 752 void *dest, unsigned size)
62266869 753{
3e2815e9 754 int rc;
62266869 755
eb3c79e6 756 /* x86 instructions are limited to 15 bytes. */
7d88bb48 757 if (unlikely(ctxt->_eip + size - ctxt->eip > 15))
eb3c79e6 758 return X86EMUL_UNHANDLEABLE;
62266869 759 while (size--) {
807941b1 760 rc = do_insn_fetch_byte(ctxt, dest++);
3e2815e9 761 if (rc != X86EMUL_CONTINUE)
62266869
AK		 762 return rc;
763 }
3e2815e9 764 return X86EMUL_CONTINUE;
62266869
AK		 765}
766
67cbc90d 767/* Fetch next part of the instruction being emulated. */
e85a1085 768#define insn_fetch(_type, _ctxt) \
67cbc90d 769({ unsigned long _x; \
e85a1085 770 rc = do_insn_fetch(_ctxt, &_x, sizeof(_type)); \
67cbc90d
TY		 771 if (rc != X86EMUL_CONTINUE) \
772 goto done; \
67cbc90d
TY		 773 (_type)_x; \
774})
775
807941b1
TY		 776#define insn_fetch_arr(_arr, _size, _ctxt) \
777({ rc = do_insn_fetch(_ctxt, _arr, (_size)); \
67cbc90d
TY		 778 if (rc != X86EMUL_CONTINUE) \
779 goto done; \
67cbc90d
TY		 780})
781
1e3c5cb0
RR		 782/*
783 * Given the 'reg' portion of a ModRM byte, and a register block, return a
784 * pointer into the block that addresses the relevant register.
785 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
786 */
dd856efa 787static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
aa9ac1a6 788 int byteop)
6aa8b732
AK		 789{
790 void *p;
aa9ac1a6 791 int highbyte_regs = (ctxt->rex_prefix == 0) && byteop;
6aa8b732 792
6aa8b732 793 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
dd856efa
AK		 794 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
795 else
796 p = reg_rmw(ctxt, modrm_reg);
6aa8b732
AK		 797 return p;
798}
799
800static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 801 struct segmented_address addr,
6aa8b732
AK		 802 u16 *size, unsigned long *address, int op_bytes)
803{
804 int rc;
805
806 if (op_bytes == 2)
807 op_bytes = 3;
808 *address = 0;
3ca3ac4d 809 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 810 if (rc != X86EMUL_CONTINUE)
6aa8b732 811 return rc;
30b31ab6 812 addr.ea += 2;
3ca3ac4d 813 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 814 return rc;
815}
816
34b77652
AK		 817FASTOP2(add);
818FASTOP2(or);
819FASTOP2(adc);
820FASTOP2(sbb);
821FASTOP2(and);
822FASTOP2(sub);
823FASTOP2(xor);
824FASTOP2(cmp);
825FASTOP2(test);
826
b9fa409b
AK		 827FASTOP1SRC2(mul, mul_ex);
828FASTOP1SRC2(imul, imul_ex);
b8c0b6ae
AK		 829FASTOP1SRC2EX(div, div_ex);
830FASTOP1SRC2EX(idiv, idiv_ex);
b9fa409b 831
34b77652
AK		 832FASTOP3WCL(shld);
833FASTOP3WCL(shrd);
834
835FASTOP2W(imul);
836
837FASTOP1(not);
838FASTOP1(neg);
839FASTOP1(inc);
840FASTOP1(dec);
841
842FASTOP2CL(rol);
843FASTOP2CL(ror);
844FASTOP2CL(rcl);
845FASTOP2CL(rcr);
846FASTOP2CL(shl);
847FASTOP2CL(shr);
848FASTOP2CL(sar);
849
850FASTOP2W(bsf);
851FASTOP2W(bsr);
852FASTOP2W(bt);
853FASTOP2W(bts);
854FASTOP2W(btr);
855FASTOP2W(btc);
856
e47a5f5f
AK		 857FASTOP2(xadd);
858
9ae9feba 859static u8 test_cc(unsigned int condition, unsigned long flags)
bbe9abbd 860{
9ae9feba
AK		 861 u8 rc;
862 void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
bbe9abbd 863
9ae9feba 864 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
3f0c3d0b 865 asm("push %[flags]; popf; call *%[fastop]"
9ae9feba
AK		 866 : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags));
867 return rc;
bbe9abbd
NK		 868}
869
91ff3cb4
AK		 870static void fetch_register_operand(struct operand *op)
871{
872 switch (op->bytes) {
873 case 1:
874 op->val = *(u8 *)op->addr.reg;
875 break;
876 case 2:
877 op->val = *(u16 *)op->addr.reg;
878 break;
879 case 4:
880 op->val = *(u32 *)op->addr.reg;
881 break;
882 case 8:
883 op->val = *(u64 *)op->addr.reg;
884 break;
885 }
886}
887
1253791d
AK		 888static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
889{
890 ctxt->ops->get_fpu(ctxt);
891 switch (reg) {
89a87c67
MK		 892 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
893 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
894 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
895 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
896 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
897 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
898 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
899 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
1253791d 900#ifdef CONFIG_X86_64
89a87c67
MK		 901 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
902 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
903 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
904 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
905 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
906 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
907 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
908 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
1253791d
AK		 909#endif
910 default: BUG();
911 }
912 ctxt->ops->put_fpu(ctxt);
913}
914
915static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
916 int reg)
917{
918 ctxt->ops->get_fpu(ctxt);
919 switch (reg) {
89a87c67
MK		 920 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
921 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
922 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
923 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
924 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
925 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
926 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
927 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
1253791d 928#ifdef CONFIG_X86_64
89a87c67
MK		 929 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
930 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
931 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
932 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
933 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
934 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
935 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
936 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
1253791d
AK		 937#endif
938 default: BUG();
939 }
940 ctxt->ops->put_fpu(ctxt);
941}
942
cbe2c9d3
AK		 943static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
944{
945 ctxt->ops->get_fpu(ctxt);
946 switch (reg) {
947 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
948 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
949 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
950 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
951 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
952 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
953 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
954 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
955 default: BUG();
956 }
957 ctxt->ops->put_fpu(ctxt);
958}
959
960static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
961{
962 ctxt->ops->get_fpu(ctxt);
963 switch (reg) {
964 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
965 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
966 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
967 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
968 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
969 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
970 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
971 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
972 default: BUG();
973 }
974 ctxt->ops->put_fpu(ctxt);
975}
976
045a282c
GN		 977static int em_fninit(struct x86_emulate_ctxt *ctxt)
978{
979 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
980 return emulate_nm(ctxt);
981
982 ctxt->ops->get_fpu(ctxt);
983 asm volatile("fninit");
984 ctxt->ops->put_fpu(ctxt);
985 return X86EMUL_CONTINUE;
986}
987
988static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
989{
990 u16 fcw;
991
992 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
993 return emulate_nm(ctxt);
994
995 ctxt->ops->get_fpu(ctxt);
996 asm volatile("fnstcw %0": "+m"(fcw));
997 ctxt->ops->put_fpu(ctxt);
998
999 /* force 2 byte destination */
1000 ctxt->dst.bytes = 2;
1001 ctxt->dst.val = fcw;
1002
1003 return X86EMUL_CONTINUE;
1004}
1005
1006static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
1007{
1008 u16 fsw;
1009
1010 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1011 return emulate_nm(ctxt);
1012
1013 ctxt->ops->get_fpu(ctxt);
1014 asm volatile("fnstsw %0": "+m"(fsw));
1015 ctxt->ops->put_fpu(ctxt);
1016
1017 /* force 2 byte destination */
1018 ctxt->dst.bytes = 2;
1019 ctxt->dst.val = fsw;
1020
1021 return X86EMUL_CONTINUE;
1022}
1023
1253791d 1024static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 1025 struct operand *op)
3c118e24 1026{
9dac77fa 1027 unsigned reg = ctxt->modrm_reg;
33615aa9 1028
9dac77fa
AK		 1029 if (!(ctxt->d & ModRM))
1030 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 1031
9dac77fa 1032 if (ctxt->d & Sse) {
1253791d
AK		 1033 op->type = OP_XMM;
1034 op->bytes = 16;
1035 op->addr.xmm = reg;
1036 read_sse_reg(ctxt, &op->vec_val, reg);
1037 return;
1038 }
cbe2c9d3
AK		 1039 if (ctxt->d & Mmx) {
1040 reg &= 7;
1041 op->type = OP_MM;
1042 op->bytes = 8;
1043 op->addr.mm = reg;
1044 return;
1045 }
1253791d 1046
3c118e24 1047 op->type = OP_REG;
6d4d85ec
GN		 1048 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1049 op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp);
1050
91ff3cb4 1051 fetch_register_operand(op);
3c118e24
AK		 1052 op->orig_val = op->val;
1053}
1054
a6e3407b
AK		 1055static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1056{
1057 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1058 ctxt->modrm_seg = VCPU_SREG_SS;
1059}
1060
1c73ef66 1061static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1062 struct operand *op)
1c73ef66 1063{
1c73ef66 1064 u8 sib;
f5b4edcd 1065 int index_reg = 0, base_reg = 0, scale;
3e2815e9 1066 int rc = X86EMUL_CONTINUE;
2dbd0dd7 1067 ulong modrm_ea = 0;
1c73ef66 1068
9dac77fa
AK		 1069 if (ctxt->rex_prefix) {
1070 ctxt->modrm_reg = (ctxt->rex_prefix & 4) << 1; /* REX.R */
1071 index_reg = (ctxt->rex_prefix & 2) << 2; /* REX.X */
1072 ctxt->modrm_rm = base_reg = (ctxt->rex_prefix & 1) << 3; /* REG.B */
1c73ef66
AK		 1073 }
1074
9dac77fa
AK		 1075 ctxt->modrm_mod |= (ctxt->modrm & 0xc0) >> 6;
1076 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
1077 ctxt->modrm_rm |= (ctxt->modrm & 0x07);
1078 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 1079
9dac77fa 1080 if (ctxt->modrm_mod == 3) {
2dbd0dd7 1081 op->type = OP_REG;
9dac77fa 1082 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
8acb4207 1083 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm,
aa9ac1a6 1084 ctxt->d & ByteOp);
9dac77fa 1085 if (ctxt->d & Sse) {
1253791d
AK		 1086 op->type = OP_XMM;
1087 op->bytes = 16;
9dac77fa
AK		 1088 op->addr.xmm = ctxt->modrm_rm;
1089 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 1090 return rc;
1091 }
cbe2c9d3
AK		 1092 if (ctxt->d & Mmx) {
1093 op->type = OP_MM;
1094 op->bytes = 8;
1095 op->addr.xmm = ctxt->modrm_rm & 7;
1096 return rc;
1097 }
2dbd0dd7 1098 fetch_register_operand(op);
1c73ef66
AK		 1099 return rc;
1100 }
1101
2dbd0dd7
AK		 1102 op->type = OP_MEM;
1103
9dac77fa 1104 if (ctxt->ad_bytes == 2) {
dd856efa
AK		 1105 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1106 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1107 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1108 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1c73ef66
AK		 1109
1110 /* 16-bit ModR/M decode. */
9dac77fa 1111 switch (ctxt->modrm_mod) {
1c73ef66 1112 case 0:
9dac77fa 1113 if (ctxt->modrm_rm == 6)
e85a1085 1114 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1115 break;
1116 case 1:
e85a1085 1117 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1118 break;
1119 case 2:
e85a1085 1120 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1121 break;
1122 }
9dac77fa 1123 switch (ctxt->modrm_rm) {
1c73ef66 1124 case 0:
2dbd0dd7 1125 modrm_ea += bx + si;
1c73ef66
AK		 1126 break;
1127 case 1:
2dbd0dd7 1128 modrm_ea += bx + di;
1c73ef66
AK		 1129 break;
1130 case 2:
2dbd0dd7 1131 modrm_ea += bp + si;
1c73ef66
AK		 1132 break;
1133 case 3:
2dbd0dd7 1134 modrm_ea += bp + di;
1c73ef66
AK		 1135 break;
1136 case 4:
2dbd0dd7 1137 modrm_ea += si;
1c73ef66
AK		 1138 break;
1139 case 5:
2dbd0dd7 1140 modrm_ea += di;
1c73ef66
AK		 1141 break;
1142 case 6:
9dac77fa 1143 if (ctxt->modrm_mod != 0)
2dbd0dd7 1144 modrm_ea += bp;
1c73ef66
AK		 1145 break;
1146 case 7:
2dbd0dd7 1147 modrm_ea += bx;
1c73ef66
AK		 1148 break;
1149 }
9dac77fa
AK		 1150 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1151 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1152 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1153 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1154 } else {
1155 /* 32/64-bit ModR/M decode. */
9dac77fa 1156 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1157 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1158 index_reg |= (sib >> 3) & 7;
1159 base_reg |= sib & 7;
1160 scale = sib >> 6;
1161
9dac77fa 1162 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1163 modrm_ea += insn_fetch(s32, ctxt);
a6e3407b 1164 else {
dd856efa 1165 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1166 adjust_modrm_seg(ctxt, base_reg);
1167 }
dc71d0f1 1168 if (index_reg != 4)
dd856efa 1169 modrm_ea += reg_read(ctxt, index_reg) << scale;
9dac77fa 1170 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
84411d85 1171 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1172 ctxt->rip_relative = 1;
a6e3407b
AK		 1173 } else {
1174 base_reg = ctxt->modrm_rm;
dd856efa 1175 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1176 adjust_modrm_seg(ctxt, base_reg);
1177 }
9dac77fa 1178 switch (ctxt->modrm_mod) {
1c73ef66 1179 case 0:
9dac77fa 1180 if (ctxt->modrm_rm == 5)
e85a1085 1181 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1182 break;
1183 case 1:
e85a1085 1184 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1185 break;
1186 case 2:
e85a1085 1187 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1188 break;
1189 }
1190 }
90de84f5 1191 op->addr.mem.ea = modrm_ea;
1c73ef66
AK		 1192done:
1193 return rc;
1194}
1195
1196static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1197 struct operand *op)
1c73ef66 1198{
3e2815e9 1199 int rc = X86EMUL_CONTINUE;
1c73ef66 1200
2dbd0dd7 1201 op->type = OP_MEM;
9dac77fa 1202 switch (ctxt->ad_bytes) {
1c73ef66 1203 case 2:
e85a1085 1204 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1205 break;
1206 case 4:
e85a1085 1207 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1208 break;
1209 case 8:
e85a1085 1210 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1211 break;
1212 }
1213done:
1214 return rc;
1215}
1216
9dac77fa 1217static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1218{
7129eeca 1219 long sv = 0, mask;
35c843c4 1220
9dac77fa
AK		 1221 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
1222 mask = ~(ctxt->dst.bytes * 8 - 1);
35c843c4 1223
9dac77fa
AK		 1224 if (ctxt->src.bytes == 2)
1225 sv = (s16)ctxt->src.val & (s16)mask;
1226 else if (ctxt->src.bytes == 4)
1227 sv = (s32)ctxt->src.val & (s32)mask;
35c843c4 1228
9dac77fa 1229 ctxt->dst.addr.mem.ea += (sv >> 3);
35c843c4 1230 }
ba7ff2b7
WY		 1231
1232 /* only subword offset */
9dac77fa 1233 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1234}
1235
dde7e6d1 1236static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1237 unsigned long addr, void *dest, unsigned size)
6aa8b732 1238{
dde7e6d1 1239 int rc;
9dac77fa 1240 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1241
f23b070e
XG		 1242 if (mc->pos < mc->end)
1243 goto read_cached;
6aa8b732 1244
f23b070e
XG		 1245 WARN_ON((mc->end + size) >= sizeof(mc->data));
1246
1247 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1248 &ctxt->exception);
1249 if (rc != X86EMUL_CONTINUE)
1250 return rc;
1251
1252 mc->end += size;
1253
1254read_cached:
1255 memcpy(dest, mc->data + mc->pos, size);
1256 mc->pos += size;
dde7e6d1
AK		 1257 return X86EMUL_CONTINUE;
1258}
6aa8b732 1259
3ca3ac4d
AK		 1260static int segmented_read(struct x86_emulate_ctxt *ctxt,
1261 struct segmented_address addr,
1262 void *data,
1263 unsigned size)
1264{
9fa088f4
AK		 1265 int rc;
1266 ulong linear;
1267
83b8795a 1268 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1269 if (rc != X86EMUL_CONTINUE)
1270 return rc;
7b105ca2 1271 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1272}
1273
1274static int segmented_write(struct x86_emulate_ctxt *ctxt,
1275 struct segmented_address addr,
1276 const void *data,
1277 unsigned size)
1278{
9fa088f4
AK		 1279 int rc;
1280 ulong linear;
1281
83b8795a 1282 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1283 if (rc != X86EMUL_CONTINUE)
1284 return rc;
0f65dd70
AK		 1285 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1286 &ctxt->exception);
3ca3ac4d
AK		 1287}
1288
1289static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1290 struct segmented_address addr,
1291 const void *orig_data, const void *data,
1292 unsigned size)
1293{
9fa088f4
AK		 1294 int rc;
1295 ulong linear;
1296
83b8795a 1297 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1298 if (rc != X86EMUL_CONTINUE)
1299 return rc;
0f65dd70
AK		 1300 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1301 size, &ctxt->exception);
3ca3ac4d
AK		 1302}
1303
dde7e6d1 1304static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1305 unsigned int size, unsigned short port,
1306 void *dest)
1307{
9dac77fa 1308 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1309
dde7e6d1 1310 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1311 unsigned int in_page, n;
9dac77fa 1312 unsigned int count = ctxt->rep_prefix ?
dd856efa 1313 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
dde7e6d1 1314 in_page = (ctxt->eflags & EFLG_DF) ?
dd856efa
AK		 1315 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1316 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
dde7e6d1
AK		 1317 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1318 count);
1319 if (n == 0)
1320 n = 1;
1321 rc->pos = rc->end = 0;
7b105ca2 1322 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1323 return 0;
1324 rc->end = n * size;
6aa8b732
AK		 1325 }
1326
e6e39f04
NA		 1327 if (ctxt->rep_prefix && (ctxt->d & String) &&
1328 !(ctxt->eflags & EFLG_DF)) {
b3356bf0
GN		 1329 ctxt->dst.data = rc->data + rc->pos;
1330 ctxt->dst.type = OP_MEM_STR;
1331 ctxt->dst.count = (rc->end - rc->pos) / size;
1332 rc->pos = rc->end;
1333 } else {
1334 memcpy(dest, rc->data + rc->pos, size);
1335 rc->pos += size;
1336 }
dde7e6d1
AK		 1337 return 1;
1338}
6aa8b732 1339
7f3d35fd
KW		 1340static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1341 u16 index, struct desc_struct *desc)
1342{
1343 struct desc_ptr dt;
1344 ulong addr;
1345
1346 ctxt->ops->get_idt(ctxt, &dt);
1347
1348 if (dt.size < index * 8 + 7)
1349 return emulate_gp(ctxt, index << 3 | 0x2);
1350
1351 addr = dt.address + index * 8;
1352 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1353 &ctxt->exception);
1354}
1355
dde7e6d1 1356static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1357 u16 selector, struct desc_ptr *dt)
1358{
0225fb50 1359 const struct x86_emulate_ops *ops = ctxt->ops;
7b105ca2 1360
dde7e6d1
AK		 1361 if (selector & 1 << 2) {
1362 struct desc_struct desc;
1aa36616
AK		 1363 u16 sel;
1364
dde7e6d1 1365 memset (dt, 0, sizeof *dt);
1aa36616 1366 if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR))
dde7e6d1 1367 return;
e09d082c 1368
dde7e6d1
AK		 1369 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1370 dt->address = get_desc_base(&desc);
1371 } else
4bff1e86 1372 ops->get_gdt(ctxt, dt);
dde7e6d1 1373}
120df890 1374
dde7e6d1
AK		 1375/* allowed just for 8 bytes segments */
1376static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
e919464b
AK		 1377 u16 selector, struct desc_struct *desc,
1378 ulong *desc_addr_p)
dde7e6d1
AK		 1379{
1380 struct desc_ptr dt;
1381 u16 index = selector >> 3;
dde7e6d1 1382 ulong addr;
120df890 1383
7b105ca2 1384 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1385
35d3d4a1
AK		 1386 if (dt.size < index * 8 + 7)
1387 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1388
e919464b 1389 *desc_addr_p = addr = dt.address + index * 8;
7b105ca2
TY		 1390 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1391 &ctxt->exception);
dde7e6d1 1392}
ef65c889 1393
dde7e6d1
AK		 1394/* allowed just for 8 bytes segments */
1395static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1396 u16 selector, struct desc_struct *desc)
1397{
1398 struct desc_ptr dt;
1399 u16 index = selector >> 3;
dde7e6d1 1400 ulong addr;
6aa8b732 1401
7b105ca2 1402 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1403
35d3d4a1
AK		 1404 if (dt.size < index * 8 + 7)
1405 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1406
dde7e6d1 1407 addr = dt.address + index * 8;
7b105ca2
TY		 1408 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1409 &ctxt->exception);
dde7e6d1 1410}
c7e75a3d 1411
5601d05b 1412/* Does not support long mode */
2356aaeb 1413static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
5045b468 1414 u16 selector, int seg, u8 cpl, bool in_task_switch)
dde7e6d1 1415{
869be99c 1416 struct desc_struct seg_desc, old_desc;
2356aaeb 1417 u8 dpl, rpl;
dde7e6d1
AK		 1418 unsigned err_vec = GP_VECTOR;
1419 u32 err_code = 0;
1420 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
e919464b 1421 ulong desc_addr;
dde7e6d1 1422 int ret;
03ebebeb 1423 u16 dummy;
69f55cb1 1424
dde7e6d1 1425 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1426
f8da94e9
KW		 1427 if (ctxt->mode == X86EMUL_MODE_REAL) {
1428 /* set real mode segment descriptor (keep limit etc. for
1429 * unreal mode) */
03ebebeb 1430 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
dde7e6d1 1431 set_desc_base(&seg_desc, selector << 4);
dde7e6d1 1432 goto load;
f8da94e9
KW		 1433 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
1434 /* VM86 needs a clean new segment descriptor */
1435 set_desc_base(&seg_desc, selector << 4);
1436 set_desc_limit(&seg_desc, 0xffff);
1437 seg_desc.type = 3;
1438 seg_desc.p = 1;
1439 seg_desc.s = 1;
1440 seg_desc.dpl = 3;
1441 goto load;
dde7e6d1
AK		 1442 }
1443
79d5b4c3 1444 rpl = selector & 3;
79d5b4c3
AK		 1445
1446 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1447 if ((seg == VCPU_SREG_CS
1448 || (seg == VCPU_SREG_SS
1449 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1450 || seg == VCPU_SREG_TR)
dde7e6d1
AK		 1451 && null_selector)
1452 goto exception;
1453
1454 /* TR should be in GDT only */
1455 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1456 goto exception;
1457
1458 if (null_selector) /* for NULL selector skip all following checks */
1459 goto load;
1460
e919464b 1461 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
dde7e6d1
AK		 1462 if (ret != X86EMUL_CONTINUE)
1463 return ret;
1464
1465 err_code = selector & 0xfffc;
1466 err_vec = GP_VECTOR;
1467
fc058680 1468 /* can't load system descriptor into segment selector */
dde7e6d1
AK		 1469 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1470 goto exception;
1471
1472 if (!seg_desc.p) {
1473 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1474 goto exception;
1475 }
1476
dde7e6d1 1477 dpl = seg_desc.dpl;
dde7e6d1
AK		 1478
1479 switch (seg) {
1480 case VCPU_SREG_SS:
1481 /*
1482 * segment is not a writable data segment or segment
1483 * selector's RPL != CPL or segment selector's RPL != CPL
1484 */
1485 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1486 goto exception;
6aa8b732 1487 break;
dde7e6d1 1488 case VCPU_SREG_CS:
5045b468
PB		 1489 if (in_task_switch && rpl != dpl)
1490 goto exception;
1491
dde7e6d1
AK		 1492 if (!(seg_desc.type & 8))
1493 goto exception;
1494
1495 if (seg_desc.type & 4) {
1496 /* conforming */
1497 if (dpl > cpl)
1498 goto exception;
1499 } else {
1500 /* nonconforming */
1501 if (rpl > cpl || dpl != cpl)
1502 goto exception;
1503 }
1504 /* CS(RPL) <- CPL */
1505 selector = (selector & 0xfffc) | cpl;
6aa8b732 1506 break;
dde7e6d1
AK		 1507 case VCPU_SREG_TR:
1508 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1509 goto exception;
869be99c
AK		 1510 old_desc = seg_desc;
1511 seg_desc.type |= 2; /* busy */
1512 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1513 sizeof(seg_desc), &ctxt->exception);
1514 if (ret != X86EMUL_CONTINUE)
1515 return ret;
dde7e6d1
AK		 1516 break;
1517 case VCPU_SREG_LDTR:
1518 if (seg_desc.s || seg_desc.type != 2)
1519 goto exception;
1520 break;
1521 default: /* DS, ES, FS, or GS */
4e62417b 1522 /*
dde7e6d1
AK		 1523 * segment is not a data or readable code segment or
1524 * ((segment is a data or nonconforming code segment)
1525 * and (both RPL and CPL > DPL))
4e62417b 1526 */
dde7e6d1
AK		 1527 if ((seg_desc.type & 0xa) == 0x8 ||
1528 (((seg_desc.type & 0xc) != 0xc) &&
1529 (rpl > dpl && cpl > dpl)))
1530 goto exception;
6aa8b732 1531 break;
dde7e6d1
AK		 1532 }
1533
1534 if (seg_desc.s) {
1535 /* mark segment as accessed */
1536 seg_desc.type |= 1;
7b105ca2 1537 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1538 if (ret != X86EMUL_CONTINUE)
1539 return ret;
1540 }
1541load:
7b105ca2 1542 ctxt->ops->set_segment(ctxt, selector, &seg_desc, 0, seg);
dde7e6d1
AK		 1543 return X86EMUL_CONTINUE;
1544exception:
1545 emulate_exception(ctxt, err_vec, err_code, true);
1546 return X86EMUL_PROPAGATE_FAULT;
1547}
1548
2356aaeb
PB		 1549static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1550 u16 selector, int seg)
1551{
1552 u8 cpl = ctxt->ops->cpl(ctxt);
5045b468 1553 return __load_segment_descriptor(ctxt, selector, seg, cpl, false);
2356aaeb
PB		 1554}
1555
31be40b3
WY		 1556static void write_register_operand(struct operand *op)
1557{
1558 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1559 switch (op->bytes) {
1560 case 1:
1561 *(u8 *)op->addr.reg = (u8)op->val;
1562 break;
1563 case 2:
1564 *(u16 *)op->addr.reg = (u16)op->val;
1565 break;
1566 case 4:
1567 *op->addr.reg = (u32)op->val;
1568 break; /* 64b: zero-extend */
1569 case 8:
1570 *op->addr.reg = op->val;
1571 break;
1572 }
1573}
1574
fb32b1ed 1575static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
dde7e6d1
AK		 1576{
1577 int rc;
dde7e6d1 1578
fb32b1ed 1579 switch (op->type) {
dde7e6d1 1580 case OP_REG:
fb32b1ed 1581 write_register_operand(op);
6aa8b732 1582 break;
dde7e6d1 1583 case OP_MEM:
9dac77fa 1584 if (ctxt->lock_prefix)
3ca3ac4d 1585 rc = segmented_cmpxchg(ctxt,
fb32b1ed
AK		 1586 op->addr.mem,
1587 &op->orig_val,
1588 &op->val,
1589 op->bytes);
341de7e3 1590 else
3ca3ac4d 1591 rc = segmented_write(ctxt,
fb32b1ed
AK		 1592 op->addr.mem,
1593 &op->val,
1594 op->bytes);
dde7e6d1
AK		 1595 if (rc != X86EMUL_CONTINUE)
1596 return rc;
a682e354 1597 break;
b3356bf0
GN		 1598 case OP_MEM_STR:
1599 rc = segmented_write(ctxt,
fb32b1ed
AK		 1600 op->addr.mem,
1601 op->data,
1602 op->bytes * op->count);
b3356bf0
GN		 1603 if (rc != X86EMUL_CONTINUE)
1604 return rc;
1605 break;
1253791d 1606 case OP_XMM:
fb32b1ed 1607 write_sse_reg(ctxt, &op->vec_val, op->addr.xmm);
1253791d 1608 break;
cbe2c9d3 1609 case OP_MM:
fb32b1ed 1610 write_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
cbe2c9d3 1611 break;
dde7e6d1
AK		 1612 case OP_NONE:
1613 /* no writeback */
414e6277 1614 break;
dde7e6d1 1615 default:
414e6277 1616 break;
6aa8b732 1617 }
dde7e6d1
AK		 1618 return X86EMUL_CONTINUE;
1619}
6aa8b732 1620
51ddff50 1621static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
dde7e6d1 1622{
4179bb02 1623 struct segmented_address addr;
0dc8d10f 1624
5ad105e5 1625 rsp_increment(ctxt, -bytes);
dd856efa 1626 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
4179bb02
TY		 1627 addr.seg = VCPU_SREG_SS;
1628
51ddff50
AK		 1629 return segmented_write(ctxt, addr, data, bytes);
1630}
1631
1632static int em_push(struct x86_emulate_ctxt *ctxt)
1633{
4179bb02 1634 /* Disable writeback. */
9dac77fa 1635 ctxt->dst.type = OP_NONE;
51ddff50 1636 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1637}
69f55cb1 1638
dde7e6d1 1639static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1640 void *dest, int len)
1641{
dde7e6d1 1642 int rc;
90de84f5 1643 struct segmented_address addr;
8b4caf66 1644
dd856efa 1645 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
90de84f5 1646 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1647 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1648 if (rc != X86EMUL_CONTINUE)
1649 return rc;
1650
5ad105e5 1651 rsp_increment(ctxt, len);
dde7e6d1 1652 return rc;
8b4caf66
LV		 1653}
1654
c54fe504
TY		 1655static int em_pop(struct x86_emulate_ctxt *ctxt)
1656{
9dac77fa 1657 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1658}
1659
dde7e6d1 1660static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1661 void *dest, int len)
9de41573
GN		 1662{
1663 int rc;
dde7e6d1
AK		 1664 unsigned long val, change_mask;
1665 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1666 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1667
3b9be3bf 1668 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1669 if (rc != X86EMUL_CONTINUE)
1670 return rc;
9de41573 1671
dde7e6d1
AK		 1672 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1673 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1674
dde7e6d1
AK		 1675 switch(ctxt->mode) {
1676 case X86EMUL_MODE_PROT64:
1677 case X86EMUL_MODE_PROT32:
1678 case X86EMUL_MODE_PROT16:
1679 if (cpl == 0)
1680 change_mask |= EFLG_IOPL;
1681 if (cpl <= iopl)
1682 change_mask |= EFLG_IF;
1683 break;
1684 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1685 if (iopl < 3)
1686 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1687 change_mask |= EFLG_IF;
1688 break;
1689 default: /* real mode */
1690 change_mask |= (EFLG_IOPL | EFLG_IF);
1691 break;
9de41573 1692 }
dde7e6d1
AK		 1693
1694 *(unsigned long *)dest =
1695 (ctxt->eflags & ~change_mask) | (val & change_mask);
1696
1697 return rc;
9de41573
GN		 1698}
1699
62aaa2f0
TY		 1700static int em_popf(struct x86_emulate_ctxt *ctxt)
1701{
9dac77fa
AK		 1702 ctxt->dst.type = OP_REG;
1703 ctxt->dst.addr.reg = &ctxt->eflags;
1704 ctxt->dst.bytes = ctxt->op_bytes;
1705 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1706}
1707
612e89f0
AK		 1708static int em_enter(struct x86_emulate_ctxt *ctxt)
1709{
1710 int rc;
1711 unsigned frame_size = ctxt->src.val;
1712 unsigned nesting_level = ctxt->src2.val & 31;
dd856efa 1713 ulong rbp;
612e89f0
AK		 1714
1715 if (nesting_level)
1716 return X86EMUL_UNHANDLEABLE;
1717
dd856efa
AK		 1718 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1719 rc = push(ctxt, &rbp, stack_size(ctxt));
612e89f0
AK		 1720 if (rc != X86EMUL_CONTINUE)
1721 return rc;
dd856efa 1722 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
612e89f0 1723 stack_mask(ctxt));
dd856efa
AK		 1724 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1725 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
612e89f0
AK		 1726 stack_mask(ctxt));
1727 return X86EMUL_CONTINUE;
1728}
1729
f47cfa31
AK		 1730static int em_leave(struct x86_emulate_ctxt *ctxt)
1731{
dd856efa 1732 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
f47cfa31 1733 stack_mask(ctxt));
dd856efa 1734 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
f47cfa31
AK		 1735}
1736
1cd196ea 1737static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1738{
1cd196ea
AK		 1739 int seg = ctxt->src2.val;
1740
9dac77fa 1741 ctxt->src.val = get_segment_selector(ctxt, seg);
7b262e90 1742
4487b3b4 1743 return em_push(ctxt);
7b262e90
GN		 1744}
1745
1cd196ea 1746static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1747{
1cd196ea 1748 int seg = ctxt->src2.val;
dde7e6d1
AK		 1749 unsigned long selector;
1750 int rc;
38ba30ba 1751
9dac77fa 1752 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
dde7e6d1
AK		 1753 if (rc != X86EMUL_CONTINUE)
1754 return rc;
1755
7b105ca2 1756 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1757 return rc;
38ba30ba
GN		 1758}
1759
b96a7fad 1760static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1761{
dd856efa 1762 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
dde7e6d1
AK		 1763 int rc = X86EMUL_CONTINUE;
1764 int reg = VCPU_REGS_RAX;
38ba30ba 1765
dde7e6d1
AK		 1766 while (reg <= VCPU_REGS_RDI) {
1767 (reg == VCPU_REGS_RSP) ?
dd856efa 1768 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
38ba30ba 1769
4487b3b4 1770 rc = em_push(ctxt);
dde7e6d1
AK		 1771 if (rc != X86EMUL_CONTINUE)
1772 return rc;
38ba30ba 1773
dde7e6d1 1774 ++reg;
38ba30ba 1775 }
38ba30ba 1776
dde7e6d1 1777 return rc;
38ba30ba
GN		 1778}
1779
62aaa2f0
TY		 1780static int em_pushf(struct x86_emulate_ctxt *ctxt)
1781{
9dac77fa 1782 ctxt->src.val = (unsigned long)ctxt->eflags;
62aaa2f0
TY		 1783 return em_push(ctxt);
1784}
1785
b96a7fad 1786static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1787{
dde7e6d1
AK		 1788 int rc = X86EMUL_CONTINUE;
1789 int reg = VCPU_REGS_RDI;
38ba30ba 1790
dde7e6d1
AK		 1791 while (reg >= VCPU_REGS_RAX) {
1792 if (reg == VCPU_REGS_RSP) {
5ad105e5 1793 rsp_increment(ctxt, ctxt->op_bytes);
dde7e6d1
AK		 1794 --reg;
1795 }
38ba30ba 1796
dd856efa 1797 rc = emulate_pop(ctxt, reg_rmw(ctxt, reg), ctxt->op_bytes);
dde7e6d1
AK		 1798 if (rc != X86EMUL_CONTINUE)
1799 break;
1800 --reg;
38ba30ba 1801 }
dde7e6d1 1802 return rc;
38ba30ba
GN		 1803}
1804
dd856efa 1805static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1806{
0225fb50 1807 const struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1808 int rc;
6e154e56
MG		 1809 struct desc_ptr dt;
1810 gva_t cs_addr;
1811 gva_t eip_addr;
1812 u16 cs, eip;
6e154e56
MG		 1813
1814 /* TODO: Add limit checks */
9dac77fa 1815 ctxt->src.val = ctxt->eflags;
4487b3b4 1816 rc = em_push(ctxt);
5c56e1cf
AK		 1817 if (rc != X86EMUL_CONTINUE)
1818 return rc;
6e154e56
MG		 1819
1820 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1821
9dac77fa 1822 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1823 rc = em_push(ctxt);
5c56e1cf
AK		 1824 if (rc != X86EMUL_CONTINUE)
1825 return rc;
6e154e56 1826
9dac77fa 1827 ctxt->src.val = ctxt->_eip;
4487b3b4 1828 rc = em_push(ctxt);
5c56e1cf
AK		 1829 if (rc != X86EMUL_CONTINUE)
1830 return rc;
1831
4bff1e86 1832 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1833
1834 eip_addr = dt.address + (irq << 2);
1835 cs_addr = dt.address + (irq << 2) + 2;
1836
0f65dd70 1837 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1838 if (rc != X86EMUL_CONTINUE)
1839 return rc;
1840
0f65dd70 1841 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1842 if (rc != X86EMUL_CONTINUE)
1843 return rc;
1844
7b105ca2 1845 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1846 if (rc != X86EMUL_CONTINUE)
1847 return rc;
1848
9dac77fa 1849 ctxt->_eip = eip;
6e154e56
MG		 1850
1851 return rc;
1852}
1853
dd856efa
AK		 1854int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
1855{
1856 int rc;
1857
1858 invalidate_registers(ctxt);
1859 rc = __emulate_int_real(ctxt, irq);
1860 if (rc == X86EMUL_CONTINUE)
1861 writeback_registers(ctxt);
1862 return rc;
1863}
1864
7b105ca2 1865static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 1866{
1867 switch(ctxt->mode) {
1868 case X86EMUL_MODE_REAL:
dd856efa 1869 return __emulate_int_real(ctxt, irq);
6e154e56
MG		 1870 case X86EMUL_MODE_VM86:
1871 case X86EMUL_MODE_PROT16:
1872 case X86EMUL_MODE_PROT32:
1873 case X86EMUL_MODE_PROT64:
1874 default:
1875 /* Protected mode interrupts unimplemented yet */
1876 return X86EMUL_UNHANDLEABLE;
1877 }
1878}
1879
7b105ca2 1880static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 1881{
dde7e6d1
AK		 1882 int rc = X86EMUL_CONTINUE;
1883 unsigned long temp_eip = 0;
1884 unsigned long temp_eflags = 0;
1885 unsigned long cs = 0;
1886 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1887 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1888 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1889 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1890
dde7e6d1 1891 /* TODO: Add stack limit check */
38ba30ba 1892
9dac77fa 1893 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 1894
dde7e6d1
AK		 1895 if (rc != X86EMUL_CONTINUE)
1896 return rc;
38ba30ba 1897
35d3d4a1
AK		 1898 if (temp_eip & ~0xffff)
1899 return emulate_gp(ctxt, 0);
38ba30ba 1900
9dac77fa 1901 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 1902
dde7e6d1
AK		 1903 if (rc != X86EMUL_CONTINUE)
1904 return rc;
38ba30ba 1905
9dac77fa 1906 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 1907
dde7e6d1
AK		 1908 if (rc != X86EMUL_CONTINUE)
1909 return rc;
38ba30ba 1910
7b105ca2 1911 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 1912
dde7e6d1
AK		 1913 if (rc != X86EMUL_CONTINUE)
1914 return rc;
38ba30ba 1915
9dac77fa 1916 ctxt->_eip = temp_eip;
38ba30ba 1917
38ba30ba 1918
9dac77fa 1919 if (ctxt->op_bytes == 4)
dde7e6d1 1920 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 1921 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 1922 ctxt->eflags &= ~0xffff;
1923 ctxt->eflags |= temp_eflags;
38ba30ba 1924 }
dde7e6d1
AK		 1925
1926 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1927 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1928
1929 return rc;
38ba30ba
GN		 1930}
1931
e01991e7 1932static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 1933{
dde7e6d1
AK		 1934 switch(ctxt->mode) {
1935 case X86EMUL_MODE_REAL:
7b105ca2 1936 return emulate_iret_real(ctxt);
dde7e6d1
AK		 1937 case X86EMUL_MODE_VM86:
1938 case X86EMUL_MODE_PROT16:
1939 case X86EMUL_MODE_PROT32:
1940 case X86EMUL_MODE_PROT64:
c37eda13 1941 default:
dde7e6d1
AK		 1942 /* iret from protected mode unimplemented yet */
1943 return X86EMUL_UNHANDLEABLE;
c37eda13 1944 }
c37eda13
WY		 1945}
1946
d2f62766
TY		 1947static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
1948{
d2f62766
TY		 1949 int rc;
1950 unsigned short sel;
1951
9dac77fa 1952 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 1953
7b105ca2 1954 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS);
d2f62766
TY		 1955 if (rc != X86EMUL_CONTINUE)
1956 return rc;
1957
9dac77fa
AK		 1958 ctxt->_eip = 0;
1959 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
d2f62766
TY		 1960 return X86EMUL_CONTINUE;
1961}
1962
51187683 1963static int em_grp45(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1964{
4179bb02 1965 int rc = X86EMUL_CONTINUE;
8cdbd2c9 1966
9dac77fa 1967 switch (ctxt->modrm_reg) {
d19292e4
MG		 1968 case 2: /* call near abs */ {
1969 long int old_eip;
9dac77fa
AK		 1970 old_eip = ctxt->_eip;
1971 ctxt->_eip = ctxt->src.val;
1972 ctxt->src.val = old_eip;
4487b3b4 1973 rc = em_push(ctxt);
d19292e4
MG		 1974 break;
1975 }
8cdbd2c9 1976 case 4: /* jmp abs */
9dac77fa 1977 ctxt->_eip = ctxt->src.val;
8cdbd2c9 1978 break;
d2f62766
TY		 1979 case 5: /* jmp far */
1980 rc = em_jmp_far(ctxt);
1981 break;
8cdbd2c9 1982 case 6: /* push */
4487b3b4 1983 rc = em_push(ctxt);
8cdbd2c9 1984 break;
8cdbd2c9 1985 }
4179bb02 1986 return rc;
8cdbd2c9
LV		 1987}
1988
e0dac408 1989static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1990{
9dac77fa 1991 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 1992
dd856efa
AK		 1993 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
1994 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
1995 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
1996 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
05f086f8 1997 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 1998 } else {
dd856efa
AK		 1999 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2000 (u32) reg_read(ctxt, VCPU_REGS_RBX);
8cdbd2c9 2001
05f086f8 2002 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 2003 }
1b30eaa8 2004 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2005}
2006
ebda02c2
TY		 2007static int em_ret(struct x86_emulate_ctxt *ctxt)
2008{
9dac77fa
AK		 2009 ctxt->dst.type = OP_REG;
2010 ctxt->dst.addr.reg = &ctxt->_eip;
2011 ctxt->dst.bytes = ctxt->op_bytes;
ebda02c2
TY		 2012 return em_pop(ctxt);
2013}
2014
e01991e7 2015static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 2016{
a77ab5ea
AK		 2017 int rc;
2018 unsigned long cs;
2019
9dac77fa 2020 rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes);
1b30eaa8 2021 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2022 return rc;
9dac77fa
AK		 2023 if (ctxt->op_bytes == 4)
2024 ctxt->_eip = (u32)ctxt->_eip;
2025 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 2026 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2027 return rc;
7b105ca2 2028 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 2029 return rc;
2030}
2031
3261107e
BR		 2032static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt)
2033{
2034 int rc;
2035
2036 rc = em_ret_far(ctxt);
2037 if (rc != X86EMUL_CONTINUE)
2038 return rc;
2039 rsp_increment(ctxt, ctxt->src.val);
2040 return X86EMUL_CONTINUE;
2041}
2042
e940b5c2
TY		 2043static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2044{
2045 /* Save real source value, then compare EAX against destination. */
2046 ctxt->src.orig_val = ctxt->src.val;
dd856efa 2047 ctxt->src.val = reg_read(ctxt, VCPU_REGS_RAX);
158de57f 2048 fastop(ctxt, em_cmp);
e940b5c2
TY		 2049
2050 if (ctxt->eflags & EFLG_ZF) {
2051 /* Success: write back to memory. */
2052 ctxt->dst.val = ctxt->src.orig_val;
2053 } else {
2054 /* Failure: write the value we saw to EAX. */
2055 ctxt->dst.type = OP_REG;
dd856efa 2056 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
e940b5c2
TY		 2057 }
2058 return X86EMUL_CONTINUE;
2059}
2060
d4b4325f 2061static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 2062{
d4b4325f 2063 int seg = ctxt->src2.val;
09b5f4d3
WY		 2064 unsigned short sel;
2065 int rc;
2066
9dac77fa 2067 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 2068
7b105ca2 2069 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 2070 if (rc != X86EMUL_CONTINUE)
2071 return rc;
2072
9dac77fa 2073 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 2074 return rc;
2075}
2076
7b105ca2 2077static void
e66bb2cc 2078setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 2079 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 2080{
e66bb2cc 2081 cs->l = 0; /* will be adjusted later */
79168fd1 2082 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 2083 cs->g = 1; /* 4kb granularity */
79168fd1 2084 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2085 cs->type = 0x0b; /* Read, Execute, Accessed */
2086 cs->s = 1;
2087 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 2088 cs->p = 1;
2089 cs->d = 1;
99245b50 2090 cs->avl = 0;
e66bb2cc 2091
79168fd1
GN		 2092 set_desc_base(ss, 0); /* flat segment */
2093 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2094 ss->g = 1; /* 4kb granularity */
2095 ss->s = 1;
2096 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2097 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2098 ss->dpl = 0;
79168fd1 2099 ss->p = 1;
99245b50
GN		 2100 ss->l = 0;
2101 ss->avl = 0;
e66bb2cc
AP		 2102}
2103
1a18a69b
AK		 2104static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2105{
2106 u32 eax, ebx, ecx, edx;
2107
2108 eax = ecx = 0;
0017f93a
AK		 2109 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2110 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1a18a69b
AK		 2111 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2112 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2113}
2114
c2226fc9
SB		 2115static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2116{
0225fb50 2117 const struct x86_emulate_ops *ops = ctxt->ops;
c2226fc9
SB		 2118 u32 eax, ebx, ecx, edx;
2119
2120 /*
2121 * syscall should always be enabled in longmode - so only become
2122 * vendor specific (cpuid) if other modes are active...
2123 */
2124 if (ctxt->mode == X86EMUL_MODE_PROT64)
2125 return true;
2126
2127 eax = 0x00000000;
2128 ecx = 0x00000000;
0017f93a
AK		 2129 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2130 /*
2131 * Intel ("GenuineIntel")
2132 * remark: Intel CPUs only support "syscall" in 64bit
2133 * longmode. Also an 64bit guest with a
2134 * 32bit compat-app running will #UD !! While this
2135 * behaviour can be fixed (by emulating) into AMD
2136 * response - CPUs of AMD can't behave like Intel.
2137 */
2138 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2139 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2140 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2141 return false;
2142
2143 /* AMD ("AuthenticAMD") */
2144 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2145 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2146 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2147 return true;
2148
2149 /* AMD ("AMDisbetter!") */
2150 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2151 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2152 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2153 return true;
c2226fc9
SB		 2154
2155 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2156 return false;
2157}
2158
e01991e7 2159static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2160{
0225fb50 2161 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2162 struct desc_struct cs, ss;
e66bb2cc 2163 u64 msr_data;
79168fd1 2164 u16 cs_sel, ss_sel;
c2ad2bb3 2165 u64 efer = 0;
e66bb2cc
AP		 2166
2167 /* syscall is not available in real mode */
2e901c4c 2168 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2169 ctxt->mode == X86EMUL_MODE_VM86)
2170 return emulate_ud(ctxt);
e66bb2cc 2171
c2226fc9
SB		 2172 if (!(em_syscall_is_enabled(ctxt)))
2173 return emulate_ud(ctxt);
2174
c2ad2bb3 2175 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2176 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2177
c2226fc9
SB		 2178 if (!(efer & EFER_SCE))
2179 return emulate_ud(ctxt);
2180
717746e3 2181 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2182 msr_data >>= 32;
79168fd1
GN		 2183 cs_sel = (u16)(msr_data & 0xfffc);
2184 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2185
c2ad2bb3 2186 if (efer & EFER_LMA) {
79168fd1 2187 cs.d = 0;
e66bb2cc
AP		 2188 cs.l = 1;
2189 }
1aa36616
AK		 2190 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2191 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2192
dd856efa 2193 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
c2ad2bb3 2194 if (efer & EFER_LMA) {
e66bb2cc 2195#ifdef CONFIG_X86_64
dd856efa 2196 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags & ~EFLG_RF;
e66bb2cc 2197
717746e3 2198 ops->get_msr(ctxt,
3fb1b5db
GN		 2199 ctxt->mode == X86EMUL_MODE_PROT64 ?
2200 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2201 ctxt->_eip = msr_data;
e66bb2cc 2202
717746e3 2203 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 2204 ctxt->eflags &= ~(msr_data | EFLG_RF);
2205#endif
2206 } else {
2207 /* legacy mode */
717746e3 2208 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2209 ctxt->_eip = (u32)msr_data;
e66bb2cc
AP		 2210
2211 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
2212 }
2213
e54cfa97 2214 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2215}
2216
e01991e7 2217static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2218{
0225fb50 2219 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2220 struct desc_struct cs, ss;
8c604352 2221 u64 msr_data;
79168fd1 2222 u16 cs_sel, ss_sel;
c2ad2bb3 2223 u64 efer = 0;
8c604352 2224
7b105ca2 2225 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2226 /* inject #GP if in real mode */
35d3d4a1
AK		 2227 if (ctxt->mode == X86EMUL_MODE_REAL)
2228 return emulate_gp(ctxt, 0);
8c604352 2229
1a18a69b
AK		 2230 /*
2231 * Not recognized on AMD in compat mode (but is recognized in legacy
2232 * mode).
2233 */
2234 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
2235 && !vendor_intel(ctxt))
2236 return emulate_ud(ctxt);
2237
8c604352
AP		 2238 /* XXX sysenter/sysexit have not been tested in 64bit mode.
2239 * Therefore, we inject an #UD.
2240 */
35d3d4a1
AK		 2241 if (ctxt->mode == X86EMUL_MODE_PROT64)
2242 return emulate_ud(ctxt);
8c604352 2243
7b105ca2 2244 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2245
717746e3 2246 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2247 switch (ctxt->mode) {
2248 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 2249 if ((msr_data & 0xfffc) == 0x0)
2250 return emulate_gp(ctxt, 0);
8c604352
AP		 2251 break;
2252 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 2253 if (msr_data == 0x0)
2254 return emulate_gp(ctxt, 0);
8c604352 2255 break;
9d1b39a9
GN		 2256 default:
2257 break;
8c604352
AP		 2258 }
2259
2260 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 2261 cs_sel = (u16)msr_data;
2262 cs_sel &= ~SELECTOR_RPL_MASK;
2263 ss_sel = cs_sel + 8;
2264 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 2265 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 2266 cs.d = 0;
8c604352
AP		 2267 cs.l = 1;
2268 }
2269
1aa36616
AK		 2270 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2271 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2272
717746e3 2273 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 2274 ctxt->_eip = msr_data;
8c604352 2275
717746e3 2276 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
dd856efa 2277 *reg_write(ctxt, VCPU_REGS_RSP) = msr_data;
8c604352 2278
e54cfa97 2279 return X86EMUL_CONTINUE;
8c604352
AP		 2280}
2281
e01991e7 2282static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2283{
0225fb50 2284 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2285 struct desc_struct cs, ss;
4668f050
AP		 2286 u64 msr_data;
2287 int usermode;
1249b96e 2288 u16 cs_sel = 0, ss_sel = 0;
4668f050 2289
a0044755
GN		 2290 /* inject #GP if in real mode or Virtual 8086 mode */
2291 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2292 ctxt->mode == X86EMUL_MODE_VM86)
2293 return emulate_gp(ctxt, 0);
4668f050 2294
7b105ca2 2295 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2296
9dac77fa 2297 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2298 usermode = X86EMUL_MODE_PROT64;
2299 else
2300 usermode = X86EMUL_MODE_PROT32;
2301
2302 cs.dpl = 3;
2303 ss.dpl = 3;
717746e3 2304 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2305 switch (usermode) {
2306 case X86EMUL_MODE_PROT32:
79168fd1 2307 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2308 if ((msr_data & 0xfffc) == 0x0)
2309 return emulate_gp(ctxt, 0);
79168fd1 2310 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2311 break;
2312 case X86EMUL_MODE_PROT64:
79168fd1 2313 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2314 if (msr_data == 0x0)
2315 return emulate_gp(ctxt, 0);
79168fd1
GN		 2316 ss_sel = cs_sel + 8;
2317 cs.d = 0;
4668f050
AP		 2318 cs.l = 1;
2319 break;
2320 }
79168fd1
GN		 2321 cs_sel |= SELECTOR_RPL_MASK;
2322 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2323
1aa36616
AK		 2324 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2325 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2326
dd856efa
AK		 2327 ctxt->_eip = reg_read(ctxt, VCPU_REGS_RDX);
2328 *reg_write(ctxt, VCPU_REGS_RSP) = reg_read(ctxt, VCPU_REGS_RCX);
4668f050 2329
e54cfa97 2330 return X86EMUL_CONTINUE;
4668f050
AP		 2331}
2332
7b105ca2 2333static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2334{
2335 int iopl;
2336 if (ctxt->mode == X86EMUL_MODE_REAL)
2337 return false;
2338 if (ctxt->mode == X86EMUL_MODE_VM86)
2339 return true;
2340 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2341 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2342}
2343
2344static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2345 u16 port, u16 len)
2346{
0225fb50 2347 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2348 struct desc_struct tr_seg;
5601d05b 2349 u32 base3;
f850e2e6 2350 int r;
1aa36616 2351 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2352 unsigned mask = (1 << len) - 1;
5601d05b 2353 unsigned long base;
f850e2e6 2354
1aa36616 2355 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2356 if (!tr_seg.p)
f850e2e6 2357 return false;
79168fd1 2358 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2359 return false;
5601d05b
GN		 2360 base = get_desc_base(&tr_seg);
2361#ifdef CONFIG_X86_64
2362 base |= ((u64)base3) << 32;
2363#endif
0f65dd70 2364 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2365 if (r != X86EMUL_CONTINUE)
2366 return false;
79168fd1 2367 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2368 return false;
0f65dd70 2369 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2370 if (r != X86EMUL_CONTINUE)
2371 return false;
2372 if ((perm >> bit_idx) & mask)
2373 return false;
2374 return true;
2375}
2376
2377static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2378 u16 port, u16 len)
2379{
4fc40f07
GN		 2380 if (ctxt->perm_ok)
2381 return true;
2382
7b105ca2
TY		 2383 if (emulator_bad_iopl(ctxt))
2384 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2385 return false;
4fc40f07
GN		 2386
2387 ctxt->perm_ok = true;
2388
f850e2e6
GN		 2389 return true;
2390}
2391
38ba30ba 2392static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2393 struct tss_segment_16 *tss)
2394{
9dac77fa 2395 tss->ip = ctxt->_eip;
38ba30ba 2396 tss->flag = ctxt->eflags;
dd856efa
AK		 2397 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2398 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2399 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2400 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2401 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2402 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2403 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2404 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2405
1aa36616
AK		 2406 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2407 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2408 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2409 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2410 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2411}
2412
2413static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2414 struct tss_segment_16 *tss)
2415{
38ba30ba 2416 int ret;
2356aaeb 2417 u8 cpl;
38ba30ba 2418
9dac77fa 2419 ctxt->_eip = tss->ip;
38ba30ba 2420 ctxt->eflags = tss->flag | 2;
dd856efa
AK		 2421 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
2422 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
2423 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
2424 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
2425 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
2426 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
2427 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
2428 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
38ba30ba
GN		 2429
2430 /*
2431 * SDM says that segment selectors are loaded before segment
2432 * descriptors
2433 */
1aa36616
AK		 2434 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2435 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2436 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2437 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2438 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba 2439
2356aaeb
PB		 2440 cpl = tss->cs & 3;
2441
38ba30ba 2442 /*
fc058680 2443 * Now load segment descriptors. If fault happens at this stage
38ba30ba
GN		 2444 * it is handled in a context of new task
2445 */
5045b468 2446 ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl, true);
38ba30ba
GN		 2447 if (ret != X86EMUL_CONTINUE)
2448 return ret;
5045b468 2449 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl, true);
38ba30ba
GN		 2450 if (ret != X86EMUL_CONTINUE)
2451 return ret;
5045b468 2452 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl, true);
38ba30ba
GN		 2453 if (ret != X86EMUL_CONTINUE)
2454 return ret;
5045b468 2455 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl, true);
38ba30ba
GN		 2456 if (ret != X86EMUL_CONTINUE)
2457 return ret;
5045b468 2458 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl, true);
38ba30ba
GN		 2459 if (ret != X86EMUL_CONTINUE)
2460 return ret;
2461
2462 return X86EMUL_CONTINUE;
2463}
2464
2465static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2466 u16 tss_selector, u16 old_tss_sel,
2467 ulong old_tss_base, struct desc_struct *new_desc)
2468{
0225fb50 2469 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2470 struct tss_segment_16 tss_seg;
2471 int ret;
bcc55cba 2472 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2473
0f65dd70 2474 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2475 &ctxt->exception);
db297e3d 2476 if (ret != X86EMUL_CONTINUE)
38ba30ba 2477 /* FIXME: need to provide precise fault address */
38ba30ba 2478 return ret;
38ba30ba 2479
7b105ca2 2480 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2481
0f65dd70 2482 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2483 &ctxt->exception);
db297e3d 2484 if (ret != X86EMUL_CONTINUE)
38ba30ba 2485 /* FIXME: need to provide precise fault address */
38ba30ba 2486 return ret;
38ba30ba 2487
0f65dd70 2488 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2489 &ctxt->exception);
db297e3d 2490 if (ret != X86EMUL_CONTINUE)
38ba30ba 2491 /* FIXME: need to provide precise fault address */
38ba30ba 2492 return ret;
38ba30ba
GN		 2493
2494 if (old_tss_sel != 0xffff) {
2495 tss_seg.prev_task_link = old_tss_sel;
2496
0f65dd70 2497 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2498 &tss_seg.prev_task_link,
2499 sizeof tss_seg.prev_task_link,
0f65dd70 2500 &ctxt->exception);
db297e3d 2501 if (ret != X86EMUL_CONTINUE)
38ba30ba 2502 /* FIXME: need to provide precise fault address */
38ba30ba 2503 return ret;
38ba30ba
GN		 2504 }
2505
7b105ca2 2506 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2507}
2508
2509static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2510 struct tss_segment_32 *tss)
2511{
5c7411e2 2512 /* CR3 and ldt selector are not saved intentionally */
9dac77fa 2513 tss->eip = ctxt->_eip;
38ba30ba 2514 tss->eflags = ctxt->eflags;
dd856efa
AK		 2515 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
2516 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
2517 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
2518 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
2519 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
2520 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
2521 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
2522 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2523
1aa36616
AK		 2524 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2525 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2526 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2527 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2528 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2529 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
38ba30ba
GN		 2530}
2531
2532static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2533 struct tss_segment_32 *tss)
2534{
38ba30ba 2535 int ret;
2356aaeb 2536 u8 cpl;
38ba30ba 2537
7b105ca2 2538 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2539 return emulate_gp(ctxt, 0);
9dac77fa 2540 ctxt->_eip = tss->eip;
38ba30ba 2541 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 2542
2543 /* General purpose registers */
dd856efa
AK		 2544 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
2545 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
2546 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
2547 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
2548 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
2549 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
2550 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
2551 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
38ba30ba
GN		 2552
2553 /*
2554 * SDM says that segment selectors are loaded before segment
2356aaeb
PB		 2555 * descriptors. This is important because CPL checks will
2556 * use CS.RPL.
38ba30ba 2557 */
1aa36616
AK		 2558 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2559 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2560 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2561 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2562 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2563 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2564 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 2565
4cee4798
KW		 2566 /*
2567 * If we're switching between Protected Mode and VM86, we need to make
2568 * sure to update the mode before loading the segment descriptors so
2569 * that the selectors are interpreted correctly.
4cee4798 2570 */
2356aaeb 2571 if (ctxt->eflags & X86_EFLAGS_VM) {
4cee4798 2572 ctxt->mode = X86EMUL_MODE_VM86;
2356aaeb
PB		 2573 cpl = 3;
2574 } else {
4cee4798 2575 ctxt->mode = X86EMUL_MODE_PROT32;
2356aaeb
PB		 2576 cpl = tss->cs & 3;
2577 }
4cee4798 2578
38ba30ba
GN		 2579 /*
2580 * Now load segment descriptors. If fault happenes at this stage
2581 * it is handled in a context of new task
2582 */
5045b468 2583 ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR, cpl, true);
38ba30ba
GN		 2584 if (ret != X86EMUL_CONTINUE)
2585 return ret;
5045b468 2586 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl, true);
38ba30ba
GN		 2587 if (ret != X86EMUL_CONTINUE)
2588 return ret;
5045b468 2589 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl, true);
38ba30ba
GN		 2590 if (ret != X86EMUL_CONTINUE)
2591 return ret;
5045b468 2592 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl, true);
38ba30ba
GN		 2593 if (ret != X86EMUL_CONTINUE)
2594 return ret;
5045b468 2595 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl, true);
38ba30ba
GN		 2596 if (ret != X86EMUL_CONTINUE)
2597 return ret;
5045b468 2598 ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl, true);
38ba30ba
GN		 2599 if (ret != X86EMUL_CONTINUE)
2600 return ret;
5045b468 2601 ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl, true);
38ba30ba
GN		 2602 if (ret != X86EMUL_CONTINUE)
2603 return ret;
2604
2605 return X86EMUL_CONTINUE;
2606}
2607
2608static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2609 u16 tss_selector, u16 old_tss_sel,
2610 ulong old_tss_base, struct desc_struct *new_desc)
2611{
0225fb50 2612 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2613 struct tss_segment_32 tss_seg;
2614 int ret;
bcc55cba 2615 u32 new_tss_base = get_desc_base(new_desc);
5c7411e2
NA		 2616 u32 eip_offset = offsetof(struct tss_segment_32, eip);
2617 u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector);
38ba30ba 2618
0f65dd70 2619 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2620 &ctxt->exception);
db297e3d 2621 if (ret != X86EMUL_CONTINUE)
38ba30ba 2622 /* FIXME: need to provide precise fault address */
38ba30ba 2623 return ret;
38ba30ba 2624
7b105ca2 2625 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2626
5c7411e2
NA		 2627 /* Only GP registers and segment selectors are saved */
2628 ret = ops->write_std(ctxt, old_tss_base + eip_offset, &tss_seg.eip,
2629 ldt_sel_offset - eip_offset, &ctxt->exception);
db297e3d 2630 if (ret != X86EMUL_CONTINUE)
38ba30ba 2631 /* FIXME: need to provide precise fault address */
38ba30ba 2632 return ret;
38ba30ba 2633
0f65dd70 2634 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2635 &ctxt->exception);
db297e3d 2636 if (ret != X86EMUL_CONTINUE)
38ba30ba 2637 /* FIXME: need to provide precise fault address */
38ba30ba 2638 return ret;
38ba30ba
GN		 2639
2640 if (old_tss_sel != 0xffff) {
2641 tss_seg.prev_task_link = old_tss_sel;
2642
0f65dd70 2643 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2644 &tss_seg.prev_task_link,
2645 sizeof tss_seg.prev_task_link,
0f65dd70 2646 &ctxt->exception);
db297e3d 2647 if (ret != X86EMUL_CONTINUE)
38ba30ba 2648 /* FIXME: need to provide precise fault address */
38ba30ba 2649 return ret;
38ba30ba
GN		 2650 }
2651
7b105ca2 2652 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2653}
2654
2655static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2656 u16 tss_selector, int idt_index, int reason,
e269fb21 2657 bool has_error_code, u32 error_code)
38ba30ba 2658{
0225fb50 2659 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2660 struct desc_struct curr_tss_desc, next_tss_desc;
2661 int ret;
1aa36616 2662 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2663 ulong old_tss_base =
4bff1e86 2664 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2665 u32 desc_limit;
e919464b 2666 ulong desc_addr;
38ba30ba
GN		 2667
2668 /* FIXME: old_tss_base == ~0 ? */
2669
e919464b 2670 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
38ba30ba
GN		 2671 if (ret != X86EMUL_CONTINUE)
2672 return ret;
e919464b 2673 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
38ba30ba
GN		 2674 if (ret != X86EMUL_CONTINUE)
2675 return ret;
2676
2677 /* FIXME: check that next_tss_desc is tss */
2678
7f3d35fd
KW		 2679 /*
2680 * Check privileges. The three cases are task switch caused by...
2681 *
2682 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2683 * 2. Exception/IRQ/iret: No check is performed
fc058680 2684 * 3. jmp/call to TSS: Check against DPL of the TSS
7f3d35fd
KW		 2685 */
2686 if (reason == TASK_SWITCH_GATE) {
2687 if (idt_index != -1) {
2688 /* Software interrupts */
2689 struct desc_struct task_gate_desc;
2690 int dpl;
2691
2692 ret = read_interrupt_descriptor(ctxt, idt_index,
2693 &task_gate_desc);
2694 if (ret != X86EMUL_CONTINUE)
2695 return ret;
2696
2697 dpl = task_gate_desc.dpl;
2698 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2699 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2700 }
2701 } else if (reason != TASK_SWITCH_IRET) {
2702 int dpl = next_tss_desc.dpl;
2703 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2704 return emulate_gp(ctxt, tss_selector);
38ba30ba
GN		 2705 }
2706
7f3d35fd 2707
ceffb459
GN		 2708 desc_limit = desc_limit_scaled(&next_tss_desc);
2709 if (!next_tss_desc.p ||
2710 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2711 desc_limit < 0x2b)) {
54b8486f 2712 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2713 return X86EMUL_PROPAGATE_FAULT;
2714 }
2715
2716 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2717 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2718 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2719 }
2720
2721 if (reason == TASK_SWITCH_IRET)
2722 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2723
2724 /* set back link to prev task only if NT bit is set in eflags
fc058680 2725 note that old_tss_sel is not used after this point */
38ba30ba
GN		 2726 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2727 old_tss_sel = 0xffff;
2728
2729 if (next_tss_desc.type & 8)
7b105ca2 2730 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2731 old_tss_base, &next_tss_desc);
2732 else
7b105ca2 2733 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2734 old_tss_base, &next_tss_desc);
0760d448
JK		 2735 if (ret != X86EMUL_CONTINUE)
2736 return ret;
38ba30ba
GN		 2737
2738 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2739 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2740
2741 if (reason != TASK_SWITCH_IRET) {
2742 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2743 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2744 }
2745
717746e3 2746 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2747 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2748
e269fb21 2749 if (has_error_code) {
9dac77fa
AK		 2750 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2751 ctxt->lock_prefix = 0;
2752 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2753 ret = em_push(ctxt);
e269fb21
JK		 2754 }
2755
38ba30ba
GN		 2756 return ret;
2757}
2758
2759int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2760 u16 tss_selector, int idt_index, int reason,
e269fb21 2761 bool has_error_code, u32 error_code)
38ba30ba 2762{
38ba30ba
GN		 2763 int rc;
2764
dd856efa 2765 invalidate_registers(ctxt);
9dac77fa
AK		 2766 ctxt->_eip = ctxt->eip;
2767 ctxt->dst.type = OP_NONE;
38ba30ba 2768
7f3d35fd 2769 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 2770 has_error_code, error_code);
38ba30ba 2771
dd856efa 2772 if (rc == X86EMUL_CONTINUE) {
9dac77fa 2773 ctxt->eip = ctxt->_eip;
dd856efa
AK		 2774 writeback_registers(ctxt);
2775 }
38ba30ba 2776
a0c0ab2f 2777 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2778}
2779
f3bd64c6
GN		 2780static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
2781 struct operand *op)
a682e354 2782{
b3356bf0 2783 int df = (ctxt->eflags & EFLG_DF) ? -op->count : op->count;
a682e354 2784
dd856efa
AK		 2785 register_address_increment(ctxt, reg_rmw(ctxt, reg), df * op->bytes);
2786 op->addr.mem.ea = register_address(ctxt, reg_read(ctxt, reg));
a682e354
GN		 2787}
2788
7af04fc0
AK		 2789static int em_das(struct x86_emulate_ctxt *ctxt)
2790{
7af04fc0
AK		 2791 u8 al, old_al;
2792 bool af, cf, old_cf;
2793
2794 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2795 al = ctxt->dst.val;
7af04fc0
AK		 2796
2797 old_al = al;
2798 old_cf = cf;
2799 cf = false;
2800 af = ctxt->eflags & X86_EFLAGS_AF;
2801 if ((al & 0x0f) > 9 || af) {
2802 al -= 6;
2803 cf = old_cf | (al >= 250);
2804 af = true;
2805 } else {
2806 af = false;
2807 }
2808 if (old_al > 0x99 || old_cf) {
2809 al -= 0x60;
2810 cf = true;
2811 }
2812
9dac77fa 2813 ctxt->dst.val = al;
7af04fc0 2814 /* Set PF, ZF, SF */
9dac77fa
AK		 2815 ctxt->src.type = OP_IMM;
2816 ctxt->src.val = 0;
2817 ctxt->src.bytes = 1;
158de57f 2818 fastop(ctxt, em_or);
7af04fc0
AK		 2819 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2820 if (cf)
2821 ctxt->eflags |= X86_EFLAGS_CF;
2822 if (af)
2823 ctxt->eflags |= X86_EFLAGS_AF;
2824 return X86EMUL_CONTINUE;
2825}
2826
a035d5c6
PB		 2827static int em_aam(struct x86_emulate_ctxt *ctxt)
2828{
2829 u8 al, ah;
2830
2831 if (ctxt->src.val == 0)
2832 return emulate_de(ctxt);
2833
2834 al = ctxt->dst.val & 0xff;
2835 ah = al / ctxt->src.val;
2836 al %= ctxt->src.val;
2837
2838 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);
2839
2840 /* Set PF, ZF, SF */
2841 ctxt->src.type = OP_IMM;
2842 ctxt->src.val = 0;
2843 ctxt->src.bytes = 1;
2844 fastop(ctxt, em_or);
2845
2846 return X86EMUL_CONTINUE;
2847}
2848
7f662273
GN		 2849static int em_aad(struct x86_emulate_ctxt *ctxt)
2850{
2851 u8 al = ctxt->dst.val & 0xff;
2852 u8 ah = (ctxt->dst.val >> 8) & 0xff;
2853
2854 al = (al + (ah * ctxt->src.val)) & 0xff;
2855
2856 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
2857
f583c29b
GN		 2858 /* Set PF, ZF, SF */
2859 ctxt->src.type = OP_IMM;
2860 ctxt->src.val = 0;
2861 ctxt->src.bytes = 1;
2862 fastop(ctxt, em_or);
7f662273
GN		 2863
2864 return X86EMUL_CONTINUE;
2865}
2866
d4ddafcd
TY		 2867static int em_call(struct x86_emulate_ctxt *ctxt)
2868{
2869 long rel = ctxt->src.val;
2870
2871 ctxt->src.val = (unsigned long)ctxt->_eip;
2872 jmp_rel(ctxt, rel);
2873 return em_push(ctxt);
2874}
2875
0ef753b8
AK		 2876static int em_call_far(struct x86_emulate_ctxt *ctxt)
2877{
0ef753b8
AK		 2878 u16 sel, old_cs;
2879 ulong old_eip;
2880 int rc;
2881
1aa36616 2882 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
9dac77fa 2883 old_eip = ctxt->_eip;
0ef753b8 2884
9dac77fa 2885 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
7b105ca2 2886 if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS))
0ef753b8
AK		 2887 return X86EMUL_CONTINUE;
2888
9dac77fa
AK		 2889 ctxt->_eip = 0;
2890 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
0ef753b8 2891
9dac77fa 2892 ctxt->src.val = old_cs;
4487b3b4 2893 rc = em_push(ctxt);
0ef753b8
AK		 2894 if (rc != X86EMUL_CONTINUE)
2895 return rc;
2896
9dac77fa 2897 ctxt->src.val = old_eip;
4487b3b4 2898 return em_push(ctxt);
0ef753b8
AK		 2899}
2900
40ece7c7
AK		 2901static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2902{
40ece7c7
AK		 2903 int rc;
2904
9dac77fa
AK		 2905 ctxt->dst.type = OP_REG;
2906 ctxt->dst.addr.reg = &ctxt->_eip;
2907 ctxt->dst.bytes = ctxt->op_bytes;
2908 rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
40ece7c7
AK		 2909 if (rc != X86EMUL_CONTINUE)
2910 return rc;
5ad105e5 2911 rsp_increment(ctxt, ctxt->src.val);
40ece7c7
AK		 2912 return X86EMUL_CONTINUE;
2913}
2914
e4f973ae
TY		 2915static int em_xchg(struct x86_emulate_ctxt *ctxt)
2916{
e4f973ae 2917 /* Write back the register source. */
9dac77fa
AK		 2918 ctxt->src.val = ctxt->dst.val;
2919 write_register_operand(&ctxt->src);
e4f973ae
TY		 2920
2921 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 2922 ctxt->dst.val = ctxt->src.orig_val;
2923 ctxt->lock_prefix = 1;
e4f973ae
TY		 2924 return X86EMUL_CONTINUE;
2925}
2926
5c82aa29
AK		 2927static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2928{
9dac77fa 2929 ctxt->dst.val = ctxt->src2.val;
4d758349 2930 return fastop(ctxt, em_imul);
5c82aa29
AK		 2931}
2932
61429142
AK		 2933static int em_cwd(struct x86_emulate_ctxt *ctxt)
2934{
9dac77fa
AK		 2935 ctxt->dst.type = OP_REG;
2936 ctxt->dst.bytes = ctxt->src.bytes;
dd856efa 2937 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
9dac77fa 2938 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 2939
2940 return X86EMUL_CONTINUE;
2941}
2942
48bb5d3c
AK		 2943static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2944{
48bb5d3c
AK		 2945 u64 tsc = 0;
2946
717746e3 2947 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
dd856efa
AK		 2948 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
2949 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
48bb5d3c
AK		 2950 return X86EMUL_CONTINUE;
2951}
2952
222d21aa
AK		 2953static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
2954{
2955 u64 pmc;
2956
dd856efa 2957 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
222d21aa 2958 return emulate_gp(ctxt, 0);
dd856efa
AK		 2959 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
2960 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
222d21aa
AK		 2961 return X86EMUL_CONTINUE;
2962}
2963
b9eac5f4
AK		 2964static int em_mov(struct x86_emulate_ctxt *ctxt)
2965{
49597d81 2966 memcpy(ctxt->dst.valptr, ctxt->src.valptr, ctxt->op_bytes);
b9eac5f4
AK		 2967 return X86EMUL_CONTINUE;
2968}
2969
84cffe49
BP		 2970#define FFL(x) bit(X86_FEATURE_##x)
2971
2972static int em_movbe(struct x86_emulate_ctxt *ctxt)
2973{
2974 u32 ebx, ecx, edx, eax = 1;
2975 u16 tmp;
2976
2977 /*
2978 * Check MOVBE is set in the guest-visible CPUID leaf.
2979 */
2980 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2981 if (!(ecx & FFL(MOVBE)))
2982 return emulate_ud(ctxt);
2983
2984 switch (ctxt->op_bytes) {
2985 case 2:
2986 /*
2987 * From MOVBE definition: "...When the operand size is 16 bits,
2988 * the upper word of the destination register remains unchanged
2989 * ..."
2990 *
2991 * Both casting ->valptr and ->val to u16 breaks strict aliasing
2992 * rules so we have to do the operation almost per hand.
2993 */
2994 tmp = (u16)ctxt->src.val;
2995 ctxt->dst.val &= ~0xffffUL;
2996 ctxt->dst.val |= (unsigned long)swab16(tmp);
2997 break;
2998 case 4:
2999 ctxt->dst.val = swab32((u32)ctxt->src.val);
3000 break;
3001 case 8:
3002 ctxt->dst.val = swab64(ctxt->src.val);
3003 break;
3004 default:
3005 return X86EMUL_PROPAGATE_FAULT;
3006 }
3007 return X86EMUL_CONTINUE;
3008}
3009
bc00f8d2
TY		 3010static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3011{
3012 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
3013 return emulate_gp(ctxt, 0);
3014
3015 /* Disable writeback. */
3016 ctxt->dst.type = OP_NONE;
3017 return X86EMUL_CONTINUE;
3018}
3019
3020static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3021{
3022 unsigned long val;
3023
3024 if (ctxt->mode == X86EMUL_MODE_PROT64)
3025 val = ctxt->src.val & ~0ULL;
3026 else
3027 val = ctxt->src.val & ~0U;
3028
3029 /* #UD condition is already handled. */
3030 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3031 return emulate_gp(ctxt, 0);
3032
3033 /* Disable writeback. */
3034 ctxt->dst.type = OP_NONE;
3035 return X86EMUL_CONTINUE;
3036}
3037
e1e210b0
TY		 3038static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3039{
3040 u64 msr_data;
3041
dd856efa
AK		 3042 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3043 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3044 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
e1e210b0
TY		 3045 return emulate_gp(ctxt, 0);
3046
3047 return X86EMUL_CONTINUE;
3048}
3049
3050static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3051{
3052 u64 msr_data;
3053
dd856efa 3054 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
e1e210b0
TY		 3055 return emulate_gp(ctxt, 0);
3056
dd856efa
AK		 3057 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3058 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
e1e210b0
TY		 3059 return X86EMUL_CONTINUE;
3060}
3061
1bd5f469
TY		 3062static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3063{
9dac77fa 3064 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3065 return emulate_ud(ctxt);
3066
9dac77fa 3067 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
1bd5f469
TY		 3068 return X86EMUL_CONTINUE;
3069}
3070
3071static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3072{
9dac77fa 3073 u16 sel = ctxt->src.val;
1bd5f469 3074
9dac77fa 3075 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3076 return emulate_ud(ctxt);
3077
9dac77fa 3078 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 3079 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3080
3081 /* Disable writeback. */
9dac77fa
AK		 3082 ctxt->dst.type = OP_NONE;
3083 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 3084}
3085
a14e579f
AK		 3086static int em_lldt(struct x86_emulate_ctxt *ctxt)
3087{
3088 u16 sel = ctxt->src.val;
3089
3090 /* Disable writeback. */
3091 ctxt->dst.type = OP_NONE;
3092 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3093}
3094
80890006
AK		 3095static int em_ltr(struct x86_emulate_ctxt *ctxt)
3096{
3097 u16 sel = ctxt->src.val;
3098
3099 /* Disable writeback. */
3100 ctxt->dst.type = OP_NONE;
3101 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3102}
3103
38503911
AK		 3104static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3105{
9fa088f4
AK		 3106 int rc;
3107 ulong linear;
3108
9dac77fa 3109 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 3110 if (rc == X86EMUL_CONTINUE)
3cb16fe7 3111 ctxt->ops->invlpg(ctxt, linear);
38503911 3112 /* Disable writeback. */
9dac77fa 3113 ctxt->dst.type = OP_NONE;
38503911
AK		 3114 return X86EMUL_CONTINUE;
3115}
3116
2d04a05b
AK		 3117static int em_clts(struct x86_emulate_ctxt *ctxt)
3118{
3119 ulong cr0;
3120
3121 cr0 = ctxt->ops->get_cr(ctxt, 0);
3122 cr0 &= ~X86_CR0_TS;
3123 ctxt->ops->set_cr(ctxt, 0, cr0);
3124 return X86EMUL_CONTINUE;
3125}
3126
26d05cc7
AK		 3127static int em_vmcall(struct x86_emulate_ctxt *ctxt)
3128{
26d05cc7
AK		 3129 int rc;
3130
9dac77fa 3131 if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1)
26d05cc7
AK		 3132 return X86EMUL_UNHANDLEABLE;
3133
3134 rc = ctxt->ops->fix_hypercall(ctxt);
3135 if (rc != X86EMUL_CONTINUE)
3136 return rc;
3137
3138 /* Let the processor re-execute the fixed hypercall */
9dac77fa 3139 ctxt->_eip = ctxt->eip;
26d05cc7 3140 /* Disable writeback. */
9dac77fa 3141 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3142 return X86EMUL_CONTINUE;
3143}
3144
96051572
AK		 3145static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3146 void (*get)(struct x86_emulate_ctxt *ctxt,
3147 struct desc_ptr *ptr))
3148{
3149 struct desc_ptr desc_ptr;
3150
3151 if (ctxt->mode == X86EMUL_MODE_PROT64)
3152 ctxt->op_bytes = 8;
3153 get(ctxt, &desc_ptr);
3154 if (ctxt->op_bytes == 2) {
3155 ctxt->op_bytes = 4;
3156 desc_ptr.address &= 0x00ffffff;
3157 }
3158 /* Disable writeback. */
3159 ctxt->dst.type = OP_NONE;
3160 return segmented_write(ctxt, ctxt->dst.addr.mem,
3161 &desc_ptr, 2 + ctxt->op_bytes);
3162}
3163
3164static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3165{
3166 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3167}
3168
3169static int em_sidt(struct x86_emulate_ctxt *ctxt)
3170{
3171 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3172}
3173
26d05cc7
AK		 3174static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3175{
26d05cc7
AK		 3176 struct desc_ptr desc_ptr;
3177 int rc;
3178
510425ff
AK		 3179 if (ctxt->mode == X86EMUL_MODE_PROT64)
3180 ctxt->op_bytes = 8;
9dac77fa 3181 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3182 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3183 ctxt->op_bytes);
26d05cc7
AK		 3184 if (rc != X86EMUL_CONTINUE)
3185 return rc;
3186 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3187 /* Disable writeback. */
9dac77fa 3188 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3189 return X86EMUL_CONTINUE;
3190}
3191
5ef39c71 3192static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3193{
26d05cc7
AK		 3194 int rc;
3195
5ef39c71
AK		 3196 rc = ctxt->ops->fix_hypercall(ctxt);
3197
26d05cc7 3198 /* Disable writeback. */
9dac77fa 3199 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3200 return rc;
3201}
3202
3203static int em_lidt(struct x86_emulate_ctxt *ctxt)
3204{
26d05cc7
AK		 3205 struct desc_ptr desc_ptr;
3206 int rc;
3207
510425ff
AK		 3208 if (ctxt->mode == X86EMUL_MODE_PROT64)
3209 ctxt->op_bytes = 8;
9dac77fa 3210 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
509cf9fe 3211 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3212 ctxt->op_bytes);
26d05cc7
AK		 3213 if (rc != X86EMUL_CONTINUE)
3214 return rc;
3215 ctxt->ops->set_idt(ctxt, &desc_ptr);
3216 /* Disable writeback. */
9dac77fa 3217 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3218 return X86EMUL_CONTINUE;
3219}
3220
3221static int em_smsw(struct x86_emulate_ctxt *ctxt)
3222{
9dac77fa
AK		 3223 ctxt->dst.bytes = 2;
3224 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3225 return X86EMUL_CONTINUE;
3226}
3227
3228static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3229{
26d05cc7 3230 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3231 | (ctxt->src.val & 0x0f));
3232 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3233 return X86EMUL_CONTINUE;
3234}
3235
d06e03ad
TY		 3236static int em_loop(struct x86_emulate_ctxt *ctxt)
3237{
dd856efa
AK		 3238 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX), -1);
3239 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
9dac77fa
AK		 3240 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
3241 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3242
3243 return X86EMUL_CONTINUE;
3244}
3245
3246static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3247{
dd856efa 3248 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
9dac77fa 3249 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3250
3251 return X86EMUL_CONTINUE;
3252}
3253
d7841a4b
TY		 3254static int em_in(struct x86_emulate_ctxt *ctxt)
3255{
3256 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3257 &ctxt->dst.val))
3258 return X86EMUL_IO_NEEDED;
3259
3260 return X86EMUL_CONTINUE;
3261}
3262
3263static int em_out(struct x86_emulate_ctxt *ctxt)
3264{
3265 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3266 &ctxt->src.val, 1);
3267 /* Disable writeback. */
3268 ctxt->dst.type = OP_NONE;
3269 return X86EMUL_CONTINUE;
3270}
3271
f411e6cd
TY		 3272static int em_cli(struct x86_emulate_ctxt *ctxt)
3273{
3274 if (emulator_bad_iopl(ctxt))
3275 return emulate_gp(ctxt, 0);
3276
3277 ctxt->eflags &= ~X86_EFLAGS_IF;
3278 return X86EMUL_CONTINUE;
3279}
3280
3281static int em_sti(struct x86_emulate_ctxt *ctxt)
3282{
3283 if (emulator_bad_iopl(ctxt))
3284 return emulate_gp(ctxt, 0);
3285
3286 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3287 ctxt->eflags |= X86_EFLAGS_IF;
3288 return X86EMUL_CONTINUE;
3289}
3290
6d6eede4
AK		 3291static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3292{
3293 u32 eax, ebx, ecx, edx;
3294
dd856efa
AK		 3295 eax = reg_read(ctxt, VCPU_REGS_RAX);
3296 ecx = reg_read(ctxt, VCPU_REGS_RCX);
6d6eede4 3297 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
dd856efa
AK		 3298 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3299 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3300 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3301 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
6d6eede4
AK		 3302 return X86EMUL_CONTINUE;
3303}
3304
98f73630
PB		 3305static int em_sahf(struct x86_emulate_ctxt *ctxt)
3306{
3307 u32 flags;
3308
3309 flags = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF;
3310 flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8;
3311
3312 ctxt->eflags &= ~0xffUL;
3313 ctxt->eflags |= flags | X86_EFLAGS_FIXED;
3314 return X86EMUL_CONTINUE;
3315}
3316
2dd7caa0
AK		 3317static int em_lahf(struct x86_emulate_ctxt *ctxt)
3318{
dd856efa
AK		 3319 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3320 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
2dd7caa0
AK		 3321 return X86EMUL_CONTINUE;
3322}
3323
9299836e
AK		 3324static int em_bswap(struct x86_emulate_ctxt *ctxt)
3325{
3326 switch (ctxt->op_bytes) {
3327#ifdef CONFIG_X86_64
3328 case 8:
3329 asm("bswap %0" : "+r"(ctxt->dst.val));
3330 break;
3331#endif
3332 default:
3333 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3334 break;
3335 }
3336 return X86EMUL_CONTINUE;
3337}
3338
cfec82cb
JR		 3339static bool valid_cr(int nr)
3340{
3341 switch (nr) {
3342 case 0:
3343 case 2 ... 4:
3344 case 8:
3345 return true;
3346 default:
3347 return false;
3348 }
3349}
3350
3351static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3352{
9dac77fa 3353 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 3354 return emulate_ud(ctxt);
3355
3356 return X86EMUL_CONTINUE;
3357}
3358
3359static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3360{
9dac77fa
AK		 3361 u64 new_val = ctxt->src.val64;
3362 int cr = ctxt->modrm_reg;
c2ad2bb3 3363 u64 efer = 0;
cfec82cb
JR		 3364
3365 static u64 cr_reserved_bits[] = {
3366 0xffffffff00000000ULL,
3367 0, 0, 0, /* CR3 checked later */
3368 CR4_RESERVED_BITS,
3369 0, 0, 0,
3370 CR8_RESERVED_BITS,
3371 };
3372
3373 if (!valid_cr(cr))
3374 return emulate_ud(ctxt);
3375
3376 if (new_val & cr_reserved_bits[cr])
3377 return emulate_gp(ctxt, 0);
3378
3379 switch (cr) {
3380 case 0: {
c2ad2bb3 3381 u64 cr4;
cfec82cb
JR		 3382 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3383 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3384 return emulate_gp(ctxt, 0);
3385
717746e3
AK		 3386 cr4 = ctxt->ops->get_cr(ctxt, 4);
3387 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3388
3389 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3390 !(cr4 & X86_CR4_PAE))
3391 return emulate_gp(ctxt, 0);
3392
3393 break;
3394 }
3395 case 3: {
3396 u64 rsvd = 0;
3397
c2ad2bb3
AK		 3398 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3399 if (efer & EFER_LMA)
cfec82cb 3400 rsvd = CR3_L_MODE_RESERVED_BITS;
cfec82cb
JR		 3401
3402 if (new_val & rsvd)
3403 return emulate_gp(ctxt, 0);
3404
3405 break;
3406 }
3407 case 4: {
717746e3 3408 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3409
3410 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3411 return emulate_gp(ctxt, 0);
3412
3413 break;
3414 }
3415 }
3416
3417 return X86EMUL_CONTINUE;
3418}
3419
3b88e41a
JR		 3420static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3421{
3422 unsigned long dr7;
3423
717746e3 3424 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 3425
3426 /* Check if DR7.Global_Enable is set */
3427 return dr7 & (1 << 13);
3428}
3429
3430static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3431{
9dac77fa 3432 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3433 u64 cr4;
3434
3435 if (dr > 7)
3436 return emulate_ud(ctxt);
3437
717746e3 3438 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 3439 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3440 return emulate_ud(ctxt);
3441
3442 if (check_dr7_gd(ctxt))
3443 return emulate_db(ctxt);
3444
3445 return X86EMUL_CONTINUE;
3446}
3447
3448static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3449{
9dac77fa
AK		 3450 u64 new_val = ctxt->src.val64;
3451 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3452
3453 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3454 return emulate_gp(ctxt, 0);
3455
3456 return check_dr_read(ctxt);
3457}
3458
01de8b09
JR		 3459static int check_svme(struct x86_emulate_ctxt *ctxt)
3460{
3461 u64 efer;
3462
717746e3 3463 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 3464
3465 if (!(efer & EFER_SVME))
3466 return emulate_ud(ctxt);
3467
3468 return X86EMUL_CONTINUE;
3469}
3470
3471static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3472{
dd856efa 3473 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
01de8b09
JR		 3474
3475 /* Valid physical address? */
d4224449 3476 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 3477 return emulate_gp(ctxt, 0);
3478
3479 return check_svme(ctxt);
3480}
3481
d7eb8203
JR		 3482static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3483{
717746e3 3484 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 3485
717746e3 3486 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 3487 return emulate_ud(ctxt);
3488
3489 return X86EMUL_CONTINUE;
3490}
3491
8061252e
JR		 3492static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3493{
717746e3 3494 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
dd856efa 3495 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
8061252e 3496
717746e3 3497 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
8061252e
JR		 3498 (rcx > 3))
3499 return emulate_gp(ctxt, 0);
3500
3501 return X86EMUL_CONTINUE;
3502}
3503
f6511935
JR		 3504static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3505{
9dac77fa
AK		 3506 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3507 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 3508 return emulate_gp(ctxt, 0);
3509
3510 return X86EMUL_CONTINUE;
3511}
3512
3513static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3514{
9dac77fa
AK		 3515 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3516 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 3517 return emulate_gp(ctxt, 0);
3518
3519 return X86EMUL_CONTINUE;
3520}
3521
73fba5f4 3522#define D(_y) { .flags = (_y) }
c4f035c6 3523#define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
d09beabd
JR		 3524#define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
3525 .check_perm = (_p) }
0b789eee 3526#define N D(NotImpl)
01de8b09 3527#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 3528#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3529#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
045a282c 3530#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
73fba5f4 3531#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
e28bbd44 3532#define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
c4f035c6
AK		 3533#define II(_f, _e, _i) \
3534 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd
JR		 3535#define IIP(_f, _e, _i, _p) \
3536 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
3537 .check_perm = (_p) }
aa97bb48 3538#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3539
8d8f4e9f 3540#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3541#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 3542#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
f7857f35 3543#define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e)
d7841a4b
TY		 3544#define I2bvIP(_f, _e, _i, _p) \
3545 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 3546
fb864fbc
AK		 3547#define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3548 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3549 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3550
fd0a0d82 3551static const struct opcode group7_rm1[] = {
1c2545be
TY		 3552 DI(SrcNone | Priv, monitor),
3553 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 3554 N, N, N, N, N, N,
3555};
3556
fd0a0d82 3557static const struct opcode group7_rm3[] = {
1c2545be 3558 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
b51e974f 3559 II(SrcNone | Prot | EmulateOnUD, em_vmmcall, vmmcall),
1c2545be
TY		 3560 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3561 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3562 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3563 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3564 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3565 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 3566};
6230f7fc 3567
fd0a0d82 3568static const struct opcode group7_rm7[] = {
d7eb8203 3569 N,
1c2545be 3570 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 3571 N, N, N, N, N, N,
3572};
d67fc27a 3573
fd0a0d82 3574static const struct opcode group1[] = {
fb864fbc
AK		 3575 F(Lock, em_add),
3576 F(Lock | PageTable, em_or),
3577 F(Lock, em_adc),
3578 F(Lock, em_sbb),
3579 F(Lock | PageTable, em_and),
3580 F(Lock, em_sub),
3581 F(Lock, em_xor),
3582 F(NoWrite, em_cmp),
73fba5f4
AK		 3583};
3584
fd0a0d82 3585static const struct opcode group1A[] = {
1c2545be 3586 I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 3587};
3588
007a3b54
AK		 3589static const struct opcode group2[] = {
3590 F(DstMem | ModRM, em_rol),
3591 F(DstMem | ModRM, em_ror),
3592 F(DstMem | ModRM, em_rcl),
3593 F(DstMem | ModRM, em_rcr),
3594 F(DstMem | ModRM, em_shl),
3595 F(DstMem | ModRM, em_shr),
3596 F(DstMem | ModRM, em_shl),
3597 F(DstMem | ModRM, em_sar),
3598};
3599
fd0a0d82 3600static const struct opcode group3[] = {
fb864fbc
AK		 3601 F(DstMem | SrcImm | NoWrite, em_test),
3602 F(DstMem | SrcImm | NoWrite, em_test),
45a1467d
AK		 3603 F(DstMem | SrcNone | Lock, em_not),
3604 F(DstMem | SrcNone | Lock, em_neg),
b9fa409b
AK		 3605 F(DstXacc | Src2Mem, em_mul_ex),
3606 F(DstXacc | Src2Mem, em_imul_ex),
b8c0b6ae
AK		 3607 F(DstXacc | Src2Mem, em_div_ex),
3608 F(DstXacc | Src2Mem, em_idiv_ex),
73fba5f4
AK		 3609};
3610
fd0a0d82 3611static const struct opcode group4[] = {
95413dc4
AK		 3612 F(ByteOp | DstMem | SrcNone | Lock, em_inc),
3613 F(ByteOp | DstMem | SrcNone | Lock, em_dec),
73fba5f4
AK		 3614 N, N, N, N, N, N,
3615};
3616
fd0a0d82 3617static const struct opcode group5[] = {
95413dc4
AK		 3618 F(DstMem | SrcNone | Lock, em_inc),
3619 F(DstMem | SrcNone | Lock, em_dec),
1c2545be
TY		 3620 I(SrcMem | Stack, em_grp45),
3621 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far),
3622 I(SrcMem | Stack, em_grp45),
3623 I(SrcMemFAddr | ImplicitOps, em_grp45),
188424ba 3624 I(SrcMem | Stack, em_grp45), D(Undefined),
73fba5f4
AK		 3625};
3626
fd0a0d82 3627static const struct opcode group6[] = {
1c2545be
TY		 3628 DI(Prot, sldt),
3629 DI(Prot, str),
a14e579f 3630 II(Prot | Priv | SrcMem16, em_lldt, lldt),
80890006 3631 II(Prot | Priv | SrcMem16, em_ltr, ltr),
dee6bb70
JR		 3632 N, N, N, N,
3633};
3634
fd0a0d82 3635static const struct group_dual group7 = { {
96051572
AK		 3636 II(Mov | DstMem | Priv, em_sgdt, sgdt),
3637 II(Mov | DstMem | Priv, em_sidt, sidt),
1c2545be
TY		 3638 II(SrcMem | Priv, em_lgdt, lgdt),
3639 II(SrcMem | Priv, em_lidt, lidt),
3640 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3641 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3642 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3643}, {
b51e974f 3644 I(SrcNone | Priv | EmulateOnUD, em_vmcall),
5ef39c71 3645 EXT(0, group7_rm1),
01de8b09 3646 N, EXT(0, group7_rm3),
1c2545be
TY		 3647 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3648 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3649 EXT(0, group7_rm7),
73fba5f4
AK		 3650} };
3651
fd0a0d82 3652static const struct opcode group8[] = {
73fba5f4 3653 N, N, N, N,
11c363ba
AK		 3654 F(DstMem | SrcImmByte | NoWrite, em_bt),
3655 F(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3656 F(DstMem | SrcImmByte | Lock, em_btr),
3657 F(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 3658};
3659
fd0a0d82 3660static const struct group_dual group9 = { {
1c2545be 3661 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 3662}, {
3663 N, N, N, N, N, N, N, N,
3664} };
3665
fd0a0d82 3666static const struct opcode group11[] = {
1c2545be 3667 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 3668 X7(D(Undefined)),
a4d4a7c1
AK		 3669};
3670
fd0a0d82 3671static const struct gprefix pfx_0f_6f_0f_7f = {
e5971755 3672 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 3673};
3674
fd0a0d82 3675static const struct gprefix pfx_vmovntpx = {
3e114eb4
AK		 3676 I(0, em_mov), N, N, N,
3677};
3678
27ce8258 3679static const struct gprefix pfx_0f_28_0f_29 = {
6fec27d8 3680 I(Aligned, em_mov), I(Aligned, em_mov), N, N,
27ce8258
IM		 3681};
3682
045a282c
GN		 3683static const struct escape escape_d9 = { {
3684 N, N, N, N, N, N, N, I(DstMem, em_fnstcw),
3685}, {
3686 /* 0xC0 - 0xC7 */
3687 N, N, N, N, N, N, N, N,
3688 /* 0xC8 - 0xCF */
3689 N, N, N, N, N, N, N, N,
3690 /* 0xD0 - 0xC7 */
3691 N, N, N, N, N, N, N, N,
3692 /* 0xD8 - 0xDF */
3693 N, N, N, N, N, N, N, N,
3694 /* 0xE0 - 0xE7 */
3695 N, N, N, N, N, N, N, N,
3696 /* 0xE8 - 0xEF */
3697 N, N, N, N, N, N, N, N,
3698 /* 0xF0 - 0xF7 */
3699 N, N, N, N, N, N, N, N,
3700 /* 0xF8 - 0xFF */
3701 N, N, N, N, N, N, N, N,
3702} };
3703
3704static const struct escape escape_db = { {
3705 N, N, N, N, N, N, N, N,
3706}, {
3707 /* 0xC0 - 0xC7 */
3708 N, N, N, N, N, N, N, N,
3709 /* 0xC8 - 0xCF */
3710 N, N, N, N, N, N, N, N,
3711 /* 0xD0 - 0xC7 */
3712 N, N, N, N, N, N, N, N,
3713 /* 0xD8 - 0xDF */
3714 N, N, N, N, N, N, N, N,
3715 /* 0xE0 - 0xE7 */
3716 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
3717 /* 0xE8 - 0xEF */
3718 N, N, N, N, N, N, N, N,
3719 /* 0xF0 - 0xF7 */
3720 N, N, N, N, N, N, N, N,
3721 /* 0xF8 - 0xFF */
3722 N, N, N, N, N, N, N, N,
3723} };
3724
3725static const struct escape escape_dd = { {
3726 N, N, N, N, N, N, N, I(DstMem, em_fnstsw),
3727}, {
3728 /* 0xC0 - 0xC7 */
3729 N, N, N, N, N, N, N, N,
3730 /* 0xC8 - 0xCF */
3731 N, N, N, N, N, N, N, N,
3732 /* 0xD0 - 0xC7 */
3733 N, N, N, N, N, N, N, N,
3734 /* 0xD8 - 0xDF */
3735 N, N, N, N, N, N, N, N,
3736 /* 0xE0 - 0xE7 */
3737 N, N, N, N, N, N, N, N,
3738 /* 0xE8 - 0xEF */
3739 N, N, N, N, N, N, N, N,
3740 /* 0xF0 - 0xF7 */
3741 N, N, N, N, N, N, N, N,
3742 /* 0xF8 - 0xFF */
3743 N, N, N, N, N, N, N, N,
3744} };
3745
fd0a0d82 3746static const struct opcode opcode_table[256] = {
73fba5f4 3747 /* 0x00 - 0x07 */
fb864fbc 3748 F6ALU(Lock, em_add),
1cd196ea
AK		 3749 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3750 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 3751 /* 0x08 - 0x0F */
fb864fbc 3752 F6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 3753 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3754 N,
73fba5f4 3755 /* 0x10 - 0x17 */
fb864fbc 3756 F6ALU(Lock, em_adc),
1cd196ea
AK		 3757 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3758 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 3759 /* 0x18 - 0x1F */
fb864fbc 3760 F6ALU(Lock, em_sbb),
1cd196ea
AK		 3761 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3762 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 3763 /* 0x20 - 0x27 */
fb864fbc 3764 F6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 3765 /* 0x28 - 0x2F */
fb864fbc 3766 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3767 /* 0x30 - 0x37 */
fb864fbc 3768 F6ALU(Lock, em_xor), N, N,
73fba5f4 3769 /* 0x38 - 0x3F */
fb864fbc 3770 F6ALU(NoWrite, em_cmp), N, N,
73fba5f4 3771 /* 0x40 - 0x4F */
95413dc4 3772 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
73fba5f4 3773 /* 0x50 - 0x57 */
63540382 3774 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3775 /* 0x58 - 0x5F */
c54fe504 3776 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3777 /* 0x60 - 0x67 */
b96a7fad
TY		 3778 I(ImplicitOps | Stack | No64, em_pusha),
3779 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3780 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3781 N, N, N, N,
3782 /* 0x68 - 0x6F */
d46164db
AK		 3783 I(SrcImm | Mov | Stack, em_push),
3784 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3785 I(SrcImmByte | Mov | Stack, em_push),
3786 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
b3356bf0 3787 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
2b5e97e1 3788 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4
AK		 3789 /* 0x70 - 0x7F */
3790 X16(D(SrcImmByte)),
3791 /* 0x80 - 0x87 */
1c2545be
TY		 3792 G(ByteOp | DstMem | SrcImm, group1),
3793 G(DstMem | SrcImm, group1),
3794 G(ByteOp | DstMem | SrcImm | No64, group1),
3795 G(DstMem | SrcImmByte, group1),
fb864fbc 3796 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
d5ae7ce8 3797 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 3798 /* 0x88 - 0x8F */
d5ae7ce8 3799 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 3800 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 3801 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 3802 D(ModRM | SrcMem | NoAccess | DstReg),
3803 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3804 G(0, group1A),
73fba5f4 3805 /* 0x90 - 0x97 */
bf608f88 3806 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3807 /* 0x98 - 0x9F */
61429142 3808 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3809 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0 3810 II(ImplicitOps | Stack, em_pushf, pushf),
98f73630
PB		 3811 II(ImplicitOps | Stack, em_popf, popf),
3812 I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf),
73fba5f4 3813 /* 0xA0 - 0xA7 */
b9eac5f4 3814 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 3815 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 3816 I2bv(SrcSI | DstDI | Mov | String, em_mov),
fb864fbc 3817 F2bv(SrcSI | DstDI | String | NoWrite, em_cmp),
73fba5f4 3818 /* 0xA8 - 0xAF */
fb864fbc 3819 F2bv(DstAcc | SrcImm | NoWrite, em_test),
b9eac5f4
AK		 3820 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3821 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
fb864fbc 3822 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp),
73fba5f4 3823 /* 0xB0 - 0xB7 */
b9eac5f4 3824 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3825 /* 0xB8 - 0xBF */
5e2c6883 3826 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
73fba5f4 3827 /* 0xC0 - 0xC7 */
007a3b54 3828 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
40ece7c7 3829 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
ebda02c2 3830 I(ImplicitOps | Stack, em_ret),
d4b4325f
AK		 3831 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
3832 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 3833 G(ByteOp, group11), G(0, group11),
73fba5f4 3834 /* 0xC8 - 0xCF */
612e89f0 3835 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
3261107e
BR		 3836 I(ImplicitOps | Stack | SrcImmU16, em_ret_far_imm),
3837 I(ImplicitOps | Stack, em_ret_far),
3c6e276f 3838 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 3839 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 3840 /* 0xD0 - 0xD7 */
007a3b54
AK		 3841 G(Src2One | ByteOp, group2), G(Src2One, group2),
3842 G(Src2CL | ByteOp, group2), G(Src2CL, group2),
a035d5c6 3843 I(DstAcc | SrcImmUByte | No64, em_aam),
326f578f
PB		 3844 I(DstAcc | SrcImmUByte | No64, em_aad),
3845 F(DstAcc | ByteOp | No64, em_salc),
7fa57952 3846 I(DstAcc | SrcXLat | ByteOp, em_mov),
73fba5f4 3847 /* 0xD8 - 0xDF */
045a282c 3848 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
73fba5f4 3849 /* 0xE0 - 0xE7 */
d06e03ad
TY		 3850 X3(I(SrcImmByte, em_loop)),
3851 I(SrcImmByte, em_jcxz),
d7841a4b
TY		 3852 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
3853 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 3854 /* 0xE8 - 0xEF */
d4ddafcd 3855 I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps),
db5b0762 3856 I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
d7841a4b
TY		 3857 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
3858 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 3859 /* 0xF0 - 0xF7 */
bf608f88 3860 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 3861 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3862 G(ByteOp, group3), G(0, group3),
73fba5f4 3863 /* 0xF8 - 0xFF */
f411e6cd
TY		 3864 D(ImplicitOps), D(ImplicitOps),
3865 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 3866 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3867};
3868
fd0a0d82 3869static const struct opcode twobyte_table[256] = {
73fba5f4 3870 /* 0x00 - 0x0F */
dee6bb70 3871 G(0, group6), GD(0, &group7), N, N,
b51e974f 3872 N, I(ImplicitOps | EmulateOnUD, em_syscall),
db5b0762 3873 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 3874 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK		 3875 N, D(ImplicitOps | ModRM), N, N,
3876 /* 0x10 - 0x1F */
103f98ea
PB		 3877 N, N, N, N, N, N, N, N,
3878 D(ImplicitOps | ModRM), N, N, N, N, N, N, D(ImplicitOps | ModRM),
73fba5f4 3879 /* 0x20 - 0x2F */
cfec82cb 3880 DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
3b88e41a 3881 DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
bc00f8d2
TY		 3882 IIP(ModRM | SrcMem | Priv | Op3264, em_cr_write, cr_write, check_cr_write),
3883 IIP(ModRM | SrcMem | Priv | Op3264, em_dr_write, dr_write, check_dr_write),
73fba5f4 3884 N, N, N, N,
27ce8258
IM		 3885 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29),
3886 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29),
3887 N, GP(ModRM | DstMem | SrcReg | Sse | Mov | Aligned, &pfx_vmovntpx),
3e114eb4 3888 N, N, N, N,
73fba5f4 3889 /* 0x30 - 0x3F */
e1e210b0 3890 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 3891 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 3892 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 3893 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
b51e974f
BP		 3894 I(ImplicitOps | EmulateOnUD, em_sysenter),
3895 I(ImplicitOps | Priv | EmulateOnUD, em_sysexit),
d867162c 3896 N, N,
73fba5f4
AK		 3897 N, N, N, N, N, N, N, N,
3898 /* 0x40 - 0x4F */
3899 X16(D(DstReg | SrcMem | ModRM | Mov)),
3900 /* 0x50 - 0x5F */
3901 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3902 /* 0x60 - 0x6F */
aa97bb48
AK		 3903 N, N, N, N,
3904 N, N, N, N,
3905 N, N, N, N,
3906 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 3907 /* 0x70 - 0x7F */
aa97bb48
AK		 3908 N, N, N, N,
3909 N, N, N, N,
3910 N, N, N, N,
3911 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK		 3912 /* 0x80 - 0x8F */
3913 X16(D(SrcImm)),
3914 /* 0x90 - 0x9F */
ee45b58e 3915 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 3916 /* 0xA0 - 0xA7 */
1cd196ea 3917 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
11c363ba
AK		 3918 II(ImplicitOps, em_cpuid, cpuid),
3919 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
0bdea068
AK		 3920 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
3921 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
73fba5f4 3922 /* 0xA8 - 0xAF */
1cd196ea 3923 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
d5ae7ce8 3924 DI(ImplicitOps, rsm),
11c363ba 3925 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
0bdea068
AK		 3926 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
3927 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
4d758349 3928 D(ModRM), F(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 3929 /* 0xB0 - 0xB7 */
e940b5c2 3930 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
d4b4325f 3931 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
11c363ba 3932 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 3933 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
3934 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 3935 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 3936 /* 0xB8 - 0xBF */
3937 N, N,
ce7faab2 3938 G(BitOp, group8),
11c363ba
AK		 3939 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
3940 F(DstReg | SrcMem | ModRM, em_bsf), F(DstReg | SrcMem | ModRM, em_bsr),
2adb5ad9 3941 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
9299836e 3942 /* 0xC0 - 0xC7 */
e47a5f5f 3943 F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd),
92f738a5 3944 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4 3945 N, N, N, GD(0, &group9),
9299836e
AK		 3946 /* 0xC8 - 0xCF */
3947 X8(I(DstReg, em_bswap)),
73fba5f4
AK		 3948 /* 0xD0 - 0xDF */
3949 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3950 /* 0xE0 - 0xEF */
3951 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3952 /* 0xF0 - 0xFF */
3953 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
3954};
3955
0bc5eedb 3956static const struct gprefix three_byte_0f_38_f0 = {
84cffe49 3957 I(DstReg | SrcMem | Mov, em_movbe), N, N, N
0bc5eedb
BP		 3958};
3959
3960static const struct gprefix three_byte_0f_38_f1 = {
84cffe49 3961 I(DstMem | SrcReg | Mov, em_movbe), N, N, N
0bc5eedb
BP		 3962};
3963
3964/*
3965 * Insns below are selected by the prefix which indexed by the third opcode
3966 * byte.
3967 */
3968static const struct opcode opcode_map_0f_38[256] = {
3969 /* 0x00 - 0x7f */
3970 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
84cffe49
BP		 3971 /* 0x80 - 0xef */
3972 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
3973 /* 0xf0 - 0xf1 */
3974 GP(EmulateOnUD | ModRM | Prefix, &three_byte_0f_38_f0),
3975 GP(EmulateOnUD | ModRM | Prefix, &three_byte_0f_38_f1),
3976 /* 0xf2 - 0xff */
3977 N, N, X4(N), X8(N)
0bc5eedb
BP		 3978};
3979
73fba5f4
AK		 3980#undef D
3981#undef N
3982#undef G
3983#undef GD
3984#undef I
aa97bb48 3985#undef GP
01de8b09 3986#undef EXT
73fba5f4 3987
8d8f4e9f 3988#undef D2bv
f6511935 3989#undef D2bvIP
8d8f4e9f 3990#undef I2bv
d7841a4b 3991#undef I2bvIP
d67fc27a 3992#undef I6ALU
8d8f4e9f 3993
9dac77fa 3994static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 3995{
3996 unsigned size;
3997
9dac77fa 3998 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 3999 if (size == 8)
4000 size = 4;
4001 return size;
4002}
4003
4004static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
4005 unsigned size, bool sign_extension)
4006{
39f21ee5
AK		 4007 int rc = X86EMUL_CONTINUE;
4008
4009 op->type = OP_IMM;
4010 op->bytes = size;
9dac77fa 4011 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 4012 /* NB. Immediates are sign-extended as necessary. */
4013 switch (op->bytes) {
4014 case 1:
e85a1085 4015 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 4016 break;
4017 case 2:
e85a1085 4018 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 4019 break;
4020 case 4:
e85a1085 4021 op->val = insn_fetch(s32, ctxt);
39f21ee5 4022 break;
5e2c6883
NA		 4023 case 8:
4024 op->val = insn_fetch(s64, ctxt);
4025 break;
39f21ee5
AK		 4026 }
4027 if (!sign_extension) {
4028 switch (op->bytes) {
4029 case 1:
4030 op->val &= 0xff;
4031 break;
4032 case 2:
4033 op->val &= 0xffff;
4034 break;
4035 case 4:
4036 op->val &= 0xffffffff;
4037 break;
4038 }
4039 }
4040done:
4041 return rc;
4042}
4043
a9945549
AK		 4044static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
4045 unsigned d)
4046{
4047 int rc = X86EMUL_CONTINUE;
4048
4049 switch (d) {
4050 case OpReg:
2adb5ad9 4051 decode_register_operand(ctxt, op);
a9945549
AK		 4052 break;
4053 case OpImmUByte:
608aabe3 4054 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 4055 break;
4056 case OpMem:
41ddf978 4057 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 4058 mem_common:
4059 *op = ctxt->memop;
4060 ctxt->memopp = op;
4061 if ((ctxt->d & BitOp) && op == &ctxt->dst)
a9945549
AK		 4062 fetch_bit_operand(ctxt);
4063 op->orig_val = op->val;
4064 break;
41ddf978
AK		 4065 case OpMem64:
4066 ctxt->memop.bytes = 8;
4067 goto mem_common;
a9945549
AK		 4068 case OpAcc:
4069 op->type = OP_REG;
4070 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 4071 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
a9945549
AK		 4072 fetch_register_operand(op);
4073 op->orig_val = op->val;
4074 break;
820207c8
AK		 4075 case OpAccLo:
4076 op->type = OP_REG;
4077 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes;
4078 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4079 fetch_register_operand(op);
4080 op->orig_val = op->val;
4081 break;
4082 case OpAccHi:
4083 if (ctxt->d & ByteOp) {
4084 op->type = OP_NONE;
4085 break;
4086 }
4087 op->type = OP_REG;
4088 op->bytes = ctxt->op_bytes;
4089 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4090 fetch_register_operand(op);
4091 op->orig_val = op->val;
4092 break;
a9945549
AK		 4093 case OpDI:
4094 op->type = OP_MEM;
4095 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4096 op->addr.mem.ea =
dd856efa 4097 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RDI));
a9945549
AK		 4098 op->addr.mem.seg = VCPU_SREG_ES;
4099 op->val = 0;
b3356bf0 4100 op->count = 1;
a9945549
AK		 4101 break;
4102 case OpDX:
4103 op->type = OP_REG;
4104 op->bytes = 2;
dd856efa 4105 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
a9945549
AK		 4106 fetch_register_operand(op);
4107 break;
4dd6a57d
AK		 4108 case OpCL:
4109 op->bytes = 1;
dd856efa 4110 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4dd6a57d
AK		 4111 break;
4112 case OpImmByte:
4113 rc = decode_imm(ctxt, op, 1, true);
4114 break;
4115 case OpOne:
4116 op->bytes = 1;
4117 op->val = 1;
4118 break;
4119 case OpImm:
4120 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4121 break;
5e2c6883
NA		 4122 case OpImm64:
4123 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
4124 break;
28867cee
AK		 4125 case OpMem8:
4126 ctxt->memop.bytes = 1;
660696d1 4127 if (ctxt->memop.type == OP_REG) {
aa9ac1a6
GN		 4128 ctxt->memop.addr.reg = decode_register(ctxt,
4129 ctxt->modrm_rm, true);
660696d1
GN		 4130 fetch_register_operand(&ctxt->memop);
4131 }
28867cee 4132 goto mem_common;
0fe59128
AK		 4133 case OpMem16:
4134 ctxt->memop.bytes = 2;
4135 goto mem_common;
4136 case OpMem32:
4137 ctxt->memop.bytes = 4;
4138 goto mem_common;
4139 case OpImmU16:
4140 rc = decode_imm(ctxt, op, 2, false);
4141 break;
4142 case OpImmU:
4143 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
4144 break;
4145 case OpSI:
4146 op->type = OP_MEM;
4147 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4148 op->addr.mem.ea =
dd856efa 4149 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RSI));
0fe59128
AK		 4150 op->addr.mem.seg = seg_override(ctxt);
4151 op->val = 0;
b3356bf0 4152 op->count = 1;
0fe59128 4153 break;
7fa57952
PB		 4154 case OpXLat:
4155 op->type = OP_MEM;
4156 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4157 op->addr.mem.ea =
4158 register_address(ctxt,
4159 reg_read(ctxt, VCPU_REGS_RBX) +
4160 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
4161 op->addr.mem.seg = seg_override(ctxt);
4162 op->val = 0;
4163 break;
0fe59128
AK		 4164 case OpImmFAddr:
4165 op->type = OP_IMM;
4166 op->addr.mem.ea = ctxt->_eip;
4167 op->bytes = ctxt->op_bytes + 2;
4168 insn_fetch_arr(op->valptr, op->bytes, ctxt);
4169 break;
4170 case OpMemFAddr:
4171 ctxt->memop.bytes = ctxt->op_bytes + 2;
4172 goto mem_common;
c191a7a0
AK		 4173 case OpES:
4174 op->val = VCPU_SREG_ES;
4175 break;
4176 case OpCS:
4177 op->val = VCPU_SREG_CS;
4178 break;
4179 case OpSS:
4180 op->val = VCPU_SREG_SS;
4181 break;
4182 case OpDS:
4183 op->val = VCPU_SREG_DS;
4184 break;
4185 case OpFS:
4186 op->val = VCPU_SREG_FS;
4187 break;
4188 case OpGS:
4189 op->val = VCPU_SREG_GS;
4190 break;
a9945549
AK		 4191 case OpImplicit:
4192 /* Special instructions do their own operand decoding. */
4193 default:
4194 op->type = OP_NONE; /* Disable writeback. */
4195 break;
4196 }
4197
4198done:
4199 return rc;
4200}
4201
ef5d75cc 4202int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 4203{
dde7e6d1
AK		 4204 int rc = X86EMUL_CONTINUE;
4205 int mode = ctxt->mode;
46561646 4206 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 4207 bool op_prefix = false;
46561646 4208 struct opcode opcode;
dde7e6d1 4209
f09ed83e
AK		 4210 ctxt->memop.type = OP_NONE;
4211 ctxt->memopp = NULL;
9dac77fa
AK		 4212 ctxt->_eip = ctxt->eip;
4213 ctxt->fetch.start = ctxt->_eip;
4214 ctxt->fetch.end = ctxt->fetch.start + insn_len;
1ce19dc1 4215 ctxt->opcode_len = 1;
dc25e89e 4216 if (insn_len > 0)
9dac77fa 4217 memcpy(ctxt->fetch.data, insn, insn_len);
dde7e6d1
AK		 4218
4219 switch (mode) {
4220 case X86EMUL_MODE_REAL:
4221 case X86EMUL_MODE_VM86:
4222 case X86EMUL_MODE_PROT16:
4223 def_op_bytes = def_ad_bytes = 2;
4224 break;
4225 case X86EMUL_MODE_PROT32:
4226 def_op_bytes = def_ad_bytes = 4;
4227 break;
4228#ifdef CONFIG_X86_64
4229 case X86EMUL_MODE_PROT64:
4230 def_op_bytes = 4;
4231 def_ad_bytes = 8;
4232 break;
4233#endif
4234 default:
1d2887e2 4235 return EMULATION_FAILED;
dde7e6d1
AK		 4236 }
4237
9dac77fa
AK		 4238 ctxt->op_bytes = def_op_bytes;
4239 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 4240
4241 /* Legacy prefixes. */
4242 for (;;) {
e85a1085 4243 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 4244 case 0x66: /* operand-size override */
0d7cdee8 4245 op_prefix = true;
dde7e6d1 4246 /* switch between 2/4 bytes */
9dac77fa 4247 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 4248 break;
4249 case 0x67: /* address-size override */
4250 if (mode == X86EMUL_MODE_PROT64)
4251 /* switch between 4/8 bytes */
9dac77fa 4252 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 4253 else
4254 /* switch between 2/4 bytes */
9dac77fa 4255 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 4256 break;
4257 case 0x26: /* ES override */
4258 case 0x2e: /* CS override */
4259 case 0x36: /* SS override */
4260 case 0x3e: /* DS override */
9dac77fa 4261 set_seg_override(ctxt, (ctxt->b >> 3) & 3);
dde7e6d1
AK		 4262 break;
4263 case 0x64: /* FS override */
4264 case 0x65: /* GS override */
9dac77fa 4265 set_seg_override(ctxt, ctxt->b & 7);
dde7e6d1
AK		 4266 break;
4267 case 0x40 ... 0x4f: /* REX */
4268 if (mode != X86EMUL_MODE_PROT64)
4269 goto done_prefixes;
9dac77fa 4270 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 4271 continue;
4272 case 0xf0: /* LOCK */
9dac77fa 4273 ctxt->lock_prefix = 1;
dde7e6d1
AK		 4274 break;
4275 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 4276 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 4277 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 4278 break;
4279 default:
4280 goto done_prefixes;
4281 }
4282
4283 /* Any legacy prefix after a REX prefix nullifies its effect. */
4284
9dac77fa 4285 ctxt->rex_prefix = 0;
dde7e6d1
AK		 4286 }
4287
4288done_prefixes:
4289
4290 /* REX prefix. */
9dac77fa
AK		 4291 if (ctxt->rex_prefix & 8)
4292 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 4293
4294 /* Opcode byte(s). */
9dac77fa 4295 opcode = opcode_table[ctxt->b];
d3ad6243 4296 /* Two-byte opcode? */
9dac77fa 4297 if (ctxt->b == 0x0f) {
1ce19dc1 4298 ctxt->opcode_len = 2;
e85a1085 4299 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 4300 opcode = twobyte_table[ctxt->b];
0bc5eedb
BP		 4301
4302 /* 0F_38 opcode map */
4303 if (ctxt->b == 0x38) {
4304 ctxt->opcode_len = 3;
4305 ctxt->b = insn_fetch(u8, ctxt);
4306 opcode = opcode_map_0f_38[ctxt->b];
4307 }
dde7e6d1 4308 }
9dac77fa 4309 ctxt->d = opcode.flags;
dde7e6d1 4310
9f4260e7
TY		 4311 if (ctxt->d & ModRM)
4312 ctxt->modrm = insn_fetch(u8, ctxt);
4313
9dac77fa
AK		 4314 while (ctxt->d & GroupMask) {
4315 switch (ctxt->d & GroupMask) {
46561646 4316 case Group:
9dac77fa 4317 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 4318 opcode = opcode.u.group[goffset];
4319 break;
4320 case GroupDual:
9dac77fa
AK		 4321 goffset = (ctxt->modrm >> 3) & 7;
4322 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 4323 opcode = opcode.u.gdual->mod3[goffset];
4324 else
4325 opcode = opcode.u.gdual->mod012[goffset];
4326 break;
4327 case RMExt:
9dac77fa 4328 goffset = ctxt->modrm & 7;
01de8b09 4329 opcode = opcode.u.group[goffset];
46561646
AK		 4330 break;
4331 case Prefix:
9dac77fa 4332 if (ctxt->rep_prefix && op_prefix)
1d2887e2 4333 return EMULATION_FAILED;
9dac77fa 4334 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 4335 switch (simd_prefix) {
4336 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4337 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4338 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4339 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4340 }
4341 break;
045a282c
GN		 4342 case Escape:
4343 if (ctxt->modrm > 0xbf)
4344 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
4345 else
4346 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
4347 break;
46561646 4348 default:
1d2887e2 4349 return EMULATION_FAILED;
0d7cdee8 4350 }
46561646 4351
b1ea50b2 4352 ctxt->d &= ~(u64)GroupMask;
9dac77fa 4353 ctxt->d |= opcode.flags;
0d7cdee8
AK		 4354 }
4355
9dac77fa
AK		 4356 ctxt->execute = opcode.u.execute;
4357 ctxt->check_perm = opcode.check_perm;
4358 ctxt->intercept = opcode.intercept;
dde7e6d1
AK		 4359
4360 /* Unrecognised? */
1146a78b 4361 if (ctxt->d == 0 || (ctxt->d & NotImpl))
1d2887e2 4362 return EMULATION_FAILED;
dde7e6d1 4363
b51e974f 4364 if (!(ctxt->d & EmulateOnUD) && ctxt->ud)
1d2887e2 4365 return EMULATION_FAILED;
d867162c 4366
9dac77fa
AK		 4367 if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
4368 ctxt->op_bytes = 8;
dde7e6d1 4369
9dac77fa 4370 if (ctxt->d & Op3264) {
7f9b4b75 4371 if (mode == X86EMUL_MODE_PROT64)
9dac77fa 4372 ctxt->op_bytes = 8;
7f9b4b75 4373 else
9dac77fa 4374 ctxt->op_bytes = 4;
7f9b4b75
AK		 4375 }
4376
9dac77fa
AK		 4377 if (ctxt->d & Sse)
4378 ctxt->op_bytes = 16;
cbe2c9d3
AK		 4379 else if (ctxt->d & Mmx)
4380 ctxt->op_bytes = 8;
1253791d 4381
dde7e6d1 4382 /* ModRM and SIB bytes. */
9dac77fa 4383 if (ctxt->d & ModRM) {
f09ed83e 4384 rc = decode_modrm(ctxt, &ctxt->memop);
9dac77fa
AK		 4385 if (!ctxt->has_seg_override)
4386 set_seg_override(ctxt, ctxt->modrm_seg);
4387 } else if (ctxt->d & MemAbs)
f09ed83e 4388 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 4389 if (rc != X86EMUL_CONTINUE)
4390 goto done;
4391
9dac77fa
AK		 4392 if (!ctxt->has_seg_override)
4393 set_seg_override(ctxt, VCPU_SREG_DS);
dde7e6d1 4394
f09ed83e 4395 ctxt->memop.addr.mem.seg = seg_override(ctxt);
dde7e6d1 4396
f09ed83e
AK		 4397 if (ctxt->memop.type == OP_MEM && ctxt->ad_bytes != 8)
4398 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
dde7e6d1 4399
dde7e6d1
AK		 4400 /*
4401 * Decode and fetch the source operand: register, memory
4402 * or immediate.
4403 */
0fe59128 4404 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 4405 if (rc != X86EMUL_CONTINUE)
4406 goto done;
4407
dde7e6d1
AK		 4408 /*
4409 * Decode and fetch the second source operand: register, memory
4410 * or immediate.
4411 */
4dd6a57d 4412 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 4413 if (rc != X86EMUL_CONTINUE)
4414 goto done;
4415
dde7e6d1 4416 /* Decode and fetch the destination operand: register or memory. */
a9945549 4417 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1
AK		 4418
4419done:
f09ed83e
AK		 4420 if (ctxt->memopp && ctxt->memopp->type == OP_MEM && ctxt->rip_relative)
4421 ctxt->memopp->addr.mem.ea += ctxt->_eip;
cb16c348 4422
1d2887e2 4423 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 4424}
4425
1cb3f3ae
XG		 4426bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4427{
4428 return ctxt->d & PageTable;
4429}
4430
3e2f65d5
GN		 4431static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4432{
3e2f65d5
GN		 4433 /* The second termination condition only applies for REPE
4434 * and REPNE. Test if the repeat string operation prefix is
4435 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4436 * corresponding termination condition according to:
4437 * - if REPE/REPZ and ZF = 0 then done
4438 * - if REPNE/REPNZ and ZF = 1 then done
4439 */
9dac77fa
AK		 4440 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4441 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4442 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 4443 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 4444 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 4445 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
4446 return true;
4447
4448 return false;
4449}
4450
cbe2c9d3
AK		 4451static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4452{
4453 bool fault = false;
4454
4455 ctxt->ops->get_fpu(ctxt);
4456 asm volatile("1: fwait \n\t"
4457 "2: \n\t"
4458 ".pushsection .fixup,\"ax\" \n\t"
4459 "3: \n\t"
4460 "movb $1, %[fault] \n\t"
4461 "jmp 2b \n\t"
4462 ".popsection \n\t"
4463 _ASM_EXTABLE(1b, 3b)
38e8a2dd 4464 : [fault]"+qm"(fault));
cbe2c9d3
AK		 4465 ctxt->ops->put_fpu(ctxt);
4466
4467 if (unlikely(fault))
4468 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4469
4470 return X86EMUL_CONTINUE;
4471}
4472
4473static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4474 struct operand *op)
4475{
4476 if (op->type == OP_MM)
4477 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4478}
4479
e28bbd44
AK		 4480static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
4481{
4482 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
b9fa409b
AK		 4483 if (!(ctxt->d & ByteOp))
4484 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
e28bbd44 4485 asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n"
b8c0b6ae
AK		 4486 : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags),
4487 [fastop]"+S"(fop)
4488 : "c"(ctxt->src2.val));
e28bbd44 4489 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
b8c0b6ae
AK		 4490 if (!fop) /* exception is returned in fop variable */
4491 return emulate_de(ctxt);
e28bbd44
AK		 4492 return X86EMUL_CONTINUE;
4493}
dd856efa 4494
7b105ca2 4495int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 4496{
0225fb50 4497 const struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 4498 int rc = X86EMUL_CONTINUE;
9dac77fa 4499 int saved_dst_type = ctxt->dst.type;
8b4caf66 4500
9dac77fa 4501 ctxt->mem_read.pos = 0;
310b5d30 4502
1146a78b
GN		 4503 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
4504 (ctxt->d & Undefined)) {
35d3d4a1 4505 rc = emulate_ud(ctxt);
1161624f
GN		 4506 goto done;
4507 }
4508
d380a5e4 4509 /* LOCK prefix is allowed only with some instructions */
9dac77fa 4510 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 4511 rc = emulate_ud(ctxt);
d380a5e4
GN		 4512 goto done;
4513 }
4514
9dac77fa 4515 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 4516 rc = emulate_ud(ctxt);
081bca0e
AK		 4517 goto done;
4518 }
4519
cbe2c9d3
AK		 4520 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4521 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
1253791d
AK		 4522 rc = emulate_ud(ctxt);
4523 goto done;
4524 }
4525
cbe2c9d3 4526 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
1253791d
AK		 4527 rc = emulate_nm(ctxt);
4528 goto done;
4529 }
4530
cbe2c9d3
AK		 4531 if (ctxt->d & Mmx) {
4532 rc = flush_pending_x87_faults(ctxt);
4533 if (rc != X86EMUL_CONTINUE)
4534 goto done;
4535 /*
4536 * Now that we know the fpu is exception safe, we can fetch
4537 * operands from it.
4538 */
4539 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4540 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4541 if (!(ctxt->d & Mov))
4542 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4543 }
4544
9dac77fa
AK		 4545 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4546 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4547 X86_ICPT_PRE_EXCEPT);
c4f035c6
AK		 4548 if (rc != X86EMUL_CONTINUE)
4549 goto done;
4550 }
4551
e92805ac 4552 /* Privileged instruction can be executed only in CPL=0 */
9dac77fa 4553 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
35d3d4a1 4554 rc = emulate_gp(ctxt, 0);
e92805ac
GN		 4555 goto done;
4556 }
4557
8ea7d6ae 4558 /* Instruction can only be executed in protected mode */
9d1b39a9 4559 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
8ea7d6ae
JR		 4560 rc = emulate_ud(ctxt);
4561 goto done;
4562 }
4563
d09beabd 4564 /* Do instruction specific permission checks */
9dac77fa
AK		 4565 if (ctxt->check_perm) {
4566 rc = ctxt->check_perm(ctxt);
d09beabd
JR		 4567 if (rc != X86EMUL_CONTINUE)
4568 goto done;
4569 }
4570
9dac77fa
AK		 4571 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4572 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4573 X86_ICPT_POST_EXCEPT);
c4f035c6
AK		 4574 if (rc != X86EMUL_CONTINUE)
4575 goto done;
4576 }
4577
9dac77fa 4578 if (ctxt->rep_prefix && (ctxt->d & String)) {
b9fa9d6b 4579 /* All REP prefixes have the same first termination condition */
dd856efa 4580 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
9dac77fa 4581 ctxt->eip = ctxt->_eip;
b9fa9d6b
AK		 4582 goto done;
4583 }
b9fa9d6b
AK		 4584 }
4585
9dac77fa
AK		 4586 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4587 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4588 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 4589 if (rc != X86EMUL_CONTINUE)
8b4caf66 4590 goto done;
9dac77fa 4591 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 4592 }
4593
9dac77fa
AK		 4594 if (ctxt->src2.type == OP_MEM) {
4595 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4596 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 4597 if (rc != X86EMUL_CONTINUE)
4598 goto done;
4599 }
4600
9dac77fa 4601 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 4602 goto special_insn;
4603
4604
9dac77fa 4605 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 4606 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 4607 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4608 &ctxt->dst.val, ctxt->dst.bytes);
69f55cb1
GN		 4609 if (rc != X86EMUL_CONTINUE)
4610 goto done;
038e51de 4611 }
9dac77fa 4612 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 4613
018a98db
AK		 4614special_insn:
4615
9dac77fa
AK		 4616 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4617 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4618 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 4619 if (rc != X86EMUL_CONTINUE)
4620 goto done;
4621 }
4622
9dac77fa 4623 if (ctxt->execute) {
e28bbd44
AK		 4624 if (ctxt->d & Fastop) {
4625 void (*fop)(struct fastop *) = (void *)ctxt->execute;
4626 rc = fastop(ctxt, fop);
4627 if (rc != X86EMUL_CONTINUE)
4628 goto done;
4629 goto writeback;
4630 }
9dac77fa 4631 rc = ctxt->execute(ctxt);
ef65c889
AK		 4632 if (rc != X86EMUL_CONTINUE)
4633 goto done;
4634 goto writeback;
4635 }
4636
1ce19dc1 4637 if (ctxt->opcode_len == 2)
6aa8b732 4638 goto twobyte_insn;
0bc5eedb
BP		 4639 else if (ctxt->opcode_len == 3)
4640 goto threebyte_insn;
6aa8b732 4641
9dac77fa 4642 switch (ctxt->b) {
6aa8b732 4643 case 0x63: /* movsxd */
8b4caf66 4644 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 4645 goto cannot_emulate;
9dac77fa 4646 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 4647 break;
b2833e3c 4648 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa
AK		 4649 if (test_cc(ctxt->b, ctxt->eflags))
4650 jmp_rel(ctxt, ctxt->src.val);
018a98db 4651 break;
7e0b54b1 4652 case 0x8d: /* lea r16/r32, m */
9dac77fa 4653 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 4654 break;
3d9e77df 4655 case 0x90 ... 0x97: /* nop / xchg reg, rax */
dd856efa 4656 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
34698d8c 4657 break;
e4f973ae
TY		 4658 rc = em_xchg(ctxt);
4659 break;
e8b6fa70 4660 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 4661 switch (ctxt->op_bytes) {
4662 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
4663 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
4664 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 4665 }
4666 break;
6e154e56 4667 case 0xcc: /* int3 */
5c5df76b
TY		 4668 rc = emulate_int(ctxt, 3);
4669 break;
6e154e56 4670 case 0xcd: /* int n */
9dac77fa 4671 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 4672 break;
4673 case 0xce: /* into */
5c5df76b
TY		 4674 if (ctxt->eflags & EFLG_OF)
4675 rc = emulate_int(ctxt, 4);
6e154e56 4676 break;
1a52e051 4677 case 0xe9: /* jmp rel */
db5b0762 4678 case 0xeb: /* jmp rel short */
9dac77fa
AK		 4679 jmp_rel(ctxt, ctxt->src.val);
4680 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4681 break;
111de5d6 4682 case 0xf4: /* hlt */
6c3287f7 4683 ctxt->ops->halt(ctxt);
19fdfa0d 4684 break;
111de5d6
AK		 4685 case 0xf5: /* cmc */
4686 /* complement carry flag from eflags reg */
4687 ctxt->eflags ^= EFLG_CF;
111de5d6
AK		 4688 break;
4689 case 0xf8: /* clc */
4690 ctxt->eflags &= ~EFLG_CF;
111de5d6 4691 break;
8744aa9a
MG		 4692 case 0xf9: /* stc */
4693 ctxt->eflags |= EFLG_CF;
4694 break;
fb4616f4
MG		 4695 case 0xfc: /* cld */
4696 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 4697 break;
4698 case 0xfd: /* std */
4699 ctxt->eflags |= EFLG_DF;
fb4616f4 4700 break;
91269b8f
AK		 4701 default:
4702 goto cannot_emulate;
6aa8b732 4703 }
018a98db 4704
7d9ddaed
AK		 4705 if (rc != X86EMUL_CONTINUE)
4706 goto done;
4707
018a98db 4708writeback:
fb32b1ed
AK		 4709 if (!(ctxt->d & NoWrite)) {
4710 rc = writeback(ctxt, &ctxt->dst);
4711 if (rc != X86EMUL_CONTINUE)
4712 goto done;
4713 }
4714 if (ctxt->d & SrcWrite) {
4715 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR);
4716 rc = writeback(ctxt, &ctxt->src);
4717 if (rc != X86EMUL_CONTINUE)
4718 goto done;
4719 }
018a98db 4720
5cd21917
GN		 4721 /*
4722 * restore dst type in case the decoding will be reused
4723 * (happens for string instruction )
4724 */
9dac77fa 4725 ctxt->dst.type = saved_dst_type;
5cd21917 4726
9dac77fa 4727 if ((ctxt->d & SrcMask) == SrcSI)
f3bd64c6 4728 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
a682e354 4729
9dac77fa 4730 if ((ctxt->d & DstMask) == DstDI)
f3bd64c6 4731 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
d9271123 4732
9dac77fa 4733 if (ctxt->rep_prefix && (ctxt->d & String)) {
b3356bf0 4734 unsigned int count;
9dac77fa 4735 struct read_cache *r = &ctxt->io_read;
b3356bf0
GN		 4736 if ((ctxt->d & SrcMask) == SrcSI)
4737 count = ctxt->src.count;
4738 else
4739 count = ctxt->dst.count;
4740 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX),
4741 -count);
3e2f65d5 4742
d2ddd1c4
GN		 4743 if (!string_insn_completed(ctxt)) {
4744 /*
4745 * Re-enter guest when pio read ahead buffer is empty
4746 * or, if it is not used, after each 1024 iteration.
4747 */
dd856efa 4748 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
d2ddd1c4
GN		 4749 (r->end == 0 || r->end != r->pos)) {
4750 /*
4751 * Reset read cache. Usually happens before
4752 * decode, but since instruction is restarted
4753 * we have to do it here.
4754 */
9dac77fa 4755 ctxt->mem_read.end = 0;
dd856efa 4756 writeback_registers(ctxt);
d2ddd1c4
GN		 4757 return EMULATION_RESTART;
4758 }
4759 goto done; /* skip rip writeback */
0fa6ccbd 4760 }
5cd21917 4761 }
d2ddd1c4 4762
9dac77fa 4763 ctxt->eip = ctxt->_eip;
018a98db
AK		 4764
4765done:
da9cb575
AK		 4766 if (rc == X86EMUL_PROPAGATE_FAULT)
4767 ctxt->have_exception = true;
775fde86
JR		 4768 if (rc == X86EMUL_INTERCEPTED)
4769 return EMULATION_INTERCEPTED;
4770
dd856efa
AK		 4771 if (rc == X86EMUL_CONTINUE)
4772 writeback_registers(ctxt);
4773
d2ddd1c4 4774 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 4775
4776twobyte_insn:
9dac77fa 4777 switch (ctxt->b) {
018a98db 4778 case 0x09: /* wbinvd */
cfb22375 4779 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 4780 break;
4781 case 0x08: /* invd */
018a98db
AK		 4782 case 0x0d: /* GrpP (prefetch) */
4783 case 0x18: /* Grp16 (prefetch/nop) */
103f98ea 4784 case 0x1f: /* nop */
018a98db
AK		 4785 break;
4786 case 0x20: /* mov cr, reg */
9dac77fa 4787 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 4788 break;
6aa8b732 4789 case 0x21: /* mov from dr to reg */
9dac77fa 4790 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 4791 break;
6aa8b732 4792 case 0x40 ... 0x4f: /* cmov */
9dac77fa
AK		 4793 ctxt->dst.val = ctxt->dst.orig_val = ctxt->src.val;
4794 if (!test_cc(ctxt->b, ctxt->eflags))
4795 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 4796 break;
b2833e3c 4797 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa
AK		 4798 if (test_cc(ctxt->b, ctxt->eflags))
4799 jmp_rel(ctxt, ctxt->src.val);
018a98db 4800 break;
ee45b58e 4801 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 4802 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 4803 break;
2a7c5b8b
GC		 4804 case 0xae: /* clflush */
4805 break;
6aa8b732 4806 case 0xb6 ... 0xb7: /* movzx */
9dac77fa 4807 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4808 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
9dac77fa 4809 : (u16) ctxt->src.val;
6aa8b732 4810 break;
6aa8b732 4811 case 0xbe ... 0xbf: /* movsx */
9dac77fa 4812 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4813 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
9dac77fa 4814 (s16) ctxt->src.val;
6aa8b732 4815 break;
a012e65a 4816 case 0xc3: /* movnti */
9dac77fa
AK		 4817 ctxt->dst.bytes = ctxt->op_bytes;
4818 ctxt->dst.val = (ctxt->op_bytes == 4) ? (u32) ctxt->src.val :
4819 (u64) ctxt->src.val;
a012e65a 4820 break;
91269b8f
AK		 4821 default:
4822 goto cannot_emulate;
6aa8b732 4823 }
7d9ddaed 4824
0bc5eedb
BP		 4825threebyte_insn:
4826
7d9ddaed
AK		 4827 if (rc != X86EMUL_CONTINUE)
4828 goto done;
4829
6aa8b732
AK		 4830 goto writeback;
4831
4832cannot_emulate:
a0c0ab2f 4833 return EMULATION_FAILED;
6aa8b732 4834}
dd856efa
AK		 4835
4836void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
4837{
4838 invalidate_registers(ctxt);
4839}
4840
4841void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
4842{
4843 writeback_registers(ctxt);
4844}
Linux 6.x block layer and io_uring tree(s)