Commit | Line | Data |
---|---|---|
6aa8b732 | 1 | /****************************************************************************** |
56e82318 | 2 | * emulate.c |
6aa8b732 AK |
3 | * |
4 | * Generic x86 (32-bit and 64-bit) instruction decoder and emulator. | |
5 | * | |
6 | * Copyright (c) 2005 Keir Fraser | |
7 | * | |
8 | * Linux coding style, mod r/m decoder, segment base fixes, real-mode | |
dcc0766b | 9 | * privileged instructions: |
6aa8b732 AK |
10 | * |
11 | * Copyright (C) 2006 Qumranet | |
221d059d | 12 | * Copyright 2010 Red Hat, Inc. and/or its affilates. |
6aa8b732 AK |
13 | * |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * Yaniv Kamay <yaniv@qumranet.com> | |
16 | * | |
17 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
18 | * the COPYING file in the top-level directory. | |
19 | * | |
20 | * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4 | |
21 | */ | |
22 | ||
23 | #ifndef __KERNEL__ | |
24 | #include <stdio.h> | |
25 | #include <stdint.h> | |
26 | #include <public/xen.h> | |
d77c26fc | 27 | #define DPRINTF(_f, _a ...) printf(_f , ## _a) |
6aa8b732 | 28 | #else |
edf88417 | 29 | #include <linux/kvm_host.h> |
5fdbf976 | 30 | #include "kvm_cache_regs.h" |
6aa8b732 AK |
31 | #define DPRINTF(x...) do {} while (0) |
32 | #endif | |
6aa8b732 | 33 | #include <linux/module.h> |
56e82318 | 34 | #include <asm/kvm_emulate.h> |
6aa8b732 | 35 | |
3eeb3288 | 36 | #include "x86.h" |
38ba30ba | 37 | #include "tss.h" |
e99f0507 | 38 | |
6aa8b732 AK |
39 | /* |
40 | * Opcode effective-address decode tables. | |
41 | * Note that we only emulate instructions that have at least one memory | |
42 | * operand (excluding implicit stack references). We assume that stack | |
43 | * references and instruction fetches will never occur in special memory | |
44 | * areas that require emulation. So, for example, 'mov <imm>,<reg>' need | |
45 | * not be handled. | |
46 | */ | |
47 | ||
48 | /* Operand sizes: 8-bit operands or specified/overridden size. */ | |
2ce49536 | 49 | #define ByteOp (1<<16) /* 8-bit operands. */ |
6aa8b732 | 50 | /* Destination operand type. */ |
2ce49536 AK |
51 | #define ImplicitOps (1<<17) /* Implicit in opcode. No generic decode. */ |
52 | #define DstReg (2<<17) /* Register operand. */ | |
53 | #define DstMem (3<<17) /* Memory operand. */ | |
54 | #define DstAcc (4<<17) /* Destination Accumulator */ | |
55 | #define DstDI (5<<17) /* Destination is in ES:(E)DI */ | |
56 | #define DstMem64 (6<<17) /* 64bit memory operand */ | |
57 | #define DstMask (7<<17) | |
6aa8b732 | 58 | /* Source operand type. */ |
9c9fddd0 GT |
59 | #define SrcNone (0<<4) /* No source operand. */ |
60 | #define SrcImplicit (0<<4) /* Source operand is implicit in the opcode. */ | |
61 | #define SrcReg (1<<4) /* Register operand. */ | |
62 | #define SrcMem (2<<4) /* Memory operand. */ | |
63 | #define SrcMem16 (3<<4) /* Memory operand (16-bit). */ | |
64 | #define SrcMem32 (4<<4) /* Memory operand (32-bit). */ | |
65 | #define SrcImm (5<<4) /* Immediate operand. */ | |
66 | #define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */ | |
bfcadf83 | 67 | #define SrcOne (7<<4) /* Implied '1' */ |
341de7e3 | 68 | #define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */ |
c9eaf20f | 69 | #define SrcImmU (9<<4) /* Immediate operand, unsigned */ |
a682e354 | 70 | #define SrcSI (0xa<<4) /* Source is in the DS:RSI */ |
414e6277 GN |
71 | #define SrcImmFAddr (0xb<<4) /* Source is immediate far address */ |
72 | #define SrcMemFAddr (0xc<<4) /* Source is far address in memory */ | |
5d55f299 | 73 | #define SrcAcc (0xd<<4) /* Source Accumulator */ |
341de7e3 | 74 | #define SrcMask (0xf<<4) |
6aa8b732 | 75 | /* Generic ModRM decode. */ |
341de7e3 | 76 | #define ModRM (1<<8) |
6aa8b732 | 77 | /* Destination is only written; never read. */ |
341de7e3 GN |
78 | #define Mov (1<<9) |
79 | #define BitOp (1<<10) | |
80 | #define MemAbs (1<<11) /* Memory operand is absolute displacement */ | |
9c9fddd0 GT |
81 | #define String (1<<12) /* String instruction (rep capable) */ |
82 | #define Stack (1<<13) /* Stack instruction (push/pop) */ | |
e09d082c AK |
83 | #define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */ |
84 | #define GroupDual (1<<15) /* Alternate decoding of mod == 3 */ | |
2ce49536 | 85 | #define GroupMask 0x0f /* Group number stored in bits 0:3 */ |
d8769fed | 86 | /* Misc flags */ |
047a4818 | 87 | #define Undefined (1<<25) /* No Such Instruction */ |
d380a5e4 | 88 | #define Lock (1<<26) /* lock prefix is allowed for the instruction */ |
e92805ac | 89 | #define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */ |
d8769fed | 90 | #define No64 (1<<28) |
0dc8d10f GT |
91 | /* Source 2 operand type */ |
92 | #define Src2None (0<<29) | |
93 | #define Src2CL (1<<29) | |
94 | #define Src2ImmByte (2<<29) | |
95 | #define Src2One (3<<29) | |
96 | #define Src2Mask (7<<29) | |
6aa8b732 | 97 | |
ea9ef04e AK |
98 | #define X2(x) x, x |
99 | #define X3(x) X2(x), x | |
83babbca | 100 | #define X4(x) X2(x), X2(x) |
ea9ef04e | 101 | #define X5(x) X4(x), x |
83babbca AK |
102 | #define X6(x) X4(x), X2(x) |
103 | #define X7(x) X4(x), X3(x) | |
104 | #define X8(x) X4(x), X4(x) | |
105 | #define X16(x) X8(x), X8(x) | |
106 | ||
43bb19cd | 107 | enum { |
e071edd5 | 108 | Group1, Group1A, Group3, Group4, Group5, Group7, Group8, Group9, |
43bb19cd AK |
109 | }; |
110 | ||
45ed60b3 | 111 | static u32 opcode_table[256] = { |
6aa8b732 | 112 | /* 0x00 - 0x07 */ |
d380a5e4 | 113 | ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock, |
6aa8b732 | 114 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, |
0934ac9d | 115 | ByteOp | DstAcc | SrcImm, DstAcc | SrcImm, |
d8769fed | 116 | ImplicitOps | Stack | No64, ImplicitOps | Stack | No64, |
6aa8b732 | 117 | /* 0x08 - 0x0F */ |
d380a5e4 | 118 | ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock, |
6aa8b732 | 119 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, |
94677e61 MG |
120 | ByteOp | DstAcc | SrcImm, DstAcc | SrcImm, |
121 | ImplicitOps | Stack | No64, 0, | |
6aa8b732 | 122 | /* 0x10 - 0x17 */ |
d380a5e4 | 123 | ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock, |
6aa8b732 | 124 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, |
0934ac9d | 125 | ByteOp | DstAcc | SrcImm, DstAcc | SrcImm, |
d8769fed | 126 | ImplicitOps | Stack | No64, ImplicitOps | Stack | No64, |
6aa8b732 | 127 | /* 0x18 - 0x1F */ |
d380a5e4 | 128 | ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock, |
6aa8b732 | 129 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, |
0934ac9d | 130 | ByteOp | DstAcc | SrcImm, DstAcc | SrcImm, |
d8769fed | 131 | ImplicitOps | Stack | No64, ImplicitOps | Stack | No64, |
6aa8b732 | 132 | /* 0x20 - 0x27 */ |
d380a5e4 | 133 | ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock, |
6aa8b732 | 134 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, |
e97e883f | 135 | ByteOp | DstAcc | SrcImmByte, DstAcc | SrcImm, 0, 0, |
6aa8b732 | 136 | /* 0x28 - 0x2F */ |
d380a5e4 | 137 | ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock, |
6aa8b732 | 138 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, |
abc19083 | 139 | ByteOp | DstAcc | SrcImmByte, DstAcc | SrcImm, 0, 0, |
6aa8b732 | 140 | /* 0x30 - 0x37 */ |
d380a5e4 | 141 | ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock, |
6aa8b732 | 142 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, |
222b7c52 | 143 | ByteOp | DstAcc | SrcImmByte, DstAcc | SrcImm, 0, 0, |
6aa8b732 AK |
144 | /* 0x38 - 0x3F */ |
145 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, | |
146 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, | |
8a9fee67 GT |
147 | ByteOp | DstAcc | SrcImm, DstAcc | SrcImm, |
148 | 0, 0, | |
749358a6 AK |
149 | /* 0x40 - 0x4F */ |
150 | X16(DstReg), | |
7f0aaee0 | 151 | /* 0x50 - 0x57 */ |
3849186c | 152 | X8(SrcReg | Stack), |
7f0aaee0 | 153 | /* 0x58 - 0x5F */ |
3849186c | 154 | X8(DstReg | Stack), |
7d316911 | 155 | /* 0x60 - 0x67 */ |
abcf14b5 MG |
156 | ImplicitOps | Stack | No64, ImplicitOps | Stack | No64, |
157 | 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ , | |
7d316911 NK |
158 | 0, 0, 0, 0, |
159 | /* 0x68 - 0x6F */ | |
91ed7a0e | 160 | SrcImm | Mov | Stack, 0, SrcImmByte | Mov | Stack, 0, |
7972995b GN |
161 | DstDI | ByteOp | Mov | String, DstDI | Mov | String, /* insb, insw/insd */ |
162 | SrcSI | ByteOp | ImplicitOps | String, SrcSI | ImplicitOps | String, /* outsb, outsw/outsd */ | |
b3ab3405 AK |
163 | /* 0x70 - 0x7F */ |
164 | X16(SrcImmByte), | |
6aa8b732 | 165 | /* 0x80 - 0x87 */ |
4968ec4e AK |
166 | ByteOp | DstMem | SrcImm | ModRM | Group | Group1, |
167 | DstMem | SrcImm | ModRM | Group | Group1, | |
168 | ByteOp | DstMem | SrcImm | ModRM | No64 | Group | Group1, | |
169 | DstMem | SrcImmByte | ModRM | Group | Group1, | |
6aa8b732 | 170 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, |
d380a5e4 | 171 | ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock, |
6aa8b732 AK |
172 | /* 0x88 - 0x8F */ |
173 | ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov, | |
174 | ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
b16b2b7b | 175 | DstMem | SrcNone | ModRM | Mov, ModRM | DstReg, |
a5046e6c | 176 | ImplicitOps | SrcMem16 | ModRM, Group | Group1A, |
b13354f8 MG |
177 | /* 0x90 - 0x97 */ |
178 | DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, | |
179 | /* 0x98 - 0x9F */ | |
414e6277 | 180 | 0, 0, SrcImmFAddr | No64, 0, |
0654169e | 181 | ImplicitOps | Stack, ImplicitOps | Stack, 0, 0, |
6aa8b732 | 182 | /* 0xA0 - 0xA7 */ |
5d55f299 WY |
183 | ByteOp | DstAcc | SrcMem | Mov | MemAbs, DstAcc | SrcMem | Mov | MemAbs, |
184 | ByteOp | DstMem | SrcAcc | Mov | MemAbs, DstMem | SrcAcc | Mov | MemAbs, | |
a682e354 GN |
185 | ByteOp | SrcSI | DstDI | Mov | String, SrcSI | DstDI | Mov | String, |
186 | ByteOp | SrcSI | DstDI | String, SrcSI | DstDI | String, | |
6aa8b732 | 187 | /* 0xA8 - 0xAF */ |
dfb507c4 | 188 | DstAcc | SrcImmByte | ByteOp, DstAcc | SrcImm, ByteOp | DstDI | Mov | String, DstDI | Mov | String, |
a682e354 GN |
189 | ByteOp | SrcSI | DstAcc | Mov | String, SrcSI | DstAcc | Mov | String, |
190 | ByteOp | DstDI | String, DstDI | String, | |
a5e2e82b | 191 | /* 0xB0 - 0xB7 */ |
b6e61538 | 192 | X8(ByteOp | DstReg | SrcImm | Mov), |
a5e2e82b | 193 | /* 0xB8 - 0xBF */ |
b6e61538 | 194 | X8(DstReg | SrcImm | Mov), |
6aa8b732 | 195 | /* 0xC0 - 0xC7 */ |
d9413cd7 | 196 | ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM, |
6e3d5dfb | 197 | 0, ImplicitOps | Stack, 0, 0, |
d9413cd7 | 198 | ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov, |
6aa8b732 | 199 | /* 0xC8 - 0xCF */ |
e637b823 | 200 | 0, 0, 0, ImplicitOps | Stack, |
d8769fed | 201 | ImplicitOps, SrcImmByte, ImplicitOps | No64, ImplicitOps, |
6aa8b732 AK |
202 | /* 0xD0 - 0xD7 */ |
203 | ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM, | |
204 | ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM, | |
205 | 0, 0, 0, 0, | |
206 | /* 0xD8 - 0xDF */ | |
207 | 0, 0, 0, 0, 0, 0, 0, 0, | |
098c937b | 208 | /* 0xE0 - 0xE7 */ |
a6a3034c | 209 | 0, 0, 0, 0, |
cf8f70bf GN |
210 | ByteOp | SrcImmUByte | DstAcc, SrcImmUByte | DstAcc, |
211 | ByteOp | SrcImmUByte | DstAcc, SrcImmUByte | DstAcc, | |
098c937b | 212 | /* 0xE8 - 0xEF */ |
d53c4777 | 213 | SrcImm | Stack, SrcImm | ImplicitOps, |
414e6277 | 214 | SrcImmFAddr | No64, SrcImmByte | ImplicitOps, |
cf8f70bf GN |
215 | SrcNone | ByteOp | DstAcc, SrcNone | DstAcc, |
216 | SrcNone | ByteOp | DstAcc, SrcNone | DstAcc, | |
6aa8b732 AK |
217 | /* 0xF0 - 0xF7 */ |
218 | 0, 0, 0, 0, | |
e071edd5 | 219 | ImplicitOps | Priv, ImplicitOps, ByteOp | Group | Group3, Group | Group3, |
6aa8b732 | 220 | /* 0xF8 - 0xFF */ |
b284be57 | 221 | ImplicitOps, 0, ImplicitOps, ImplicitOps, |
fb4616f4 | 222 | ImplicitOps, ImplicitOps, Group | Group4, Group | Group5, |
6aa8b732 AK |
223 | }; |
224 | ||
45ed60b3 | 225 | static u32 twobyte_table[256] = { |
6aa8b732 | 226 | /* 0x00 - 0x0F */ |
e92805ac GN |
227 | 0, Group | GroupDual | Group7, 0, 0, |
228 | 0, ImplicitOps, ImplicitOps | Priv, 0, | |
229 | ImplicitOps | Priv, ImplicitOps | Priv, 0, 0, | |
230 | 0, ImplicitOps | ModRM, 0, 0, | |
6aa8b732 AK |
231 | /* 0x10 - 0x1F */ |
232 | 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0, | |
233 | /* 0x20 - 0x2F */ | |
e92805ac GN |
234 | ModRM | ImplicitOps | Priv, ModRM | Priv, |
235 | ModRM | ImplicitOps | Priv, ModRM | Priv, | |
236 | 0, 0, 0, 0, | |
6aa8b732 AK |
237 | 0, 0, 0, 0, 0, 0, 0, 0, |
238 | /* 0x30 - 0x3F */ | |
e92805ac GN |
239 | ImplicitOps | Priv, 0, ImplicitOps | Priv, 0, |
240 | ImplicitOps, ImplicitOps | Priv, 0, 0, | |
e99f0507 | 241 | 0, 0, 0, 0, 0, 0, 0, 0, |
be8eacdd AK |
242 | /* 0x40 - 0x4F */ |
243 | X16(DstReg | SrcMem | ModRM | Mov), | |
6aa8b732 AK |
244 | /* 0x50 - 0x5F */ |
245 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
246 | /* 0x60 - 0x6F */ | |
247 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
248 | /* 0x70 - 0x7F */ | |
249 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
250 | /* 0x80 - 0x8F */ | |
880a1883 | 251 | X16(SrcImm), |
6aa8b732 AK |
252 | /* 0x90 - 0x9F */ |
253 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
254 | /* 0xA0 - 0xA7 */ | |
0934ac9d MG |
255 | ImplicitOps | Stack, ImplicitOps | Stack, |
256 | 0, DstMem | SrcReg | ModRM | BitOp, | |
9bf8ea42 GT |
257 | DstMem | SrcReg | Src2ImmByte | ModRM, |
258 | DstMem | SrcReg | Src2CL | ModRM, 0, 0, | |
6aa8b732 | 259 | /* 0xA8 - 0xAF */ |
0934ac9d | 260 | ImplicitOps | Stack, ImplicitOps | Stack, |
d380a5e4 | 261 | 0, DstMem | SrcReg | ModRM | BitOp | Lock, |
9bf8ea42 GT |
262 | DstMem | SrcReg | Src2ImmByte | ModRM, |
263 | DstMem | SrcReg | Src2CL | ModRM, | |
264 | ModRM, 0, | |
6aa8b732 | 265 | /* 0xB0 - 0xB7 */ |
d380a5e4 GN |
266 | ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock, |
267 | 0, DstMem | SrcReg | ModRM | BitOp | Lock, | |
6aa8b732 AK |
268 | 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov, |
269 | DstReg | SrcMem16 | ModRM | Mov, | |
270 | /* 0xB8 - 0xBF */ | |
d380a5e4 GN |
271 | 0, 0, |
272 | Group | Group8, DstMem | SrcReg | ModRM | BitOp | Lock, | |
6aa8b732 AK |
273 | 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov, |
274 | DstReg | SrcMem16 | ModRM | Mov, | |
275 | /* 0xC0 - 0xCF */ | |
60a29d4e GN |
276 | 0, 0, 0, DstMem | SrcReg | ModRM | Mov, |
277 | 0, 0, 0, Group | GroupDual | Group9, | |
a012e65a | 278 | 0, 0, 0, 0, 0, 0, 0, 0, |
6aa8b732 AK |
279 | /* 0xD0 - 0xDF */ |
280 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
281 | /* 0xE0 - 0xEF */ | |
282 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
283 | /* 0xF0 - 0xFF */ | |
284 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 | |
285 | }; | |
286 | ||
45ed60b3 | 287 | static u32 group_table[] = { |
4968ec4e AK |
288 | [Group1*8] = |
289 | X7(Lock), 0, | |
43bb19cd AK |
290 | [Group1A*8] = |
291 | DstMem | SrcNone | ModRM | Mov | Stack, 0, 0, 0, 0, 0, 0, 0, | |
7d858a19 | 292 | [Group3*8] = |
7d5993d6 | 293 | DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM, |
dfe11481 | 294 | DstMem | SrcNone | ModRM | Lock, DstMem | SrcNone | ModRM | Lock, |
e071edd5 | 295 | X4(Undefined), |
fd60754e | 296 | [Group4*8] = |
c0e0608c | 297 | ByteOp | DstMem | SrcNone | ModRM | Lock, ByteOp | DstMem | SrcNone | ModRM | Lock, |
fd60754e AK |
298 | 0, 0, 0, 0, 0, 0, |
299 | [Group5*8] = | |
c0e0608c | 300 | DstMem | SrcNone | ModRM | Lock, DstMem | SrcNone | ModRM | Lock, |
d19292e4 | 301 | SrcMem | ModRM | Stack, 0, |
414e6277 | 302 | SrcMem | ModRM | Stack, SrcMemFAddr | ModRM | ImplicitOps, |
ea79849d | 303 | SrcMem | ModRM | Stack, 0, |
d95058a1 | 304 | [Group7*8] = |
e92805ac | 305 | 0, 0, ModRM | SrcMem | Priv, ModRM | SrcMem | Priv, |
16286d08 | 306 | SrcNone | ModRM | DstMem | Mov, 0, |
e92805ac | 307 | SrcMem16 | ModRM | Mov | Priv, SrcMem | ModRM | ByteOp | Priv, |
2db2c2eb GN |
308 | [Group8*8] = |
309 | 0, 0, 0, 0, | |
d380a5e4 GN |
310 | DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM | Lock, |
311 | DstMem | SrcImmByte | ModRM | Lock, DstMem | SrcImmByte | ModRM | Lock, | |
60a29d4e | 312 | [Group9*8] = |
6550e1f1 | 313 | 0, DstMem64 | ModRM | Lock, 0, 0, 0, 0, 0, 0, |
e09d082c AK |
314 | }; |
315 | ||
45ed60b3 | 316 | static u32 group2_table[] = { |
d95058a1 | 317 | [Group7*8] = |
835e6b80 | 318 | SrcNone | ModRM | Priv, 0, 0, SrcNone | ModRM | Priv, |
16286d08 | 319 | SrcNone | ModRM | DstMem | Mov, 0, |
835e6b80 | 320 | SrcMem16 | ModRM | Mov | Priv, 0, |
60a29d4e GN |
321 | [Group9*8] = |
322 | 0, 0, 0, 0, 0, 0, 0, 0, | |
e09d082c AK |
323 | }; |
324 | ||
6aa8b732 | 325 | /* EFLAGS bit definitions. */ |
d4c6a154 GN |
326 | #define EFLG_ID (1<<21) |
327 | #define EFLG_VIP (1<<20) | |
328 | #define EFLG_VIF (1<<19) | |
329 | #define EFLG_AC (1<<18) | |
b1d86143 AP |
330 | #define EFLG_VM (1<<17) |
331 | #define EFLG_RF (1<<16) | |
d4c6a154 GN |
332 | #define EFLG_IOPL (3<<12) |
333 | #define EFLG_NT (1<<14) | |
6aa8b732 AK |
334 | #define EFLG_OF (1<<11) |
335 | #define EFLG_DF (1<<10) | |
b1d86143 | 336 | #define EFLG_IF (1<<9) |
d4c6a154 | 337 | #define EFLG_TF (1<<8) |
6aa8b732 AK |
338 | #define EFLG_SF (1<<7) |
339 | #define EFLG_ZF (1<<6) | |
340 | #define EFLG_AF (1<<4) | |
341 | #define EFLG_PF (1<<2) | |
342 | #define EFLG_CF (1<<0) | |
343 | ||
62bd430e MG |
344 | #define EFLG_RESERVED_ZEROS_MASK 0xffc0802a |
345 | #define EFLG_RESERVED_ONE_MASK 2 | |
346 | ||
6aa8b732 AK |
347 | /* |
348 | * Instruction emulation: | |
349 | * Most instructions are emulated directly via a fragment of inline assembly | |
350 | * code. This allows us to save/restore EFLAGS and thus very easily pick up | |
351 | * any modified flags. | |
352 | */ | |
353 | ||
05b3e0c2 | 354 | #if defined(CONFIG_X86_64) |
6aa8b732 AK |
355 | #define _LO32 "k" /* force 32-bit operand */ |
356 | #define _STK "%%rsp" /* stack pointer */ | |
357 | #elif defined(__i386__) | |
358 | #define _LO32 "" /* force 32-bit operand */ | |
359 | #define _STK "%%esp" /* stack pointer */ | |
360 | #endif | |
361 | ||
362 | /* | |
363 | * These EFLAGS bits are restored from saved value during emulation, and | |
364 | * any changes are written back to the saved value after emulation. | |
365 | */ | |
366 | #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF) | |
367 | ||
368 | /* Before executing instruction: restore necessary bits in EFLAGS. */ | |
e934c9c1 AK |
369 | #define _PRE_EFLAGS(_sav, _msk, _tmp) \ |
370 | /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \ | |
371 | "movl %"_sav",%"_LO32 _tmp"; " \ | |
372 | "push %"_tmp"; " \ | |
373 | "push %"_tmp"; " \ | |
374 | "movl %"_msk",%"_LO32 _tmp"; " \ | |
375 | "andl %"_LO32 _tmp",("_STK"); " \ | |
376 | "pushf; " \ | |
377 | "notl %"_LO32 _tmp"; " \ | |
378 | "andl %"_LO32 _tmp",("_STK"); " \ | |
379 | "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \ | |
380 | "pop %"_tmp"; " \ | |
381 | "orl %"_LO32 _tmp",("_STK"); " \ | |
382 | "popf; " \ | |
383 | "pop %"_sav"; " | |
6aa8b732 AK |
384 | |
385 | /* After executing instruction: write-back necessary bits in EFLAGS. */ | |
386 | #define _POST_EFLAGS(_sav, _msk, _tmp) \ | |
387 | /* _sav |= EFLAGS & _msk; */ \ | |
388 | "pushf; " \ | |
389 | "pop %"_tmp"; " \ | |
390 | "andl %"_msk",%"_LO32 _tmp"; " \ | |
391 | "orl %"_LO32 _tmp",%"_sav"; " | |
392 | ||
dda96d8f AK |
393 | #ifdef CONFIG_X86_64 |
394 | #define ON64(x) x | |
395 | #else | |
396 | #define ON64(x) | |
397 | #endif | |
398 | ||
6b7ad61f AK |
399 | #define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix) \ |
400 | do { \ | |
401 | __asm__ __volatile__ ( \ | |
402 | _PRE_EFLAGS("0", "4", "2") \ | |
403 | _op _suffix " %"_x"3,%1; " \ | |
404 | _POST_EFLAGS("0", "4", "2") \ | |
405 | : "=m" (_eflags), "=m" ((_dst).val), \ | |
406 | "=&r" (_tmp) \ | |
407 | : _y ((_src).val), "i" (EFLAGS_MASK)); \ | |
f3fd92fb | 408 | } while (0) |
6b7ad61f AK |
409 | |
410 | ||
6aa8b732 AK |
411 | /* Raw emulation: instruction has two explicit operands. */ |
412 | #define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \ | |
6b7ad61f AK |
413 | do { \ |
414 | unsigned long _tmp; \ | |
415 | \ | |
416 | switch ((_dst).bytes) { \ | |
417 | case 2: \ | |
418 | ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w"); \ | |
419 | break; \ | |
420 | case 4: \ | |
421 | ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l"); \ | |
422 | break; \ | |
423 | case 8: \ | |
424 | ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q")); \ | |
425 | break; \ | |
426 | } \ | |
6aa8b732 AK |
427 | } while (0) |
428 | ||
429 | #define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \ | |
430 | do { \ | |
6b7ad61f | 431 | unsigned long _tmp; \ |
d77c26fc | 432 | switch ((_dst).bytes) { \ |
6aa8b732 | 433 | case 1: \ |
6b7ad61f | 434 | ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b"); \ |
6aa8b732 AK |
435 | break; \ |
436 | default: \ | |
437 | __emulate_2op_nobyte(_op, _src, _dst, _eflags, \ | |
438 | _wx, _wy, _lx, _ly, _qx, _qy); \ | |
439 | break; \ | |
440 | } \ | |
441 | } while (0) | |
442 | ||
443 | /* Source operand is byte-sized and may be restricted to just %cl. */ | |
444 | #define emulate_2op_SrcB(_op, _src, _dst, _eflags) \ | |
445 | __emulate_2op(_op, _src, _dst, _eflags, \ | |
446 | "b", "c", "b", "c", "b", "c", "b", "c") | |
447 | ||
448 | /* Source operand is byte, word, long or quad sized. */ | |
449 | #define emulate_2op_SrcV(_op, _src, _dst, _eflags) \ | |
450 | __emulate_2op(_op, _src, _dst, _eflags, \ | |
451 | "b", "q", "w", "r", _LO32, "r", "", "r") | |
452 | ||
453 | /* Source operand is word, long or quad sized. */ | |
454 | #define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \ | |
455 | __emulate_2op_nobyte(_op, _src, _dst, _eflags, \ | |
456 | "w", "r", _LO32, "r", "", "r") | |
457 | ||
d175226a GT |
458 | /* Instruction has three operands and one operand is stored in ECX register */ |
459 | #define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \ | |
460 | do { \ | |
461 | unsigned long _tmp; \ | |
462 | _type _clv = (_cl).val; \ | |
463 | _type _srcv = (_src).val; \ | |
464 | _type _dstv = (_dst).val; \ | |
465 | \ | |
466 | __asm__ __volatile__ ( \ | |
467 | _PRE_EFLAGS("0", "5", "2") \ | |
468 | _op _suffix " %4,%1 \n" \ | |
469 | _POST_EFLAGS("0", "5", "2") \ | |
470 | : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \ | |
471 | : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \ | |
472 | ); \ | |
473 | \ | |
474 | (_cl).val = (unsigned long) _clv; \ | |
475 | (_src).val = (unsigned long) _srcv; \ | |
476 | (_dst).val = (unsigned long) _dstv; \ | |
477 | } while (0) | |
478 | ||
479 | #define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \ | |
480 | do { \ | |
481 | switch ((_dst).bytes) { \ | |
482 | case 2: \ | |
483 | __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \ | |
484 | "w", unsigned short); \ | |
485 | break; \ | |
486 | case 4: \ | |
487 | __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \ | |
488 | "l", unsigned int); \ | |
489 | break; \ | |
490 | case 8: \ | |
491 | ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \ | |
492 | "q", unsigned long)); \ | |
493 | break; \ | |
494 | } \ | |
495 | } while (0) | |
496 | ||
dda96d8f | 497 | #define __emulate_1op(_op, _dst, _eflags, _suffix) \ |
6aa8b732 AK |
498 | do { \ |
499 | unsigned long _tmp; \ | |
500 | \ | |
dda96d8f AK |
501 | __asm__ __volatile__ ( \ |
502 | _PRE_EFLAGS("0", "3", "2") \ | |
503 | _op _suffix " %1; " \ | |
504 | _POST_EFLAGS("0", "3", "2") \ | |
505 | : "=m" (_eflags), "+m" ((_dst).val), \ | |
506 | "=&r" (_tmp) \ | |
507 | : "i" (EFLAGS_MASK)); \ | |
508 | } while (0) | |
509 | ||
510 | /* Instruction has only one explicit operand (no source operand). */ | |
511 | #define emulate_1op(_op, _dst, _eflags) \ | |
512 | do { \ | |
d77c26fc | 513 | switch ((_dst).bytes) { \ |
dda96d8f AK |
514 | case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \ |
515 | case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \ | |
516 | case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \ | |
517 | case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \ | |
6aa8b732 AK |
518 | } \ |
519 | } while (0) | |
520 | ||
6aa8b732 AK |
521 | /* Fetch next part of the instruction being emulated. */ |
522 | #define insn_fetch(_type, _size, _eip) \ | |
523 | ({ unsigned long _x; \ | |
62266869 | 524 | rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \ |
af5b4f7f | 525 | if (rc != X86EMUL_CONTINUE) \ |
6aa8b732 AK |
526 | goto done; \ |
527 | (_eip) += (_size); \ | |
528 | (_type)_x; \ | |
529 | }) | |
530 | ||
414e6277 GN |
531 | #define insn_fetch_arr(_arr, _size, _eip) \ |
532 | ({ rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size)); \ | |
533 | if (rc != X86EMUL_CONTINUE) \ | |
534 | goto done; \ | |
535 | (_eip) += (_size); \ | |
536 | }) | |
537 | ||
ddcb2885 HH |
538 | static inline unsigned long ad_mask(struct decode_cache *c) |
539 | { | |
540 | return (1UL << (c->ad_bytes << 3)) - 1; | |
541 | } | |
542 | ||
6aa8b732 | 543 | /* Access/update address held in a register, based on addressing mode. */ |
e4706772 HH |
544 | static inline unsigned long |
545 | address_mask(struct decode_cache *c, unsigned long reg) | |
546 | { | |
547 | if (c->ad_bytes == sizeof(unsigned long)) | |
548 | return reg; | |
549 | else | |
550 | return reg & ad_mask(c); | |
551 | } | |
552 | ||
553 | static inline unsigned long | |
554 | register_address(struct decode_cache *c, unsigned long base, unsigned long reg) | |
555 | { | |
556 | return base + address_mask(c, reg); | |
557 | } | |
558 | ||
7a957275 HH |
559 | static inline void |
560 | register_address_increment(struct decode_cache *c, unsigned long *reg, int inc) | |
561 | { | |
562 | if (c->ad_bytes == sizeof(unsigned long)) | |
563 | *reg += inc; | |
564 | else | |
565 | *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c)); | |
566 | } | |
6aa8b732 | 567 | |
7a957275 HH |
568 | static inline void jmp_rel(struct decode_cache *c, int rel) |
569 | { | |
570 | register_address_increment(c, &c->eip, rel); | |
571 | } | |
098c937b | 572 | |
7a5b56df AK |
573 | static void set_seg_override(struct decode_cache *c, int seg) |
574 | { | |
575 | c->has_seg_override = true; | |
576 | c->seg_override = seg; | |
577 | } | |
578 | ||
79168fd1 GN |
579 | static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, |
580 | struct x86_emulate_ops *ops, int seg) | |
7a5b56df AK |
581 | { |
582 | if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS) | |
583 | return 0; | |
584 | ||
79168fd1 | 585 | return ops->get_cached_segment_base(seg, ctxt->vcpu); |
7a5b56df AK |
586 | } |
587 | ||
588 | static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt, | |
79168fd1 | 589 | struct x86_emulate_ops *ops, |
7a5b56df AK |
590 | struct decode_cache *c) |
591 | { | |
592 | if (!c->has_seg_override) | |
593 | return 0; | |
594 | ||
79168fd1 | 595 | return seg_base(ctxt, ops, c->seg_override); |
7a5b56df AK |
596 | } |
597 | ||
79168fd1 GN |
598 | static unsigned long es_base(struct x86_emulate_ctxt *ctxt, |
599 | struct x86_emulate_ops *ops) | |
7a5b56df | 600 | { |
79168fd1 | 601 | return seg_base(ctxt, ops, VCPU_SREG_ES); |
7a5b56df AK |
602 | } |
603 | ||
79168fd1 GN |
604 | static unsigned long ss_base(struct x86_emulate_ctxt *ctxt, |
605 | struct x86_emulate_ops *ops) | |
7a5b56df | 606 | { |
79168fd1 | 607 | return seg_base(ctxt, ops, VCPU_SREG_SS); |
7a5b56df AK |
608 | } |
609 | ||
54b8486f GN |
610 | static void emulate_exception(struct x86_emulate_ctxt *ctxt, int vec, |
611 | u32 error, bool valid) | |
612 | { | |
613 | ctxt->exception = vec; | |
614 | ctxt->error_code = error; | |
615 | ctxt->error_code_valid = valid; | |
616 | ctxt->restart = false; | |
617 | } | |
618 | ||
619 | static void emulate_gp(struct x86_emulate_ctxt *ctxt, int err) | |
620 | { | |
621 | emulate_exception(ctxt, GP_VECTOR, err, true); | |
622 | } | |
623 | ||
624 | static void emulate_pf(struct x86_emulate_ctxt *ctxt, unsigned long addr, | |
625 | int err) | |
626 | { | |
627 | ctxt->cr2 = addr; | |
628 | emulate_exception(ctxt, PF_VECTOR, err, true); | |
629 | } | |
630 | ||
631 | static void emulate_ud(struct x86_emulate_ctxt *ctxt) | |
632 | { | |
633 | emulate_exception(ctxt, UD_VECTOR, 0, false); | |
634 | } | |
635 | ||
636 | static void emulate_ts(struct x86_emulate_ctxt *ctxt, int err) | |
637 | { | |
638 | emulate_exception(ctxt, TS_VECTOR, err, true); | |
639 | } | |
640 | ||
62266869 AK |
641 | static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt, |
642 | struct x86_emulate_ops *ops, | |
2fb53ad8 | 643 | unsigned long eip, u8 *dest) |
62266869 AK |
644 | { |
645 | struct fetch_cache *fc = &ctxt->decode.fetch; | |
646 | int rc; | |
2fb53ad8 | 647 | int size, cur_size; |
62266869 | 648 | |
2fb53ad8 AK |
649 | if (eip == fc->end) { |
650 | cur_size = fc->end - fc->start; | |
651 | size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip)); | |
652 | rc = ops->fetch(ctxt->cs_base + eip, fc->data + cur_size, | |
653 | size, ctxt->vcpu, NULL); | |
3e2815e9 | 654 | if (rc != X86EMUL_CONTINUE) |
62266869 | 655 | return rc; |
2fb53ad8 | 656 | fc->end += size; |
62266869 | 657 | } |
2fb53ad8 | 658 | *dest = fc->data[eip - fc->start]; |
3e2815e9 | 659 | return X86EMUL_CONTINUE; |
62266869 AK |
660 | } |
661 | ||
662 | static int do_insn_fetch(struct x86_emulate_ctxt *ctxt, | |
663 | struct x86_emulate_ops *ops, | |
664 | unsigned long eip, void *dest, unsigned size) | |
665 | { | |
3e2815e9 | 666 | int rc; |
62266869 | 667 | |
eb3c79e6 | 668 | /* x86 instructions are limited to 15 bytes. */ |
063db061 | 669 | if (eip + size - ctxt->eip > 15) |
eb3c79e6 | 670 | return X86EMUL_UNHANDLEABLE; |
62266869 AK |
671 | while (size--) { |
672 | rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++); | |
3e2815e9 | 673 | if (rc != X86EMUL_CONTINUE) |
62266869 AK |
674 | return rc; |
675 | } | |
3e2815e9 | 676 | return X86EMUL_CONTINUE; |
62266869 AK |
677 | } |
678 | ||
1e3c5cb0 RR |
679 | /* |
680 | * Given the 'reg' portion of a ModRM byte, and a register block, return a | |
681 | * pointer into the block that addresses the relevant register. | |
682 | * @highbyte_regs specifies whether to decode AH,CH,DH,BH. | |
683 | */ | |
684 | static void *decode_register(u8 modrm_reg, unsigned long *regs, | |
685 | int highbyte_regs) | |
6aa8b732 AK |
686 | { |
687 | void *p; | |
688 | ||
689 | p = ®s[modrm_reg]; | |
690 | if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8) | |
691 | p = (unsigned char *)®s[modrm_reg & 3] + 1; | |
692 | return p; | |
693 | } | |
694 | ||
695 | static int read_descriptor(struct x86_emulate_ctxt *ctxt, | |
696 | struct x86_emulate_ops *ops, | |
697 | void *ptr, | |
698 | u16 *size, unsigned long *address, int op_bytes) | |
699 | { | |
700 | int rc; | |
701 | ||
702 | if (op_bytes == 2) | |
703 | op_bytes = 3; | |
704 | *address = 0; | |
cebff02b | 705 | rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2, |
1871c602 | 706 | ctxt->vcpu, NULL); |
1b30eaa8 | 707 | if (rc != X86EMUL_CONTINUE) |
6aa8b732 | 708 | return rc; |
cebff02b | 709 | rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes, |
1871c602 | 710 | ctxt->vcpu, NULL); |
6aa8b732 AK |
711 | return rc; |
712 | } | |
713 | ||
bbe9abbd NK |
714 | static int test_cc(unsigned int condition, unsigned int flags) |
715 | { | |
716 | int rc = 0; | |
717 | ||
718 | switch ((condition & 15) >> 1) { | |
719 | case 0: /* o */ | |
720 | rc |= (flags & EFLG_OF); | |
721 | break; | |
722 | case 1: /* b/c/nae */ | |
723 | rc |= (flags & EFLG_CF); | |
724 | break; | |
725 | case 2: /* z/e */ | |
726 | rc |= (flags & EFLG_ZF); | |
727 | break; | |
728 | case 3: /* be/na */ | |
729 | rc |= (flags & (EFLG_CF|EFLG_ZF)); | |
730 | break; | |
731 | case 4: /* s */ | |
732 | rc |= (flags & EFLG_SF); | |
733 | break; | |
734 | case 5: /* p/pe */ | |
735 | rc |= (flags & EFLG_PF); | |
736 | break; | |
737 | case 7: /* le/ng */ | |
738 | rc |= (flags & EFLG_ZF); | |
739 | /* fall through */ | |
740 | case 6: /* l/nge */ | |
741 | rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF)); | |
742 | break; | |
743 | } | |
744 | ||
745 | /* Odd condition identifiers (lsb == 1) have inverted sense. */ | |
746 | return (!!rc ^ (condition & 1)); | |
747 | } | |
748 | ||
3c118e24 AK |
749 | static void decode_register_operand(struct operand *op, |
750 | struct decode_cache *c, | |
3c118e24 AK |
751 | int inhibit_bytereg) |
752 | { | |
33615aa9 | 753 | unsigned reg = c->modrm_reg; |
9f1ef3f8 | 754 | int highbyte_regs = c->rex_prefix == 0; |
33615aa9 AK |
755 | |
756 | if (!(c->d & ModRM)) | |
757 | reg = (c->b & 7) | ((c->rex_prefix & 1) << 3); | |
3c118e24 AK |
758 | op->type = OP_REG; |
759 | if ((c->d & ByteOp) && !inhibit_bytereg) { | |
33615aa9 | 760 | op->ptr = decode_register(reg, c->regs, highbyte_regs); |
3c118e24 AK |
761 | op->val = *(u8 *)op->ptr; |
762 | op->bytes = 1; | |
763 | } else { | |
33615aa9 | 764 | op->ptr = decode_register(reg, c->regs, 0); |
3c118e24 AK |
765 | op->bytes = c->op_bytes; |
766 | switch (op->bytes) { | |
767 | case 2: | |
768 | op->val = *(u16 *)op->ptr; | |
769 | break; | |
770 | case 4: | |
771 | op->val = *(u32 *)op->ptr; | |
772 | break; | |
773 | case 8: | |
774 | op->val = *(u64 *) op->ptr; | |
775 | break; | |
776 | } | |
777 | } | |
778 | op->orig_val = op->val; | |
779 | } | |
780 | ||
1c73ef66 AK |
781 | static int decode_modrm(struct x86_emulate_ctxt *ctxt, |
782 | struct x86_emulate_ops *ops) | |
783 | { | |
784 | struct decode_cache *c = &ctxt->decode; | |
785 | u8 sib; | |
f5b4edcd | 786 | int index_reg = 0, base_reg = 0, scale; |
3e2815e9 | 787 | int rc = X86EMUL_CONTINUE; |
1c73ef66 AK |
788 | |
789 | if (c->rex_prefix) { | |
790 | c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */ | |
791 | index_reg = (c->rex_prefix & 2) << 2; /* REX.X */ | |
792 | c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */ | |
793 | } | |
794 | ||
795 | c->modrm = insn_fetch(u8, 1, c->eip); | |
796 | c->modrm_mod |= (c->modrm & 0xc0) >> 6; | |
797 | c->modrm_reg |= (c->modrm & 0x38) >> 3; | |
798 | c->modrm_rm |= (c->modrm & 0x07); | |
799 | c->modrm_ea = 0; | |
800 | c->use_modrm_ea = 1; | |
801 | ||
802 | if (c->modrm_mod == 3) { | |
107d6d2e AK |
803 | c->modrm_ptr = decode_register(c->modrm_rm, |
804 | c->regs, c->d & ByteOp); | |
805 | c->modrm_val = *(unsigned long *)c->modrm_ptr; | |
1c73ef66 AK |
806 | return rc; |
807 | } | |
808 | ||
809 | if (c->ad_bytes == 2) { | |
810 | unsigned bx = c->regs[VCPU_REGS_RBX]; | |
811 | unsigned bp = c->regs[VCPU_REGS_RBP]; | |
812 | unsigned si = c->regs[VCPU_REGS_RSI]; | |
813 | unsigned di = c->regs[VCPU_REGS_RDI]; | |
814 | ||
815 | /* 16-bit ModR/M decode. */ | |
816 | switch (c->modrm_mod) { | |
817 | case 0: | |
818 | if (c->modrm_rm == 6) | |
819 | c->modrm_ea += insn_fetch(u16, 2, c->eip); | |
820 | break; | |
821 | case 1: | |
822 | c->modrm_ea += insn_fetch(s8, 1, c->eip); | |
823 | break; | |
824 | case 2: | |
825 | c->modrm_ea += insn_fetch(u16, 2, c->eip); | |
826 | break; | |
827 | } | |
828 | switch (c->modrm_rm) { | |
829 | case 0: | |
830 | c->modrm_ea += bx + si; | |
831 | break; | |
832 | case 1: | |
833 | c->modrm_ea += bx + di; | |
834 | break; | |
835 | case 2: | |
836 | c->modrm_ea += bp + si; | |
837 | break; | |
838 | case 3: | |
839 | c->modrm_ea += bp + di; | |
840 | break; | |
841 | case 4: | |
842 | c->modrm_ea += si; | |
843 | break; | |
844 | case 5: | |
845 | c->modrm_ea += di; | |
846 | break; | |
847 | case 6: | |
848 | if (c->modrm_mod != 0) | |
849 | c->modrm_ea += bp; | |
850 | break; | |
851 | case 7: | |
852 | c->modrm_ea += bx; | |
853 | break; | |
854 | } | |
855 | if (c->modrm_rm == 2 || c->modrm_rm == 3 || | |
856 | (c->modrm_rm == 6 && c->modrm_mod != 0)) | |
7a5b56df AK |
857 | if (!c->has_seg_override) |
858 | set_seg_override(c, VCPU_SREG_SS); | |
1c73ef66 AK |
859 | c->modrm_ea = (u16)c->modrm_ea; |
860 | } else { | |
861 | /* 32/64-bit ModR/M decode. */ | |
84411d85 | 862 | if ((c->modrm_rm & 7) == 4) { |
1c73ef66 AK |
863 | sib = insn_fetch(u8, 1, c->eip); |
864 | index_reg |= (sib >> 3) & 7; | |
865 | base_reg |= sib & 7; | |
866 | scale = sib >> 6; | |
867 | ||
dc71d0f1 AK |
868 | if ((base_reg & 7) == 5 && c->modrm_mod == 0) |
869 | c->modrm_ea += insn_fetch(s32, 4, c->eip); | |
870 | else | |
1c73ef66 | 871 | c->modrm_ea += c->regs[base_reg]; |
dc71d0f1 | 872 | if (index_reg != 4) |
1c73ef66 | 873 | c->modrm_ea += c->regs[index_reg] << scale; |
84411d85 AK |
874 | } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) { |
875 | if (ctxt->mode == X86EMUL_MODE_PROT64) | |
f5b4edcd | 876 | c->rip_relative = 1; |
84411d85 | 877 | } else |
1c73ef66 | 878 | c->modrm_ea += c->regs[c->modrm_rm]; |
1c73ef66 AK |
879 | switch (c->modrm_mod) { |
880 | case 0: | |
881 | if (c->modrm_rm == 5) | |
882 | c->modrm_ea += insn_fetch(s32, 4, c->eip); | |
883 | break; | |
884 | case 1: | |
885 | c->modrm_ea += insn_fetch(s8, 1, c->eip); | |
886 | break; | |
887 | case 2: | |
888 | c->modrm_ea += insn_fetch(s32, 4, c->eip); | |
889 | break; | |
890 | } | |
891 | } | |
1c73ef66 AK |
892 | done: |
893 | return rc; | |
894 | } | |
895 | ||
896 | static int decode_abs(struct x86_emulate_ctxt *ctxt, | |
897 | struct x86_emulate_ops *ops) | |
898 | { | |
899 | struct decode_cache *c = &ctxt->decode; | |
3e2815e9 | 900 | int rc = X86EMUL_CONTINUE; |
1c73ef66 AK |
901 | |
902 | switch (c->ad_bytes) { | |
903 | case 2: | |
904 | c->modrm_ea = insn_fetch(u16, 2, c->eip); | |
905 | break; | |
906 | case 4: | |
907 | c->modrm_ea = insn_fetch(u32, 4, c->eip); | |
908 | break; | |
909 | case 8: | |
910 | c->modrm_ea = insn_fetch(u64, 8, c->eip); | |
911 | break; | |
912 | } | |
913 | done: | |
914 | return rc; | |
915 | } | |
916 | ||
6aa8b732 | 917 | int |
8b4caf66 | 918 | x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) |
6aa8b732 | 919 | { |
e4e03ded | 920 | struct decode_cache *c = &ctxt->decode; |
3e2815e9 | 921 | int rc = X86EMUL_CONTINUE; |
6aa8b732 | 922 | int mode = ctxt->mode; |
52811d7d | 923 | int def_op_bytes, def_ad_bytes, group, dual; |
6aa8b732 | 924 | |
6aa8b732 | 925 | |
5cd21917 GN |
926 | /* we cannot decode insn before we complete previous rep insn */ |
927 | WARN_ON(ctxt->restart); | |
928 | ||
063db061 | 929 | c->eip = ctxt->eip; |
2fb53ad8 | 930 | c->fetch.start = c->fetch.end = c->eip; |
79168fd1 | 931 | ctxt->cs_base = seg_base(ctxt, ops, VCPU_SREG_CS); |
6aa8b732 AK |
932 | |
933 | switch (mode) { | |
934 | case X86EMUL_MODE_REAL: | |
a0044755 | 935 | case X86EMUL_MODE_VM86: |
6aa8b732 | 936 | case X86EMUL_MODE_PROT16: |
f21b8bf4 | 937 | def_op_bytes = def_ad_bytes = 2; |
6aa8b732 AK |
938 | break; |
939 | case X86EMUL_MODE_PROT32: | |
f21b8bf4 | 940 | def_op_bytes = def_ad_bytes = 4; |
6aa8b732 | 941 | break; |
05b3e0c2 | 942 | #ifdef CONFIG_X86_64 |
6aa8b732 | 943 | case X86EMUL_MODE_PROT64: |
f21b8bf4 AK |
944 | def_op_bytes = 4; |
945 | def_ad_bytes = 8; | |
6aa8b732 AK |
946 | break; |
947 | #endif | |
948 | default: | |
949 | return -1; | |
950 | } | |
951 | ||
f21b8bf4 AK |
952 | c->op_bytes = def_op_bytes; |
953 | c->ad_bytes = def_ad_bytes; | |
954 | ||
6aa8b732 | 955 | /* Legacy prefixes. */ |
b4c6abfe | 956 | for (;;) { |
e4e03ded | 957 | switch (c->b = insn_fetch(u8, 1, c->eip)) { |
6aa8b732 | 958 | case 0x66: /* operand-size override */ |
f21b8bf4 AK |
959 | /* switch between 2/4 bytes */ |
960 | c->op_bytes = def_op_bytes ^ 6; | |
6aa8b732 AK |
961 | break; |
962 | case 0x67: /* address-size override */ | |
963 | if (mode == X86EMUL_MODE_PROT64) | |
e4e03ded | 964 | /* switch between 4/8 bytes */ |
f21b8bf4 | 965 | c->ad_bytes = def_ad_bytes ^ 12; |
6aa8b732 | 966 | else |
e4e03ded | 967 | /* switch between 2/4 bytes */ |
f21b8bf4 | 968 | c->ad_bytes = def_ad_bytes ^ 6; |
6aa8b732 | 969 | break; |
7a5b56df | 970 | case 0x26: /* ES override */ |
6aa8b732 | 971 | case 0x2e: /* CS override */ |
7a5b56df | 972 | case 0x36: /* SS override */ |
6aa8b732 | 973 | case 0x3e: /* DS override */ |
7a5b56df | 974 | set_seg_override(c, (c->b >> 3) & 3); |
6aa8b732 AK |
975 | break; |
976 | case 0x64: /* FS override */ | |
6aa8b732 | 977 | case 0x65: /* GS override */ |
7a5b56df | 978 | set_seg_override(c, c->b & 7); |
6aa8b732 | 979 | break; |
b4c6abfe LV |
980 | case 0x40 ... 0x4f: /* REX */ |
981 | if (mode != X86EMUL_MODE_PROT64) | |
982 | goto done_prefixes; | |
33615aa9 | 983 | c->rex_prefix = c->b; |
b4c6abfe | 984 | continue; |
6aa8b732 | 985 | case 0xf0: /* LOCK */ |
e4e03ded | 986 | c->lock_prefix = 1; |
6aa8b732 | 987 | break; |
ae6200ba | 988 | case 0xf2: /* REPNE/REPNZ */ |
90e0a28f GT |
989 | c->rep_prefix = REPNE_PREFIX; |
990 | break; | |
6aa8b732 | 991 | case 0xf3: /* REP/REPE/REPZ */ |
90e0a28f | 992 | c->rep_prefix = REPE_PREFIX; |
6aa8b732 | 993 | break; |
6aa8b732 AK |
994 | default: |
995 | goto done_prefixes; | |
996 | } | |
b4c6abfe LV |
997 | |
998 | /* Any legacy prefix after a REX prefix nullifies its effect. */ | |
999 | ||
33615aa9 | 1000 | c->rex_prefix = 0; |
6aa8b732 AK |
1001 | } |
1002 | ||
1003 | done_prefixes: | |
1004 | ||
1005 | /* REX prefix. */ | |
1c73ef66 | 1006 | if (c->rex_prefix) |
33615aa9 | 1007 | if (c->rex_prefix & 8) |
e4e03ded | 1008 | c->op_bytes = 8; /* REX.W */ |
6aa8b732 AK |
1009 | |
1010 | /* Opcode byte(s). */ | |
e4e03ded LV |
1011 | c->d = opcode_table[c->b]; |
1012 | if (c->d == 0) { | |
6aa8b732 | 1013 | /* Two-byte opcode? */ |
e4e03ded LV |
1014 | if (c->b == 0x0f) { |
1015 | c->twobyte = 1; | |
1016 | c->b = insn_fetch(u8, 1, c->eip); | |
1017 | c->d = twobyte_table[c->b]; | |
6aa8b732 | 1018 | } |
e09d082c | 1019 | } |
6aa8b732 | 1020 | |
e09d082c AK |
1021 | if (c->d & Group) { |
1022 | group = c->d & GroupMask; | |
52811d7d | 1023 | dual = c->d & GroupDual; |
e09d082c AK |
1024 | c->modrm = insn_fetch(u8, 1, c->eip); |
1025 | --c->eip; | |
1026 | ||
1027 | group = (group << 3) + ((c->modrm >> 3) & 7); | |
52811d7d AK |
1028 | c->d &= ~(Group | GroupDual | GroupMask); |
1029 | if (dual && (c->modrm >> 6) == 3) | |
1030 | c->d |= group2_table[group]; | |
e09d082c | 1031 | else |
52811d7d | 1032 | c->d |= group_table[group]; |
e09d082c AK |
1033 | } |
1034 | ||
1035 | /* Unrecognised? */ | |
047a4818 | 1036 | if (c->d == 0 || (c->d & Undefined)) { |
e09d082c AK |
1037 | DPRINTF("Cannot emulate %02x\n", c->b); |
1038 | return -1; | |
6aa8b732 AK |
1039 | } |
1040 | ||
6e3d5dfb AK |
1041 | if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack)) |
1042 | c->op_bytes = 8; | |
1043 | ||
6aa8b732 | 1044 | /* ModRM and SIB bytes. */ |
1c73ef66 AK |
1045 | if (c->d & ModRM) |
1046 | rc = decode_modrm(ctxt, ops); | |
1047 | else if (c->d & MemAbs) | |
1048 | rc = decode_abs(ctxt, ops); | |
3e2815e9 | 1049 | if (rc != X86EMUL_CONTINUE) |
1c73ef66 | 1050 | goto done; |
6aa8b732 | 1051 | |
7a5b56df AK |
1052 | if (!c->has_seg_override) |
1053 | set_seg_override(c, VCPU_SREG_DS); | |
c7e75a3d | 1054 | |
7a5b56df | 1055 | if (!(!c->twobyte && c->b == 0x8d)) |
79168fd1 | 1056 | c->modrm_ea += seg_override_base(ctxt, ops, c); |
c7e75a3d AK |
1057 | |
1058 | if (c->ad_bytes != 8) | |
1059 | c->modrm_ea = (u32)c->modrm_ea; | |
69f55cb1 GN |
1060 | |
1061 | if (c->rip_relative) | |
1062 | c->modrm_ea += c->eip; | |
1063 | ||
6aa8b732 AK |
1064 | /* |
1065 | * Decode and fetch the source operand: register, memory | |
1066 | * or immediate. | |
1067 | */ | |
e4e03ded | 1068 | switch (c->d & SrcMask) { |
6aa8b732 AK |
1069 | case SrcNone: |
1070 | break; | |
1071 | case SrcReg: | |
9f1ef3f8 | 1072 | decode_register_operand(&c->src, c, 0); |
6aa8b732 AK |
1073 | break; |
1074 | case SrcMem16: | |
e4e03ded | 1075 | c->src.bytes = 2; |
6aa8b732 AK |
1076 | goto srcmem_common; |
1077 | case SrcMem32: | |
e4e03ded | 1078 | c->src.bytes = 4; |
6aa8b732 AK |
1079 | goto srcmem_common; |
1080 | case SrcMem: | |
e4e03ded LV |
1081 | c->src.bytes = (c->d & ByteOp) ? 1 : |
1082 | c->op_bytes; | |
b85b9ee9 | 1083 | /* Don't fetch the address for invlpg: it could be unmapped. */ |
d77c26fc | 1084 | if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7) |
b85b9ee9 | 1085 | break; |
d77c26fc | 1086 | srcmem_common: |
4e62417b AJ |
1087 | /* |
1088 | * For instructions with a ModR/M byte, switch to register | |
1089 | * access if Mod = 3. | |
1090 | */ | |
e4e03ded LV |
1091 | if ((c->d & ModRM) && c->modrm_mod == 3) { |
1092 | c->src.type = OP_REG; | |
66b85505 | 1093 | c->src.val = c->modrm_val; |
107d6d2e | 1094 | c->src.ptr = c->modrm_ptr; |
4e62417b AJ |
1095 | break; |
1096 | } | |
e4e03ded | 1097 | c->src.type = OP_MEM; |
69f55cb1 GN |
1098 | c->src.ptr = (unsigned long *)c->modrm_ea; |
1099 | c->src.val = 0; | |
6aa8b732 AK |
1100 | break; |
1101 | case SrcImm: | |
c9eaf20f | 1102 | case SrcImmU: |
e4e03ded LV |
1103 | c->src.type = OP_IMM; |
1104 | c->src.ptr = (unsigned long *)c->eip; | |
1105 | c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
1106 | if (c->src.bytes == 8) | |
1107 | c->src.bytes = 4; | |
6aa8b732 | 1108 | /* NB. Immediates are sign-extended as necessary. */ |
e4e03ded | 1109 | switch (c->src.bytes) { |
6aa8b732 | 1110 | case 1: |
e4e03ded | 1111 | c->src.val = insn_fetch(s8, 1, c->eip); |
6aa8b732 AK |
1112 | break; |
1113 | case 2: | |
e4e03ded | 1114 | c->src.val = insn_fetch(s16, 2, c->eip); |
6aa8b732 AK |
1115 | break; |
1116 | case 4: | |
e4e03ded | 1117 | c->src.val = insn_fetch(s32, 4, c->eip); |
6aa8b732 AK |
1118 | break; |
1119 | } | |
c9eaf20f AK |
1120 | if ((c->d & SrcMask) == SrcImmU) { |
1121 | switch (c->src.bytes) { | |
1122 | case 1: | |
1123 | c->src.val &= 0xff; | |
1124 | break; | |
1125 | case 2: | |
1126 | c->src.val &= 0xffff; | |
1127 | break; | |
1128 | case 4: | |
1129 | c->src.val &= 0xffffffff; | |
1130 | break; | |
1131 | } | |
1132 | } | |
6aa8b732 AK |
1133 | break; |
1134 | case SrcImmByte: | |
341de7e3 | 1135 | case SrcImmUByte: |
e4e03ded LV |
1136 | c->src.type = OP_IMM; |
1137 | c->src.ptr = (unsigned long *)c->eip; | |
1138 | c->src.bytes = 1; | |
341de7e3 GN |
1139 | if ((c->d & SrcMask) == SrcImmByte) |
1140 | c->src.val = insn_fetch(s8, 1, c->eip); | |
1141 | else | |
1142 | c->src.val = insn_fetch(u8, 1, c->eip); | |
6aa8b732 | 1143 | break; |
5d55f299 WY |
1144 | case SrcAcc: |
1145 | c->src.type = OP_REG; | |
1146 | c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
1147 | c->src.ptr = &c->regs[VCPU_REGS_RAX]; | |
1148 | switch (c->src.bytes) { | |
1149 | case 1: | |
1150 | c->src.val = *(u8 *)c->src.ptr; | |
1151 | break; | |
1152 | case 2: | |
1153 | c->src.val = *(u16 *)c->src.ptr; | |
1154 | break; | |
1155 | case 4: | |
1156 | c->src.val = *(u32 *)c->src.ptr; | |
1157 | break; | |
1158 | case 8: | |
1159 | c->src.val = *(u64 *)c->src.ptr; | |
1160 | break; | |
1161 | } | |
1162 | break; | |
bfcadf83 GT |
1163 | case SrcOne: |
1164 | c->src.bytes = 1; | |
1165 | c->src.val = 1; | |
1166 | break; | |
a682e354 GN |
1167 | case SrcSI: |
1168 | c->src.type = OP_MEM; | |
1169 | c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
1170 | c->src.ptr = (unsigned long *) | |
79168fd1 | 1171 | register_address(c, seg_override_base(ctxt, ops, c), |
a682e354 GN |
1172 | c->regs[VCPU_REGS_RSI]); |
1173 | c->src.val = 0; | |
1174 | break; | |
414e6277 GN |
1175 | case SrcImmFAddr: |
1176 | c->src.type = OP_IMM; | |
1177 | c->src.ptr = (unsigned long *)c->eip; | |
1178 | c->src.bytes = c->op_bytes + 2; | |
1179 | insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip); | |
1180 | break; | |
1181 | case SrcMemFAddr: | |
1182 | c->src.type = OP_MEM; | |
1183 | c->src.ptr = (unsigned long *)c->modrm_ea; | |
1184 | c->src.bytes = c->op_bytes + 2; | |
1185 | break; | |
6aa8b732 AK |
1186 | } |
1187 | ||
0dc8d10f GT |
1188 | /* |
1189 | * Decode and fetch the second source operand: register, memory | |
1190 | * or immediate. | |
1191 | */ | |
1192 | switch (c->d & Src2Mask) { | |
1193 | case Src2None: | |
1194 | break; | |
1195 | case Src2CL: | |
1196 | c->src2.bytes = 1; | |
1197 | c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8; | |
1198 | break; | |
1199 | case Src2ImmByte: | |
1200 | c->src2.type = OP_IMM; | |
1201 | c->src2.ptr = (unsigned long *)c->eip; | |
1202 | c->src2.bytes = 1; | |
1203 | c->src2.val = insn_fetch(u8, 1, c->eip); | |
1204 | break; | |
1205 | case Src2One: | |
1206 | c->src2.bytes = 1; | |
1207 | c->src2.val = 1; | |
1208 | break; | |
1209 | } | |
1210 | ||
038e51de | 1211 | /* Decode and fetch the destination operand: register or memory. */ |
e4e03ded | 1212 | switch (c->d & DstMask) { |
038e51de AK |
1213 | case ImplicitOps: |
1214 | /* Special instructions do their own operand decoding. */ | |
8b4caf66 | 1215 | return 0; |
038e51de | 1216 | case DstReg: |
9f1ef3f8 | 1217 | decode_register_operand(&c->dst, c, |
3c118e24 | 1218 | c->twobyte && (c->b == 0xb6 || c->b == 0xb7)); |
038e51de AK |
1219 | break; |
1220 | case DstMem: | |
6550e1f1 | 1221 | case DstMem64: |
e4e03ded | 1222 | if ((c->d & ModRM) && c->modrm_mod == 3) { |
89c69638 | 1223 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; |
e4e03ded | 1224 | c->dst.type = OP_REG; |
66b85505 | 1225 | c->dst.val = c->dst.orig_val = c->modrm_val; |
107d6d2e | 1226 | c->dst.ptr = c->modrm_ptr; |
4e62417b AJ |
1227 | break; |
1228 | } | |
8b4caf66 | 1229 | c->dst.type = OP_MEM; |
69f55cb1 | 1230 | c->dst.ptr = (unsigned long *)c->modrm_ea; |
6550e1f1 GN |
1231 | if ((c->d & DstMask) == DstMem64) |
1232 | c->dst.bytes = 8; | |
1233 | else | |
1234 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
69f55cb1 GN |
1235 | c->dst.val = 0; |
1236 | if (c->d & BitOp) { | |
1237 | unsigned long mask = ~(c->dst.bytes * 8 - 1); | |
1238 | ||
1239 | c->dst.ptr = (void *)c->dst.ptr + | |
1240 | (c->src.val & mask) / 8; | |
1241 | } | |
8b4caf66 | 1242 | break; |
9c9fddd0 GT |
1243 | case DstAcc: |
1244 | c->dst.type = OP_REG; | |
d6d367d6 | 1245 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; |
9c9fddd0 | 1246 | c->dst.ptr = &c->regs[VCPU_REGS_RAX]; |
d6d367d6 | 1247 | switch (c->dst.bytes) { |
9c9fddd0 GT |
1248 | case 1: |
1249 | c->dst.val = *(u8 *)c->dst.ptr; | |
1250 | break; | |
1251 | case 2: | |
1252 | c->dst.val = *(u16 *)c->dst.ptr; | |
1253 | break; | |
1254 | case 4: | |
1255 | c->dst.val = *(u32 *)c->dst.ptr; | |
1256 | break; | |
d6d367d6 GN |
1257 | case 8: |
1258 | c->dst.val = *(u64 *)c->dst.ptr; | |
1259 | break; | |
9c9fddd0 GT |
1260 | } |
1261 | c->dst.orig_val = c->dst.val; | |
1262 | break; | |
a682e354 GN |
1263 | case DstDI: |
1264 | c->dst.type = OP_MEM; | |
1265 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
1266 | c->dst.ptr = (unsigned long *) | |
79168fd1 | 1267 | register_address(c, es_base(ctxt, ops), |
a682e354 GN |
1268 | c->regs[VCPU_REGS_RDI]); |
1269 | c->dst.val = 0; | |
1270 | break; | |
8b4caf66 LV |
1271 | } |
1272 | ||
1273 | done: | |
1274 | return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0; | |
1275 | } | |
1276 | ||
9de41573 GN |
1277 | static int read_emulated(struct x86_emulate_ctxt *ctxt, |
1278 | struct x86_emulate_ops *ops, | |
1279 | unsigned long addr, void *dest, unsigned size) | |
1280 | { | |
1281 | int rc; | |
1282 | struct read_cache *mc = &ctxt->decode.mem_read; | |
8fe681e9 | 1283 | u32 err; |
9de41573 GN |
1284 | |
1285 | while (size) { | |
1286 | int n = min(size, 8u); | |
1287 | size -= n; | |
1288 | if (mc->pos < mc->end) | |
1289 | goto read_cached; | |
1290 | ||
8fe681e9 GN |
1291 | rc = ops->read_emulated(addr, mc->data + mc->end, n, &err, |
1292 | ctxt->vcpu); | |
1293 | if (rc == X86EMUL_PROPAGATE_FAULT) | |
54b8486f | 1294 | emulate_pf(ctxt, addr, err); |
9de41573 GN |
1295 | if (rc != X86EMUL_CONTINUE) |
1296 | return rc; | |
1297 | mc->end += n; | |
1298 | ||
1299 | read_cached: | |
1300 | memcpy(dest, mc->data + mc->pos, n); | |
1301 | mc->pos += n; | |
1302 | dest += n; | |
1303 | addr += n; | |
1304 | } | |
1305 | return X86EMUL_CONTINUE; | |
1306 | } | |
1307 | ||
7b262e90 GN |
1308 | static int pio_in_emulated(struct x86_emulate_ctxt *ctxt, |
1309 | struct x86_emulate_ops *ops, | |
1310 | unsigned int size, unsigned short port, | |
1311 | void *dest) | |
1312 | { | |
1313 | struct read_cache *rc = &ctxt->decode.io_read; | |
1314 | ||
1315 | if (rc->pos == rc->end) { /* refill pio read ahead */ | |
1316 | struct decode_cache *c = &ctxt->decode; | |
1317 | unsigned int in_page, n; | |
1318 | unsigned int count = c->rep_prefix ? | |
1319 | address_mask(c, c->regs[VCPU_REGS_RCX]) : 1; | |
1320 | in_page = (ctxt->eflags & EFLG_DF) ? | |
1321 | offset_in_page(c->regs[VCPU_REGS_RDI]) : | |
1322 | PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]); | |
1323 | n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size, | |
1324 | count); | |
1325 | if (n == 0) | |
1326 | n = 1; | |
1327 | rc->pos = rc->end = 0; | |
1328 | if (!ops->pio_in_emulated(size, port, rc->data, n, ctxt->vcpu)) | |
1329 | return 0; | |
1330 | rc->end = n * size; | |
1331 | } | |
1332 | ||
1333 | memcpy(dest, rc->data + rc->pos, size); | |
1334 | rc->pos += size; | |
1335 | return 1; | |
1336 | } | |
1337 | ||
38ba30ba GN |
1338 | static u32 desc_limit_scaled(struct desc_struct *desc) |
1339 | { | |
1340 | u32 limit = get_desc_limit(desc); | |
1341 | ||
1342 | return desc->g ? (limit << 12) | 0xfff : limit; | |
1343 | } | |
1344 | ||
1345 | static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt, | |
1346 | struct x86_emulate_ops *ops, | |
1347 | u16 selector, struct desc_ptr *dt) | |
1348 | { | |
1349 | if (selector & 1 << 2) { | |
1350 | struct desc_struct desc; | |
1351 | memset (dt, 0, sizeof *dt); | |
1352 | if (!ops->get_cached_descriptor(&desc, VCPU_SREG_LDTR, ctxt->vcpu)) | |
1353 | return; | |
1354 | ||
1355 | dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */ | |
1356 | dt->address = get_desc_base(&desc); | |
1357 | } else | |
1358 | ops->get_gdt(dt, ctxt->vcpu); | |
1359 | } | |
1360 | ||
1361 | /* allowed just for 8 bytes segments */ | |
1362 | static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt, | |
1363 | struct x86_emulate_ops *ops, | |
1364 | u16 selector, struct desc_struct *desc) | |
1365 | { | |
1366 | struct desc_ptr dt; | |
1367 | u16 index = selector >> 3; | |
1368 | int ret; | |
1369 | u32 err; | |
1370 | ulong addr; | |
1371 | ||
1372 | get_descriptor_table_ptr(ctxt, ops, selector, &dt); | |
1373 | ||
1374 | if (dt.size < index * 8 + 7) { | |
54b8486f | 1375 | emulate_gp(ctxt, selector & 0xfffc); |
38ba30ba GN |
1376 | return X86EMUL_PROPAGATE_FAULT; |
1377 | } | |
1378 | addr = dt.address + index * 8; | |
1379 | ret = ops->read_std(addr, desc, sizeof *desc, ctxt->vcpu, &err); | |
1380 | if (ret == X86EMUL_PROPAGATE_FAULT) | |
54b8486f | 1381 | emulate_pf(ctxt, addr, err); |
38ba30ba GN |
1382 | |
1383 | return ret; | |
1384 | } | |
1385 | ||
1386 | /* allowed just for 8 bytes segments */ | |
1387 | static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt, | |
1388 | struct x86_emulate_ops *ops, | |
1389 | u16 selector, struct desc_struct *desc) | |
1390 | { | |
1391 | struct desc_ptr dt; | |
1392 | u16 index = selector >> 3; | |
1393 | u32 err; | |
1394 | ulong addr; | |
1395 | int ret; | |
1396 | ||
1397 | get_descriptor_table_ptr(ctxt, ops, selector, &dt); | |
1398 | ||
1399 | if (dt.size < index * 8 + 7) { | |
54b8486f | 1400 | emulate_gp(ctxt, selector & 0xfffc); |
38ba30ba GN |
1401 | return X86EMUL_PROPAGATE_FAULT; |
1402 | } | |
1403 | ||
1404 | addr = dt.address + index * 8; | |
1405 | ret = ops->write_std(addr, desc, sizeof *desc, ctxt->vcpu, &err); | |
1406 | if (ret == X86EMUL_PROPAGATE_FAULT) | |
54b8486f | 1407 | emulate_pf(ctxt, addr, err); |
38ba30ba GN |
1408 | |
1409 | return ret; | |
1410 | } | |
1411 | ||
1412 | static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt, | |
1413 | struct x86_emulate_ops *ops, | |
1414 | u16 selector, int seg) | |
1415 | { | |
1416 | struct desc_struct seg_desc; | |
1417 | u8 dpl, rpl, cpl; | |
1418 | unsigned err_vec = GP_VECTOR; | |
1419 | u32 err_code = 0; | |
1420 | bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */ | |
1421 | int ret; | |
1422 | ||
1423 | memset(&seg_desc, 0, sizeof seg_desc); | |
1424 | ||
1425 | if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) | |
1426 | || ctxt->mode == X86EMUL_MODE_REAL) { | |
1427 | /* set real mode segment descriptor */ | |
1428 | set_desc_base(&seg_desc, selector << 4); | |
1429 | set_desc_limit(&seg_desc, 0xffff); | |
1430 | seg_desc.type = 3; | |
1431 | seg_desc.p = 1; | |
1432 | seg_desc.s = 1; | |
1433 | goto load; | |
1434 | } | |
1435 | ||
1436 | /* NULL selector is not valid for TR, CS and SS */ | |
1437 | if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR) | |
1438 | && null_selector) | |
1439 | goto exception; | |
1440 | ||
1441 | /* TR should be in GDT only */ | |
1442 | if (seg == VCPU_SREG_TR && (selector & (1 << 2))) | |
1443 | goto exception; | |
1444 | ||
1445 | if (null_selector) /* for NULL selector skip all following checks */ | |
1446 | goto load; | |
1447 | ||
1448 | ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc); | |
1449 | if (ret != X86EMUL_CONTINUE) | |
1450 | return ret; | |
1451 | ||
1452 | err_code = selector & 0xfffc; | |
1453 | err_vec = GP_VECTOR; | |
1454 | ||
1455 | /* can't load system descriptor into segment selecor */ | |
1456 | if (seg <= VCPU_SREG_GS && !seg_desc.s) | |
1457 | goto exception; | |
1458 | ||
1459 | if (!seg_desc.p) { | |
1460 | err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR; | |
1461 | goto exception; | |
1462 | } | |
1463 | ||
1464 | rpl = selector & 3; | |
1465 | dpl = seg_desc.dpl; | |
1466 | cpl = ops->cpl(ctxt->vcpu); | |
1467 | ||
1468 | switch (seg) { | |
1469 | case VCPU_SREG_SS: | |
1470 | /* | |
1471 | * segment is not a writable data segment or segment | |
1472 | * selector's RPL != CPL or segment selector's RPL != CPL | |
1473 | */ | |
1474 | if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl) | |
1475 | goto exception; | |
1476 | break; | |
1477 | case VCPU_SREG_CS: | |
1478 | if (!(seg_desc.type & 8)) | |
1479 | goto exception; | |
1480 | ||
1481 | if (seg_desc.type & 4) { | |
1482 | /* conforming */ | |
1483 | if (dpl > cpl) | |
1484 | goto exception; | |
1485 | } else { | |
1486 | /* nonconforming */ | |
1487 | if (rpl > cpl || dpl != cpl) | |
1488 | goto exception; | |
1489 | } | |
1490 | /* CS(RPL) <- CPL */ | |
1491 | selector = (selector & 0xfffc) | cpl; | |
1492 | break; | |
1493 | case VCPU_SREG_TR: | |
1494 | if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9)) | |
1495 | goto exception; | |
1496 | break; | |
1497 | case VCPU_SREG_LDTR: | |
1498 | if (seg_desc.s || seg_desc.type != 2) | |
1499 | goto exception; | |
1500 | break; | |
1501 | default: /* DS, ES, FS, or GS */ | |
1502 | /* | |
1503 | * segment is not a data or readable code segment or | |
1504 | * ((segment is a data or nonconforming code segment) | |
1505 | * and (both RPL and CPL > DPL)) | |
1506 | */ | |
1507 | if ((seg_desc.type & 0xa) == 0x8 || | |
1508 | (((seg_desc.type & 0xc) != 0xc) && | |
1509 | (rpl > dpl && cpl > dpl))) | |
1510 | goto exception; | |
1511 | break; | |
1512 | } | |
1513 | ||
1514 | if (seg_desc.s) { | |
1515 | /* mark segment as accessed */ | |
1516 | seg_desc.type |= 1; | |
1517 | ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc); | |
1518 | if (ret != X86EMUL_CONTINUE) | |
1519 | return ret; | |
1520 | } | |
1521 | load: | |
1522 | ops->set_segment_selector(selector, seg, ctxt->vcpu); | |
1523 | ops->set_cached_descriptor(&seg_desc, seg, ctxt->vcpu); | |
1524 | return X86EMUL_CONTINUE; | |
1525 | exception: | |
54b8486f | 1526 | emulate_exception(ctxt, err_vec, err_code, true); |
38ba30ba GN |
1527 | return X86EMUL_PROPAGATE_FAULT; |
1528 | } | |
1529 | ||
c37eda13 WY |
1530 | static inline int writeback(struct x86_emulate_ctxt *ctxt, |
1531 | struct x86_emulate_ops *ops) | |
1532 | { | |
1533 | int rc; | |
1534 | struct decode_cache *c = &ctxt->decode; | |
1535 | u32 err; | |
1536 | ||
1537 | switch (c->dst.type) { | |
1538 | case OP_REG: | |
1539 | /* The 4-byte case *is* correct: | |
1540 | * in 64-bit mode we zero-extend. | |
1541 | */ | |
1542 | switch (c->dst.bytes) { | |
1543 | case 1: | |
1544 | *(u8 *)c->dst.ptr = (u8)c->dst.val; | |
1545 | break; | |
1546 | case 2: | |
1547 | *(u16 *)c->dst.ptr = (u16)c->dst.val; | |
1548 | break; | |
1549 | case 4: | |
1550 | *c->dst.ptr = (u32)c->dst.val; | |
1551 | break; /* 64b: zero-ext */ | |
1552 | case 8: | |
1553 | *c->dst.ptr = c->dst.val; | |
1554 | break; | |
1555 | } | |
1556 | break; | |
1557 | case OP_MEM: | |
1558 | if (c->lock_prefix) | |
1559 | rc = ops->cmpxchg_emulated( | |
1560 | (unsigned long)c->dst.ptr, | |
1561 | &c->dst.orig_val, | |
1562 | &c->dst.val, | |
1563 | c->dst.bytes, | |
1564 | &err, | |
1565 | ctxt->vcpu); | |
1566 | else | |
1567 | rc = ops->write_emulated( | |
1568 | (unsigned long)c->dst.ptr, | |
1569 | &c->dst.val, | |
1570 | c->dst.bytes, | |
1571 | &err, | |
1572 | ctxt->vcpu); | |
1573 | if (rc == X86EMUL_PROPAGATE_FAULT) | |
1574 | emulate_pf(ctxt, | |
1575 | (unsigned long)c->dst.ptr, err); | |
1576 | if (rc != X86EMUL_CONTINUE) | |
1577 | return rc; | |
1578 | break; | |
1579 | case OP_NONE: | |
1580 | /* no writeback */ | |
1581 | break; | |
1582 | default: | |
1583 | break; | |
1584 | } | |
1585 | return X86EMUL_CONTINUE; | |
1586 | } | |
1587 | ||
79168fd1 GN |
1588 | static inline void emulate_push(struct x86_emulate_ctxt *ctxt, |
1589 | struct x86_emulate_ops *ops) | |
8cdbd2c9 LV |
1590 | { |
1591 | struct decode_cache *c = &ctxt->decode; | |
1592 | ||
1593 | c->dst.type = OP_MEM; | |
1594 | c->dst.bytes = c->op_bytes; | |
1595 | c->dst.val = c->src.val; | |
7a957275 | 1596 | register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes); |
79168fd1 | 1597 | c->dst.ptr = (void *) register_address(c, ss_base(ctxt, ops), |
8cdbd2c9 LV |
1598 | c->regs[VCPU_REGS_RSP]); |
1599 | } | |
1600 | ||
faa5a3ae | 1601 | static int emulate_pop(struct x86_emulate_ctxt *ctxt, |
350f69dc AK |
1602 | struct x86_emulate_ops *ops, |
1603 | void *dest, int len) | |
8cdbd2c9 LV |
1604 | { |
1605 | struct decode_cache *c = &ctxt->decode; | |
1606 | int rc; | |
1607 | ||
79168fd1 | 1608 | rc = read_emulated(ctxt, ops, register_address(c, ss_base(ctxt, ops), |
9de41573 GN |
1609 | c->regs[VCPU_REGS_RSP]), |
1610 | dest, len); | |
b60d513c | 1611 | if (rc != X86EMUL_CONTINUE) |
8cdbd2c9 LV |
1612 | return rc; |
1613 | ||
350f69dc | 1614 | register_address_increment(c, &c->regs[VCPU_REGS_RSP], len); |
faa5a3ae AK |
1615 | return rc; |
1616 | } | |
8cdbd2c9 | 1617 | |
d4c6a154 GN |
1618 | static int emulate_popf(struct x86_emulate_ctxt *ctxt, |
1619 | struct x86_emulate_ops *ops, | |
1620 | void *dest, int len) | |
1621 | { | |
1622 | int rc; | |
1623 | unsigned long val, change_mask; | |
1624 | int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; | |
9c537244 | 1625 | int cpl = ops->cpl(ctxt->vcpu); |
d4c6a154 GN |
1626 | |
1627 | rc = emulate_pop(ctxt, ops, &val, len); | |
1628 | if (rc != X86EMUL_CONTINUE) | |
1629 | return rc; | |
1630 | ||
1631 | change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF | |
1632 | | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID; | |
1633 | ||
1634 | switch(ctxt->mode) { | |
1635 | case X86EMUL_MODE_PROT64: | |
1636 | case X86EMUL_MODE_PROT32: | |
1637 | case X86EMUL_MODE_PROT16: | |
1638 | if (cpl == 0) | |
1639 | change_mask |= EFLG_IOPL; | |
1640 | if (cpl <= iopl) | |
1641 | change_mask |= EFLG_IF; | |
1642 | break; | |
1643 | case X86EMUL_MODE_VM86: | |
1644 | if (iopl < 3) { | |
54b8486f | 1645 | emulate_gp(ctxt, 0); |
d4c6a154 GN |
1646 | return X86EMUL_PROPAGATE_FAULT; |
1647 | } | |
1648 | change_mask |= EFLG_IF; | |
1649 | break; | |
1650 | default: /* real mode */ | |
1651 | change_mask |= (EFLG_IOPL | EFLG_IF); | |
1652 | break; | |
1653 | } | |
1654 | ||
1655 | *(unsigned long *)dest = | |
1656 | (ctxt->eflags & ~change_mask) | (val & change_mask); | |
1657 | ||
1658 | return rc; | |
1659 | } | |
1660 | ||
79168fd1 GN |
1661 | static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt, |
1662 | struct x86_emulate_ops *ops, int seg) | |
0934ac9d MG |
1663 | { |
1664 | struct decode_cache *c = &ctxt->decode; | |
0934ac9d | 1665 | |
79168fd1 | 1666 | c->src.val = ops->get_segment_selector(seg, ctxt->vcpu); |
0934ac9d | 1667 | |
79168fd1 | 1668 | emulate_push(ctxt, ops); |
0934ac9d MG |
1669 | } |
1670 | ||
1671 | static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt, | |
1672 | struct x86_emulate_ops *ops, int seg) | |
1673 | { | |
1674 | struct decode_cache *c = &ctxt->decode; | |
1675 | unsigned long selector; | |
1676 | int rc; | |
1677 | ||
1678 | rc = emulate_pop(ctxt, ops, &selector, c->op_bytes); | |
1b30eaa8 | 1679 | if (rc != X86EMUL_CONTINUE) |
0934ac9d MG |
1680 | return rc; |
1681 | ||
2e873022 | 1682 | rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg); |
0934ac9d MG |
1683 | return rc; |
1684 | } | |
1685 | ||
c37eda13 | 1686 | static int emulate_pusha(struct x86_emulate_ctxt *ctxt, |
79168fd1 | 1687 | struct x86_emulate_ops *ops) |
abcf14b5 MG |
1688 | { |
1689 | struct decode_cache *c = &ctxt->decode; | |
1690 | unsigned long old_esp = c->regs[VCPU_REGS_RSP]; | |
c37eda13 | 1691 | int rc = X86EMUL_CONTINUE; |
abcf14b5 MG |
1692 | int reg = VCPU_REGS_RAX; |
1693 | ||
1694 | while (reg <= VCPU_REGS_RDI) { | |
1695 | (reg == VCPU_REGS_RSP) ? | |
1696 | (c->src.val = old_esp) : (c->src.val = c->regs[reg]); | |
1697 | ||
79168fd1 | 1698 | emulate_push(ctxt, ops); |
c37eda13 WY |
1699 | |
1700 | rc = writeback(ctxt, ops); | |
1701 | if (rc != X86EMUL_CONTINUE) | |
1702 | return rc; | |
1703 | ||
abcf14b5 MG |
1704 | ++reg; |
1705 | } | |
c37eda13 WY |
1706 | |
1707 | /* Disable writeback. */ | |
1708 | c->dst.type = OP_NONE; | |
1709 | ||
1710 | return rc; | |
abcf14b5 MG |
1711 | } |
1712 | ||
1713 | static int emulate_popa(struct x86_emulate_ctxt *ctxt, | |
1714 | struct x86_emulate_ops *ops) | |
1715 | { | |
1716 | struct decode_cache *c = &ctxt->decode; | |
1b30eaa8 | 1717 | int rc = X86EMUL_CONTINUE; |
abcf14b5 MG |
1718 | int reg = VCPU_REGS_RDI; |
1719 | ||
1720 | while (reg >= VCPU_REGS_RAX) { | |
1721 | if (reg == VCPU_REGS_RSP) { | |
1722 | register_address_increment(c, &c->regs[VCPU_REGS_RSP], | |
1723 | c->op_bytes); | |
1724 | --reg; | |
1725 | } | |
1726 | ||
1727 | rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes); | |
1b30eaa8 | 1728 | if (rc != X86EMUL_CONTINUE) |
abcf14b5 MG |
1729 | break; |
1730 | --reg; | |
1731 | } | |
1732 | return rc; | |
1733 | } | |
1734 | ||
62bd430e MG |
1735 | static int emulate_iret_real(struct x86_emulate_ctxt *ctxt, |
1736 | struct x86_emulate_ops *ops) | |
1737 | { | |
1738 | struct decode_cache *c = &ctxt->decode; | |
1739 | int rc = X86EMUL_CONTINUE; | |
1740 | unsigned long temp_eip = 0; | |
1741 | unsigned long temp_eflags = 0; | |
1742 | unsigned long cs = 0; | |
1743 | unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF | | |
1744 | EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF | | |
1745 | EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */ | |
1746 | unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP; | |
1747 | ||
1748 | /* TODO: Add stack limit check */ | |
1749 | ||
1750 | rc = emulate_pop(ctxt, ops, &temp_eip, c->op_bytes); | |
1751 | ||
1752 | if (rc != X86EMUL_CONTINUE) | |
1753 | return rc; | |
1754 | ||
1755 | if (temp_eip & ~0xffff) { | |
1756 | emulate_gp(ctxt, 0); | |
1757 | return X86EMUL_PROPAGATE_FAULT; | |
1758 | } | |
1759 | ||
1760 | rc = emulate_pop(ctxt, ops, &cs, c->op_bytes); | |
1761 | ||
1762 | if (rc != X86EMUL_CONTINUE) | |
1763 | return rc; | |
1764 | ||
1765 | rc = emulate_pop(ctxt, ops, &temp_eflags, c->op_bytes); | |
1766 | ||
1767 | if (rc != X86EMUL_CONTINUE) | |
1768 | return rc; | |
1769 | ||
1770 | rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS); | |
1771 | ||
1772 | if (rc != X86EMUL_CONTINUE) | |
1773 | return rc; | |
1774 | ||
1775 | c->eip = temp_eip; | |
1776 | ||
1777 | ||
1778 | if (c->op_bytes == 4) | |
1779 | ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask)); | |
1780 | else if (c->op_bytes == 2) { | |
1781 | ctxt->eflags &= ~0xffff; | |
1782 | ctxt->eflags |= temp_eflags; | |
1783 | } | |
1784 | ||
1785 | ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */ | |
1786 | ctxt->eflags |= EFLG_RESERVED_ONE_MASK; | |
1787 | ||
1788 | return rc; | |
1789 | } | |
1790 | ||
1791 | static inline int emulate_iret(struct x86_emulate_ctxt *ctxt, | |
1792 | struct x86_emulate_ops* ops) | |
1793 | { | |
1794 | switch(ctxt->mode) { | |
1795 | case X86EMUL_MODE_REAL: | |
1796 | return emulate_iret_real(ctxt, ops); | |
1797 | case X86EMUL_MODE_VM86: | |
1798 | case X86EMUL_MODE_PROT16: | |
1799 | case X86EMUL_MODE_PROT32: | |
1800 | case X86EMUL_MODE_PROT64: | |
1801 | default: | |
1802 | /* iret from protected mode unimplemented yet */ | |
1803 | return X86EMUL_UNHANDLEABLE; | |
1804 | } | |
1805 | } | |
1806 | ||
faa5a3ae AK |
1807 | static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt, |
1808 | struct x86_emulate_ops *ops) | |
1809 | { | |
1810 | struct decode_cache *c = &ctxt->decode; | |
faa5a3ae | 1811 | |
1b30eaa8 | 1812 | return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes); |
8cdbd2c9 LV |
1813 | } |
1814 | ||
05f086f8 | 1815 | static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt) |
8cdbd2c9 | 1816 | { |
05f086f8 | 1817 | struct decode_cache *c = &ctxt->decode; |
8cdbd2c9 LV |
1818 | switch (c->modrm_reg) { |
1819 | case 0: /* rol */ | |
05f086f8 | 1820 | emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1821 | break; |
1822 | case 1: /* ror */ | |
05f086f8 | 1823 | emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1824 | break; |
1825 | case 2: /* rcl */ | |
05f086f8 | 1826 | emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1827 | break; |
1828 | case 3: /* rcr */ | |
05f086f8 | 1829 | emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1830 | break; |
1831 | case 4: /* sal/shl */ | |
1832 | case 6: /* sal/shl */ | |
05f086f8 | 1833 | emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1834 | break; |
1835 | case 5: /* shr */ | |
05f086f8 | 1836 | emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1837 | break; |
1838 | case 7: /* sar */ | |
05f086f8 | 1839 | emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1840 | break; |
1841 | } | |
1842 | } | |
1843 | ||
1844 | static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt, | |
05f086f8 | 1845 | struct x86_emulate_ops *ops) |
8cdbd2c9 LV |
1846 | { |
1847 | struct decode_cache *c = &ctxt->decode; | |
8cdbd2c9 LV |
1848 | |
1849 | switch (c->modrm_reg) { | |
1850 | case 0 ... 1: /* test */ | |
05f086f8 | 1851 | emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1852 | break; |
1853 | case 2: /* not */ | |
1854 | c->dst.val = ~c->dst.val; | |
1855 | break; | |
1856 | case 3: /* neg */ | |
05f086f8 | 1857 | emulate_1op("neg", c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1858 | break; |
1859 | default: | |
aca06a83 | 1860 | return 0; |
8cdbd2c9 | 1861 | } |
aca06a83 | 1862 | return 1; |
8cdbd2c9 LV |
1863 | } |
1864 | ||
1865 | static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt, | |
a01af5ec | 1866 | struct x86_emulate_ops *ops) |
8cdbd2c9 LV |
1867 | { |
1868 | struct decode_cache *c = &ctxt->decode; | |
8cdbd2c9 LV |
1869 | |
1870 | switch (c->modrm_reg) { | |
1871 | case 0: /* inc */ | |
05f086f8 | 1872 | emulate_1op("inc", c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1873 | break; |
1874 | case 1: /* dec */ | |
05f086f8 | 1875 | emulate_1op("dec", c->dst, ctxt->eflags); |
8cdbd2c9 | 1876 | break; |
d19292e4 MG |
1877 | case 2: /* call near abs */ { |
1878 | long int old_eip; | |
1879 | old_eip = c->eip; | |
1880 | c->eip = c->src.val; | |
1881 | c->src.val = old_eip; | |
79168fd1 | 1882 | emulate_push(ctxt, ops); |
d19292e4 MG |
1883 | break; |
1884 | } | |
8cdbd2c9 | 1885 | case 4: /* jmp abs */ |
fd60754e | 1886 | c->eip = c->src.val; |
8cdbd2c9 LV |
1887 | break; |
1888 | case 6: /* push */ | |
79168fd1 | 1889 | emulate_push(ctxt, ops); |
8cdbd2c9 | 1890 | break; |
8cdbd2c9 | 1891 | } |
1b30eaa8 | 1892 | return X86EMUL_CONTINUE; |
8cdbd2c9 LV |
1893 | } |
1894 | ||
1895 | static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt, | |
69f55cb1 | 1896 | struct x86_emulate_ops *ops) |
8cdbd2c9 LV |
1897 | { |
1898 | struct decode_cache *c = &ctxt->decode; | |
16518d5a | 1899 | u64 old = c->dst.orig_val64; |
8cdbd2c9 LV |
1900 | |
1901 | if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) || | |
1902 | ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) { | |
8cdbd2c9 LV |
1903 | c->regs[VCPU_REGS_RAX] = (u32) (old >> 0); |
1904 | c->regs[VCPU_REGS_RDX] = (u32) (old >> 32); | |
05f086f8 | 1905 | ctxt->eflags &= ~EFLG_ZF; |
8cdbd2c9 | 1906 | } else { |
16518d5a AK |
1907 | c->dst.val64 = ((u64)c->regs[VCPU_REGS_RCX] << 32) | |
1908 | (u32) c->regs[VCPU_REGS_RBX]; | |
8cdbd2c9 | 1909 | |
05f086f8 | 1910 | ctxt->eflags |= EFLG_ZF; |
8cdbd2c9 | 1911 | } |
1b30eaa8 | 1912 | return X86EMUL_CONTINUE; |
8cdbd2c9 LV |
1913 | } |
1914 | ||
a77ab5ea AK |
1915 | static int emulate_ret_far(struct x86_emulate_ctxt *ctxt, |
1916 | struct x86_emulate_ops *ops) | |
1917 | { | |
1918 | struct decode_cache *c = &ctxt->decode; | |
1919 | int rc; | |
1920 | unsigned long cs; | |
1921 | ||
1922 | rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes); | |
1b30eaa8 | 1923 | if (rc != X86EMUL_CONTINUE) |
a77ab5ea AK |
1924 | return rc; |
1925 | if (c->op_bytes == 4) | |
1926 | c->eip = (u32)c->eip; | |
1927 | rc = emulate_pop(ctxt, ops, &cs, c->op_bytes); | |
1b30eaa8 | 1928 | if (rc != X86EMUL_CONTINUE) |
a77ab5ea | 1929 | return rc; |
2e873022 | 1930 | rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS); |
a77ab5ea AK |
1931 | return rc; |
1932 | } | |
1933 | ||
e66bb2cc AP |
1934 | static inline void |
1935 | setup_syscalls_segments(struct x86_emulate_ctxt *ctxt, | |
79168fd1 GN |
1936 | struct x86_emulate_ops *ops, struct desc_struct *cs, |
1937 | struct desc_struct *ss) | |
e66bb2cc | 1938 | { |
79168fd1 GN |
1939 | memset(cs, 0, sizeof(struct desc_struct)); |
1940 | ops->get_cached_descriptor(cs, VCPU_SREG_CS, ctxt->vcpu); | |
1941 | memset(ss, 0, sizeof(struct desc_struct)); | |
e66bb2cc AP |
1942 | |
1943 | cs->l = 0; /* will be adjusted later */ | |
79168fd1 | 1944 | set_desc_base(cs, 0); /* flat segment */ |
e66bb2cc | 1945 | cs->g = 1; /* 4kb granularity */ |
79168fd1 | 1946 | set_desc_limit(cs, 0xfffff); /* 4GB limit */ |
e66bb2cc AP |
1947 | cs->type = 0x0b; /* Read, Execute, Accessed */ |
1948 | cs->s = 1; | |
1949 | cs->dpl = 0; /* will be adjusted later */ | |
79168fd1 GN |
1950 | cs->p = 1; |
1951 | cs->d = 1; | |
e66bb2cc | 1952 | |
79168fd1 GN |
1953 | set_desc_base(ss, 0); /* flat segment */ |
1954 | set_desc_limit(ss, 0xfffff); /* 4GB limit */ | |
e66bb2cc AP |
1955 | ss->g = 1; /* 4kb granularity */ |
1956 | ss->s = 1; | |
1957 | ss->type = 0x03; /* Read/Write, Accessed */ | |
79168fd1 | 1958 | ss->d = 1; /* 32bit stack segment */ |
e66bb2cc | 1959 | ss->dpl = 0; |
79168fd1 | 1960 | ss->p = 1; |
e66bb2cc AP |
1961 | } |
1962 | ||
1963 | static int | |
3fb1b5db | 1964 | emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) |
e66bb2cc AP |
1965 | { |
1966 | struct decode_cache *c = &ctxt->decode; | |
79168fd1 | 1967 | struct desc_struct cs, ss; |
e66bb2cc | 1968 | u64 msr_data; |
79168fd1 | 1969 | u16 cs_sel, ss_sel; |
e66bb2cc AP |
1970 | |
1971 | /* syscall is not available in real mode */ | |
2e901c4c GN |
1972 | if (ctxt->mode == X86EMUL_MODE_REAL || |
1973 | ctxt->mode == X86EMUL_MODE_VM86) { | |
54b8486f | 1974 | emulate_ud(ctxt); |
2e901c4c GN |
1975 | return X86EMUL_PROPAGATE_FAULT; |
1976 | } | |
e66bb2cc | 1977 | |
79168fd1 | 1978 | setup_syscalls_segments(ctxt, ops, &cs, &ss); |
e66bb2cc | 1979 | |
3fb1b5db | 1980 | ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data); |
e66bb2cc | 1981 | msr_data >>= 32; |
79168fd1 GN |
1982 | cs_sel = (u16)(msr_data & 0xfffc); |
1983 | ss_sel = (u16)(msr_data + 8); | |
e66bb2cc AP |
1984 | |
1985 | if (is_long_mode(ctxt->vcpu)) { | |
79168fd1 | 1986 | cs.d = 0; |
e66bb2cc AP |
1987 | cs.l = 1; |
1988 | } | |
79168fd1 GN |
1989 | ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu); |
1990 | ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu); | |
1991 | ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu); | |
1992 | ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu); | |
e66bb2cc AP |
1993 | |
1994 | c->regs[VCPU_REGS_RCX] = c->eip; | |
1995 | if (is_long_mode(ctxt->vcpu)) { | |
1996 | #ifdef CONFIG_X86_64 | |
1997 | c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF; | |
1998 | ||
3fb1b5db GN |
1999 | ops->get_msr(ctxt->vcpu, |
2000 | ctxt->mode == X86EMUL_MODE_PROT64 ? | |
2001 | MSR_LSTAR : MSR_CSTAR, &msr_data); | |
e66bb2cc AP |
2002 | c->eip = msr_data; |
2003 | ||
3fb1b5db | 2004 | ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data); |
e66bb2cc AP |
2005 | ctxt->eflags &= ~(msr_data | EFLG_RF); |
2006 | #endif | |
2007 | } else { | |
2008 | /* legacy mode */ | |
3fb1b5db | 2009 | ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data); |
e66bb2cc AP |
2010 | c->eip = (u32)msr_data; |
2011 | ||
2012 | ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF); | |
2013 | } | |
2014 | ||
e54cfa97 | 2015 | return X86EMUL_CONTINUE; |
e66bb2cc AP |
2016 | } |
2017 | ||
8c604352 | 2018 | static int |
3fb1b5db | 2019 | emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) |
8c604352 AP |
2020 | { |
2021 | struct decode_cache *c = &ctxt->decode; | |
79168fd1 | 2022 | struct desc_struct cs, ss; |
8c604352 | 2023 | u64 msr_data; |
79168fd1 | 2024 | u16 cs_sel, ss_sel; |
8c604352 | 2025 | |
a0044755 GN |
2026 | /* inject #GP if in real mode */ |
2027 | if (ctxt->mode == X86EMUL_MODE_REAL) { | |
54b8486f | 2028 | emulate_gp(ctxt, 0); |
2e901c4c | 2029 | return X86EMUL_PROPAGATE_FAULT; |
8c604352 AP |
2030 | } |
2031 | ||
2032 | /* XXX sysenter/sysexit have not been tested in 64bit mode. | |
2033 | * Therefore, we inject an #UD. | |
2034 | */ | |
2e901c4c | 2035 | if (ctxt->mode == X86EMUL_MODE_PROT64) { |
54b8486f | 2036 | emulate_ud(ctxt); |
2e901c4c GN |
2037 | return X86EMUL_PROPAGATE_FAULT; |
2038 | } | |
8c604352 | 2039 | |
79168fd1 | 2040 | setup_syscalls_segments(ctxt, ops, &cs, &ss); |
8c604352 | 2041 | |
3fb1b5db | 2042 | ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data); |
8c604352 AP |
2043 | switch (ctxt->mode) { |
2044 | case X86EMUL_MODE_PROT32: | |
2045 | if ((msr_data & 0xfffc) == 0x0) { | |
54b8486f | 2046 | emulate_gp(ctxt, 0); |
e54cfa97 | 2047 | return X86EMUL_PROPAGATE_FAULT; |
8c604352 AP |
2048 | } |
2049 | break; | |
2050 | case X86EMUL_MODE_PROT64: | |
2051 | if (msr_data == 0x0) { | |
54b8486f | 2052 | emulate_gp(ctxt, 0); |
e54cfa97 | 2053 | return X86EMUL_PROPAGATE_FAULT; |
8c604352 AP |
2054 | } |
2055 | break; | |
2056 | } | |
2057 | ||
2058 | ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF); | |
79168fd1 GN |
2059 | cs_sel = (u16)msr_data; |
2060 | cs_sel &= ~SELECTOR_RPL_MASK; | |
2061 | ss_sel = cs_sel + 8; | |
2062 | ss_sel &= ~SELECTOR_RPL_MASK; | |
8c604352 AP |
2063 | if (ctxt->mode == X86EMUL_MODE_PROT64 |
2064 | || is_long_mode(ctxt->vcpu)) { | |
79168fd1 | 2065 | cs.d = 0; |
8c604352 AP |
2066 | cs.l = 1; |
2067 | } | |
2068 | ||
79168fd1 GN |
2069 | ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu); |
2070 | ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu); | |
2071 | ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu); | |
2072 | ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu); | |
8c604352 | 2073 | |
3fb1b5db | 2074 | ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data); |
8c604352 AP |
2075 | c->eip = msr_data; |
2076 | ||
3fb1b5db | 2077 | ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data); |
8c604352 AP |
2078 | c->regs[VCPU_REGS_RSP] = msr_data; |
2079 | ||
e54cfa97 | 2080 | return X86EMUL_CONTINUE; |
8c604352 AP |
2081 | } |
2082 | ||
4668f050 | 2083 | static int |
3fb1b5db | 2084 | emulate_sysexit(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) |
4668f050 AP |
2085 | { |
2086 | struct decode_cache *c = &ctxt->decode; | |
79168fd1 | 2087 | struct desc_struct cs, ss; |
4668f050 AP |
2088 | u64 msr_data; |
2089 | int usermode; | |
79168fd1 | 2090 | u16 cs_sel, ss_sel; |
4668f050 | 2091 | |
a0044755 GN |
2092 | /* inject #GP if in real mode or Virtual 8086 mode */ |
2093 | if (ctxt->mode == X86EMUL_MODE_REAL || | |
2094 | ctxt->mode == X86EMUL_MODE_VM86) { | |
54b8486f | 2095 | emulate_gp(ctxt, 0); |
2e901c4c | 2096 | return X86EMUL_PROPAGATE_FAULT; |
4668f050 AP |
2097 | } |
2098 | ||
79168fd1 | 2099 | setup_syscalls_segments(ctxt, ops, &cs, &ss); |
4668f050 AP |
2100 | |
2101 | if ((c->rex_prefix & 0x8) != 0x0) | |
2102 | usermode = X86EMUL_MODE_PROT64; | |
2103 | else | |
2104 | usermode = X86EMUL_MODE_PROT32; | |
2105 | ||
2106 | cs.dpl = 3; | |
2107 | ss.dpl = 3; | |
3fb1b5db | 2108 | ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data); |
4668f050 AP |
2109 | switch (usermode) { |
2110 | case X86EMUL_MODE_PROT32: | |
79168fd1 | 2111 | cs_sel = (u16)(msr_data + 16); |
4668f050 | 2112 | if ((msr_data & 0xfffc) == 0x0) { |
54b8486f | 2113 | emulate_gp(ctxt, 0); |
e54cfa97 | 2114 | return X86EMUL_PROPAGATE_FAULT; |
4668f050 | 2115 | } |
79168fd1 | 2116 | ss_sel = (u16)(msr_data + 24); |
4668f050 AP |
2117 | break; |
2118 | case X86EMUL_MODE_PROT64: | |
79168fd1 | 2119 | cs_sel = (u16)(msr_data + 32); |
4668f050 | 2120 | if (msr_data == 0x0) { |
54b8486f | 2121 | emulate_gp(ctxt, 0); |
e54cfa97 | 2122 | return X86EMUL_PROPAGATE_FAULT; |
4668f050 | 2123 | } |
79168fd1 GN |
2124 | ss_sel = cs_sel + 8; |
2125 | cs.d = 0; | |
4668f050 AP |
2126 | cs.l = 1; |
2127 | break; | |
2128 | } | |
79168fd1 GN |
2129 | cs_sel |= SELECTOR_RPL_MASK; |
2130 | ss_sel |= SELECTOR_RPL_MASK; | |
4668f050 | 2131 | |
79168fd1 GN |
2132 | ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu); |
2133 | ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu); | |
2134 | ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu); | |
2135 | ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu); | |
4668f050 | 2136 | |
bdb475a3 GN |
2137 | c->eip = c->regs[VCPU_REGS_RDX]; |
2138 | c->regs[VCPU_REGS_RSP] = c->regs[VCPU_REGS_RCX]; | |
4668f050 | 2139 | |
e54cfa97 | 2140 | return X86EMUL_CONTINUE; |
4668f050 AP |
2141 | } |
2142 | ||
9c537244 GN |
2143 | static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt, |
2144 | struct x86_emulate_ops *ops) | |
f850e2e6 GN |
2145 | { |
2146 | int iopl; | |
2147 | if (ctxt->mode == X86EMUL_MODE_REAL) | |
2148 | return false; | |
2149 | if (ctxt->mode == X86EMUL_MODE_VM86) | |
2150 | return true; | |
2151 | iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; | |
9c537244 | 2152 | return ops->cpl(ctxt->vcpu) > iopl; |
f850e2e6 GN |
2153 | } |
2154 | ||
2155 | static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt, | |
2156 | struct x86_emulate_ops *ops, | |
2157 | u16 port, u16 len) | |
2158 | { | |
79168fd1 | 2159 | struct desc_struct tr_seg; |
f850e2e6 GN |
2160 | int r; |
2161 | u16 io_bitmap_ptr; | |
2162 | u8 perm, bit_idx = port & 0x7; | |
2163 | unsigned mask = (1 << len) - 1; | |
2164 | ||
79168fd1 GN |
2165 | ops->get_cached_descriptor(&tr_seg, VCPU_SREG_TR, ctxt->vcpu); |
2166 | if (!tr_seg.p) | |
f850e2e6 | 2167 | return false; |
79168fd1 | 2168 | if (desc_limit_scaled(&tr_seg) < 103) |
f850e2e6 | 2169 | return false; |
79168fd1 GN |
2170 | r = ops->read_std(get_desc_base(&tr_seg) + 102, &io_bitmap_ptr, 2, |
2171 | ctxt->vcpu, NULL); | |
f850e2e6 GN |
2172 | if (r != X86EMUL_CONTINUE) |
2173 | return false; | |
79168fd1 | 2174 | if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg)) |
f850e2e6 | 2175 | return false; |
79168fd1 GN |
2176 | r = ops->read_std(get_desc_base(&tr_seg) + io_bitmap_ptr + port/8, |
2177 | &perm, 1, ctxt->vcpu, NULL); | |
f850e2e6 GN |
2178 | if (r != X86EMUL_CONTINUE) |
2179 | return false; | |
2180 | if ((perm >> bit_idx) & mask) | |
2181 | return false; | |
2182 | return true; | |
2183 | } | |
2184 | ||
2185 | static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt, | |
2186 | struct x86_emulate_ops *ops, | |
2187 | u16 port, u16 len) | |
2188 | { | |
9c537244 | 2189 | if (emulator_bad_iopl(ctxt, ops)) |
f850e2e6 GN |
2190 | if (!emulator_io_port_access_allowed(ctxt, ops, port, len)) |
2191 | return false; | |
2192 | return true; | |
2193 | } | |
2194 | ||
38ba30ba GN |
2195 | static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt, |
2196 | struct x86_emulate_ops *ops, | |
2197 | struct tss_segment_16 *tss) | |
2198 | { | |
2199 | struct decode_cache *c = &ctxt->decode; | |
2200 | ||
2201 | tss->ip = c->eip; | |
2202 | tss->flag = ctxt->eflags; | |
2203 | tss->ax = c->regs[VCPU_REGS_RAX]; | |
2204 | tss->cx = c->regs[VCPU_REGS_RCX]; | |
2205 | tss->dx = c->regs[VCPU_REGS_RDX]; | |
2206 | tss->bx = c->regs[VCPU_REGS_RBX]; | |
2207 | tss->sp = c->regs[VCPU_REGS_RSP]; | |
2208 | tss->bp = c->regs[VCPU_REGS_RBP]; | |
2209 | tss->si = c->regs[VCPU_REGS_RSI]; | |
2210 | tss->di = c->regs[VCPU_REGS_RDI]; | |
2211 | ||
2212 | tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu); | |
2213 | tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu); | |
2214 | tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu); | |
2215 | tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu); | |
2216 | tss->ldt = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu); | |
2217 | } | |
2218 | ||
2219 | static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt, | |
2220 | struct x86_emulate_ops *ops, | |
2221 | struct tss_segment_16 *tss) | |
2222 | { | |
2223 | struct decode_cache *c = &ctxt->decode; | |
2224 | int ret; | |
2225 | ||
2226 | c->eip = tss->ip; | |
2227 | ctxt->eflags = tss->flag | 2; | |
2228 | c->regs[VCPU_REGS_RAX] = tss->ax; | |
2229 | c->regs[VCPU_REGS_RCX] = tss->cx; | |
2230 | c->regs[VCPU_REGS_RDX] = tss->dx; | |
2231 | c->regs[VCPU_REGS_RBX] = tss->bx; | |
2232 | c->regs[VCPU_REGS_RSP] = tss->sp; | |
2233 | c->regs[VCPU_REGS_RBP] = tss->bp; | |
2234 | c->regs[VCPU_REGS_RSI] = tss->si; | |
2235 | c->regs[VCPU_REGS_RDI] = tss->di; | |
2236 | ||
2237 | /* | |
2238 | * SDM says that segment selectors are loaded before segment | |
2239 | * descriptors | |
2240 | */ | |
2241 | ops->set_segment_selector(tss->ldt, VCPU_SREG_LDTR, ctxt->vcpu); | |
2242 | ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu); | |
2243 | ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu); | |
2244 | ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu); | |
2245 | ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu); | |
2246 | ||
2247 | /* | |
2248 | * Now load segment descriptors. If fault happenes at this stage | |
2249 | * it is handled in a context of new task | |
2250 | */ | |
2251 | ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR); | |
2252 | if (ret != X86EMUL_CONTINUE) | |
2253 | return ret; | |
2254 | ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES); | |
2255 | if (ret != X86EMUL_CONTINUE) | |
2256 | return ret; | |
2257 | ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS); | |
2258 | if (ret != X86EMUL_CONTINUE) | |
2259 | return ret; | |
2260 | ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS); | |
2261 | if (ret != X86EMUL_CONTINUE) | |
2262 | return ret; | |
2263 | ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS); | |
2264 | if (ret != X86EMUL_CONTINUE) | |
2265 | return ret; | |
2266 | ||
2267 | return X86EMUL_CONTINUE; | |
2268 | } | |
2269 | ||
2270 | static int task_switch_16(struct x86_emulate_ctxt *ctxt, | |
2271 | struct x86_emulate_ops *ops, | |
2272 | u16 tss_selector, u16 old_tss_sel, | |
2273 | ulong old_tss_base, struct desc_struct *new_desc) | |
2274 | { | |
2275 | struct tss_segment_16 tss_seg; | |
2276 | int ret; | |
2277 | u32 err, new_tss_base = get_desc_base(new_desc); | |
2278 | ||
2279 | ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
2280 | &err); | |
2281 | if (ret == X86EMUL_PROPAGATE_FAULT) { | |
2282 | /* FIXME: need to provide precise fault address */ | |
54b8486f | 2283 | emulate_pf(ctxt, old_tss_base, err); |
38ba30ba GN |
2284 | return ret; |
2285 | } | |
2286 | ||
2287 | save_state_to_tss16(ctxt, ops, &tss_seg); | |
2288 | ||
2289 | ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
2290 | &err); | |
2291 | if (ret == X86EMUL_PROPAGATE_FAULT) { | |
2292 | /* FIXME: need to provide precise fault address */ | |
54b8486f | 2293 | emulate_pf(ctxt, old_tss_base, err); |
38ba30ba GN |
2294 | return ret; |
2295 | } | |
2296 | ||
2297 | ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
2298 | &err); | |
2299 | if (ret == X86EMUL_PROPAGATE_FAULT) { | |
2300 | /* FIXME: need to provide precise fault address */ | |
54b8486f | 2301 | emulate_pf(ctxt, new_tss_base, err); |
38ba30ba GN |
2302 | return ret; |
2303 | } | |
2304 | ||
2305 | if (old_tss_sel != 0xffff) { | |
2306 | tss_seg.prev_task_link = old_tss_sel; | |
2307 | ||
2308 | ret = ops->write_std(new_tss_base, | |
2309 | &tss_seg.prev_task_link, | |
2310 | sizeof tss_seg.prev_task_link, | |
2311 | ctxt->vcpu, &err); | |
2312 | if (ret == X86EMUL_PROPAGATE_FAULT) { | |
2313 | /* FIXME: need to provide precise fault address */ | |
54b8486f | 2314 | emulate_pf(ctxt, new_tss_base, err); |
38ba30ba GN |
2315 | return ret; |
2316 | } | |
2317 | } | |
2318 | ||
2319 | return load_state_from_tss16(ctxt, ops, &tss_seg); | |
2320 | } | |
2321 | ||
2322 | static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt, | |
2323 | struct x86_emulate_ops *ops, | |
2324 | struct tss_segment_32 *tss) | |
2325 | { | |
2326 | struct decode_cache *c = &ctxt->decode; | |
2327 | ||
2328 | tss->cr3 = ops->get_cr(3, ctxt->vcpu); | |
2329 | tss->eip = c->eip; | |
2330 | tss->eflags = ctxt->eflags; | |
2331 | tss->eax = c->regs[VCPU_REGS_RAX]; | |
2332 | tss->ecx = c->regs[VCPU_REGS_RCX]; | |
2333 | tss->edx = c->regs[VCPU_REGS_RDX]; | |
2334 | tss->ebx = c->regs[VCPU_REGS_RBX]; | |
2335 | tss->esp = c->regs[VCPU_REGS_RSP]; | |
2336 | tss->ebp = c->regs[VCPU_REGS_RBP]; | |
2337 | tss->esi = c->regs[VCPU_REGS_RSI]; | |
2338 | tss->edi = c->regs[VCPU_REGS_RDI]; | |
2339 | ||
2340 | tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu); | |
2341 | tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu); | |
2342 | tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu); | |
2343 | tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu); | |
2344 | tss->fs = ops->get_segment_selector(VCPU_SREG_FS, ctxt->vcpu); | |
2345 | tss->gs = ops->get_segment_selector(VCPU_SREG_GS, ctxt->vcpu); | |
2346 | tss->ldt_selector = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu); | |
2347 | } | |
2348 | ||
2349 | static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt, | |
2350 | struct x86_emulate_ops *ops, | |
2351 | struct tss_segment_32 *tss) | |
2352 | { | |
2353 | struct decode_cache *c = &ctxt->decode; | |
2354 | int ret; | |
2355 | ||
0f12244f | 2356 | if (ops->set_cr(3, tss->cr3, ctxt->vcpu)) { |
54b8486f | 2357 | emulate_gp(ctxt, 0); |
0f12244f GN |
2358 | return X86EMUL_PROPAGATE_FAULT; |
2359 | } | |
38ba30ba GN |
2360 | c->eip = tss->eip; |
2361 | ctxt->eflags = tss->eflags | 2; | |
2362 | c->regs[VCPU_REGS_RAX] = tss->eax; | |
2363 | c->regs[VCPU_REGS_RCX] = tss->ecx; | |
2364 | c->regs[VCPU_REGS_RDX] = tss->edx; | |
2365 | c->regs[VCPU_REGS_RBX] = tss->ebx; | |
2366 | c->regs[VCPU_REGS_RSP] = tss->esp; | |
2367 | c->regs[VCPU_REGS_RBP] = tss->ebp; | |
2368 | c->regs[VCPU_REGS_RSI] = tss->esi; | |
2369 | c->regs[VCPU_REGS_RDI] = tss->edi; | |
2370 | ||
2371 | /* | |
2372 | * SDM says that segment selectors are loaded before segment | |
2373 | * descriptors | |
2374 | */ | |
2375 | ops->set_segment_selector(tss->ldt_selector, VCPU_SREG_LDTR, ctxt->vcpu); | |
2376 | ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu); | |
2377 | ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu); | |
2378 | ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu); | |
2379 | ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu); | |
2380 | ops->set_segment_selector(tss->fs, VCPU_SREG_FS, ctxt->vcpu); | |
2381 | ops->set_segment_selector(tss->gs, VCPU_SREG_GS, ctxt->vcpu); | |
2382 | ||
2383 | /* | |
2384 | * Now load segment descriptors. If fault happenes at this stage | |
2385 | * it is handled in a context of new task | |
2386 | */ | |
2387 | ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR); | |
2388 | if (ret != X86EMUL_CONTINUE) | |
2389 | return ret; | |
2390 | ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES); | |
2391 | if (ret != X86EMUL_CONTINUE) | |
2392 | return ret; | |
2393 | ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS); | |
2394 | if (ret != X86EMUL_CONTINUE) | |
2395 | return ret; | |
2396 | ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS); | |
2397 | if (ret != X86EMUL_CONTINUE) | |
2398 | return ret; | |
2399 | ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS); | |
2400 | if (ret != X86EMUL_CONTINUE) | |
2401 | return ret; | |
2402 | ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS); | |
2403 | if (ret != X86EMUL_CONTINUE) | |
2404 | return ret; | |
2405 | ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS); | |
2406 | if (ret != X86EMUL_CONTINUE) | |
2407 | return ret; | |
2408 | ||
2409 | return X86EMUL_CONTINUE; | |
2410 | } | |
2411 | ||
2412 | static int task_switch_32(struct x86_emulate_ctxt *ctxt, | |
2413 | struct x86_emulate_ops *ops, | |
2414 | u16 tss_selector, u16 old_tss_sel, | |
2415 | ulong old_tss_base, struct desc_struct *new_desc) | |
2416 | { | |
2417 | struct tss_segment_32 tss_seg; | |
2418 | int ret; | |
2419 | u32 err, new_tss_base = get_desc_base(new_desc); | |
2420 | ||
2421 | ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
2422 | &err); | |
2423 | if (ret == X86EMUL_PROPAGATE_FAULT) { | |
2424 | /* FIXME: need to provide precise fault address */ | |
54b8486f | 2425 | emulate_pf(ctxt, old_tss_base, err); |
38ba30ba GN |
2426 | return ret; |
2427 | } | |
2428 | ||
2429 | save_state_to_tss32(ctxt, ops, &tss_seg); | |
2430 | ||
2431 | ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
2432 | &err); | |
2433 | if (ret == X86EMUL_PROPAGATE_FAULT) { | |
2434 | /* FIXME: need to provide precise fault address */ | |
54b8486f | 2435 | emulate_pf(ctxt, old_tss_base, err); |
38ba30ba GN |
2436 | return ret; |
2437 | } | |
2438 | ||
2439 | ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
2440 | &err); | |
2441 | if (ret == X86EMUL_PROPAGATE_FAULT) { | |
2442 | /* FIXME: need to provide precise fault address */ | |
54b8486f | 2443 | emulate_pf(ctxt, new_tss_base, err); |
38ba30ba GN |
2444 | return ret; |
2445 | } | |
2446 | ||
2447 | if (old_tss_sel != 0xffff) { | |
2448 | tss_seg.prev_task_link = old_tss_sel; | |
2449 | ||
2450 | ret = ops->write_std(new_tss_base, | |
2451 | &tss_seg.prev_task_link, | |
2452 | sizeof tss_seg.prev_task_link, | |
2453 | ctxt->vcpu, &err); | |
2454 | if (ret == X86EMUL_PROPAGATE_FAULT) { | |
2455 | /* FIXME: need to provide precise fault address */ | |
54b8486f | 2456 | emulate_pf(ctxt, new_tss_base, err); |
38ba30ba GN |
2457 | return ret; |
2458 | } | |
2459 | } | |
2460 | ||
2461 | return load_state_from_tss32(ctxt, ops, &tss_seg); | |
2462 | } | |
2463 | ||
2464 | static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt, | |
e269fb21 JK |
2465 | struct x86_emulate_ops *ops, |
2466 | u16 tss_selector, int reason, | |
2467 | bool has_error_code, u32 error_code) | |
38ba30ba GN |
2468 | { |
2469 | struct desc_struct curr_tss_desc, next_tss_desc; | |
2470 | int ret; | |
2471 | u16 old_tss_sel = ops->get_segment_selector(VCPU_SREG_TR, ctxt->vcpu); | |
2472 | ulong old_tss_base = | |
5951c442 | 2473 | ops->get_cached_segment_base(VCPU_SREG_TR, ctxt->vcpu); |
ceffb459 | 2474 | u32 desc_limit; |
38ba30ba GN |
2475 | |
2476 | /* FIXME: old_tss_base == ~0 ? */ | |
2477 | ||
2478 | ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc); | |
2479 | if (ret != X86EMUL_CONTINUE) | |
2480 | return ret; | |
2481 | ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc); | |
2482 | if (ret != X86EMUL_CONTINUE) | |
2483 | return ret; | |
2484 | ||
2485 | /* FIXME: check that next_tss_desc is tss */ | |
2486 | ||
2487 | if (reason != TASK_SWITCH_IRET) { | |
2488 | if ((tss_selector & 3) > next_tss_desc.dpl || | |
2489 | ops->cpl(ctxt->vcpu) > next_tss_desc.dpl) { | |
54b8486f | 2490 | emulate_gp(ctxt, 0); |
38ba30ba GN |
2491 | return X86EMUL_PROPAGATE_FAULT; |
2492 | } | |
2493 | } | |
2494 | ||
ceffb459 GN |
2495 | desc_limit = desc_limit_scaled(&next_tss_desc); |
2496 | if (!next_tss_desc.p || | |
2497 | ((desc_limit < 0x67 && (next_tss_desc.type & 8)) || | |
2498 | desc_limit < 0x2b)) { | |
54b8486f | 2499 | emulate_ts(ctxt, tss_selector & 0xfffc); |
38ba30ba GN |
2500 | return X86EMUL_PROPAGATE_FAULT; |
2501 | } | |
2502 | ||
2503 | if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) { | |
2504 | curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */ | |
2505 | write_segment_descriptor(ctxt, ops, old_tss_sel, | |
2506 | &curr_tss_desc); | |
2507 | } | |
2508 | ||
2509 | if (reason == TASK_SWITCH_IRET) | |
2510 | ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT; | |
2511 | ||
2512 | /* set back link to prev task only if NT bit is set in eflags | |
2513 | note that old_tss_sel is not used afetr this point */ | |
2514 | if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE) | |
2515 | old_tss_sel = 0xffff; | |
2516 | ||
2517 | if (next_tss_desc.type & 8) | |
2518 | ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel, | |
2519 | old_tss_base, &next_tss_desc); | |
2520 | else | |
2521 | ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel, | |
2522 | old_tss_base, &next_tss_desc); | |
0760d448 JK |
2523 | if (ret != X86EMUL_CONTINUE) |
2524 | return ret; | |
38ba30ba GN |
2525 | |
2526 | if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) | |
2527 | ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT; | |
2528 | ||
2529 | if (reason != TASK_SWITCH_IRET) { | |
2530 | next_tss_desc.type |= (1 << 1); /* set busy flag */ | |
2531 | write_segment_descriptor(ctxt, ops, tss_selector, | |
2532 | &next_tss_desc); | |
2533 | } | |
2534 | ||
2535 | ops->set_cr(0, ops->get_cr(0, ctxt->vcpu) | X86_CR0_TS, ctxt->vcpu); | |
2536 | ops->set_cached_descriptor(&next_tss_desc, VCPU_SREG_TR, ctxt->vcpu); | |
2537 | ops->set_segment_selector(tss_selector, VCPU_SREG_TR, ctxt->vcpu); | |
2538 | ||
e269fb21 JK |
2539 | if (has_error_code) { |
2540 | struct decode_cache *c = &ctxt->decode; | |
2541 | ||
2542 | c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2; | |
2543 | c->lock_prefix = 0; | |
2544 | c->src.val = (unsigned long) error_code; | |
79168fd1 | 2545 | emulate_push(ctxt, ops); |
e269fb21 JK |
2546 | } |
2547 | ||
38ba30ba GN |
2548 | return ret; |
2549 | } | |
2550 | ||
2551 | int emulator_task_switch(struct x86_emulate_ctxt *ctxt, | |
2552 | struct x86_emulate_ops *ops, | |
e269fb21 JK |
2553 | u16 tss_selector, int reason, |
2554 | bool has_error_code, u32 error_code) | |
38ba30ba GN |
2555 | { |
2556 | struct decode_cache *c = &ctxt->decode; | |
2557 | int rc; | |
2558 | ||
38ba30ba | 2559 | c->eip = ctxt->eip; |
e269fb21 | 2560 | c->dst.type = OP_NONE; |
38ba30ba | 2561 | |
e269fb21 JK |
2562 | rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason, |
2563 | has_error_code, error_code); | |
38ba30ba GN |
2564 | |
2565 | if (rc == X86EMUL_CONTINUE) { | |
e269fb21 | 2566 | rc = writeback(ctxt, ops); |
95c55886 GN |
2567 | if (rc == X86EMUL_CONTINUE) |
2568 | ctxt->eip = c->eip; | |
38ba30ba GN |
2569 | } |
2570 | ||
19d04437 | 2571 | return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0; |
38ba30ba GN |
2572 | } |
2573 | ||
a682e354 | 2574 | static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned long base, |
d9271123 | 2575 | int reg, struct operand *op) |
a682e354 GN |
2576 | { |
2577 | struct decode_cache *c = &ctxt->decode; | |
2578 | int df = (ctxt->eflags & EFLG_DF) ? -1 : 1; | |
2579 | ||
d9271123 GN |
2580 | register_address_increment(c, &c->regs[reg], df * op->bytes); |
2581 | op->ptr = (unsigned long *)register_address(c, base, c->regs[reg]); | |
a682e354 GN |
2582 | } |
2583 | ||
8b4caf66 | 2584 | int |
1be3aa47 | 2585 | x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) |
8b4caf66 | 2586 | { |
8b4caf66 | 2587 | u64 msr_data; |
8b4caf66 | 2588 | struct decode_cache *c = &ctxt->decode; |
1b30eaa8 | 2589 | int rc = X86EMUL_CONTINUE; |
5cd21917 | 2590 | int saved_dst_type = c->dst.type; |
8b4caf66 | 2591 | |
9de41573 | 2592 | ctxt->decode.mem_read.pos = 0; |
310b5d30 | 2593 | |
1161624f | 2594 | if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) { |
54b8486f | 2595 | emulate_ud(ctxt); |
1161624f GN |
2596 | goto done; |
2597 | } | |
2598 | ||
d380a5e4 | 2599 | /* LOCK prefix is allowed only with some instructions */ |
a41ffb75 | 2600 | if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) { |
54b8486f | 2601 | emulate_ud(ctxt); |
d380a5e4 GN |
2602 | goto done; |
2603 | } | |
2604 | ||
e92805ac | 2605 | /* Privileged instruction can be executed only in CPL=0 */ |
9c537244 | 2606 | if ((c->d & Priv) && ops->cpl(ctxt->vcpu)) { |
54b8486f | 2607 | emulate_gp(ctxt, 0); |
e92805ac GN |
2608 | goto done; |
2609 | } | |
2610 | ||
b9fa9d6b | 2611 | if (c->rep_prefix && (c->d & String)) { |
5cd21917 | 2612 | ctxt->restart = true; |
b9fa9d6b | 2613 | /* All REP prefixes have the same first termination condition */ |
c73e197b | 2614 | if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) { |
5cd21917 GN |
2615 | string_done: |
2616 | ctxt->restart = false; | |
95c55886 | 2617 | ctxt->eip = c->eip; |
b9fa9d6b AK |
2618 | goto done; |
2619 | } | |
2620 | /* The second termination condition only applies for REPE | |
2621 | * and REPNE. Test if the repeat string operation prefix is | |
2622 | * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the | |
2623 | * corresponding termination condition according to: | |
2624 | * - if REPE/REPZ and ZF = 0 then done | |
2625 | * - if REPNE/REPNZ and ZF = 1 then done | |
2626 | */ | |
2627 | if ((c->b == 0xa6) || (c->b == 0xa7) || | |
5cd21917 | 2628 | (c->b == 0xae) || (c->b == 0xaf)) { |
b9fa9d6b | 2629 | if ((c->rep_prefix == REPE_PREFIX) && |
5cd21917 GN |
2630 | ((ctxt->eflags & EFLG_ZF) == 0)) |
2631 | goto string_done; | |
b9fa9d6b | 2632 | if ((c->rep_prefix == REPNE_PREFIX) && |
5cd21917 GN |
2633 | ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)) |
2634 | goto string_done; | |
b9fa9d6b | 2635 | } |
063db061 | 2636 | c->eip = ctxt->eip; |
b9fa9d6b AK |
2637 | } |
2638 | ||
8b4caf66 | 2639 | if (c->src.type == OP_MEM) { |
9de41573 | 2640 | rc = read_emulated(ctxt, ops, (unsigned long)c->src.ptr, |
414e6277 | 2641 | c->src.valptr, c->src.bytes); |
b60d513c | 2642 | if (rc != X86EMUL_CONTINUE) |
8b4caf66 | 2643 | goto done; |
16518d5a | 2644 | c->src.orig_val64 = c->src.val64; |
8b4caf66 LV |
2645 | } |
2646 | ||
e35b7b9c | 2647 | if (c->src2.type == OP_MEM) { |
9de41573 GN |
2648 | rc = read_emulated(ctxt, ops, (unsigned long)c->src2.ptr, |
2649 | &c->src2.val, c->src2.bytes); | |
e35b7b9c GN |
2650 | if (rc != X86EMUL_CONTINUE) |
2651 | goto done; | |
2652 | } | |
2653 | ||
8b4caf66 LV |
2654 | if ((c->d & DstMask) == ImplicitOps) |
2655 | goto special_insn; | |
2656 | ||
2657 | ||
69f55cb1 GN |
2658 | if ((c->dst.type == OP_MEM) && !(c->d & Mov)) { |
2659 | /* optimisation - avoid slow emulated read if Mov */ | |
9de41573 GN |
2660 | rc = read_emulated(ctxt, ops, (unsigned long)c->dst.ptr, |
2661 | &c->dst.val, c->dst.bytes); | |
69f55cb1 GN |
2662 | if (rc != X86EMUL_CONTINUE) |
2663 | goto done; | |
038e51de | 2664 | } |
e4e03ded | 2665 | c->dst.orig_val = c->dst.val; |
038e51de | 2666 | |
018a98db AK |
2667 | special_insn: |
2668 | ||
e4e03ded | 2669 | if (c->twobyte) |
6aa8b732 AK |
2670 | goto twobyte_insn; |
2671 | ||
e4e03ded | 2672 | switch (c->b) { |
6aa8b732 AK |
2673 | case 0x00 ... 0x05: |
2674 | add: /* add */ | |
05f086f8 | 2675 | emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 2676 | break; |
0934ac9d | 2677 | case 0x06: /* push es */ |
79168fd1 | 2678 | emulate_push_sreg(ctxt, ops, VCPU_SREG_ES); |
0934ac9d MG |
2679 | break; |
2680 | case 0x07: /* pop es */ | |
0934ac9d | 2681 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES); |
1b30eaa8 | 2682 | if (rc != X86EMUL_CONTINUE) |
0934ac9d MG |
2683 | goto done; |
2684 | break; | |
6aa8b732 AK |
2685 | case 0x08 ... 0x0d: |
2686 | or: /* or */ | |
05f086f8 | 2687 | emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 2688 | break; |
0934ac9d | 2689 | case 0x0e: /* push cs */ |
79168fd1 | 2690 | emulate_push_sreg(ctxt, ops, VCPU_SREG_CS); |
0934ac9d | 2691 | break; |
6aa8b732 AK |
2692 | case 0x10 ... 0x15: |
2693 | adc: /* adc */ | |
05f086f8 | 2694 | emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 2695 | break; |
0934ac9d | 2696 | case 0x16: /* push ss */ |
79168fd1 | 2697 | emulate_push_sreg(ctxt, ops, VCPU_SREG_SS); |
0934ac9d MG |
2698 | break; |
2699 | case 0x17: /* pop ss */ | |
0934ac9d | 2700 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS); |
1b30eaa8 | 2701 | if (rc != X86EMUL_CONTINUE) |
0934ac9d MG |
2702 | goto done; |
2703 | break; | |
6aa8b732 AK |
2704 | case 0x18 ... 0x1d: |
2705 | sbb: /* sbb */ | |
05f086f8 | 2706 | emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 2707 | break; |
0934ac9d | 2708 | case 0x1e: /* push ds */ |
79168fd1 | 2709 | emulate_push_sreg(ctxt, ops, VCPU_SREG_DS); |
0934ac9d MG |
2710 | break; |
2711 | case 0x1f: /* pop ds */ | |
0934ac9d | 2712 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS); |
1b30eaa8 | 2713 | if (rc != X86EMUL_CONTINUE) |
0934ac9d MG |
2714 | goto done; |
2715 | break; | |
aa3a816b | 2716 | case 0x20 ... 0x25: |
6aa8b732 | 2717 | and: /* and */ |
05f086f8 | 2718 | emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
2719 | break; |
2720 | case 0x28 ... 0x2d: | |
2721 | sub: /* sub */ | |
05f086f8 | 2722 | emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
2723 | break; |
2724 | case 0x30 ... 0x35: | |
2725 | xor: /* xor */ | |
05f086f8 | 2726 | emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
2727 | break; |
2728 | case 0x38 ... 0x3d: | |
2729 | cmp: /* cmp */ | |
05f086f8 | 2730 | emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 2731 | break; |
33615aa9 AK |
2732 | case 0x40 ... 0x47: /* inc r16/r32 */ |
2733 | emulate_1op("inc", c->dst, ctxt->eflags); | |
2734 | break; | |
2735 | case 0x48 ... 0x4f: /* dec r16/r32 */ | |
2736 | emulate_1op("dec", c->dst, ctxt->eflags); | |
2737 | break; | |
2738 | case 0x50 ... 0x57: /* push reg */ | |
79168fd1 | 2739 | emulate_push(ctxt, ops); |
33615aa9 AK |
2740 | break; |
2741 | case 0x58 ... 0x5f: /* pop reg */ | |
2742 | pop_instruction: | |
350f69dc | 2743 | rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes); |
1b30eaa8 | 2744 | if (rc != X86EMUL_CONTINUE) |
33615aa9 | 2745 | goto done; |
33615aa9 | 2746 | break; |
abcf14b5 | 2747 | case 0x60: /* pusha */ |
c37eda13 WY |
2748 | rc = emulate_pusha(ctxt, ops); |
2749 | if (rc != X86EMUL_CONTINUE) | |
2750 | goto done; | |
abcf14b5 MG |
2751 | break; |
2752 | case 0x61: /* popa */ | |
2753 | rc = emulate_popa(ctxt, ops); | |
1b30eaa8 | 2754 | if (rc != X86EMUL_CONTINUE) |
abcf14b5 MG |
2755 | goto done; |
2756 | break; | |
6aa8b732 | 2757 | case 0x63: /* movsxd */ |
8b4caf66 | 2758 | if (ctxt->mode != X86EMUL_MODE_PROT64) |
6aa8b732 | 2759 | goto cannot_emulate; |
e4e03ded | 2760 | c->dst.val = (s32) c->src.val; |
6aa8b732 | 2761 | break; |
91ed7a0e | 2762 | case 0x68: /* push imm */ |
018a98db | 2763 | case 0x6a: /* push imm8 */ |
79168fd1 | 2764 | emulate_push(ctxt, ops); |
018a98db AK |
2765 | break; |
2766 | case 0x6c: /* insb */ | |
2767 | case 0x6d: /* insw/insd */ | |
7972995b | 2768 | c->dst.bytes = min(c->dst.bytes, 4u); |
f850e2e6 | 2769 | if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX], |
7972995b | 2770 | c->dst.bytes)) { |
54b8486f | 2771 | emulate_gp(ctxt, 0); |
f850e2e6 GN |
2772 | goto done; |
2773 | } | |
7b262e90 GN |
2774 | if (!pio_in_emulated(ctxt, ops, c->dst.bytes, |
2775 | c->regs[VCPU_REGS_RDX], &c->dst.val)) | |
7972995b GN |
2776 | goto done; /* IO is needed, skip writeback */ |
2777 | break; | |
018a98db AK |
2778 | case 0x6e: /* outsb */ |
2779 | case 0x6f: /* outsw/outsd */ | |
7972995b | 2780 | c->src.bytes = min(c->src.bytes, 4u); |
f850e2e6 | 2781 | if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX], |
7972995b | 2782 | c->src.bytes)) { |
54b8486f | 2783 | emulate_gp(ctxt, 0); |
f850e2e6 GN |
2784 | goto done; |
2785 | } | |
7972995b GN |
2786 | ops->pio_out_emulated(c->src.bytes, c->regs[VCPU_REGS_RDX], |
2787 | &c->src.val, 1, ctxt->vcpu); | |
2788 | ||
2789 | c->dst.type = OP_NONE; /* nothing to writeback */ | |
2790 | break; | |
b2833e3c | 2791 | case 0x70 ... 0x7f: /* jcc (short) */ |
018a98db | 2792 | if (test_cc(c->b, ctxt->eflags)) |
b2833e3c | 2793 | jmp_rel(c, c->src.val); |
018a98db | 2794 | break; |
6aa8b732 | 2795 | case 0x80 ... 0x83: /* Grp1 */ |
e4e03ded | 2796 | switch (c->modrm_reg) { |
6aa8b732 AK |
2797 | case 0: |
2798 | goto add; | |
2799 | case 1: | |
2800 | goto or; | |
2801 | case 2: | |
2802 | goto adc; | |
2803 | case 3: | |
2804 | goto sbb; | |
2805 | case 4: | |
2806 | goto and; | |
2807 | case 5: | |
2808 | goto sub; | |
2809 | case 6: | |
2810 | goto xor; | |
2811 | case 7: | |
2812 | goto cmp; | |
2813 | } | |
2814 | break; | |
2815 | case 0x84 ... 0x85: | |
dfb507c4 | 2816 | test: |
05f086f8 | 2817 | emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
2818 | break; |
2819 | case 0x86 ... 0x87: /* xchg */ | |
b13354f8 | 2820 | xchg: |
6aa8b732 | 2821 | /* Write back the register source. */ |
e4e03ded | 2822 | switch (c->dst.bytes) { |
6aa8b732 | 2823 | case 1: |
e4e03ded | 2824 | *(u8 *) c->src.ptr = (u8) c->dst.val; |
6aa8b732 AK |
2825 | break; |
2826 | case 2: | |
e4e03ded | 2827 | *(u16 *) c->src.ptr = (u16) c->dst.val; |
6aa8b732 AK |
2828 | break; |
2829 | case 4: | |
e4e03ded | 2830 | *c->src.ptr = (u32) c->dst.val; |
6aa8b732 AK |
2831 | break; /* 64b reg: zero-extend */ |
2832 | case 8: | |
e4e03ded | 2833 | *c->src.ptr = c->dst.val; |
6aa8b732 AK |
2834 | break; |
2835 | } | |
2836 | /* | |
2837 | * Write back the memory destination with implicit LOCK | |
2838 | * prefix. | |
2839 | */ | |
e4e03ded LV |
2840 | c->dst.val = c->src.val; |
2841 | c->lock_prefix = 1; | |
6aa8b732 | 2842 | break; |
6aa8b732 | 2843 | case 0x88 ... 0x8b: /* mov */ |
7de75248 | 2844 | goto mov; |
79168fd1 GN |
2845 | case 0x8c: /* mov r/m, sreg */ |
2846 | if (c->modrm_reg > VCPU_SREG_GS) { | |
54b8486f | 2847 | emulate_ud(ctxt); |
5e3ae6c5 | 2848 | goto done; |
38d5bc6d | 2849 | } |
79168fd1 | 2850 | c->dst.val = ops->get_segment_selector(c->modrm_reg, ctxt->vcpu); |
38d5bc6d | 2851 | break; |
7e0b54b1 | 2852 | case 0x8d: /* lea r16/r32, m */ |
f9b7aab3 | 2853 | c->dst.val = c->modrm_ea; |
7e0b54b1 | 2854 | break; |
4257198a GT |
2855 | case 0x8e: { /* mov seg, r/m16 */ |
2856 | uint16_t sel; | |
4257198a GT |
2857 | |
2858 | sel = c->src.val; | |
8b9f4414 | 2859 | |
c697518a GN |
2860 | if (c->modrm_reg == VCPU_SREG_CS || |
2861 | c->modrm_reg > VCPU_SREG_GS) { | |
54b8486f | 2862 | emulate_ud(ctxt); |
8b9f4414 GN |
2863 | goto done; |
2864 | } | |
2865 | ||
310b5d30 | 2866 | if (c->modrm_reg == VCPU_SREG_SS) |
95cb2295 | 2867 | ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS; |
310b5d30 | 2868 | |
2e873022 | 2869 | rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg); |
4257198a GT |
2870 | |
2871 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
2872 | break; | |
2873 | } | |
6aa8b732 | 2874 | case 0x8f: /* pop (sole member of Grp1a) */ |
8cdbd2c9 | 2875 | rc = emulate_grp1a(ctxt, ops); |
1b30eaa8 | 2876 | if (rc != X86EMUL_CONTINUE) |
6aa8b732 | 2877 | goto done; |
6aa8b732 | 2878 | break; |
b13354f8 | 2879 | case 0x90: /* nop / xchg r8,rax */ |
b8a98945 GN |
2880 | if (c->dst.ptr == (unsigned long *)&c->regs[VCPU_REGS_RAX]) { |
2881 | c->dst.type = OP_NONE; /* nop */ | |
b13354f8 MG |
2882 | break; |
2883 | } | |
2884 | case 0x91 ... 0x97: /* xchg reg,rax */ | |
f0c13ef1 GN |
2885 | c->src.type = OP_REG; |
2886 | c->src.bytes = c->op_bytes; | |
b13354f8 MG |
2887 | c->src.ptr = (unsigned long *) &c->regs[VCPU_REGS_RAX]; |
2888 | c->src.val = *(c->src.ptr); | |
2889 | goto xchg; | |
fd2a7608 | 2890 | case 0x9c: /* pushf */ |
05f086f8 | 2891 | c->src.val = (unsigned long) ctxt->eflags; |
79168fd1 | 2892 | emulate_push(ctxt, ops); |
8cdbd2c9 | 2893 | break; |
535eabcf | 2894 | case 0x9d: /* popf */ |
2b48cc75 | 2895 | c->dst.type = OP_REG; |
05f086f8 | 2896 | c->dst.ptr = (unsigned long *) &ctxt->eflags; |
2b48cc75 | 2897 | c->dst.bytes = c->op_bytes; |
d4c6a154 GN |
2898 | rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes); |
2899 | if (rc != X86EMUL_CONTINUE) | |
2900 | goto done; | |
2901 | break; | |
5d55f299 | 2902 | case 0xa0 ... 0xa3: /* mov */ |
6aa8b732 | 2903 | case 0xa4 ... 0xa5: /* movs */ |
a682e354 | 2904 | goto mov; |
6aa8b732 | 2905 | case 0xa6 ... 0xa7: /* cmps */ |
d7e5117a | 2906 | c->dst.type = OP_NONE; /* Disable writeback. */ |
d7e5117a | 2907 | DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr); |
a682e354 | 2908 | goto cmp; |
dfb507c4 MG |
2909 | case 0xa8 ... 0xa9: /* test ax, imm */ |
2910 | goto test; | |
6aa8b732 | 2911 | case 0xaa ... 0xab: /* stos */ |
e4e03ded | 2912 | c->dst.val = c->regs[VCPU_REGS_RAX]; |
6aa8b732 AK |
2913 | break; |
2914 | case 0xac ... 0xad: /* lods */ | |
a682e354 | 2915 | goto mov; |
6aa8b732 AK |
2916 | case 0xae ... 0xaf: /* scas */ |
2917 | DPRINTF("Urk! I don't handle SCAS.\n"); | |
2918 | goto cannot_emulate; | |
a5e2e82b | 2919 | case 0xb0 ... 0xbf: /* mov r, imm */ |
615ac125 | 2920 | goto mov; |
018a98db AK |
2921 | case 0xc0 ... 0xc1: |
2922 | emulate_grp2(ctxt); | |
2923 | break; | |
111de5d6 | 2924 | case 0xc3: /* ret */ |
cf5de4f8 | 2925 | c->dst.type = OP_REG; |
111de5d6 | 2926 | c->dst.ptr = &c->eip; |
cf5de4f8 | 2927 | c->dst.bytes = c->op_bytes; |
111de5d6 | 2928 | goto pop_instruction; |
018a98db AK |
2929 | case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */ |
2930 | mov: | |
2931 | c->dst.val = c->src.val; | |
2932 | break; | |
a77ab5ea AK |
2933 | case 0xcb: /* ret far */ |
2934 | rc = emulate_ret_far(ctxt, ops); | |
62bd430e MG |
2935 | if (rc != X86EMUL_CONTINUE) |
2936 | goto done; | |
2937 | break; | |
2938 | case 0xcf: /* iret */ | |
2939 | rc = emulate_iret(ctxt, ops); | |
2940 | ||
1b30eaa8 | 2941 | if (rc != X86EMUL_CONTINUE) |
a77ab5ea AK |
2942 | goto done; |
2943 | break; | |
018a98db AK |
2944 | case 0xd0 ... 0xd1: /* Grp2 */ |
2945 | c->src.val = 1; | |
2946 | emulate_grp2(ctxt); | |
2947 | break; | |
2948 | case 0xd2 ... 0xd3: /* Grp2 */ | |
2949 | c->src.val = c->regs[VCPU_REGS_RCX]; | |
2950 | emulate_grp2(ctxt); | |
2951 | break; | |
a6a3034c MG |
2952 | case 0xe4: /* inb */ |
2953 | case 0xe5: /* in */ | |
cf8f70bf | 2954 | goto do_io_in; |
a6a3034c MG |
2955 | case 0xe6: /* outb */ |
2956 | case 0xe7: /* out */ | |
cf8f70bf | 2957 | goto do_io_out; |
1a52e051 | 2958 | case 0xe8: /* call (near) */ { |
d53c4777 | 2959 | long int rel = c->src.val; |
e4e03ded | 2960 | c->src.val = (unsigned long) c->eip; |
7a957275 | 2961 | jmp_rel(c, rel); |
79168fd1 | 2962 | emulate_push(ctxt, ops); |
8cdbd2c9 | 2963 | break; |
1a52e051 NK |
2964 | } |
2965 | case 0xe9: /* jmp rel */ | |
954cd36f | 2966 | goto jmp; |
414e6277 GN |
2967 | case 0xea: { /* jmp far */ |
2968 | unsigned short sel; | |
ea79849d | 2969 | jump_far: |
414e6277 GN |
2970 | memcpy(&sel, c->src.valptr + c->op_bytes, 2); |
2971 | ||
2972 | if (load_segment_descriptor(ctxt, ops, sel, VCPU_SREG_CS)) | |
c697518a | 2973 | goto done; |
954cd36f | 2974 | |
414e6277 GN |
2975 | c->eip = 0; |
2976 | memcpy(&c->eip, c->src.valptr, c->op_bytes); | |
954cd36f | 2977 | break; |
414e6277 | 2978 | } |
954cd36f GT |
2979 | case 0xeb: |
2980 | jmp: /* jmp rel short */ | |
7a957275 | 2981 | jmp_rel(c, c->src.val); |
a01af5ec | 2982 | c->dst.type = OP_NONE; /* Disable writeback. */ |
1a52e051 | 2983 | break; |
a6a3034c MG |
2984 | case 0xec: /* in al,dx */ |
2985 | case 0xed: /* in (e/r)ax,dx */ | |
cf8f70bf GN |
2986 | c->src.val = c->regs[VCPU_REGS_RDX]; |
2987 | do_io_in: | |
2988 | c->dst.bytes = min(c->dst.bytes, 4u); | |
2989 | if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) { | |
54b8486f | 2990 | emulate_gp(ctxt, 0); |
cf8f70bf GN |
2991 | goto done; |
2992 | } | |
7b262e90 GN |
2993 | if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val, |
2994 | &c->dst.val)) | |
cf8f70bf GN |
2995 | goto done; /* IO is needed */ |
2996 | break; | |
ce7a0ad3 WY |
2997 | case 0xee: /* out dx,al */ |
2998 | case 0xef: /* out dx,(e/r)ax */ | |
cf8f70bf GN |
2999 | c->src.val = c->regs[VCPU_REGS_RDX]; |
3000 | do_io_out: | |
3001 | c->dst.bytes = min(c->dst.bytes, 4u); | |
3002 | if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) { | |
54b8486f | 3003 | emulate_gp(ctxt, 0); |
f850e2e6 GN |
3004 | goto done; |
3005 | } | |
cf8f70bf GN |
3006 | ops->pio_out_emulated(c->dst.bytes, c->src.val, &c->dst.val, 1, |
3007 | ctxt->vcpu); | |
3008 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
e93f36bc | 3009 | break; |
111de5d6 | 3010 | case 0xf4: /* hlt */ |
ad312c7c | 3011 | ctxt->vcpu->arch.halt_request = 1; |
19fdfa0d | 3012 | break; |
111de5d6 AK |
3013 | case 0xf5: /* cmc */ |
3014 | /* complement carry flag from eflags reg */ | |
3015 | ctxt->eflags ^= EFLG_CF; | |
3016 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
3017 | break; | |
018a98db | 3018 | case 0xf6 ... 0xf7: /* Grp3 */ |
aca06a83 GN |
3019 | if (!emulate_grp3(ctxt, ops)) |
3020 | goto cannot_emulate; | |
018a98db | 3021 | break; |
111de5d6 AK |
3022 | case 0xf8: /* clc */ |
3023 | ctxt->eflags &= ~EFLG_CF; | |
3024 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
3025 | break; | |
3026 | case 0xfa: /* cli */ | |
07cbc6c1 | 3027 | if (emulator_bad_iopl(ctxt, ops)) { |
54b8486f | 3028 | emulate_gp(ctxt, 0); |
07cbc6c1 WY |
3029 | goto done; |
3030 | } else { | |
f850e2e6 GN |
3031 | ctxt->eflags &= ~X86_EFLAGS_IF; |
3032 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
3033 | } | |
111de5d6 AK |
3034 | break; |
3035 | case 0xfb: /* sti */ | |
07cbc6c1 | 3036 | if (emulator_bad_iopl(ctxt, ops)) { |
54b8486f | 3037 | emulate_gp(ctxt, 0); |
07cbc6c1 WY |
3038 | goto done; |
3039 | } else { | |
95cb2295 | 3040 | ctxt->interruptibility = KVM_X86_SHADOW_INT_STI; |
f850e2e6 GN |
3041 | ctxt->eflags |= X86_EFLAGS_IF; |
3042 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
3043 | } | |
111de5d6 | 3044 | break; |
fb4616f4 MG |
3045 | case 0xfc: /* cld */ |
3046 | ctxt->eflags &= ~EFLG_DF; | |
3047 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
3048 | break; | |
3049 | case 0xfd: /* std */ | |
3050 | ctxt->eflags |= EFLG_DF; | |
3051 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
3052 | break; | |
ea79849d GN |
3053 | case 0xfe: /* Grp4 */ |
3054 | grp45: | |
018a98db | 3055 | rc = emulate_grp45(ctxt, ops); |
1b30eaa8 | 3056 | if (rc != X86EMUL_CONTINUE) |
018a98db AK |
3057 | goto done; |
3058 | break; | |
ea79849d GN |
3059 | case 0xff: /* Grp5 */ |
3060 | if (c->modrm_reg == 5) | |
3061 | goto jump_far; | |
3062 | goto grp45; | |
91269b8f AK |
3063 | default: |
3064 | goto cannot_emulate; | |
6aa8b732 | 3065 | } |
018a98db AK |
3066 | |
3067 | writeback: | |
3068 | rc = writeback(ctxt, ops); | |
1b30eaa8 | 3069 | if (rc != X86EMUL_CONTINUE) |
018a98db AK |
3070 | goto done; |
3071 | ||
5cd21917 GN |
3072 | /* |
3073 | * restore dst type in case the decoding will be reused | |
3074 | * (happens for string instruction ) | |
3075 | */ | |
3076 | c->dst.type = saved_dst_type; | |
3077 | ||
a682e354 | 3078 | if ((c->d & SrcMask) == SrcSI) |
79168fd1 GN |
3079 | string_addr_inc(ctxt, seg_override_base(ctxt, ops, c), |
3080 | VCPU_REGS_RSI, &c->src); | |
a682e354 GN |
3081 | |
3082 | if ((c->d & DstMask) == DstDI) | |
79168fd1 GN |
3083 | string_addr_inc(ctxt, es_base(ctxt, ops), VCPU_REGS_RDI, |
3084 | &c->dst); | |
d9271123 | 3085 | |
5cd21917 | 3086 | if (c->rep_prefix && (c->d & String)) { |
7b262e90 | 3087 | struct read_cache *rc = &ctxt->decode.io_read; |
d9271123 | 3088 | register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1); |
7b262e90 GN |
3089 | /* |
3090 | * Re-enter guest when pio read ahead buffer is empty or, | |
3091 | * if it is not used, after each 1024 iteration. | |
3092 | */ | |
3093 | if ((rc->end == 0 && !(c->regs[VCPU_REGS_RCX] & 0x3ff)) || | |
3094 | (rc->end != 0 && rc->end == rc->pos)) | |
5cd21917 GN |
3095 | ctxt->restart = false; |
3096 | } | |
9de41573 GN |
3097 | /* |
3098 | * reset read cache here in case string instruction is restared | |
3099 | * without decoding | |
3100 | */ | |
3101 | ctxt->decode.mem_read.end = 0; | |
95c55886 | 3102 | ctxt->eip = c->eip; |
018a98db AK |
3103 | |
3104 | done: | |
cb404fe0 | 3105 | return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0; |
6aa8b732 AK |
3106 | |
3107 | twobyte_insn: | |
e4e03ded | 3108 | switch (c->b) { |
6aa8b732 | 3109 | case 0x01: /* lgdt, lidt, lmsw */ |
e4e03ded | 3110 | switch (c->modrm_reg) { |
6aa8b732 AK |
3111 | u16 size; |
3112 | unsigned long address; | |
3113 | ||
aca7f966 | 3114 | case 0: /* vmcall */ |
e4e03ded | 3115 | if (c->modrm_mod != 3 || c->modrm_rm != 1) |
aca7f966 AL |
3116 | goto cannot_emulate; |
3117 | ||
7aa81cc0 | 3118 | rc = kvm_fix_hypercall(ctxt->vcpu); |
1b30eaa8 | 3119 | if (rc != X86EMUL_CONTINUE) |
7aa81cc0 AL |
3120 | goto done; |
3121 | ||
33e3885d | 3122 | /* Let the processor re-execute the fixed hypercall */ |
063db061 | 3123 | c->eip = ctxt->eip; |
16286d08 AK |
3124 | /* Disable writeback. */ |
3125 | c->dst.type = OP_NONE; | |
aca7f966 | 3126 | break; |
6aa8b732 | 3127 | case 2: /* lgdt */ |
e4e03ded LV |
3128 | rc = read_descriptor(ctxt, ops, c->src.ptr, |
3129 | &size, &address, c->op_bytes); | |
1b30eaa8 | 3130 | if (rc != X86EMUL_CONTINUE) |
6aa8b732 AK |
3131 | goto done; |
3132 | realmode_lgdt(ctxt->vcpu, size, address); | |
16286d08 AK |
3133 | /* Disable writeback. */ |
3134 | c->dst.type = OP_NONE; | |
6aa8b732 | 3135 | break; |
aca7f966 | 3136 | case 3: /* lidt/vmmcall */ |
2b3d2a20 AK |
3137 | if (c->modrm_mod == 3) { |
3138 | switch (c->modrm_rm) { | |
3139 | case 1: | |
3140 | rc = kvm_fix_hypercall(ctxt->vcpu); | |
1b30eaa8 | 3141 | if (rc != X86EMUL_CONTINUE) |
2b3d2a20 AK |
3142 | goto done; |
3143 | break; | |
3144 | default: | |
3145 | goto cannot_emulate; | |
3146 | } | |
aca7f966 | 3147 | } else { |
e4e03ded | 3148 | rc = read_descriptor(ctxt, ops, c->src.ptr, |
aca7f966 | 3149 | &size, &address, |
e4e03ded | 3150 | c->op_bytes); |
1b30eaa8 | 3151 | if (rc != X86EMUL_CONTINUE) |
aca7f966 AL |
3152 | goto done; |
3153 | realmode_lidt(ctxt->vcpu, size, address); | |
3154 | } | |
16286d08 AK |
3155 | /* Disable writeback. */ |
3156 | c->dst.type = OP_NONE; | |
6aa8b732 AK |
3157 | break; |
3158 | case 4: /* smsw */ | |
16286d08 | 3159 | c->dst.bytes = 2; |
52a46617 | 3160 | c->dst.val = ops->get_cr(0, ctxt->vcpu); |
6aa8b732 AK |
3161 | break; |
3162 | case 6: /* lmsw */ | |
93a152be GN |
3163 | ops->set_cr(0, (ops->get_cr(0, ctxt->vcpu) & ~0x0ful) | |
3164 | (c->src.val & 0x0f), ctxt->vcpu); | |
dc7457ea | 3165 | c->dst.type = OP_NONE; |
6aa8b732 | 3166 | break; |
6e1e5ffe | 3167 | case 5: /* not defined */ |
54b8486f | 3168 | emulate_ud(ctxt); |
6e1e5ffe | 3169 | goto done; |
6aa8b732 | 3170 | case 7: /* invlpg*/ |
69f55cb1 | 3171 | emulate_invlpg(ctxt->vcpu, c->modrm_ea); |
16286d08 AK |
3172 | /* Disable writeback. */ |
3173 | c->dst.type = OP_NONE; | |
6aa8b732 AK |
3174 | break; |
3175 | default: | |
3176 | goto cannot_emulate; | |
3177 | } | |
3178 | break; | |
e99f0507 | 3179 | case 0x05: /* syscall */ |
3fb1b5db | 3180 | rc = emulate_syscall(ctxt, ops); |
e54cfa97 TY |
3181 | if (rc != X86EMUL_CONTINUE) |
3182 | goto done; | |
e66bb2cc AP |
3183 | else |
3184 | goto writeback; | |
e99f0507 | 3185 | break; |
018a98db AK |
3186 | case 0x06: |
3187 | emulate_clts(ctxt->vcpu); | |
3188 | c->dst.type = OP_NONE; | |
3189 | break; | |
018a98db | 3190 | case 0x09: /* wbinvd */ |
f5f48ee1 SY |
3191 | kvm_emulate_wbinvd(ctxt->vcpu); |
3192 | c->dst.type = OP_NONE; | |
3193 | break; | |
3194 | case 0x08: /* invd */ | |
018a98db AK |
3195 | case 0x0d: /* GrpP (prefetch) */ |
3196 | case 0x18: /* Grp16 (prefetch/nop) */ | |
3197 | c->dst.type = OP_NONE; | |
3198 | break; | |
3199 | case 0x20: /* mov cr, reg */ | |
6aebfa6e GN |
3200 | switch (c->modrm_reg) { |
3201 | case 1: | |
3202 | case 5 ... 7: | |
3203 | case 9 ... 15: | |
54b8486f | 3204 | emulate_ud(ctxt); |
6aebfa6e GN |
3205 | goto done; |
3206 | } | |
52a46617 | 3207 | c->regs[c->modrm_rm] = ops->get_cr(c->modrm_reg, ctxt->vcpu); |
018a98db AK |
3208 | c->dst.type = OP_NONE; /* no writeback */ |
3209 | break; | |
6aa8b732 | 3210 | case 0x21: /* mov from dr to reg */ |
1e470be5 GN |
3211 | if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) && |
3212 | (c->modrm_reg == 4 || c->modrm_reg == 5)) { | |
54b8486f | 3213 | emulate_ud(ctxt); |
1e470be5 GN |
3214 | goto done; |
3215 | } | |
35aa5375 | 3216 | ops->get_dr(c->modrm_reg, &c->regs[c->modrm_rm], ctxt->vcpu); |
a01af5ec | 3217 | c->dst.type = OP_NONE; /* no writeback */ |
6aa8b732 | 3218 | break; |
018a98db | 3219 | case 0x22: /* mov reg, cr */ |
0f12244f | 3220 | if (ops->set_cr(c->modrm_reg, c->modrm_val, ctxt->vcpu)) { |
54b8486f | 3221 | emulate_gp(ctxt, 0); |
0f12244f GN |
3222 | goto done; |
3223 | } | |
018a98db AK |
3224 | c->dst.type = OP_NONE; |
3225 | break; | |
6aa8b732 | 3226 | case 0x23: /* mov from reg to dr */ |
1e470be5 GN |
3227 | if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) && |
3228 | (c->modrm_reg == 4 || c->modrm_reg == 5)) { | |
54b8486f | 3229 | emulate_ud(ctxt); |
1e470be5 GN |
3230 | goto done; |
3231 | } | |
35aa5375 | 3232 | |
338dbc97 GN |
3233 | if (ops->set_dr(c->modrm_reg, c->regs[c->modrm_rm] & |
3234 | ((ctxt->mode == X86EMUL_MODE_PROT64) ? | |
3235 | ~0ULL : ~0U), ctxt->vcpu) < 0) { | |
3236 | /* #UD condition is already handled by the code above */ | |
54b8486f | 3237 | emulate_gp(ctxt, 0); |
338dbc97 GN |
3238 | goto done; |
3239 | } | |
3240 | ||
a01af5ec | 3241 | c->dst.type = OP_NONE; /* no writeback */ |
6aa8b732 | 3242 | break; |
018a98db AK |
3243 | case 0x30: |
3244 | /* wrmsr */ | |
3245 | msr_data = (u32)c->regs[VCPU_REGS_RAX] | |
3246 | | ((u64)c->regs[VCPU_REGS_RDX] << 32); | |
3fb1b5db | 3247 | if (ops->set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data)) { |
54b8486f | 3248 | emulate_gp(ctxt, 0); |
fd525365 | 3249 | goto done; |
018a98db AK |
3250 | } |
3251 | rc = X86EMUL_CONTINUE; | |
3252 | c->dst.type = OP_NONE; | |
3253 | break; | |
3254 | case 0x32: | |
3255 | /* rdmsr */ | |
3fb1b5db | 3256 | if (ops->get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data)) { |
54b8486f | 3257 | emulate_gp(ctxt, 0); |
fd525365 | 3258 | goto done; |
018a98db AK |
3259 | } else { |
3260 | c->regs[VCPU_REGS_RAX] = (u32)msr_data; | |
3261 | c->regs[VCPU_REGS_RDX] = msr_data >> 32; | |
3262 | } | |
3263 | rc = X86EMUL_CONTINUE; | |
3264 | c->dst.type = OP_NONE; | |
3265 | break; | |
e99f0507 | 3266 | case 0x34: /* sysenter */ |
3fb1b5db | 3267 | rc = emulate_sysenter(ctxt, ops); |
e54cfa97 TY |
3268 | if (rc != X86EMUL_CONTINUE) |
3269 | goto done; | |
8c604352 AP |
3270 | else |
3271 | goto writeback; | |
e99f0507 AP |
3272 | break; |
3273 | case 0x35: /* sysexit */ | |
3fb1b5db | 3274 | rc = emulate_sysexit(ctxt, ops); |
e54cfa97 TY |
3275 | if (rc != X86EMUL_CONTINUE) |
3276 | goto done; | |
4668f050 AP |
3277 | else |
3278 | goto writeback; | |
e99f0507 | 3279 | break; |
6aa8b732 | 3280 | case 0x40 ... 0x4f: /* cmov */ |
e4e03ded | 3281 | c->dst.val = c->dst.orig_val = c->src.val; |
a01af5ec LV |
3282 | if (!test_cc(c->b, ctxt->eflags)) |
3283 | c->dst.type = OP_NONE; /* no writeback */ | |
6aa8b732 | 3284 | break; |
b2833e3c | 3285 | case 0x80 ... 0x8f: /* jnz rel, etc*/ |
018a98db | 3286 | if (test_cc(c->b, ctxt->eflags)) |
b2833e3c | 3287 | jmp_rel(c, c->src.val); |
018a98db AK |
3288 | c->dst.type = OP_NONE; |
3289 | break; | |
0934ac9d | 3290 | case 0xa0: /* push fs */ |
79168fd1 | 3291 | emulate_push_sreg(ctxt, ops, VCPU_SREG_FS); |
0934ac9d MG |
3292 | break; |
3293 | case 0xa1: /* pop fs */ | |
3294 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS); | |
1b30eaa8 | 3295 | if (rc != X86EMUL_CONTINUE) |
0934ac9d MG |
3296 | goto done; |
3297 | break; | |
7de75248 NK |
3298 | case 0xa3: |
3299 | bt: /* bt */ | |
e4f8e039 | 3300 | c->dst.type = OP_NONE; |
e4e03ded LV |
3301 | /* only subword offset */ |
3302 | c->src.val &= (c->dst.bytes << 3) - 1; | |
05f086f8 | 3303 | emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags); |
7de75248 | 3304 | break; |
9bf8ea42 GT |
3305 | case 0xa4: /* shld imm8, r, r/m */ |
3306 | case 0xa5: /* shld cl, r, r/m */ | |
3307 | emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags); | |
3308 | break; | |
0934ac9d | 3309 | case 0xa8: /* push gs */ |
79168fd1 | 3310 | emulate_push_sreg(ctxt, ops, VCPU_SREG_GS); |
0934ac9d MG |
3311 | break; |
3312 | case 0xa9: /* pop gs */ | |
3313 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS); | |
1b30eaa8 | 3314 | if (rc != X86EMUL_CONTINUE) |
0934ac9d MG |
3315 | goto done; |
3316 | break; | |
7de75248 NK |
3317 | case 0xab: |
3318 | bts: /* bts */ | |
e4e03ded LV |
3319 | /* only subword offset */ |
3320 | c->src.val &= (c->dst.bytes << 3) - 1; | |
05f086f8 | 3321 | emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags); |
7de75248 | 3322 | break; |
9bf8ea42 GT |
3323 | case 0xac: /* shrd imm8, r, r/m */ |
3324 | case 0xad: /* shrd cl, r, r/m */ | |
3325 | emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags); | |
3326 | break; | |
2a7c5b8b GC |
3327 | case 0xae: /* clflush */ |
3328 | break; | |
6aa8b732 AK |
3329 | case 0xb0 ... 0xb1: /* cmpxchg */ |
3330 | /* | |
3331 | * Save real source value, then compare EAX against | |
3332 | * destination. | |
3333 | */ | |
e4e03ded LV |
3334 | c->src.orig_val = c->src.val; |
3335 | c->src.val = c->regs[VCPU_REGS_RAX]; | |
05f086f8 LV |
3336 | emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags); |
3337 | if (ctxt->eflags & EFLG_ZF) { | |
6aa8b732 | 3338 | /* Success: write back to memory. */ |
e4e03ded | 3339 | c->dst.val = c->src.orig_val; |
6aa8b732 AK |
3340 | } else { |
3341 | /* Failure: write the value we saw to EAX. */ | |
e4e03ded LV |
3342 | c->dst.type = OP_REG; |
3343 | c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX]; | |
6aa8b732 AK |
3344 | } |
3345 | break; | |
6aa8b732 AK |
3346 | case 0xb3: |
3347 | btr: /* btr */ | |
e4e03ded LV |
3348 | /* only subword offset */ |
3349 | c->src.val &= (c->dst.bytes << 3) - 1; | |
05f086f8 | 3350 | emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 3351 | break; |
6aa8b732 | 3352 | case 0xb6 ... 0xb7: /* movzx */ |
e4e03ded LV |
3353 | c->dst.bytes = c->op_bytes; |
3354 | c->dst.val = (c->d & ByteOp) ? (u8) c->src.val | |
3355 | : (u16) c->src.val; | |
6aa8b732 | 3356 | break; |
6aa8b732 | 3357 | case 0xba: /* Grp8 */ |
e4e03ded | 3358 | switch (c->modrm_reg & 3) { |
6aa8b732 AK |
3359 | case 0: |
3360 | goto bt; | |
3361 | case 1: | |
3362 | goto bts; | |
3363 | case 2: | |
3364 | goto btr; | |
3365 | case 3: | |
3366 | goto btc; | |
3367 | } | |
3368 | break; | |
7de75248 NK |
3369 | case 0xbb: |
3370 | btc: /* btc */ | |
e4e03ded LV |
3371 | /* only subword offset */ |
3372 | c->src.val &= (c->dst.bytes << 3) - 1; | |
05f086f8 | 3373 | emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags); |
7de75248 | 3374 | break; |
6aa8b732 | 3375 | case 0xbe ... 0xbf: /* movsx */ |
e4e03ded LV |
3376 | c->dst.bytes = c->op_bytes; |
3377 | c->dst.val = (c->d & ByteOp) ? (s8) c->src.val : | |
3378 | (s16) c->src.val; | |
6aa8b732 | 3379 | break; |
a012e65a | 3380 | case 0xc3: /* movnti */ |
e4e03ded LV |
3381 | c->dst.bytes = c->op_bytes; |
3382 | c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val : | |
3383 | (u64) c->src.val; | |
a012e65a | 3384 | break; |
6aa8b732 | 3385 | case 0xc7: /* Grp9 (cmpxchg8b) */ |
69f55cb1 | 3386 | rc = emulate_grp9(ctxt, ops); |
1b30eaa8 | 3387 | if (rc != X86EMUL_CONTINUE) |
8cdbd2c9 LV |
3388 | goto done; |
3389 | break; | |
91269b8f AK |
3390 | default: |
3391 | goto cannot_emulate; | |
6aa8b732 AK |
3392 | } |
3393 | goto writeback; | |
3394 | ||
3395 | cannot_emulate: | |
e4e03ded | 3396 | DPRINTF("Cannot emulate %02x\n", c->b); |
6aa8b732 AK |
3397 | return -1; |
3398 | } |