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KVM: x86 emulator: Allow LOCK prefix for NEG and NOT
[linux-2.6-block.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
221d059d 12 * Copyright 2010 Red Hat, Inc. and/or its affilates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
23#ifndef __KERNEL__
24#include <stdio.h>
25#include <stdint.h>
26#include <public/xen.h>
d77c26fc 27#define DPRINTF(_f, _a ...) printf(_f , ## _a)
6aa8b732 28#else
edf88417 29#include <linux/kvm_host.h>
5fdbf976 30#include "kvm_cache_regs.h"
6aa8b732
AK		 31#define DPRINTF(x...) do {} while (0)
32#endif
6aa8b732 33#include <linux/module.h>
56e82318 34#include <asm/kvm_emulate.h>
6aa8b732 35
3eeb3288 36#include "x86.h"
38ba30ba 37#include "tss.h"
e99f0507 38
6aa8b732
AK		 39/*
40 * Opcode effective-address decode tables.
41 * Note that we only emulate instructions that have at least one memory
42 * operand (excluding implicit stack references). We assume that stack
43 * references and instruction fetches will never occur in special memory
44 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
45 * not be handled.
46 */
47
48/* Operand sizes: 8-bit operands or specified/overridden size. */
2ce49536 49#define ByteOp (1<<16) /* 8-bit operands. */
6aa8b732 50/* Destination operand type. */
2ce49536
AK		 51#define ImplicitOps (1<<17) /* Implicit in opcode. No generic decode. */
52#define DstReg (2<<17) /* Register operand. */
53#define DstMem (3<<17) /* Memory operand. */
54#define DstAcc (4<<17) /* Destination Accumulator */
55#define DstDI (5<<17) /* Destination is in ES:(E)DI */
56#define DstMem64 (6<<17) /* 64bit memory operand */
57#define DstMask (7<<17)
6aa8b732 58/* Source operand type. */
9c9fddd0
GT		 59#define SrcNone (0<<4) /* No source operand. */
60#define SrcImplicit (0<<4) /* Source operand is implicit in the opcode. */
61#define SrcReg (1<<4) /* Register operand. */
62#define SrcMem (2<<4) /* Memory operand. */
63#define SrcMem16 (3<<4) /* Memory operand (16-bit). */
64#define SrcMem32 (4<<4) /* Memory operand (32-bit). */
65#define SrcImm (5<<4) /* Immediate operand. */
66#define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
bfcadf83 67#define SrcOne (7<<4) /* Implied '1' */
341de7e3 68#define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
c9eaf20f 69#define SrcImmU (9<<4) /* Immediate operand, unsigned */
a682e354 70#define SrcSI (0xa<<4) /* Source is in the DS:RSI */
414e6277
GN		 71#define SrcImmFAddr (0xb<<4) /* Source is immediate far address */
72#define SrcMemFAddr (0xc<<4) /* Source is far address in memory */
5d55f299 73#define SrcAcc (0xd<<4) /* Source Accumulator */
341de7e3 74#define SrcMask (0xf<<4)
6aa8b732 75/* Generic ModRM decode. */
341de7e3 76#define ModRM (1<<8)
6aa8b732 77/* Destination is only written; never read. */
341de7e3
GN		 78#define Mov (1<<9)
79#define BitOp (1<<10)
80#define MemAbs (1<<11) /* Memory operand is absolute displacement */
9c9fddd0
GT		 81#define String (1<<12) /* String instruction (rep capable) */
82#define Stack (1<<13) /* Stack instruction (push/pop) */
e09d082c
AK		 83#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
84#define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
2ce49536 85#define GroupMask 0x0f /* Group number stored in bits 0:3 */
d8769fed 86/* Misc flags */
047a4818 87#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 88#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 89#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 90#define No64 (1<<28)
0dc8d10f
GT		 91/* Source 2 operand type */
92#define Src2None (0<<29)
93#define Src2CL (1<<29)
94#define Src2ImmByte (2<<29)
95#define Src2One (3<<29)
96#define Src2Mask (7<<29)
6aa8b732 97
83babbca
AK		 98#define X2(x) (x), (x)
99#define X3(x) X2(x), (x)
100#define X4(x) X2(x), X2(x)
101#define X5(x) X4(x), (x)
102#define X6(x) X4(x), X2(x)
103#define X7(x) X4(x), X3(x)
104#define X8(x) X4(x), X4(x)
105#define X16(x) X8(x), X8(x)
106
43bb19cd 107enum {
4968ec4e 108 Group1, Group1A, Group3_Byte, Group3, Group4, Group5, Group7,
60a29d4e 109 Group8, Group9,
43bb19cd
AK		 110};
111
45ed60b3 112static u32 opcode_table[256] = {
6aa8b732 113 /* 0x00 - 0x07 */
d380a5e4 114 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732 115 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
0934ac9d 116 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
d8769fed 117 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
6aa8b732 118 /* 0x08 - 0x0F */
d380a5e4 119 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732 120 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
94677e61
MG		 121 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
122 ImplicitOps | Stack | No64, 0,
6aa8b732 123 /* 0x10 - 0x17 */
d380a5e4 124 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732 125 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
0934ac9d 126 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
d8769fed 127 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
6aa8b732 128 /* 0x18 - 0x1F */
d380a5e4 129 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732 130 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
0934ac9d 131 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
d8769fed 132 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
6aa8b732 133 /* 0x20 - 0x27 */
d380a5e4 134 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732 135 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
e97e883f 136 ByteOp | DstAcc | SrcImmByte, DstAcc | SrcImm, 0, 0,
6aa8b732 137 /* 0x28 - 0x2F */
d380a5e4 138 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732 139 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
abc19083 140 ByteOp | DstAcc | SrcImmByte, DstAcc | SrcImm, 0, 0,
6aa8b732 141 /* 0x30 - 0x37 */
d380a5e4 142 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732 143 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
222b7c52 144 ByteOp | DstAcc | SrcImmByte, DstAcc | SrcImm, 0, 0,
6aa8b732
AK		 145 /* 0x38 - 0x3F */
146 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
147 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
8a9fee67
GT		 148 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
149 0, 0,
749358a6
AK		 150 /* 0x40 - 0x4F */
151 X16(DstReg),
7f0aaee0 152 /* 0x50 - 0x57 */
3849186c 153 X8(SrcReg | Stack),
7f0aaee0 154 /* 0x58 - 0x5F */
3849186c 155 X8(DstReg | Stack),
7d316911 156 /* 0x60 - 0x67 */
abcf14b5
MG		 157 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
158 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ ,
7d316911
NK		 159 0, 0, 0, 0,
160 /* 0x68 - 0x6F */
91ed7a0e 161 SrcImm | Mov | Stack, 0, SrcImmByte | Mov | Stack, 0,
7972995b
GN		 162 DstDI | ByteOp | Mov | String, DstDI | Mov | String, /* insb, insw/insd */
163 SrcSI | ByteOp | ImplicitOps | String, SrcSI | ImplicitOps | String, /* outsb, outsw/outsd */
b3ab3405
AK		 164 /* 0x70 - 0x7F */
165 X16(SrcImmByte),
6aa8b732 166 /* 0x80 - 0x87 */
4968ec4e
AK		 167 ByteOp | DstMem | SrcImm | ModRM | Group | Group1,
168 DstMem | SrcImm | ModRM | Group | Group1,
169 ByteOp | DstMem | SrcImm | ModRM | No64 | Group | Group1,
170 DstMem | SrcImmByte | ModRM | Group | Group1,
6aa8b732 171 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
d380a5e4 172 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732
AK		 173 /* 0x88 - 0x8F */
174 ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov,
175 ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
b16b2b7b 176 DstMem | SrcNone | ModRM | Mov, ModRM | DstReg,
a5046e6c 177 ImplicitOps | SrcMem16 | ModRM, Group | Group1A,
b13354f8
MG		 178 /* 0x90 - 0x97 */
179 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
180 /* 0x98 - 0x9F */
414e6277 181 0, 0, SrcImmFAddr | No64, 0,
0654169e 182 ImplicitOps | Stack, ImplicitOps | Stack, 0, 0,
6aa8b732 183 /* 0xA0 - 0xA7 */
5d55f299
WY		 184 ByteOp | DstAcc | SrcMem | Mov | MemAbs, DstAcc | SrcMem | Mov | MemAbs,
185 ByteOp | DstMem | SrcAcc | Mov | MemAbs, DstMem | SrcAcc | Mov | MemAbs,
a682e354
GN		 186 ByteOp | SrcSI | DstDI | Mov | String, SrcSI | DstDI | Mov | String,
187 ByteOp | SrcSI | DstDI | String, SrcSI | DstDI | String,
6aa8b732 188 /* 0xA8 - 0xAF */
dfb507c4 189 DstAcc | SrcImmByte | ByteOp, DstAcc | SrcImm, ByteOp | DstDI | Mov | String, DstDI | Mov | String,
a682e354
GN		 190 ByteOp | SrcSI | DstAcc | Mov | String, SrcSI | DstAcc | Mov | String,
191 ByteOp | DstDI | String, DstDI | String,
a5e2e82b 192 /* 0xB0 - 0xB7 */
b6e61538 193 X8(ByteOp | DstReg | SrcImm | Mov),
a5e2e82b 194 /* 0xB8 - 0xBF */
b6e61538 195 X8(DstReg | SrcImm | Mov),
6aa8b732 196 /* 0xC0 - 0xC7 */
d9413cd7 197 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
6e3d5dfb 198 0, ImplicitOps | Stack, 0, 0,
d9413cd7 199 ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov,
6aa8b732 200 /* 0xC8 - 0xCF */
e637b823 201 0, 0, 0, ImplicitOps | Stack,
d8769fed 202 ImplicitOps, SrcImmByte, ImplicitOps | No64, ImplicitOps,
6aa8b732
AK		 203 /* 0xD0 - 0xD7 */
204 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
205 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
206 0, 0, 0, 0,
207 /* 0xD8 - 0xDF */
208 0, 0, 0, 0, 0, 0, 0, 0,
098c937b 209 /* 0xE0 - 0xE7 */
a6a3034c 210 0, 0, 0, 0,
cf8f70bf
GN		 211 ByteOp | SrcImmUByte | DstAcc, SrcImmUByte | DstAcc,
212 ByteOp | SrcImmUByte | DstAcc, SrcImmUByte | DstAcc,
098c937b 213 /* 0xE8 - 0xEF */
d53c4777 214 SrcImm | Stack, SrcImm | ImplicitOps,
414e6277 215 SrcImmFAddr | No64, SrcImmByte | ImplicitOps,
cf8f70bf
GN		 216 SrcNone | ByteOp | DstAcc, SrcNone | DstAcc,
217 SrcNone | ByteOp | DstAcc, SrcNone | DstAcc,
6aa8b732
AK		 218 /* 0xF0 - 0xF7 */
219 0, 0, 0, 0,
e92805ac 220 ImplicitOps | Priv, ImplicitOps, Group | Group3_Byte, Group | Group3,
6aa8b732 221 /* 0xF8 - 0xFF */
b284be57 222 ImplicitOps, 0, ImplicitOps, ImplicitOps,
fb4616f4 223 ImplicitOps, ImplicitOps, Group | Group4, Group | Group5,
6aa8b732
AK		 224};
225
45ed60b3 226static u32 twobyte_table[256] = {
6aa8b732 227 /* 0x00 - 0x0F */
e92805ac
GN		 228 0, Group | GroupDual | Group7, 0, 0,
229 0, ImplicitOps, ImplicitOps | Priv, 0,
230 ImplicitOps | Priv, ImplicitOps | Priv, 0, 0,
231 0, ImplicitOps | ModRM, 0, 0,
6aa8b732
AK		 232 /* 0x10 - 0x1F */
233 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0,
234 /* 0x20 - 0x2F */
e92805ac
GN		 235 ModRM | ImplicitOps | Priv, ModRM | Priv,
236 ModRM | ImplicitOps | Priv, ModRM | Priv,
237 0, 0, 0, 0,
6aa8b732
AK		 238 0, 0, 0, 0, 0, 0, 0, 0,
239 /* 0x30 - 0x3F */
e92805ac
GN		 240 ImplicitOps | Priv, 0, ImplicitOps | Priv, 0,
241 ImplicitOps, ImplicitOps | Priv, 0, 0,
e99f0507 242 0, 0, 0, 0, 0, 0, 0, 0,
be8eacdd
AK		 243 /* 0x40 - 0x4F */
244 X16(DstReg | SrcMem | ModRM | Mov),
6aa8b732
AK		 245 /* 0x50 - 0x5F */
246 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
247 /* 0x60 - 0x6F */
248 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
249 /* 0x70 - 0x7F */
250 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
251 /* 0x80 - 0x8F */
880a1883 252 X16(SrcImm),
6aa8b732
AK		 253 /* 0x90 - 0x9F */
254 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
255 /* 0xA0 - 0xA7 */
0934ac9d
MG		 256 ImplicitOps | Stack, ImplicitOps | Stack,
257 0, DstMem | SrcReg | ModRM | BitOp,
9bf8ea42
GT		 258 DstMem | SrcReg | Src2ImmByte | ModRM,
259 DstMem | SrcReg | Src2CL | ModRM, 0, 0,
6aa8b732 260 /* 0xA8 - 0xAF */
0934ac9d 261 ImplicitOps | Stack, ImplicitOps | Stack,
d380a5e4 262 0, DstMem | SrcReg | ModRM | BitOp | Lock,
9bf8ea42
GT		 263 DstMem | SrcReg | Src2ImmByte | ModRM,
264 DstMem | SrcReg | Src2CL | ModRM,
265 ModRM, 0,
6aa8b732 266 /* 0xB0 - 0xB7 */
d380a5e4
GN		 267 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
268 0, DstMem | SrcReg | ModRM | BitOp | Lock,
6aa8b732
AK		 269 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
270 DstReg | SrcMem16 | ModRM | Mov,
271 /* 0xB8 - 0xBF */
d380a5e4
GN		 272 0, 0,
273 Group | Group8, DstMem | SrcReg | ModRM | BitOp | Lock,
6aa8b732
AK		 274 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
275 DstReg | SrcMem16 | ModRM | Mov,
276 /* 0xC0 - 0xCF */
60a29d4e
GN		 277 0, 0, 0, DstMem | SrcReg | ModRM | Mov,
278 0, 0, 0, Group | GroupDual | Group9,
a012e65a 279 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 280 /* 0xD0 - 0xDF */
281 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
282 /* 0xE0 - 0xEF */
283 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
284 /* 0xF0 - 0xFF */
285 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
286};
287
45ed60b3 288static u32 group_table[] = {
4968ec4e
AK		 289 [Group1*8] =
290 X7(Lock), 0,
43bb19cd
AK		 291 [Group1A*8] =
292 DstMem | SrcNone | ModRM | Mov | Stack, 0, 0, 0, 0, 0, 0, 0,
7d858a19 293 [Group3_Byte*8] =
7d5993d6 294 ByteOp | SrcImm | DstMem | ModRM, ByteOp | SrcImm | DstMem | ModRM,
dfe11481 295 ByteOp | DstMem | SrcNone | ModRM | Lock, ByteOp | DstMem | SrcNone | ModRM | Lock,
7d858a19
AK		 296 0, 0, 0, 0,
297 [Group3*8] =
7d5993d6 298 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
dfe11481 299 DstMem | SrcNone | ModRM | Lock, DstMem | SrcNone | ModRM | Lock,
7d858a19 300 0, 0, 0, 0,
fd60754e 301 [Group4*8] =
c0e0608c 302 ByteOp | DstMem | SrcNone | ModRM | Lock, ByteOp | DstMem | SrcNone | ModRM | Lock,
fd60754e
AK		 303 0, 0, 0, 0, 0, 0,
304 [Group5*8] =
c0e0608c 305 DstMem | SrcNone | ModRM | Lock, DstMem | SrcNone | ModRM | Lock,
d19292e4 306 SrcMem | ModRM | Stack, 0,
414e6277 307 SrcMem | ModRM | Stack, SrcMemFAddr | ModRM | ImplicitOps,
ea79849d 308 SrcMem | ModRM | Stack, 0,
d95058a1 309 [Group7*8] =
e92805ac 310 0, 0, ModRM | SrcMem | Priv, ModRM | SrcMem | Priv,
16286d08 311 SrcNone | ModRM | DstMem | Mov, 0,
e92805ac 312 SrcMem16 | ModRM | Mov | Priv, SrcMem | ModRM | ByteOp | Priv,
2db2c2eb
GN		 313 [Group8*8] =
314 0, 0, 0, 0,
d380a5e4
GN		 315 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM | Lock,
316 DstMem | SrcImmByte | ModRM | Lock, DstMem | SrcImmByte | ModRM | Lock,
60a29d4e 317 [Group9*8] =
6550e1f1 318 0, DstMem64 | ModRM | Lock, 0, 0, 0, 0, 0, 0,
e09d082c
AK		 319};
320
45ed60b3 321static u32 group2_table[] = {
d95058a1 322 [Group7*8] =
835e6b80 323 SrcNone | ModRM | Priv, 0, 0, SrcNone | ModRM | Priv,
16286d08 324 SrcNone | ModRM | DstMem | Mov, 0,
835e6b80 325 SrcMem16 | ModRM | Mov | Priv, 0,
60a29d4e
GN		 326 [Group9*8] =
327 0, 0, 0, 0, 0, 0, 0, 0,
e09d082c
AK		 328};
329
6aa8b732 330/* EFLAGS bit definitions. */
d4c6a154
GN		 331#define EFLG_ID (1<<21)
332#define EFLG_VIP (1<<20)
333#define EFLG_VIF (1<<19)
334#define EFLG_AC (1<<18)
b1d86143
AP		 335#define EFLG_VM (1<<17)
336#define EFLG_RF (1<<16)
d4c6a154
GN		 337#define EFLG_IOPL (3<<12)
338#define EFLG_NT (1<<14)
6aa8b732
AK		 339#define EFLG_OF (1<<11)
340#define EFLG_DF (1<<10)
b1d86143 341#define EFLG_IF (1<<9)
d4c6a154 342#define EFLG_TF (1<<8)
6aa8b732
AK		 343#define EFLG_SF (1<<7)
344#define EFLG_ZF (1<<6)
345#define EFLG_AF (1<<4)
346#define EFLG_PF (1<<2)
347#define EFLG_CF (1<<0)
348
349/*
350 * Instruction emulation:
351 * Most instructions are emulated directly via a fragment of inline assembly
352 * code. This allows us to save/restore EFLAGS and thus very easily pick up
353 * any modified flags.
354 */
355
05b3e0c2 356#if defined(CONFIG_X86_64)
6aa8b732
AK		 357#define _LO32 "k" /* force 32-bit operand */
358#define _STK "%%rsp" /* stack pointer */
359#elif defined(__i386__)
360#define _LO32 "" /* force 32-bit operand */
361#define _STK "%%esp" /* stack pointer */
362#endif
363
364/*
365 * These EFLAGS bits are restored from saved value during emulation, and
366 * any changes are written back to the saved value after emulation.
367 */
368#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
369
370/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 371#define _PRE_EFLAGS(_sav, _msk, _tmp) \
372 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
373 "movl %"_sav",%"_LO32 _tmp"; " \
374 "push %"_tmp"; " \
375 "push %"_tmp"; " \
376 "movl %"_msk",%"_LO32 _tmp"; " \
377 "andl %"_LO32 _tmp",("_STK"); " \
378 "pushf; " \
379 "notl %"_LO32 _tmp"; " \
380 "andl %"_LO32 _tmp",("_STK"); " \
381 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
382 "pop %"_tmp"; " \
383 "orl %"_LO32 _tmp",("_STK"); " \
384 "popf; " \
385 "pop %"_sav"; "
6aa8b732
AK		 386
387/* After executing instruction: write-back necessary bits in EFLAGS. */
388#define _POST_EFLAGS(_sav, _msk, _tmp) \
389 /* _sav |= EFLAGS & _msk; */ \
390 "pushf; " \
391 "pop %"_tmp"; " \
392 "andl %"_msk",%"_LO32 _tmp"; " \
393 "orl %"_LO32 _tmp",%"_sav"; "
394
dda96d8f
AK		 395#ifdef CONFIG_X86_64
396#define ON64(x) x
397#else
398#define ON64(x)
399#endif
400
6b7ad61f
AK		 401#define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix) \
402 do { \
403 __asm__ __volatile__ ( \
404 _PRE_EFLAGS("0", "4", "2") \
405 _op _suffix " %"_x"3,%1; " \
406 _POST_EFLAGS("0", "4", "2") \
407 : "=m" (_eflags), "=m" ((_dst).val), \
408 "=&r" (_tmp) \
409 : _y ((_src).val), "i" (EFLAGS_MASK)); \
f3fd92fb 410 } while (0)
6b7ad61f
AK		 411
412
6aa8b732
AK		 413/* Raw emulation: instruction has two explicit operands. */
414#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 415 do { \
416 unsigned long _tmp; \
417 \
418 switch ((_dst).bytes) { \
419 case 2: \
420 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w"); \
421 break; \
422 case 4: \
423 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l"); \
424 break; \
425 case 8: \
426 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q")); \
427 break; \
428 } \
6aa8b732
AK		 429 } while (0)
430
431#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
432 do { \
6b7ad61f 433 unsigned long _tmp; \
d77c26fc 434 switch ((_dst).bytes) { \
6aa8b732 435 case 1: \
6b7ad61f 436 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b"); \
6aa8b732
AK		 437 break; \
438 default: \
439 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
440 _wx, _wy, _lx, _ly, _qx, _qy); \
441 break; \
442 } \
443 } while (0)
444
445/* Source operand is byte-sized and may be restricted to just %cl. */
446#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
447 __emulate_2op(_op, _src, _dst, _eflags, \
448 "b", "c", "b", "c", "b", "c", "b", "c")
449
450/* Source operand is byte, word, long or quad sized. */
451#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
452 __emulate_2op(_op, _src, _dst, _eflags, \
453 "b", "q", "w", "r", _LO32, "r", "", "r")
454
455/* Source operand is word, long or quad sized. */
456#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
457 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
458 "w", "r", _LO32, "r", "", "r")
459
d175226a
GT		 460/* Instruction has three operands and one operand is stored in ECX register */
461#define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
462 do { \
463 unsigned long _tmp; \
464 _type _clv = (_cl).val; \
465 _type _srcv = (_src).val; \
466 _type _dstv = (_dst).val; \
467 \
468 __asm__ __volatile__ ( \
469 _PRE_EFLAGS("0", "5", "2") \
470 _op _suffix " %4,%1 \n" \
471 _POST_EFLAGS("0", "5", "2") \
472 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
473 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
474 ); \
475 \
476 (_cl).val = (unsigned long) _clv; \
477 (_src).val = (unsigned long) _srcv; \
478 (_dst).val = (unsigned long) _dstv; \
479 } while (0)
480
481#define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
482 do { \
483 switch ((_dst).bytes) { \
484 case 2: \
485 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
486 "w", unsigned short); \
487 break; \
488 case 4: \
489 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
490 "l", unsigned int); \
491 break; \
492 case 8: \
493 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
494 "q", unsigned long)); \
495 break; \
496 } \
497 } while (0)
498
dda96d8f 499#define __emulate_1op(_op, _dst, _eflags, _suffix) \
6aa8b732
AK		 500 do { \
501 unsigned long _tmp; \
502 \
dda96d8f
AK		 503 __asm__ __volatile__ ( \
504 _PRE_EFLAGS("0", "3", "2") \
505 _op _suffix " %1; " \
506 _POST_EFLAGS("0", "3", "2") \
507 : "=m" (_eflags), "+m" ((_dst).val), \
508 "=&r" (_tmp) \
509 : "i" (EFLAGS_MASK)); \
510 } while (0)
511
512/* Instruction has only one explicit operand (no source operand). */
513#define emulate_1op(_op, _dst, _eflags) \
514 do { \
d77c26fc 515 switch ((_dst).bytes) { \
dda96d8f
AK		 516 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
517 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
518 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
519 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
6aa8b732
AK		 520 } \
521 } while (0)
522
6aa8b732
AK		 523/* Fetch next part of the instruction being emulated. */
524#define insn_fetch(_type, _size, _eip) \
525({ unsigned long _x; \
62266869 526 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
af5b4f7f 527 if (rc != X86EMUL_CONTINUE) \
6aa8b732
AK		 528 goto done; \
529 (_eip) += (_size); \
530 (_type)_x; \
531})
532
414e6277
GN		 533#define insn_fetch_arr(_arr, _size, _eip) \
534({ rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size)); \
535 if (rc != X86EMUL_CONTINUE) \
536 goto done; \
537 (_eip) += (_size); \
538})
539
ddcb2885
HH		 540static inline unsigned long ad_mask(struct decode_cache *c)
541{
542 return (1UL << (c->ad_bytes << 3)) - 1;
543}
544
6aa8b732 545/* Access/update address held in a register, based on addressing mode. */
e4706772
HH		 546static inline unsigned long
547address_mask(struct decode_cache *c, unsigned long reg)
548{
549 if (c->ad_bytes == sizeof(unsigned long))
550 return reg;
551 else
552 return reg & ad_mask(c);
553}
554
555static inline unsigned long
556register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
557{
558 return base + address_mask(c, reg);
559}
560
7a957275
HH		 561static inline void
562register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
563{
564 if (c->ad_bytes == sizeof(unsigned long))
565 *reg += inc;
566 else
567 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
568}
6aa8b732 569
7a957275
HH		 570static inline void jmp_rel(struct decode_cache *c, int rel)
571{
572 register_address_increment(c, &c->eip, rel);
573}
098c937b 574
7a5b56df
AK		 575static void set_seg_override(struct decode_cache *c, int seg)
576{
577 c->has_seg_override = true;
578 c->seg_override = seg;
579}
580
79168fd1
GN		 581static unsigned long seg_base(struct x86_emulate_ctxt *ctxt,
582 struct x86_emulate_ops *ops, int seg)
7a5b56df
AK		 583{
584 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
585 return 0;
586
79168fd1 587 return ops->get_cached_segment_base(seg, ctxt->vcpu);
7a5b56df
AK		 588}
589
590static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt,
79168fd1 591 struct x86_emulate_ops *ops,
7a5b56df
AK		 592 struct decode_cache *c)
593{
594 if (!c->has_seg_override)
595 return 0;
596
79168fd1 597 return seg_base(ctxt, ops, c->seg_override);
7a5b56df
AK		 598}
599
79168fd1
GN		 600static unsigned long es_base(struct x86_emulate_ctxt *ctxt,
601 struct x86_emulate_ops *ops)
7a5b56df 602{
79168fd1 603 return seg_base(ctxt, ops, VCPU_SREG_ES);
7a5b56df
AK		 604}
605
79168fd1
GN		 606static unsigned long ss_base(struct x86_emulate_ctxt *ctxt,
607 struct x86_emulate_ops *ops)
7a5b56df 608{
79168fd1 609 return seg_base(ctxt, ops, VCPU_SREG_SS);
7a5b56df
AK		 610}
611
54b8486f
GN		 612static void emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
613 u32 error, bool valid)
614{
615 ctxt->exception = vec;
616 ctxt->error_code = error;
617 ctxt->error_code_valid = valid;
618 ctxt->restart = false;
619}
620
621static void emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
622{
623 emulate_exception(ctxt, GP_VECTOR, err, true);
624}
625
626static void emulate_pf(struct x86_emulate_ctxt *ctxt, unsigned long addr,
627 int err)
628{
629 ctxt->cr2 = addr;
630 emulate_exception(ctxt, PF_VECTOR, err, true);
631}
632
633static void emulate_ud(struct x86_emulate_ctxt *ctxt)
634{
635 emulate_exception(ctxt, UD_VECTOR, 0, false);
636}
637
638static void emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
639{
640 emulate_exception(ctxt, TS_VECTOR, err, true);
641}
642
62266869
AK		 643static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
644 struct x86_emulate_ops *ops,
2fb53ad8 645 unsigned long eip, u8 *dest)
62266869
AK		 646{
647 struct fetch_cache *fc = &ctxt->decode.fetch;
648 int rc;
2fb53ad8 649 int size, cur_size;
62266869 650
2fb53ad8
AK		 651 if (eip == fc->end) {
652 cur_size = fc->end - fc->start;
653 size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip));
654 rc = ops->fetch(ctxt->cs_base + eip, fc->data + cur_size,
655 size, ctxt->vcpu, NULL);
3e2815e9 656 if (rc != X86EMUL_CONTINUE)
62266869 657 return rc;
2fb53ad8 658 fc->end += size;
62266869 659 }
2fb53ad8 660 *dest = fc->data[eip - fc->start];
3e2815e9 661 return X86EMUL_CONTINUE;
62266869
AK		 662}
663
664static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
665 struct x86_emulate_ops *ops,
666 unsigned long eip, void *dest, unsigned size)
667{
3e2815e9 668 int rc;
62266869 669
eb3c79e6 670 /* x86 instructions are limited to 15 bytes. */
063db061 671 if (eip + size - ctxt->eip > 15)
eb3c79e6 672 return X86EMUL_UNHANDLEABLE;
62266869
AK		 673 while (size--) {
674 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
3e2815e9 675 if (rc != X86EMUL_CONTINUE)
62266869
AK		 676 return rc;
677 }
3e2815e9 678 return X86EMUL_CONTINUE;
62266869
AK		 679}
680
1e3c5cb0
RR		 681/*
682 * Given the 'reg' portion of a ModRM byte, and a register block, return a
683 * pointer into the block that addresses the relevant register.
684 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
685 */
686static void *decode_register(u8 modrm_reg, unsigned long *regs,
687 int highbyte_regs)
6aa8b732
AK		 688{
689 void *p;
690
691 p = &regs[modrm_reg];
692 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
693 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
694 return p;
695}
696
697static int read_descriptor(struct x86_emulate_ctxt *ctxt,
698 struct x86_emulate_ops *ops,
699 void *ptr,
700 u16 *size, unsigned long *address, int op_bytes)
701{
702 int rc;
703
704 if (op_bytes == 2)
705 op_bytes = 3;
706 *address = 0;
cebff02b 707 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
1871c602 708 ctxt->vcpu, NULL);
1b30eaa8 709 if (rc != X86EMUL_CONTINUE)
6aa8b732 710 return rc;
cebff02b 711 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
1871c602 712 ctxt->vcpu, NULL);
6aa8b732
AK		 713 return rc;
714}
715
bbe9abbd
NK		 716static int test_cc(unsigned int condition, unsigned int flags)
717{
718 int rc = 0;
719
720 switch ((condition & 15) >> 1) {
721 case 0: /* o */
722 rc |= (flags & EFLG_OF);
723 break;
724 case 1: /* b/c/nae */
725 rc |= (flags & EFLG_CF);
726 break;
727 case 2: /* z/e */
728 rc |= (flags & EFLG_ZF);
729 break;
730 case 3: /* be/na */
731 rc |= (flags & (EFLG_CF|EFLG_ZF));
732 break;
733 case 4: /* s */
734 rc |= (flags & EFLG_SF);
735 break;
736 case 5: /* p/pe */
737 rc |= (flags & EFLG_PF);
738 break;
739 case 7: /* le/ng */
740 rc |= (flags & EFLG_ZF);
741 /* fall through */
742 case 6: /* l/nge */
743 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
744 break;
745 }
746
747 /* Odd condition identifiers (lsb == 1) have inverted sense. */
748 return (!!rc ^ (condition & 1));
749}
750
3c118e24
AK		 751static void decode_register_operand(struct operand *op,
752 struct decode_cache *c,
3c118e24
AK		 753 int inhibit_bytereg)
754{
33615aa9 755 unsigned reg = c->modrm_reg;
9f1ef3f8 756 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 757
758 if (!(c->d & ModRM))
759 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
3c118e24
AK		 760 op->type = OP_REG;
761 if ((c->d & ByteOp) && !inhibit_bytereg) {
33615aa9 762 op->ptr = decode_register(reg, c->regs, highbyte_regs);
3c118e24
AK		 763 op->val = *(u8 *)op->ptr;
764 op->bytes = 1;
765 } else {
33615aa9 766 op->ptr = decode_register(reg, c->regs, 0);
3c118e24
AK		 767 op->bytes = c->op_bytes;
768 switch (op->bytes) {
769 case 2:
770 op->val = *(u16 *)op->ptr;
771 break;
772 case 4:
773 op->val = *(u32 *)op->ptr;
774 break;
775 case 8:
776 op->val = *(u64 *) op->ptr;
777 break;
778 }
779 }
780 op->orig_val = op->val;
781}
782
1c73ef66
AK		 783static int decode_modrm(struct x86_emulate_ctxt *ctxt,
784 struct x86_emulate_ops *ops)
785{
786 struct decode_cache *c = &ctxt->decode;
787 u8 sib;
f5b4edcd 788 int index_reg = 0, base_reg = 0, scale;
3e2815e9 789 int rc = X86EMUL_CONTINUE;
1c73ef66
AK		 790
791 if (c->rex_prefix) {
792 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
793 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
794 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
795 }
796
797 c->modrm = insn_fetch(u8, 1, c->eip);
798 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
799 c->modrm_reg |= (c->modrm & 0x38) >> 3;
800 c->modrm_rm |= (c->modrm & 0x07);
801 c->modrm_ea = 0;
802 c->use_modrm_ea = 1;
803
804 if (c->modrm_mod == 3) {
107d6d2e
AK		 805 c->modrm_ptr = decode_register(c->modrm_rm,
806 c->regs, c->d & ByteOp);
807 c->modrm_val = *(unsigned long *)c->modrm_ptr;
1c73ef66
AK		 808 return rc;
809 }
810
811 if (c->ad_bytes == 2) {
812 unsigned bx = c->regs[VCPU_REGS_RBX];
813 unsigned bp = c->regs[VCPU_REGS_RBP];
814 unsigned si = c->regs[VCPU_REGS_RSI];
815 unsigned di = c->regs[VCPU_REGS_RDI];
816
817 /* 16-bit ModR/M decode. */
818 switch (c->modrm_mod) {
819 case 0:
820 if (c->modrm_rm == 6)
821 c->modrm_ea += insn_fetch(u16, 2, c->eip);
822 break;
823 case 1:
824 c->modrm_ea += insn_fetch(s8, 1, c->eip);
825 break;
826 case 2:
827 c->modrm_ea += insn_fetch(u16, 2, c->eip);
828 break;
829 }
830 switch (c->modrm_rm) {
831 case 0:
832 c->modrm_ea += bx + si;
833 break;
834 case 1:
835 c->modrm_ea += bx + di;
836 break;
837 case 2:
838 c->modrm_ea += bp + si;
839 break;
840 case 3:
841 c->modrm_ea += bp + di;
842 break;
843 case 4:
844 c->modrm_ea += si;
845 break;
846 case 5:
847 c->modrm_ea += di;
848 break;
849 case 6:
850 if (c->modrm_mod != 0)
851 c->modrm_ea += bp;
852 break;
853 case 7:
854 c->modrm_ea += bx;
855 break;
856 }
857 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
858 (c->modrm_rm == 6 && c->modrm_mod != 0))
7a5b56df
AK		 859 if (!c->has_seg_override)
860 set_seg_override(c, VCPU_SREG_SS);
1c73ef66
AK		 861 c->modrm_ea = (u16)c->modrm_ea;
862 } else {
863 /* 32/64-bit ModR/M decode. */
84411d85 864 if ((c->modrm_rm & 7) == 4) {
1c73ef66
AK		 865 sib = insn_fetch(u8, 1, c->eip);
866 index_reg |= (sib >> 3) & 7;
867 base_reg |= sib & 7;
868 scale = sib >> 6;
869
dc71d0f1
AK		 870 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
871 c->modrm_ea += insn_fetch(s32, 4, c->eip);
872 else
1c73ef66 873 c->modrm_ea += c->regs[base_reg];
dc71d0f1 874 if (index_reg != 4)
1c73ef66 875 c->modrm_ea += c->regs[index_reg] << scale;
84411d85
AK		 876 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
877 if (ctxt->mode == X86EMUL_MODE_PROT64)
f5b4edcd 878 c->rip_relative = 1;
84411d85 879 } else
1c73ef66 880 c->modrm_ea += c->regs[c->modrm_rm];
1c73ef66
AK		 881 switch (c->modrm_mod) {
882 case 0:
883 if (c->modrm_rm == 5)
884 c->modrm_ea += insn_fetch(s32, 4, c->eip);
885 break;
886 case 1:
887 c->modrm_ea += insn_fetch(s8, 1, c->eip);
888 break;
889 case 2:
890 c->modrm_ea += insn_fetch(s32, 4, c->eip);
891 break;
892 }
893 }
1c73ef66
AK		 894done:
895 return rc;
896}
897
898static int decode_abs(struct x86_emulate_ctxt *ctxt,
899 struct x86_emulate_ops *ops)
900{
901 struct decode_cache *c = &ctxt->decode;
3e2815e9 902 int rc = X86EMUL_CONTINUE;
1c73ef66
AK		 903
904 switch (c->ad_bytes) {
905 case 2:
906 c->modrm_ea = insn_fetch(u16, 2, c->eip);
907 break;
908 case 4:
909 c->modrm_ea = insn_fetch(u32, 4, c->eip);
910 break;
911 case 8:
912 c->modrm_ea = insn_fetch(u64, 8, c->eip);
913 break;
914 }
915done:
916 return rc;
917}
918
6aa8b732 919int
8b4caf66 920x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
6aa8b732 921{
e4e03ded 922 struct decode_cache *c = &ctxt->decode;
3e2815e9 923 int rc = X86EMUL_CONTINUE;
6aa8b732 924 int mode = ctxt->mode;
52811d7d 925 int def_op_bytes, def_ad_bytes, group, dual;
6aa8b732 926
6aa8b732 927
5cd21917
GN		 928 /* we cannot decode insn before we complete previous rep insn */
929 WARN_ON(ctxt->restart);
930
063db061 931 c->eip = ctxt->eip;
2fb53ad8 932 c->fetch.start = c->fetch.end = c->eip;
79168fd1 933 ctxt->cs_base = seg_base(ctxt, ops, VCPU_SREG_CS);
6aa8b732
AK		 934
935 switch (mode) {
936 case X86EMUL_MODE_REAL:
a0044755 937 case X86EMUL_MODE_VM86:
6aa8b732 938 case X86EMUL_MODE_PROT16:
f21b8bf4 939 def_op_bytes = def_ad_bytes = 2;
6aa8b732
AK		 940 break;
941 case X86EMUL_MODE_PROT32:
f21b8bf4 942 def_op_bytes = def_ad_bytes = 4;
6aa8b732 943 break;
05b3e0c2 944#ifdef CONFIG_X86_64
6aa8b732 945 case X86EMUL_MODE_PROT64:
f21b8bf4
AK		 946 def_op_bytes = 4;
947 def_ad_bytes = 8;
6aa8b732
AK		 948 break;
949#endif
950 default:
951 return -1;
952 }
953
f21b8bf4
AK		 954 c->op_bytes = def_op_bytes;
955 c->ad_bytes = def_ad_bytes;
956
6aa8b732 957 /* Legacy prefixes. */
b4c6abfe 958 for (;;) {
e4e03ded 959 switch (c->b = insn_fetch(u8, 1, c->eip)) {
6aa8b732 960 case 0x66: /* operand-size override */
f21b8bf4
AK		 961 /* switch between 2/4 bytes */
962 c->op_bytes = def_op_bytes ^ 6;
6aa8b732
AK		 963 break;
964 case 0x67: /* address-size override */
965 if (mode == X86EMUL_MODE_PROT64)
e4e03ded 966 /* switch between 4/8 bytes */
f21b8bf4 967 c->ad_bytes = def_ad_bytes ^ 12;
6aa8b732 968 else
e4e03ded 969 /* switch between 2/4 bytes */
f21b8bf4 970 c->ad_bytes = def_ad_bytes ^ 6;
6aa8b732 971 break;
7a5b56df 972 case 0x26: /* ES override */
6aa8b732 973 case 0x2e: /* CS override */
7a5b56df 974 case 0x36: /* SS override */
6aa8b732 975 case 0x3e: /* DS override */
7a5b56df 976 set_seg_override(c, (c->b >> 3) & 3);
6aa8b732
AK		 977 break;
978 case 0x64: /* FS override */
6aa8b732 979 case 0x65: /* GS override */
7a5b56df 980 set_seg_override(c, c->b & 7);
6aa8b732 981 break;
b4c6abfe
LV		 982 case 0x40 ... 0x4f: /* REX */
983 if (mode != X86EMUL_MODE_PROT64)
984 goto done_prefixes;
33615aa9 985 c->rex_prefix = c->b;
b4c6abfe 986 continue;
6aa8b732 987 case 0xf0: /* LOCK */
e4e03ded 988 c->lock_prefix = 1;
6aa8b732 989 break;
ae6200ba 990 case 0xf2: /* REPNE/REPNZ */
90e0a28f
GT		 991 c->rep_prefix = REPNE_PREFIX;
992 break;
6aa8b732 993 case 0xf3: /* REP/REPE/REPZ */
90e0a28f 994 c->rep_prefix = REPE_PREFIX;
6aa8b732 995 break;
6aa8b732
AK		 996 default:
997 goto done_prefixes;
998 }
b4c6abfe
LV		 999
1000 /* Any legacy prefix after a REX prefix nullifies its effect. */
1001
33615aa9 1002 c->rex_prefix = 0;
6aa8b732
AK		 1003 }
1004
1005done_prefixes:
1006
1007 /* REX prefix. */
1c73ef66 1008 if (c->rex_prefix)
33615aa9 1009 if (c->rex_prefix & 8)
e4e03ded 1010 c->op_bytes = 8; /* REX.W */
6aa8b732
AK		 1011
1012 /* Opcode byte(s). */
e4e03ded
LV		 1013 c->d = opcode_table[c->b];
1014 if (c->d == 0) {
6aa8b732 1015 /* Two-byte opcode? */
e4e03ded
LV		 1016 if (c->b == 0x0f) {
1017 c->twobyte = 1;
1018 c->b = insn_fetch(u8, 1, c->eip);
1019 c->d = twobyte_table[c->b];
6aa8b732 1020 }
e09d082c 1021 }
6aa8b732 1022
e09d082c
AK		 1023 if (c->d & Group) {
1024 group = c->d & GroupMask;
52811d7d 1025 dual = c->d & GroupDual;
e09d082c
AK		 1026 c->modrm = insn_fetch(u8, 1, c->eip);
1027 --c->eip;
1028
1029 group = (group << 3) + ((c->modrm >> 3) & 7);
52811d7d
AK		 1030 c->d &= ~(Group | GroupDual | GroupMask);
1031 if (dual && (c->modrm >> 6) == 3)
1032 c->d |= group2_table[group];
e09d082c 1033 else
52811d7d 1034 c->d |= group_table[group];
e09d082c
AK		 1035 }
1036
1037 /* Unrecognised? */
047a4818 1038 if (c->d == 0 || (c->d & Undefined)) {
e09d082c
AK		 1039 DPRINTF("Cannot emulate %02x\n", c->b);
1040 return -1;
6aa8b732
AK		 1041 }
1042
6e3d5dfb
AK		 1043 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
1044 c->op_bytes = 8;
1045
6aa8b732 1046 /* ModRM and SIB bytes. */
1c73ef66
AK		 1047 if (c->d & ModRM)
1048 rc = decode_modrm(ctxt, ops);
1049 else if (c->d & MemAbs)
1050 rc = decode_abs(ctxt, ops);
3e2815e9 1051 if (rc != X86EMUL_CONTINUE)
1c73ef66 1052 goto done;
6aa8b732 1053
7a5b56df
AK		 1054 if (!c->has_seg_override)
1055 set_seg_override(c, VCPU_SREG_DS);
c7e75a3d 1056
7a5b56df 1057 if (!(!c->twobyte && c->b == 0x8d))
79168fd1 1058 c->modrm_ea += seg_override_base(ctxt, ops, c);
c7e75a3d
AK		 1059
1060 if (c->ad_bytes != 8)
1061 c->modrm_ea = (u32)c->modrm_ea;
69f55cb1
GN		 1062
1063 if (c->rip_relative)
1064 c->modrm_ea += c->eip;
1065
6aa8b732
AK		 1066 /*
1067 * Decode and fetch the source operand: register, memory
1068 * or immediate.
1069 */
e4e03ded 1070 switch (c->d & SrcMask) {
6aa8b732
AK		 1071 case SrcNone:
1072 break;
1073 case SrcReg:
9f1ef3f8 1074 decode_register_operand(&c->src, c, 0);
6aa8b732
AK		 1075 break;
1076 case SrcMem16:
e4e03ded 1077 c->src.bytes = 2;
6aa8b732
AK		 1078 goto srcmem_common;
1079 case SrcMem32:
e4e03ded 1080 c->src.bytes = 4;
6aa8b732
AK		 1081 goto srcmem_common;
1082 case SrcMem:
e4e03ded
LV		 1083 c->src.bytes = (c->d & ByteOp) ? 1 :
1084 c->op_bytes;
b85b9ee9 1085 /* Don't fetch the address for invlpg: it could be unmapped. */
d77c26fc 1086 if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7)
b85b9ee9 1087 break;
d77c26fc 1088 srcmem_common:
4e62417b
AJ		 1089 /*
1090 * For instructions with a ModR/M byte, switch to register
1091 * access if Mod = 3.
1092 */
e4e03ded
LV		 1093 if ((c->d & ModRM) && c->modrm_mod == 3) {
1094 c->src.type = OP_REG;
66b85505 1095 c->src.val = c->modrm_val;
107d6d2e 1096 c->src.ptr = c->modrm_ptr;
4e62417b
AJ		 1097 break;
1098 }
e4e03ded 1099 c->src.type = OP_MEM;
69f55cb1
GN		 1100 c->src.ptr = (unsigned long *)c->modrm_ea;
1101 c->src.val = 0;
6aa8b732
AK		 1102 break;
1103 case SrcImm:
c9eaf20f 1104 case SrcImmU:
e4e03ded
LV		 1105 c->src.type = OP_IMM;
1106 c->src.ptr = (unsigned long *)c->eip;
1107 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1108 if (c->src.bytes == 8)
1109 c->src.bytes = 4;
6aa8b732 1110 /* NB. Immediates are sign-extended as necessary. */
e4e03ded 1111 switch (c->src.bytes) {
6aa8b732 1112 case 1:
e4e03ded 1113 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 1114 break;
1115 case 2:
e4e03ded 1116 c->src.val = insn_fetch(s16, 2, c->eip);
6aa8b732
AK		 1117 break;
1118 case 4:
e4e03ded 1119 c->src.val = insn_fetch(s32, 4, c->eip);
6aa8b732
AK		 1120 break;
1121 }
c9eaf20f
AK		 1122 if ((c->d & SrcMask) == SrcImmU) {
1123 switch (c->src.bytes) {
1124 case 1:
1125 c->src.val &= 0xff;
1126 break;
1127 case 2:
1128 c->src.val &= 0xffff;
1129 break;
1130 case 4:
1131 c->src.val &= 0xffffffff;
1132 break;
1133 }
1134 }
6aa8b732
AK		 1135 break;
1136 case SrcImmByte:
341de7e3 1137 case SrcImmUByte:
e4e03ded
LV		 1138 c->src.type = OP_IMM;
1139 c->src.ptr = (unsigned long *)c->eip;
1140 c->src.bytes = 1;
341de7e3
GN		 1141 if ((c->d & SrcMask) == SrcImmByte)
1142 c->src.val = insn_fetch(s8, 1, c->eip);
1143 else
1144 c->src.val = insn_fetch(u8, 1, c->eip);
6aa8b732 1145 break;
5d55f299
WY		 1146 case SrcAcc:
1147 c->src.type = OP_REG;
1148 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1149 c->src.ptr = &c->regs[VCPU_REGS_RAX];
1150 switch (c->src.bytes) {
1151 case 1:
1152 c->src.val = *(u8 *)c->src.ptr;
1153 break;
1154 case 2:
1155 c->src.val = *(u16 *)c->src.ptr;
1156 break;
1157 case 4:
1158 c->src.val = *(u32 *)c->src.ptr;
1159 break;
1160 case 8:
1161 c->src.val = *(u64 *)c->src.ptr;
1162 break;
1163 }
1164 break;
bfcadf83
GT		 1165 case SrcOne:
1166 c->src.bytes = 1;
1167 c->src.val = 1;
1168 break;
a682e354
GN		 1169 case SrcSI:
1170 c->src.type = OP_MEM;
1171 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1172 c->src.ptr = (unsigned long *)
79168fd1 1173 register_address(c, seg_override_base(ctxt, ops, c),
a682e354
GN		 1174 c->regs[VCPU_REGS_RSI]);
1175 c->src.val = 0;
1176 break;
414e6277
GN		 1177 case SrcImmFAddr:
1178 c->src.type = OP_IMM;
1179 c->src.ptr = (unsigned long *)c->eip;
1180 c->src.bytes = c->op_bytes + 2;
1181 insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip);
1182 break;
1183 case SrcMemFAddr:
1184 c->src.type = OP_MEM;
1185 c->src.ptr = (unsigned long *)c->modrm_ea;
1186 c->src.bytes = c->op_bytes + 2;
1187 break;
6aa8b732
AK		 1188 }
1189
0dc8d10f
GT		 1190 /*
1191 * Decode and fetch the second source operand: register, memory
1192 * or immediate.
1193 */
1194 switch (c->d & Src2Mask) {
1195 case Src2None:
1196 break;
1197 case Src2CL:
1198 c->src2.bytes = 1;
1199 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
1200 break;
1201 case Src2ImmByte:
1202 c->src2.type = OP_IMM;
1203 c->src2.ptr = (unsigned long *)c->eip;
1204 c->src2.bytes = 1;
1205 c->src2.val = insn_fetch(u8, 1, c->eip);
1206 break;
1207 case Src2One:
1208 c->src2.bytes = 1;
1209 c->src2.val = 1;
1210 break;
1211 }
1212
038e51de 1213 /* Decode and fetch the destination operand: register or memory. */
e4e03ded 1214 switch (c->d & DstMask) {
038e51de
AK		 1215 case ImplicitOps:
1216 /* Special instructions do their own operand decoding. */
8b4caf66 1217 return 0;
038e51de 1218 case DstReg:
9f1ef3f8 1219 decode_register_operand(&c->dst, c,
3c118e24 1220 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
038e51de
AK		 1221 break;
1222 case DstMem:
6550e1f1 1223 case DstMem64:
e4e03ded 1224 if ((c->d & ModRM) && c->modrm_mod == 3) {
89c69638 1225 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4e03ded 1226 c->dst.type = OP_REG;
66b85505 1227 c->dst.val = c->dst.orig_val = c->modrm_val;
107d6d2e 1228 c->dst.ptr = c->modrm_ptr;
4e62417b
AJ		 1229 break;
1230 }
8b4caf66 1231 c->dst.type = OP_MEM;
69f55cb1 1232 c->dst.ptr = (unsigned long *)c->modrm_ea;
6550e1f1
GN		 1233 if ((c->d & DstMask) == DstMem64)
1234 c->dst.bytes = 8;
1235 else
1236 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
69f55cb1
GN		 1237 c->dst.val = 0;
1238 if (c->d & BitOp) {
1239 unsigned long mask = ~(c->dst.bytes * 8 - 1);
1240
1241 c->dst.ptr = (void *)c->dst.ptr +
1242 (c->src.val & mask) / 8;
1243 }
8b4caf66 1244 break;
9c9fddd0
GT		 1245 case DstAcc:
1246 c->dst.type = OP_REG;
d6d367d6 1247 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
9c9fddd0 1248 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
d6d367d6 1249 switch (c->dst.bytes) {
9c9fddd0
GT		 1250 case 1:
1251 c->dst.val = *(u8 *)c->dst.ptr;
1252 break;
1253 case 2:
1254 c->dst.val = *(u16 *)c->dst.ptr;
1255 break;
1256 case 4:
1257 c->dst.val = *(u32 *)c->dst.ptr;
1258 break;
d6d367d6
GN		 1259 case 8:
1260 c->dst.val = *(u64 *)c->dst.ptr;
1261 break;
9c9fddd0
GT		 1262 }
1263 c->dst.orig_val = c->dst.val;
1264 break;
a682e354
GN		 1265 case DstDI:
1266 c->dst.type = OP_MEM;
1267 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1268 c->dst.ptr = (unsigned long *)
79168fd1 1269 register_address(c, es_base(ctxt, ops),
a682e354
GN		 1270 c->regs[VCPU_REGS_RDI]);
1271 c->dst.val = 0;
1272 break;
8b4caf66
LV		 1273 }
1274
1275done:
1276 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
1277}
1278
9de41573
GN		 1279static int read_emulated(struct x86_emulate_ctxt *ctxt,
1280 struct x86_emulate_ops *ops,
1281 unsigned long addr, void *dest, unsigned size)
1282{
1283 int rc;
1284 struct read_cache *mc = &ctxt->decode.mem_read;
8fe681e9 1285 u32 err;
9de41573
GN		 1286
1287 while (size) {
1288 int n = min(size, 8u);
1289 size -= n;
1290 if (mc->pos < mc->end)
1291 goto read_cached;
1292
8fe681e9
GN		 1293 rc = ops->read_emulated(addr, mc->data + mc->end, n, &err,
1294 ctxt->vcpu);
1295 if (rc == X86EMUL_PROPAGATE_FAULT)
54b8486f 1296 emulate_pf(ctxt, addr, err);
9de41573
GN		 1297 if (rc != X86EMUL_CONTINUE)
1298 return rc;
1299 mc->end += n;
1300
1301 read_cached:
1302 memcpy(dest, mc->data + mc->pos, n);
1303 mc->pos += n;
1304 dest += n;
1305 addr += n;
1306 }
1307 return X86EMUL_CONTINUE;
1308}
1309
7b262e90
GN		 1310static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
1311 struct x86_emulate_ops *ops,
1312 unsigned int size, unsigned short port,
1313 void *dest)
1314{
1315 struct read_cache *rc = &ctxt->decode.io_read;
1316
1317 if (rc->pos == rc->end) { /* refill pio read ahead */
1318 struct decode_cache *c = &ctxt->decode;
1319 unsigned int in_page, n;
1320 unsigned int count = c->rep_prefix ?
1321 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1;
1322 in_page = (ctxt->eflags & EFLG_DF) ?
1323 offset_in_page(c->regs[VCPU_REGS_RDI]) :
1324 PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]);
1325 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1326 count);
1327 if (n == 0)
1328 n = 1;
1329 rc->pos = rc->end = 0;
1330 if (!ops->pio_in_emulated(size, port, rc->data, n, ctxt->vcpu))
1331 return 0;
1332 rc->end = n * size;
1333 }
1334
1335 memcpy(dest, rc->data + rc->pos, size);
1336 rc->pos += size;
1337 return 1;
1338}
1339
38ba30ba
GN		 1340static u32 desc_limit_scaled(struct desc_struct *desc)
1341{
1342 u32 limit = get_desc_limit(desc);
1343
1344 return desc->g ? (limit << 12) | 0xfff : limit;
1345}
1346
1347static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
1348 struct x86_emulate_ops *ops,
1349 u16 selector, struct desc_ptr *dt)
1350{
1351 if (selector & 1 << 2) {
1352 struct desc_struct desc;
1353 memset (dt, 0, sizeof *dt);
1354 if (!ops->get_cached_descriptor(&desc, VCPU_SREG_LDTR, ctxt->vcpu))
1355 return;
1356
1357 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1358 dt->address = get_desc_base(&desc);
1359 } else
1360 ops->get_gdt(dt, ctxt->vcpu);
1361}
1362
1363/* allowed just for 8 bytes segments */
1364static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1365 struct x86_emulate_ops *ops,
1366 u16 selector, struct desc_struct *desc)
1367{
1368 struct desc_ptr dt;
1369 u16 index = selector >> 3;
1370 int ret;
1371 u32 err;
1372 ulong addr;
1373
1374 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
1375
1376 if (dt.size < index * 8 + 7) {
54b8486f 1377 emulate_gp(ctxt, selector & 0xfffc);
38ba30ba
GN		 1378 return X86EMUL_PROPAGATE_FAULT;
1379 }
1380 addr = dt.address + index * 8;
1381 ret = ops->read_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
1382 if (ret == X86EMUL_PROPAGATE_FAULT)
54b8486f 1383 emulate_pf(ctxt, addr, err);
38ba30ba
GN		 1384
1385 return ret;
1386}
1387
1388/* allowed just for 8 bytes segments */
1389static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1390 struct x86_emulate_ops *ops,
1391 u16 selector, struct desc_struct *desc)
1392{
1393 struct desc_ptr dt;
1394 u16 index = selector >> 3;
1395 u32 err;
1396 ulong addr;
1397 int ret;
1398
1399 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
1400
1401 if (dt.size < index * 8 + 7) {
54b8486f 1402 emulate_gp(ctxt, selector & 0xfffc);
38ba30ba
GN		 1403 return X86EMUL_PROPAGATE_FAULT;
1404 }
1405
1406 addr = dt.address + index * 8;
1407 ret = ops->write_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
1408 if (ret == X86EMUL_PROPAGATE_FAULT)
54b8486f 1409 emulate_pf(ctxt, addr, err);
38ba30ba
GN		 1410
1411 return ret;
1412}
1413
1414static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1415 struct x86_emulate_ops *ops,
1416 u16 selector, int seg)
1417{
1418 struct desc_struct seg_desc;
1419 u8 dpl, rpl, cpl;
1420 unsigned err_vec = GP_VECTOR;
1421 u32 err_code = 0;
1422 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1423 int ret;
1424
1425 memset(&seg_desc, 0, sizeof seg_desc);
1426
1427 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1428 || ctxt->mode == X86EMUL_MODE_REAL) {
1429 /* set real mode segment descriptor */
1430 set_desc_base(&seg_desc, selector << 4);
1431 set_desc_limit(&seg_desc, 0xffff);
1432 seg_desc.type = 3;
1433 seg_desc.p = 1;
1434 seg_desc.s = 1;
1435 goto load;
1436 }
1437
1438 /* NULL selector is not valid for TR, CS and SS */
1439 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
1440 && null_selector)
1441 goto exception;
1442
1443 /* TR should be in GDT only */
1444 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1445 goto exception;
1446
1447 if (null_selector) /* for NULL selector skip all following checks */
1448 goto load;
1449
1450 ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc);
1451 if (ret != X86EMUL_CONTINUE)
1452 return ret;
1453
1454 err_code = selector & 0xfffc;
1455 err_vec = GP_VECTOR;
1456
1457 /* can't load system descriptor into segment selecor */
1458 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1459 goto exception;
1460
1461 if (!seg_desc.p) {
1462 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1463 goto exception;
1464 }
1465
1466 rpl = selector & 3;
1467 dpl = seg_desc.dpl;
1468 cpl = ops->cpl(ctxt->vcpu);
1469
1470 switch (seg) {
1471 case VCPU_SREG_SS:
1472 /*
1473 * segment is not a writable data segment or segment
1474 * selector's RPL != CPL or segment selector's RPL != CPL
1475 */
1476 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1477 goto exception;
1478 break;
1479 case VCPU_SREG_CS:
1480 if (!(seg_desc.type & 8))
1481 goto exception;
1482
1483 if (seg_desc.type & 4) {
1484 /* conforming */
1485 if (dpl > cpl)
1486 goto exception;
1487 } else {
1488 /* nonconforming */
1489 if (rpl > cpl || dpl != cpl)
1490 goto exception;
1491 }
1492 /* CS(RPL) <- CPL */
1493 selector = (selector & 0xfffc) | cpl;
1494 break;
1495 case VCPU_SREG_TR:
1496 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1497 goto exception;
1498 break;
1499 case VCPU_SREG_LDTR:
1500 if (seg_desc.s || seg_desc.type != 2)
1501 goto exception;
1502 break;
1503 default: /* DS, ES, FS, or GS */
1504 /*
1505 * segment is not a data or readable code segment or
1506 * ((segment is a data or nonconforming code segment)
1507 * and (both RPL and CPL > DPL))
1508 */
1509 if ((seg_desc.type & 0xa) == 0x8 ||
1510 (((seg_desc.type & 0xc) != 0xc) &&
1511 (rpl > dpl && cpl > dpl)))
1512 goto exception;
1513 break;
1514 }
1515
1516 if (seg_desc.s) {
1517 /* mark segment as accessed */
1518 seg_desc.type |= 1;
1519 ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc);
1520 if (ret != X86EMUL_CONTINUE)
1521 return ret;
1522 }
1523load:
1524 ops->set_segment_selector(selector, seg, ctxt->vcpu);
1525 ops->set_cached_descriptor(&seg_desc, seg, ctxt->vcpu);
1526 return X86EMUL_CONTINUE;
1527exception:
54b8486f 1528 emulate_exception(ctxt, err_vec, err_code, true);
38ba30ba
GN		 1529 return X86EMUL_PROPAGATE_FAULT;
1530}
1531
c37eda13
WY		 1532static inline int writeback(struct x86_emulate_ctxt *ctxt,
1533 struct x86_emulate_ops *ops)
1534{
1535 int rc;
1536 struct decode_cache *c = &ctxt->decode;
1537 u32 err;
1538
1539 switch (c->dst.type) {
1540 case OP_REG:
1541 /* The 4-byte case *is* correct:
1542 * in 64-bit mode we zero-extend.
1543 */
1544 switch (c->dst.bytes) {
1545 case 1:
1546 *(u8 *)c->dst.ptr = (u8)c->dst.val;
1547 break;
1548 case 2:
1549 *(u16 *)c->dst.ptr = (u16)c->dst.val;
1550 break;
1551 case 4:
1552 *c->dst.ptr = (u32)c->dst.val;
1553 break; /* 64b: zero-ext */
1554 case 8:
1555 *c->dst.ptr = c->dst.val;
1556 break;
1557 }
1558 break;
1559 case OP_MEM:
1560 if (c->lock_prefix)
1561 rc = ops->cmpxchg_emulated(
1562 (unsigned long)c->dst.ptr,
1563 &c->dst.orig_val,
1564 &c->dst.val,
1565 c->dst.bytes,
1566 &err,
1567 ctxt->vcpu);
1568 else
1569 rc = ops->write_emulated(
1570 (unsigned long)c->dst.ptr,
1571 &c->dst.val,
1572 c->dst.bytes,
1573 &err,
1574 ctxt->vcpu);
1575 if (rc == X86EMUL_PROPAGATE_FAULT)
1576 emulate_pf(ctxt,
1577 (unsigned long)c->dst.ptr, err);
1578 if (rc != X86EMUL_CONTINUE)
1579 return rc;
1580 break;
1581 case OP_NONE:
1582 /* no writeback */
1583 break;
1584 default:
1585 break;
1586 }
1587 return X86EMUL_CONTINUE;
1588}
1589
79168fd1
GN		 1590static inline void emulate_push(struct x86_emulate_ctxt *ctxt,
1591 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1592{
1593 struct decode_cache *c = &ctxt->decode;
1594
1595 c->dst.type = OP_MEM;
1596 c->dst.bytes = c->op_bytes;
1597 c->dst.val = c->src.val;
7a957275 1598 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
79168fd1 1599 c->dst.ptr = (void *) register_address(c, ss_base(ctxt, ops),
8cdbd2c9
LV		 1600 c->regs[VCPU_REGS_RSP]);
1601}
1602
faa5a3ae 1603static int emulate_pop(struct x86_emulate_ctxt *ctxt,
350f69dc
AK		 1604 struct x86_emulate_ops *ops,
1605 void *dest, int len)
8cdbd2c9
LV		 1606{
1607 struct decode_cache *c = &ctxt->decode;
1608 int rc;
1609
79168fd1 1610 rc = read_emulated(ctxt, ops, register_address(c, ss_base(ctxt, ops),
9de41573
GN		 1611 c->regs[VCPU_REGS_RSP]),
1612 dest, len);
b60d513c 1613 if (rc != X86EMUL_CONTINUE)
8cdbd2c9
LV		 1614 return rc;
1615
350f69dc 1616 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
faa5a3ae
AK		 1617 return rc;
1618}
8cdbd2c9 1619
d4c6a154
GN		 1620static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1621 struct x86_emulate_ops *ops,
1622 void *dest, int len)
1623{
1624 int rc;
1625 unsigned long val, change_mask;
1626 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
9c537244 1627 int cpl = ops->cpl(ctxt->vcpu);
d4c6a154
GN		 1628
1629 rc = emulate_pop(ctxt, ops, &val, len);
1630 if (rc != X86EMUL_CONTINUE)
1631 return rc;
1632
1633 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1634 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
1635
1636 switch(ctxt->mode) {
1637 case X86EMUL_MODE_PROT64:
1638 case X86EMUL_MODE_PROT32:
1639 case X86EMUL_MODE_PROT16:
1640 if (cpl == 0)
1641 change_mask |= EFLG_IOPL;
1642 if (cpl <= iopl)
1643 change_mask |= EFLG_IF;
1644 break;
1645 case X86EMUL_MODE_VM86:
1646 if (iopl < 3) {
54b8486f 1647 emulate_gp(ctxt, 0);
d4c6a154
GN		 1648 return X86EMUL_PROPAGATE_FAULT;
1649 }
1650 change_mask |= EFLG_IF;
1651 break;
1652 default: /* real mode */
1653 change_mask |= (EFLG_IOPL | EFLG_IF);
1654 break;
1655 }
1656
1657 *(unsigned long *)dest =
1658 (ctxt->eflags & ~change_mask) | (val & change_mask);
1659
1660 return rc;
1661}
1662
79168fd1
GN		 1663static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt,
1664 struct x86_emulate_ops *ops, int seg)
0934ac9d
MG		 1665{
1666 struct decode_cache *c = &ctxt->decode;
0934ac9d 1667
79168fd1 1668 c->src.val = ops->get_segment_selector(seg, ctxt->vcpu);
0934ac9d 1669
79168fd1 1670 emulate_push(ctxt, ops);
0934ac9d
MG		 1671}
1672
1673static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
1674 struct x86_emulate_ops *ops, int seg)
1675{
1676 struct decode_cache *c = &ctxt->decode;
1677 unsigned long selector;
1678 int rc;
1679
1680 rc = emulate_pop(ctxt, ops, &selector, c->op_bytes);
1b30eaa8 1681 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 1682 return rc;
1683
2e873022 1684 rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg);
0934ac9d
MG		 1685 return rc;
1686}
1687
c37eda13 1688static int emulate_pusha(struct x86_emulate_ctxt *ctxt,
79168fd1 1689 struct x86_emulate_ops *ops)
abcf14b5
MG		 1690{
1691 struct decode_cache *c = &ctxt->decode;
1692 unsigned long old_esp = c->regs[VCPU_REGS_RSP];
c37eda13 1693 int rc = X86EMUL_CONTINUE;
abcf14b5
MG		 1694 int reg = VCPU_REGS_RAX;
1695
1696 while (reg <= VCPU_REGS_RDI) {
1697 (reg == VCPU_REGS_RSP) ?
1698 (c->src.val = old_esp) : (c->src.val = c->regs[reg]);
1699
79168fd1 1700 emulate_push(ctxt, ops);
c37eda13
WY		 1701
1702 rc = writeback(ctxt, ops);
1703 if (rc != X86EMUL_CONTINUE)
1704 return rc;
1705
abcf14b5
MG		 1706 ++reg;
1707 }
c37eda13
WY		 1708
1709 /* Disable writeback. */
1710 c->dst.type = OP_NONE;
1711
1712 return rc;
abcf14b5
MG		 1713}
1714
1715static int emulate_popa(struct x86_emulate_ctxt *ctxt,
1716 struct x86_emulate_ops *ops)
1717{
1718 struct decode_cache *c = &ctxt->decode;
1b30eaa8 1719 int rc = X86EMUL_CONTINUE;
abcf14b5
MG		 1720 int reg = VCPU_REGS_RDI;
1721
1722 while (reg >= VCPU_REGS_RAX) {
1723 if (reg == VCPU_REGS_RSP) {
1724 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1725 c->op_bytes);
1726 --reg;
1727 }
1728
1729 rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes);
1b30eaa8 1730 if (rc != X86EMUL_CONTINUE)
abcf14b5
MG		 1731 break;
1732 --reg;
1733 }
1734 return rc;
1735}
1736
faa5a3ae
AK		 1737static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1738 struct x86_emulate_ops *ops)
1739{
1740 struct decode_cache *c = &ctxt->decode;
faa5a3ae 1741
1b30eaa8 1742 return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
8cdbd2c9
LV		 1743}
1744
05f086f8 1745static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1746{
05f086f8 1747 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1748 switch (c->modrm_reg) {
1749 case 0: /* rol */
05f086f8 1750 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1751 break;
1752 case 1: /* ror */
05f086f8 1753 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1754 break;
1755 case 2: /* rcl */
05f086f8 1756 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1757 break;
1758 case 3: /* rcr */
05f086f8 1759 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1760 break;
1761 case 4: /* sal/shl */
1762 case 6: /* sal/shl */
05f086f8 1763 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1764 break;
1765 case 5: /* shr */
05f086f8 1766 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1767 break;
1768 case 7: /* sar */
05f086f8 1769 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1770 break;
1771 }
1772}
1773
1774static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 1775 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1776{
1777 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1778
1779 switch (c->modrm_reg) {
1780 case 0 ... 1: /* test */
05f086f8 1781 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1782 break;
1783 case 2: /* not */
1784 c->dst.val = ~c->dst.val;
1785 break;
1786 case 3: /* neg */
05f086f8 1787 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1788 break;
1789 default:
aca06a83 1790 return 0;
8cdbd2c9 1791 }
aca06a83 1792 return 1;
8cdbd2c9
LV		 1793}
1794
1795static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
a01af5ec 1796 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1797{
1798 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1799
1800 switch (c->modrm_reg) {
1801 case 0: /* inc */
05f086f8 1802 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1803 break;
1804 case 1: /* dec */
05f086f8 1805 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9 1806 break;
d19292e4
MG		 1807 case 2: /* call near abs */ {
1808 long int old_eip;
1809 old_eip = c->eip;
1810 c->eip = c->src.val;
1811 c->src.val = old_eip;
79168fd1 1812 emulate_push(ctxt, ops);
d19292e4
MG		 1813 break;
1814 }
8cdbd2c9 1815 case 4: /* jmp abs */
fd60754e 1816 c->eip = c->src.val;
8cdbd2c9
LV		 1817 break;
1818 case 6: /* push */
79168fd1 1819 emulate_push(ctxt, ops);
8cdbd2c9 1820 break;
8cdbd2c9 1821 }
1b30eaa8 1822 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1823}
1824
1825static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
69f55cb1 1826 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1827{
1828 struct decode_cache *c = &ctxt->decode;
16518d5a 1829 u64 old = c->dst.orig_val64;
8cdbd2c9
LV		 1830
1831 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1832 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
8cdbd2c9
LV		 1833 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1834 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1835 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 1836 } else {
16518d5a
AK		 1837 c->dst.val64 = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1838 (u32) c->regs[VCPU_REGS_RBX];
8cdbd2c9 1839
05f086f8 1840 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 1841 }
1b30eaa8 1842 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1843}
1844
a77ab5ea
AK		 1845static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1846 struct x86_emulate_ops *ops)
1847{
1848 struct decode_cache *c = &ctxt->decode;
1849 int rc;
1850 unsigned long cs;
1851
1852 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1b30eaa8 1853 if (rc != X86EMUL_CONTINUE)
a77ab5ea
AK		 1854 return rc;
1855 if (c->op_bytes == 4)
1856 c->eip = (u32)c->eip;
1857 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1b30eaa8 1858 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1859 return rc;
2e873022 1860 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 1861 return rc;
1862}
1863
e66bb2cc
AP		 1864static inline void
1865setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
79168fd1
GN		 1866 struct x86_emulate_ops *ops, struct desc_struct *cs,
1867 struct desc_struct *ss)
e66bb2cc 1868{
79168fd1
GN		 1869 memset(cs, 0, sizeof(struct desc_struct));
1870 ops->get_cached_descriptor(cs, VCPU_SREG_CS, ctxt->vcpu);
1871 memset(ss, 0, sizeof(struct desc_struct));
e66bb2cc
AP		 1872
1873 cs->l = 0; /* will be adjusted later */
79168fd1 1874 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 1875 cs->g = 1; /* 4kb granularity */
79168fd1 1876 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1877 cs->type = 0x0b; /* Read, Execute, Accessed */
1878 cs->s = 1;
1879 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 1880 cs->p = 1;
1881 cs->d = 1;
e66bb2cc 1882
79168fd1
GN		 1883 set_desc_base(ss, 0); /* flat segment */
1884 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1885 ss->g = 1; /* 4kb granularity */
1886 ss->s = 1;
1887 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 1888 ss->d = 1; /* 32bit stack segment */
e66bb2cc 1889 ss->dpl = 0;
79168fd1 1890 ss->p = 1;
e66bb2cc
AP		 1891}
1892
1893static int
3fb1b5db 1894emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
e66bb2cc
AP		 1895{
1896 struct decode_cache *c = &ctxt->decode;
79168fd1 1897 struct desc_struct cs, ss;
e66bb2cc 1898 u64 msr_data;
79168fd1 1899 u16 cs_sel, ss_sel;
e66bb2cc
AP		 1900
1901 /* syscall is not available in real mode */
2e901c4c
GN		 1902 if (ctxt->mode == X86EMUL_MODE_REAL ||
1903 ctxt->mode == X86EMUL_MODE_VM86) {
54b8486f 1904 emulate_ud(ctxt);
2e901c4c
GN		 1905 return X86EMUL_PROPAGATE_FAULT;
1906 }
e66bb2cc 1907
79168fd1 1908 setup_syscalls_segments(ctxt, ops, &cs, &ss);
e66bb2cc 1909
3fb1b5db 1910 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
e66bb2cc 1911 msr_data >>= 32;
79168fd1
GN		 1912 cs_sel = (u16)(msr_data & 0xfffc);
1913 ss_sel = (u16)(msr_data + 8);
e66bb2cc
AP		 1914
1915 if (is_long_mode(ctxt->vcpu)) {
79168fd1 1916 cs.d = 0;
e66bb2cc
AP		 1917 cs.l = 1;
1918 }
79168fd1
GN		 1919 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
1920 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
1921 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
1922 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
e66bb2cc
AP		 1923
1924 c->regs[VCPU_REGS_RCX] = c->eip;
1925 if (is_long_mode(ctxt->vcpu)) {
1926#ifdef CONFIG_X86_64
1927 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
1928
3fb1b5db
GN		 1929 ops->get_msr(ctxt->vcpu,
1930 ctxt->mode == X86EMUL_MODE_PROT64 ?
1931 MSR_LSTAR : MSR_CSTAR, &msr_data);
e66bb2cc
AP		 1932 c->eip = msr_data;
1933
3fb1b5db 1934 ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 1935 ctxt->eflags &= ~(msr_data | EFLG_RF);
1936#endif
1937 } else {
1938 /* legacy mode */
3fb1b5db 1939 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
e66bb2cc
AP		 1940 c->eip = (u32)msr_data;
1941
1942 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1943 }
1944
e54cfa97 1945 return X86EMUL_CONTINUE;
e66bb2cc
AP		 1946}
1947
8c604352 1948static int
3fb1b5db 1949emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8c604352
AP		 1950{
1951 struct decode_cache *c = &ctxt->decode;
79168fd1 1952 struct desc_struct cs, ss;
8c604352 1953 u64 msr_data;
79168fd1 1954 u16 cs_sel, ss_sel;
8c604352 1955
a0044755
GN		 1956 /* inject #GP if in real mode */
1957 if (ctxt->mode == X86EMUL_MODE_REAL) {
54b8486f 1958 emulate_gp(ctxt, 0);
2e901c4c 1959 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 1960 }
1961
1962 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1963 * Therefore, we inject an #UD.
1964 */
2e901c4c 1965 if (ctxt->mode == X86EMUL_MODE_PROT64) {
54b8486f 1966 emulate_ud(ctxt);
2e901c4c
GN		 1967 return X86EMUL_PROPAGATE_FAULT;
1968 }
8c604352 1969
79168fd1 1970 setup_syscalls_segments(ctxt, ops, &cs, &ss);
8c604352 1971
3fb1b5db 1972 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 1973 switch (ctxt->mode) {
1974 case X86EMUL_MODE_PROT32:
1975 if ((msr_data & 0xfffc) == 0x0) {
54b8486f 1976 emulate_gp(ctxt, 0);
e54cfa97 1977 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 1978 }
1979 break;
1980 case X86EMUL_MODE_PROT64:
1981 if (msr_data == 0x0) {
54b8486f 1982 emulate_gp(ctxt, 0);
e54cfa97 1983 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 1984 }
1985 break;
1986 }
1987
1988 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 1989 cs_sel = (u16)msr_data;
1990 cs_sel &= ~SELECTOR_RPL_MASK;
1991 ss_sel = cs_sel + 8;
1992 ss_sel &= ~SELECTOR_RPL_MASK;
8c604352
AP		 1993 if (ctxt->mode == X86EMUL_MODE_PROT64
1994 || is_long_mode(ctxt->vcpu)) {
79168fd1 1995 cs.d = 0;
8c604352
AP		 1996 cs.l = 1;
1997 }
1998
79168fd1
GN		 1999 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
2000 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
2001 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
2002 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
8c604352 2003
3fb1b5db 2004 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data);
8c604352
AP		 2005 c->eip = msr_data;
2006
3fb1b5db 2007 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data);
8c604352
AP		 2008 c->regs[VCPU_REGS_RSP] = msr_data;
2009
e54cfa97 2010 return X86EMUL_CONTINUE;
8c604352
AP		 2011}
2012
4668f050 2013static int
3fb1b5db 2014emulate_sysexit(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
4668f050
AP		 2015{
2016 struct decode_cache *c = &ctxt->decode;
79168fd1 2017 struct desc_struct cs, ss;
4668f050
AP		 2018 u64 msr_data;
2019 int usermode;
79168fd1 2020 u16 cs_sel, ss_sel;
4668f050 2021
a0044755
GN		 2022 /* inject #GP if in real mode or Virtual 8086 mode */
2023 if (ctxt->mode == X86EMUL_MODE_REAL ||
2024 ctxt->mode == X86EMUL_MODE_VM86) {
54b8486f 2025 emulate_gp(ctxt, 0);
2e901c4c 2026 return X86EMUL_PROPAGATE_FAULT;
4668f050
AP		 2027 }
2028
79168fd1 2029 setup_syscalls_segments(ctxt, ops, &cs, &ss);
4668f050
AP		 2030
2031 if ((c->rex_prefix & 0x8) != 0x0)
2032 usermode = X86EMUL_MODE_PROT64;
2033 else
2034 usermode = X86EMUL_MODE_PROT32;
2035
2036 cs.dpl = 3;
2037 ss.dpl = 3;
3fb1b5db 2038 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2039 switch (usermode) {
2040 case X86EMUL_MODE_PROT32:
79168fd1 2041 cs_sel = (u16)(msr_data + 16);
4668f050 2042 if ((msr_data & 0xfffc) == 0x0) {
54b8486f 2043 emulate_gp(ctxt, 0);
e54cfa97 2044 return X86EMUL_PROPAGATE_FAULT;
4668f050 2045 }
79168fd1 2046 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2047 break;
2048 case X86EMUL_MODE_PROT64:
79168fd1 2049 cs_sel = (u16)(msr_data + 32);
4668f050 2050 if (msr_data == 0x0) {
54b8486f 2051 emulate_gp(ctxt, 0);
e54cfa97 2052 return X86EMUL_PROPAGATE_FAULT;
4668f050 2053 }
79168fd1
GN		 2054 ss_sel = cs_sel + 8;
2055 cs.d = 0;
4668f050
AP		 2056 cs.l = 1;
2057 break;
2058 }
79168fd1
GN		 2059 cs_sel |= SELECTOR_RPL_MASK;
2060 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2061
79168fd1
GN		 2062 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
2063 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
2064 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
2065 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
4668f050 2066
bdb475a3
GN		 2067 c->eip = c->regs[VCPU_REGS_RDX];
2068 c->regs[VCPU_REGS_RSP] = c->regs[VCPU_REGS_RCX];
4668f050 2069
e54cfa97 2070 return X86EMUL_CONTINUE;
4668f050
AP		 2071}
2072
9c537244
GN		 2073static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt,
2074 struct x86_emulate_ops *ops)
f850e2e6
GN		 2075{
2076 int iopl;
2077 if (ctxt->mode == X86EMUL_MODE_REAL)
2078 return false;
2079 if (ctxt->mode == X86EMUL_MODE_VM86)
2080 return true;
2081 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
9c537244 2082 return ops->cpl(ctxt->vcpu) > iopl;
f850e2e6
GN		 2083}
2084
2085static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
2086 struct x86_emulate_ops *ops,
2087 u16 port, u16 len)
2088{
79168fd1 2089 struct desc_struct tr_seg;
f850e2e6
GN		 2090 int r;
2091 u16 io_bitmap_ptr;
2092 u8 perm, bit_idx = port & 0x7;
2093 unsigned mask = (1 << len) - 1;
2094
79168fd1
GN		 2095 ops->get_cached_descriptor(&tr_seg, VCPU_SREG_TR, ctxt->vcpu);
2096 if (!tr_seg.p)
f850e2e6 2097 return false;
79168fd1 2098 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2099 return false;
79168fd1
GN		 2100 r = ops->read_std(get_desc_base(&tr_seg) + 102, &io_bitmap_ptr, 2,
2101 ctxt->vcpu, NULL);
f850e2e6
GN		 2102 if (r != X86EMUL_CONTINUE)
2103 return false;
79168fd1 2104 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2105 return false;
79168fd1
GN		 2106 r = ops->read_std(get_desc_base(&tr_seg) + io_bitmap_ptr + port/8,
2107 &perm, 1, ctxt->vcpu, NULL);
f850e2e6
GN		 2108 if (r != X86EMUL_CONTINUE)
2109 return false;
2110 if ((perm >> bit_idx) & mask)
2111 return false;
2112 return true;
2113}
2114
2115static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
2116 struct x86_emulate_ops *ops,
2117 u16 port, u16 len)
2118{
9c537244 2119 if (emulator_bad_iopl(ctxt, ops))
f850e2e6
GN		 2120 if (!emulator_io_port_access_allowed(ctxt, ops, port, len))
2121 return false;
2122 return true;
2123}
2124
38ba30ba
GN		 2125static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
2126 struct x86_emulate_ops *ops,
2127 struct tss_segment_16 *tss)
2128{
2129 struct decode_cache *c = &ctxt->decode;
2130
2131 tss->ip = c->eip;
2132 tss->flag = ctxt->eflags;
2133 tss->ax = c->regs[VCPU_REGS_RAX];
2134 tss->cx = c->regs[VCPU_REGS_RCX];
2135 tss->dx = c->regs[VCPU_REGS_RDX];
2136 tss->bx = c->regs[VCPU_REGS_RBX];
2137 tss->sp = c->regs[VCPU_REGS_RSP];
2138 tss->bp = c->regs[VCPU_REGS_RBP];
2139 tss->si = c->regs[VCPU_REGS_RSI];
2140 tss->di = c->regs[VCPU_REGS_RDI];
2141
2142 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
2143 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2144 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
2145 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
2146 tss->ldt = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
2147}
2148
2149static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
2150 struct x86_emulate_ops *ops,
2151 struct tss_segment_16 *tss)
2152{
2153 struct decode_cache *c = &ctxt->decode;
2154 int ret;
2155
2156 c->eip = tss->ip;
2157 ctxt->eflags = tss->flag | 2;
2158 c->regs[VCPU_REGS_RAX] = tss->ax;
2159 c->regs[VCPU_REGS_RCX] = tss->cx;
2160 c->regs[VCPU_REGS_RDX] = tss->dx;
2161 c->regs[VCPU_REGS_RBX] = tss->bx;
2162 c->regs[VCPU_REGS_RSP] = tss->sp;
2163 c->regs[VCPU_REGS_RBP] = tss->bp;
2164 c->regs[VCPU_REGS_RSI] = tss->si;
2165 c->regs[VCPU_REGS_RDI] = tss->di;
2166
2167 /*
2168 * SDM says that segment selectors are loaded before segment
2169 * descriptors
2170 */
2171 ops->set_segment_selector(tss->ldt, VCPU_SREG_LDTR, ctxt->vcpu);
2172 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
2173 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
2174 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
2175 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
2176
2177 /*
2178 * Now load segment descriptors. If fault happenes at this stage
2179 * it is handled in a context of new task
2180 */
2181 ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR);
2182 if (ret != X86EMUL_CONTINUE)
2183 return ret;
2184 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2185 if (ret != X86EMUL_CONTINUE)
2186 return ret;
2187 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2188 if (ret != X86EMUL_CONTINUE)
2189 return ret;
2190 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2191 if (ret != X86EMUL_CONTINUE)
2192 return ret;
2193 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2194 if (ret != X86EMUL_CONTINUE)
2195 return ret;
2196
2197 return X86EMUL_CONTINUE;
2198}
2199
2200static int task_switch_16(struct x86_emulate_ctxt *ctxt,
2201 struct x86_emulate_ops *ops,
2202 u16 tss_selector, u16 old_tss_sel,
2203 ulong old_tss_base, struct desc_struct *new_desc)
2204{
2205 struct tss_segment_16 tss_seg;
2206 int ret;
2207 u32 err, new_tss_base = get_desc_base(new_desc);
2208
2209 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2210 &err);
2211 if (ret == X86EMUL_PROPAGATE_FAULT) {
2212 /* FIXME: need to provide precise fault address */
54b8486f 2213 emulate_pf(ctxt, old_tss_base, err);
38ba30ba
GN		 2214 return ret;
2215 }
2216
2217 save_state_to_tss16(ctxt, ops, &tss_seg);
2218
2219 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2220 &err);
2221 if (ret == X86EMUL_PROPAGATE_FAULT) {
2222 /* FIXME: need to provide precise fault address */
54b8486f 2223 emulate_pf(ctxt, old_tss_base, err);
38ba30ba
GN		 2224 return ret;
2225 }
2226
2227 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2228 &err);
2229 if (ret == X86EMUL_PROPAGATE_FAULT) {
2230 /* FIXME: need to provide precise fault address */
54b8486f 2231 emulate_pf(ctxt, new_tss_base, err);
38ba30ba
GN		 2232 return ret;
2233 }
2234
2235 if (old_tss_sel != 0xffff) {
2236 tss_seg.prev_task_link = old_tss_sel;
2237
2238 ret = ops->write_std(new_tss_base,
2239 &tss_seg.prev_task_link,
2240 sizeof tss_seg.prev_task_link,
2241 ctxt->vcpu, &err);
2242 if (ret == X86EMUL_PROPAGATE_FAULT) {
2243 /* FIXME: need to provide precise fault address */
54b8486f 2244 emulate_pf(ctxt, new_tss_base, err);
38ba30ba
GN		 2245 return ret;
2246 }
2247 }
2248
2249 return load_state_from_tss16(ctxt, ops, &tss_seg);
2250}
2251
2252static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
2253 struct x86_emulate_ops *ops,
2254 struct tss_segment_32 *tss)
2255{
2256 struct decode_cache *c = &ctxt->decode;
2257
2258 tss->cr3 = ops->get_cr(3, ctxt->vcpu);
2259 tss->eip = c->eip;
2260 tss->eflags = ctxt->eflags;
2261 tss->eax = c->regs[VCPU_REGS_RAX];
2262 tss->ecx = c->regs[VCPU_REGS_RCX];
2263 tss->edx = c->regs[VCPU_REGS_RDX];
2264 tss->ebx = c->regs[VCPU_REGS_RBX];
2265 tss->esp = c->regs[VCPU_REGS_RSP];
2266 tss->ebp = c->regs[VCPU_REGS_RBP];
2267 tss->esi = c->regs[VCPU_REGS_RSI];
2268 tss->edi = c->regs[VCPU_REGS_RDI];
2269
2270 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
2271 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2272 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
2273 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
2274 tss->fs = ops->get_segment_selector(VCPU_SREG_FS, ctxt->vcpu);
2275 tss->gs = ops->get_segment_selector(VCPU_SREG_GS, ctxt->vcpu);
2276 tss->ldt_selector = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
2277}
2278
2279static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
2280 struct x86_emulate_ops *ops,
2281 struct tss_segment_32 *tss)
2282{
2283 struct decode_cache *c = &ctxt->decode;
2284 int ret;
2285
0f12244f 2286 if (ops->set_cr(3, tss->cr3, ctxt->vcpu)) {
54b8486f 2287 emulate_gp(ctxt, 0);
0f12244f
GN		 2288 return X86EMUL_PROPAGATE_FAULT;
2289 }
38ba30ba
GN		 2290 c->eip = tss->eip;
2291 ctxt->eflags = tss->eflags | 2;
2292 c->regs[VCPU_REGS_RAX] = tss->eax;
2293 c->regs[VCPU_REGS_RCX] = tss->ecx;
2294 c->regs[VCPU_REGS_RDX] = tss->edx;
2295 c->regs[VCPU_REGS_RBX] = tss->ebx;
2296 c->regs[VCPU_REGS_RSP] = tss->esp;
2297 c->regs[VCPU_REGS_RBP] = tss->ebp;
2298 c->regs[VCPU_REGS_RSI] = tss->esi;
2299 c->regs[VCPU_REGS_RDI] = tss->edi;
2300
2301 /*
2302 * SDM says that segment selectors are loaded before segment
2303 * descriptors
2304 */
2305 ops->set_segment_selector(tss->ldt_selector, VCPU_SREG_LDTR, ctxt->vcpu);
2306 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
2307 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
2308 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
2309 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
2310 ops->set_segment_selector(tss->fs, VCPU_SREG_FS, ctxt->vcpu);
2311 ops->set_segment_selector(tss->gs, VCPU_SREG_GS, ctxt->vcpu);
2312
2313 /*
2314 * Now load segment descriptors. If fault happenes at this stage
2315 * it is handled in a context of new task
2316 */
2317 ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR);
2318 if (ret != X86EMUL_CONTINUE)
2319 return ret;
2320 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2321 if (ret != X86EMUL_CONTINUE)
2322 return ret;
2323 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2324 if (ret != X86EMUL_CONTINUE)
2325 return ret;
2326 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2327 if (ret != X86EMUL_CONTINUE)
2328 return ret;
2329 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2330 if (ret != X86EMUL_CONTINUE)
2331 return ret;
2332 ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS);
2333 if (ret != X86EMUL_CONTINUE)
2334 return ret;
2335 ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS);
2336 if (ret != X86EMUL_CONTINUE)
2337 return ret;
2338
2339 return X86EMUL_CONTINUE;
2340}
2341
2342static int task_switch_32(struct x86_emulate_ctxt *ctxt,
2343 struct x86_emulate_ops *ops,
2344 u16 tss_selector, u16 old_tss_sel,
2345 ulong old_tss_base, struct desc_struct *new_desc)
2346{
2347 struct tss_segment_32 tss_seg;
2348 int ret;
2349 u32 err, new_tss_base = get_desc_base(new_desc);
2350
2351 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2352 &err);
2353 if (ret == X86EMUL_PROPAGATE_FAULT) {
2354 /* FIXME: need to provide precise fault address */
54b8486f 2355 emulate_pf(ctxt, old_tss_base, err);
38ba30ba
GN		 2356 return ret;
2357 }
2358
2359 save_state_to_tss32(ctxt, ops, &tss_seg);
2360
2361 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2362 &err);
2363 if (ret == X86EMUL_PROPAGATE_FAULT) {
2364 /* FIXME: need to provide precise fault address */
54b8486f 2365 emulate_pf(ctxt, old_tss_base, err);
38ba30ba
GN		 2366 return ret;
2367 }
2368
2369 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2370 &err);
2371 if (ret == X86EMUL_PROPAGATE_FAULT) {
2372 /* FIXME: need to provide precise fault address */
54b8486f 2373 emulate_pf(ctxt, new_tss_base, err);
38ba30ba
GN		 2374 return ret;
2375 }
2376
2377 if (old_tss_sel != 0xffff) {
2378 tss_seg.prev_task_link = old_tss_sel;
2379
2380 ret = ops->write_std(new_tss_base,
2381 &tss_seg.prev_task_link,
2382 sizeof tss_seg.prev_task_link,
2383 ctxt->vcpu, &err);
2384 if (ret == X86EMUL_PROPAGATE_FAULT) {
2385 /* FIXME: need to provide precise fault address */
54b8486f 2386 emulate_pf(ctxt, new_tss_base, err);
38ba30ba
GN		 2387 return ret;
2388 }
2389 }
2390
2391 return load_state_from_tss32(ctxt, ops, &tss_seg);
2392}
2393
2394static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2395 struct x86_emulate_ops *ops,
2396 u16 tss_selector, int reason,
2397 bool has_error_code, u32 error_code)
38ba30ba
GN		 2398{
2399 struct desc_struct curr_tss_desc, next_tss_desc;
2400 int ret;
2401 u16 old_tss_sel = ops->get_segment_selector(VCPU_SREG_TR, ctxt->vcpu);
2402 ulong old_tss_base =
5951c442 2403 ops->get_cached_segment_base(VCPU_SREG_TR, ctxt->vcpu);
ceffb459 2404 u32 desc_limit;
38ba30ba
GN		 2405
2406 /* FIXME: old_tss_base == ~0 ? */
2407
2408 ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc);
2409 if (ret != X86EMUL_CONTINUE)
2410 return ret;
2411 ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc);
2412 if (ret != X86EMUL_CONTINUE)
2413 return ret;
2414
2415 /* FIXME: check that next_tss_desc is tss */
2416
2417 if (reason != TASK_SWITCH_IRET) {
2418 if ((tss_selector & 3) > next_tss_desc.dpl ||
2419 ops->cpl(ctxt->vcpu) > next_tss_desc.dpl) {
54b8486f 2420 emulate_gp(ctxt, 0);
38ba30ba
GN		 2421 return X86EMUL_PROPAGATE_FAULT;
2422 }
2423 }
2424
ceffb459
GN		 2425 desc_limit = desc_limit_scaled(&next_tss_desc);
2426 if (!next_tss_desc.p ||
2427 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2428 desc_limit < 0x2b)) {
54b8486f 2429 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2430 return X86EMUL_PROPAGATE_FAULT;
2431 }
2432
2433 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2434 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2435 write_segment_descriptor(ctxt, ops, old_tss_sel,
2436 &curr_tss_desc);
2437 }
2438
2439 if (reason == TASK_SWITCH_IRET)
2440 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2441
2442 /* set back link to prev task only if NT bit is set in eflags
2443 note that old_tss_sel is not used afetr this point */
2444 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2445 old_tss_sel = 0xffff;
2446
2447 if (next_tss_desc.type & 8)
2448 ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel,
2449 old_tss_base, &next_tss_desc);
2450 else
2451 ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel,
2452 old_tss_base, &next_tss_desc);
0760d448
JK		 2453 if (ret != X86EMUL_CONTINUE)
2454 return ret;
38ba30ba
GN		 2455
2456 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2457 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2458
2459 if (reason != TASK_SWITCH_IRET) {
2460 next_tss_desc.type |= (1 << 1); /* set busy flag */
2461 write_segment_descriptor(ctxt, ops, tss_selector,
2462 &next_tss_desc);
2463 }
2464
2465 ops->set_cr(0, ops->get_cr(0, ctxt->vcpu) | X86_CR0_TS, ctxt->vcpu);
2466 ops->set_cached_descriptor(&next_tss_desc, VCPU_SREG_TR, ctxt->vcpu);
2467 ops->set_segment_selector(tss_selector, VCPU_SREG_TR, ctxt->vcpu);
2468
e269fb21
JK		 2469 if (has_error_code) {
2470 struct decode_cache *c = &ctxt->decode;
2471
2472 c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2473 c->lock_prefix = 0;
2474 c->src.val = (unsigned long) error_code;
79168fd1 2475 emulate_push(ctxt, ops);
e269fb21
JK		 2476 }
2477
38ba30ba
GN		 2478 return ret;
2479}
2480
2481int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
2482 struct x86_emulate_ops *ops,
e269fb21
JK		 2483 u16 tss_selector, int reason,
2484 bool has_error_code, u32 error_code)
38ba30ba
GN		 2485{
2486 struct decode_cache *c = &ctxt->decode;
2487 int rc;
2488
38ba30ba 2489 c->eip = ctxt->eip;
e269fb21 2490 c->dst.type = OP_NONE;
38ba30ba 2491
e269fb21
JK		 2492 rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason,
2493 has_error_code, error_code);
38ba30ba
GN		 2494
2495 if (rc == X86EMUL_CONTINUE) {
e269fb21 2496 rc = writeback(ctxt, ops);
95c55886
GN		 2497 if (rc == X86EMUL_CONTINUE)
2498 ctxt->eip = c->eip;
38ba30ba
GN		 2499 }
2500
19d04437 2501 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
38ba30ba
GN		 2502}
2503
a682e354 2504static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned long base,
d9271123 2505 int reg, struct operand *op)
a682e354
GN		 2506{
2507 struct decode_cache *c = &ctxt->decode;
2508 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2509
d9271123
GN		 2510 register_address_increment(c, &c->regs[reg], df * op->bytes);
2511 op->ptr = (unsigned long *)register_address(c, base, c->regs[reg]);
a682e354
GN		 2512}
2513
8b4caf66 2514int
1be3aa47 2515x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8b4caf66 2516{
8b4caf66 2517 u64 msr_data;
8b4caf66 2518 struct decode_cache *c = &ctxt->decode;
1b30eaa8 2519 int rc = X86EMUL_CONTINUE;
5cd21917 2520 int saved_dst_type = c->dst.type;
8b4caf66 2521
9de41573 2522 ctxt->decode.mem_read.pos = 0;
310b5d30 2523
1161624f 2524 if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
54b8486f 2525 emulate_ud(ctxt);
1161624f
GN		 2526 goto done;
2527 }
2528
d380a5e4 2529 /* LOCK prefix is allowed only with some instructions */
a41ffb75 2530 if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) {
54b8486f 2531 emulate_ud(ctxt);
d380a5e4
GN		 2532 goto done;
2533 }
2534
e92805ac 2535 /* Privileged instruction can be executed only in CPL=0 */
9c537244 2536 if ((c->d & Priv) && ops->cpl(ctxt->vcpu)) {
54b8486f 2537 emulate_gp(ctxt, 0);
e92805ac
GN		 2538 goto done;
2539 }
2540
b9fa9d6b 2541 if (c->rep_prefix && (c->d & String)) {
5cd21917 2542 ctxt->restart = true;
b9fa9d6b 2543 /* All REP prefixes have the same first termination condition */
c73e197b 2544 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) {
5cd21917
GN		 2545 string_done:
2546 ctxt->restart = false;
95c55886 2547 ctxt->eip = c->eip;
b9fa9d6b
AK		 2548 goto done;
2549 }
2550 /* The second termination condition only applies for REPE
2551 * and REPNE. Test if the repeat string operation prefix is
2552 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
2553 * corresponding termination condition according to:
2554 * - if REPE/REPZ and ZF = 0 then done
2555 * - if REPNE/REPNZ and ZF = 1 then done
2556 */
2557 if ((c->b == 0xa6) || (c->b == 0xa7) ||
5cd21917 2558 (c->b == 0xae) || (c->b == 0xaf)) {
b9fa9d6b 2559 if ((c->rep_prefix == REPE_PREFIX) &&
5cd21917
GN		 2560 ((ctxt->eflags & EFLG_ZF) == 0))
2561 goto string_done;
b9fa9d6b 2562 if ((c->rep_prefix == REPNE_PREFIX) &&
5cd21917
GN		 2563 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))
2564 goto string_done;
b9fa9d6b 2565 }
063db061 2566 c->eip = ctxt->eip;
b9fa9d6b
AK		 2567 }
2568
8b4caf66 2569 if (c->src.type == OP_MEM) {
9de41573 2570 rc = read_emulated(ctxt, ops, (unsigned long)c->src.ptr,
414e6277 2571 c->src.valptr, c->src.bytes);
b60d513c 2572 if (rc != X86EMUL_CONTINUE)
8b4caf66 2573 goto done;
16518d5a 2574 c->src.orig_val64 = c->src.val64;
8b4caf66
LV		 2575 }
2576
e35b7b9c 2577 if (c->src2.type == OP_MEM) {
9de41573
GN		 2578 rc = read_emulated(ctxt, ops, (unsigned long)c->src2.ptr,
2579 &c->src2.val, c->src2.bytes);
e35b7b9c
GN		 2580 if (rc != X86EMUL_CONTINUE)
2581 goto done;
2582 }
2583
8b4caf66
LV		 2584 if ((c->d & DstMask) == ImplicitOps)
2585 goto special_insn;
2586
2587
69f55cb1
GN		 2588 if ((c->dst.type == OP_MEM) && !(c->d & Mov)) {
2589 /* optimisation - avoid slow emulated read if Mov */
9de41573
GN		 2590 rc = read_emulated(ctxt, ops, (unsigned long)c->dst.ptr,
2591 &c->dst.val, c->dst.bytes);
69f55cb1
GN		 2592 if (rc != X86EMUL_CONTINUE)
2593 goto done;
038e51de 2594 }
e4e03ded 2595 c->dst.orig_val = c->dst.val;
038e51de 2596
018a98db
AK		 2597special_insn:
2598
e4e03ded 2599 if (c->twobyte)
6aa8b732
AK		 2600 goto twobyte_insn;
2601
e4e03ded 2602 switch (c->b) {
6aa8b732
AK		 2603 case 0x00 ... 0x05:
2604 add: /* add */
05f086f8 2605 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
6aa8b732 2606 break;
0934ac9d 2607 case 0x06: /* push es */
79168fd1 2608 emulate_push_sreg(ctxt, ops, VCPU_SREG_ES);
0934ac9d
MG		 2609 break;
2610 case 0x07: /* pop es */
0934ac9d 2611 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
1b30eaa8 2612 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 2613 goto done;
2614 break;
6aa8b732
AK		 2615 case 0x08 ... 0x0d:
2616 or: /* or */
05f086f8 2617 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
6aa8b732 2618 break;
0934ac9d 2619 case 0x0e: /* push cs */
79168fd1 2620 emulate_push_sreg(ctxt, ops, VCPU_SREG_CS);
0934ac9d 2621 break;
6aa8b732
AK		 2622 case 0x10 ... 0x15:
2623 adc: /* adc */
05f086f8 2624 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
6aa8b732 2625 break;
0934ac9d 2626 case 0x16: /* push ss */
79168fd1 2627 emulate_push_sreg(ctxt, ops, VCPU_SREG_SS);
0934ac9d
MG		 2628 break;
2629 case 0x17: /* pop ss */
0934ac9d 2630 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
1b30eaa8 2631 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 2632 goto done;
2633 break;
6aa8b732
AK		 2634 case 0x18 ... 0x1d:
2635 sbb: /* sbb */
05f086f8 2636 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
6aa8b732 2637 break;
0934ac9d 2638 case 0x1e: /* push ds */
79168fd1 2639 emulate_push_sreg(ctxt, ops, VCPU_SREG_DS);
0934ac9d
MG		 2640 break;
2641 case 0x1f: /* pop ds */
0934ac9d 2642 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
1b30eaa8 2643 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 2644 goto done;
2645 break;
aa3a816b 2646 case 0x20 ... 0x25:
6aa8b732 2647 and: /* and */
05f086f8 2648 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2649 break;
2650 case 0x28 ... 0x2d:
2651 sub: /* sub */
05f086f8 2652 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2653 break;
2654 case 0x30 ... 0x35:
2655 xor: /* xor */
05f086f8 2656 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2657 break;
2658 case 0x38 ... 0x3d:
2659 cmp: /* cmp */
05f086f8 2660 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
6aa8b732 2661 break;
33615aa9
AK		 2662 case 0x40 ... 0x47: /* inc r16/r32 */
2663 emulate_1op("inc", c->dst, ctxt->eflags);
2664 break;
2665 case 0x48 ... 0x4f: /* dec r16/r32 */
2666 emulate_1op("dec", c->dst, ctxt->eflags);
2667 break;
2668 case 0x50 ... 0x57: /* push reg */
79168fd1 2669 emulate_push(ctxt, ops);
33615aa9
AK		 2670 break;
2671 case 0x58 ... 0x5f: /* pop reg */
2672 pop_instruction:
350f69dc 2673 rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes);
1b30eaa8 2674 if (rc != X86EMUL_CONTINUE)
33615aa9 2675 goto done;
33615aa9 2676 break;
abcf14b5 2677 case 0x60: /* pusha */
c37eda13
WY		 2678 rc = emulate_pusha(ctxt, ops);
2679 if (rc != X86EMUL_CONTINUE)
2680 goto done;
abcf14b5
MG		 2681 break;
2682 case 0x61: /* popa */
2683 rc = emulate_popa(ctxt, ops);
1b30eaa8 2684 if (rc != X86EMUL_CONTINUE)
abcf14b5
MG		 2685 goto done;
2686 break;
6aa8b732 2687 case 0x63: /* movsxd */
8b4caf66 2688 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 2689 goto cannot_emulate;
e4e03ded 2690 c->dst.val = (s32) c->src.val;
6aa8b732 2691 break;
91ed7a0e 2692 case 0x68: /* push imm */
018a98db 2693 case 0x6a: /* push imm8 */
79168fd1 2694 emulate_push(ctxt, ops);
018a98db
AK		 2695 break;
2696 case 0x6c: /* insb */
2697 case 0x6d: /* insw/insd */
7972995b 2698 c->dst.bytes = min(c->dst.bytes, 4u);
f850e2e6 2699 if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX],
7972995b 2700 c->dst.bytes)) {
54b8486f 2701 emulate_gp(ctxt, 0);
f850e2e6
GN		 2702 goto done;
2703 }
7b262e90
GN		 2704 if (!pio_in_emulated(ctxt, ops, c->dst.bytes,
2705 c->regs[VCPU_REGS_RDX], &c->dst.val))
7972995b
GN		 2706 goto done; /* IO is needed, skip writeback */
2707 break;
018a98db
AK		 2708 case 0x6e: /* outsb */
2709 case 0x6f: /* outsw/outsd */
7972995b 2710 c->src.bytes = min(c->src.bytes, 4u);
f850e2e6 2711 if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX],
7972995b 2712 c->src.bytes)) {
54b8486f 2713 emulate_gp(ctxt, 0);
f850e2e6
GN		 2714 goto done;
2715 }
7972995b
GN		 2716 ops->pio_out_emulated(c->src.bytes, c->regs[VCPU_REGS_RDX],
2717 &c->src.val, 1, ctxt->vcpu);
2718
2719 c->dst.type = OP_NONE; /* nothing to writeback */
2720 break;
b2833e3c 2721 case 0x70 ... 0x7f: /* jcc (short) */
018a98db 2722 if (test_cc(c->b, ctxt->eflags))
b2833e3c 2723 jmp_rel(c, c->src.val);
018a98db 2724 break;
6aa8b732 2725 case 0x80 ... 0x83: /* Grp1 */
e4e03ded 2726 switch (c->modrm_reg) {
6aa8b732
AK		 2727 case 0:
2728 goto add;
2729 case 1:
2730 goto or;
2731 case 2:
2732 goto adc;
2733 case 3:
2734 goto sbb;
2735 case 4:
2736 goto and;
2737 case 5:
2738 goto sub;
2739 case 6:
2740 goto xor;
2741 case 7:
2742 goto cmp;
2743 }
2744 break;
2745 case 0x84 ... 0x85:
dfb507c4 2746 test:
05f086f8 2747 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2748 break;
2749 case 0x86 ... 0x87: /* xchg */
b13354f8 2750 xchg:
6aa8b732 2751 /* Write back the register source. */
e4e03ded 2752 switch (c->dst.bytes) {
6aa8b732 2753 case 1:
e4e03ded 2754 *(u8 *) c->src.ptr = (u8) c->dst.val;
6aa8b732
AK		 2755 break;
2756 case 2:
e4e03ded 2757 *(u16 *) c->src.ptr = (u16) c->dst.val;
6aa8b732
AK		 2758 break;
2759 case 4:
e4e03ded 2760 *c->src.ptr = (u32) c->dst.val;
6aa8b732
AK		 2761 break; /* 64b reg: zero-extend */
2762 case 8:
e4e03ded 2763 *c->src.ptr = c->dst.val;
6aa8b732
AK		 2764 break;
2765 }
2766 /*
2767 * Write back the memory destination with implicit LOCK
2768 * prefix.
2769 */
e4e03ded
LV		 2770 c->dst.val = c->src.val;
2771 c->lock_prefix = 1;
6aa8b732 2772 break;
6aa8b732 2773 case 0x88 ... 0x8b: /* mov */
7de75248 2774 goto mov;
79168fd1
GN		 2775 case 0x8c: /* mov r/m, sreg */
2776 if (c->modrm_reg > VCPU_SREG_GS) {
54b8486f 2777 emulate_ud(ctxt);
5e3ae6c5 2778 goto done;
38d5bc6d 2779 }
79168fd1 2780 c->dst.val = ops->get_segment_selector(c->modrm_reg, ctxt->vcpu);
38d5bc6d 2781 break;
7e0b54b1 2782 case 0x8d: /* lea r16/r32, m */
f9b7aab3 2783 c->dst.val = c->modrm_ea;
7e0b54b1 2784 break;
4257198a
GT		 2785 case 0x8e: { /* mov seg, r/m16 */
2786 uint16_t sel;
4257198a
GT		 2787
2788 sel = c->src.val;
8b9f4414 2789
c697518a
GN		 2790 if (c->modrm_reg == VCPU_SREG_CS ||
2791 c->modrm_reg > VCPU_SREG_GS) {
54b8486f 2792 emulate_ud(ctxt);
8b9f4414
GN		 2793 goto done;
2794 }
2795
310b5d30 2796 if (c->modrm_reg == VCPU_SREG_SS)
95cb2295 2797 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
310b5d30 2798
2e873022 2799 rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg);
4257198a
GT		 2800
2801 c->dst.type = OP_NONE; /* Disable writeback. */
2802 break;
2803 }
6aa8b732 2804 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9 2805 rc = emulate_grp1a(ctxt, ops);
1b30eaa8 2806 if (rc != X86EMUL_CONTINUE)
6aa8b732 2807 goto done;
6aa8b732 2808 break;
b13354f8 2809 case 0x90: /* nop / xchg r8,rax */
b8a98945
GN		 2810 if (c->dst.ptr == (unsigned long *)&c->regs[VCPU_REGS_RAX]) {
2811 c->dst.type = OP_NONE; /* nop */
b13354f8
MG		 2812 break;
2813 }
2814 case 0x91 ... 0x97: /* xchg reg,rax */
f0c13ef1
GN		 2815 c->src.type = OP_REG;
2816 c->src.bytes = c->op_bytes;
b13354f8
MG		 2817 c->src.ptr = (unsigned long *) &c->regs[VCPU_REGS_RAX];
2818 c->src.val = *(c->src.ptr);
2819 goto xchg;
fd2a7608 2820 case 0x9c: /* pushf */
05f086f8 2821 c->src.val = (unsigned long) ctxt->eflags;
79168fd1 2822 emulate_push(ctxt, ops);
8cdbd2c9 2823 break;
535eabcf 2824 case 0x9d: /* popf */
2b48cc75 2825 c->dst.type = OP_REG;
05f086f8 2826 c->dst.ptr = (unsigned long *) &ctxt->eflags;
2b48cc75 2827 c->dst.bytes = c->op_bytes;
d4c6a154
GN		 2828 rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes);
2829 if (rc != X86EMUL_CONTINUE)
2830 goto done;
2831 break;
5d55f299 2832 case 0xa0 ... 0xa3: /* mov */
6aa8b732 2833 case 0xa4 ... 0xa5: /* movs */
a682e354 2834 goto mov;
6aa8b732 2835 case 0xa6 ... 0xa7: /* cmps */
d7e5117a 2836 c->dst.type = OP_NONE; /* Disable writeback. */
d7e5117a 2837 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr);
a682e354 2838 goto cmp;
dfb507c4
MG		 2839 case 0xa8 ... 0xa9: /* test ax, imm */
2840 goto test;
6aa8b732 2841 case 0xaa ... 0xab: /* stos */
e4e03ded 2842 c->dst.val = c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 2843 break;
2844 case 0xac ... 0xad: /* lods */
a682e354 2845 goto mov;
6aa8b732
AK		 2846 case 0xae ... 0xaf: /* scas */
2847 DPRINTF("Urk! I don't handle SCAS.\n");
2848 goto cannot_emulate;
a5e2e82b 2849 case 0xb0 ... 0xbf: /* mov r, imm */
615ac125 2850 goto mov;
018a98db
AK		 2851 case 0xc0 ... 0xc1:
2852 emulate_grp2(ctxt);
2853 break;
111de5d6 2854 case 0xc3: /* ret */
cf5de4f8 2855 c->dst.type = OP_REG;
111de5d6 2856 c->dst.ptr = &c->eip;
cf5de4f8 2857 c->dst.bytes = c->op_bytes;
111de5d6 2858 goto pop_instruction;
018a98db
AK		 2859 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
2860 mov:
2861 c->dst.val = c->src.val;
2862 break;
a77ab5ea
AK		 2863 case 0xcb: /* ret far */
2864 rc = emulate_ret_far(ctxt, ops);
1b30eaa8 2865 if (rc != X86EMUL_CONTINUE)
a77ab5ea
AK		 2866 goto done;
2867 break;
018a98db
AK		 2868 case 0xd0 ... 0xd1: /* Grp2 */
2869 c->src.val = 1;
2870 emulate_grp2(ctxt);
2871 break;
2872 case 0xd2 ... 0xd3: /* Grp2 */
2873 c->src.val = c->regs[VCPU_REGS_RCX];
2874 emulate_grp2(ctxt);
2875 break;
a6a3034c
MG		 2876 case 0xe4: /* inb */
2877 case 0xe5: /* in */
cf8f70bf 2878 goto do_io_in;
a6a3034c
MG		 2879 case 0xe6: /* outb */
2880 case 0xe7: /* out */
cf8f70bf 2881 goto do_io_out;
1a52e051 2882 case 0xe8: /* call (near) */ {
d53c4777 2883 long int rel = c->src.val;
e4e03ded 2884 c->src.val = (unsigned long) c->eip;
7a957275 2885 jmp_rel(c, rel);
79168fd1 2886 emulate_push(ctxt, ops);
8cdbd2c9 2887 break;
1a52e051
NK		 2888 }
2889 case 0xe9: /* jmp rel */
954cd36f 2890 goto jmp;
414e6277
GN		 2891 case 0xea: { /* jmp far */
2892 unsigned short sel;
ea79849d 2893 jump_far:
414e6277
GN		 2894 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
2895
2896 if (load_segment_descriptor(ctxt, ops, sel, VCPU_SREG_CS))
c697518a 2897 goto done;
954cd36f 2898
414e6277
GN		 2899 c->eip = 0;
2900 memcpy(&c->eip, c->src.valptr, c->op_bytes);
954cd36f 2901 break;
414e6277 2902 }
954cd36f
GT		 2903 case 0xeb:
2904 jmp: /* jmp rel short */
7a957275 2905 jmp_rel(c, c->src.val);
a01af5ec 2906 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 2907 break;
a6a3034c
MG		 2908 case 0xec: /* in al,dx */
2909 case 0xed: /* in (e/r)ax,dx */
cf8f70bf
GN		 2910 c->src.val = c->regs[VCPU_REGS_RDX];
2911 do_io_in:
2912 c->dst.bytes = min(c->dst.bytes, 4u);
2913 if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) {
54b8486f 2914 emulate_gp(ctxt, 0);
cf8f70bf
GN		 2915 goto done;
2916 }
7b262e90
GN		 2917 if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val,
2918 &c->dst.val))
cf8f70bf
GN		 2919 goto done; /* IO is needed */
2920 break;
ce7a0ad3
WY		 2921 case 0xee: /* out dx,al */
2922 case 0xef: /* out dx,(e/r)ax */
cf8f70bf
GN		 2923 c->src.val = c->regs[VCPU_REGS_RDX];
2924 do_io_out:
2925 c->dst.bytes = min(c->dst.bytes, 4u);
2926 if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) {
54b8486f 2927 emulate_gp(ctxt, 0);
f850e2e6
GN		 2928 goto done;
2929 }
cf8f70bf
GN		 2930 ops->pio_out_emulated(c->dst.bytes, c->src.val, &c->dst.val, 1,
2931 ctxt->vcpu);
2932 c->dst.type = OP_NONE; /* Disable writeback. */
e93f36bc 2933 break;
111de5d6 2934 case 0xf4: /* hlt */
ad312c7c 2935 ctxt->vcpu->arch.halt_request = 1;
19fdfa0d 2936 break;
111de5d6
AK		 2937 case 0xf5: /* cmc */
2938 /* complement carry flag from eflags reg */
2939 ctxt->eflags ^= EFLG_CF;
2940 c->dst.type = OP_NONE; /* Disable writeback. */
2941 break;
018a98db 2942 case 0xf6 ... 0xf7: /* Grp3 */
aca06a83
GN		 2943 if (!emulate_grp3(ctxt, ops))
2944 goto cannot_emulate;
018a98db 2945 break;
111de5d6
AK		 2946 case 0xf8: /* clc */
2947 ctxt->eflags &= ~EFLG_CF;
2948 c->dst.type = OP_NONE; /* Disable writeback. */
2949 break;
2950 case 0xfa: /* cli */
07cbc6c1 2951 if (emulator_bad_iopl(ctxt, ops)) {
54b8486f 2952 emulate_gp(ctxt, 0);
07cbc6c1
WY		 2953 goto done;
2954 } else {
f850e2e6
GN		 2955 ctxt->eflags &= ~X86_EFLAGS_IF;
2956 c->dst.type = OP_NONE; /* Disable writeback. */
2957 }
111de5d6
AK		 2958 break;
2959 case 0xfb: /* sti */
07cbc6c1 2960 if (emulator_bad_iopl(ctxt, ops)) {
54b8486f 2961 emulate_gp(ctxt, 0);
07cbc6c1
WY		 2962 goto done;
2963 } else {
95cb2295 2964 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
f850e2e6
GN		 2965 ctxt->eflags |= X86_EFLAGS_IF;
2966 c->dst.type = OP_NONE; /* Disable writeback. */
2967 }
111de5d6 2968 break;
fb4616f4
MG		 2969 case 0xfc: /* cld */
2970 ctxt->eflags &= ~EFLG_DF;
2971 c->dst.type = OP_NONE; /* Disable writeback. */
2972 break;
2973 case 0xfd: /* std */
2974 ctxt->eflags |= EFLG_DF;
2975 c->dst.type = OP_NONE; /* Disable writeback. */
2976 break;
ea79849d
GN		 2977 case 0xfe: /* Grp4 */
2978 grp45:
018a98db 2979 rc = emulate_grp45(ctxt, ops);
1b30eaa8 2980 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 2981 goto done;
2982 break;
ea79849d
GN		 2983 case 0xff: /* Grp5 */
2984 if (c->modrm_reg == 5)
2985 goto jump_far;
2986 goto grp45;
91269b8f
AK		 2987 default:
2988 goto cannot_emulate;
6aa8b732 2989 }
018a98db
AK		 2990
2991writeback:
2992 rc = writeback(ctxt, ops);
1b30eaa8 2993 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 2994 goto done;
2995
5cd21917
GN		 2996 /*
2997 * restore dst type in case the decoding will be reused
2998 * (happens for string instruction )
2999 */
3000 c->dst.type = saved_dst_type;
3001
a682e354 3002 if ((c->d & SrcMask) == SrcSI)
79168fd1
GN		 3003 string_addr_inc(ctxt, seg_override_base(ctxt, ops, c),
3004 VCPU_REGS_RSI, &c->src);
a682e354
GN		 3005
3006 if ((c->d & DstMask) == DstDI)
79168fd1
GN		 3007 string_addr_inc(ctxt, es_base(ctxt, ops), VCPU_REGS_RDI,
3008 &c->dst);
d9271123 3009
5cd21917 3010 if (c->rep_prefix && (c->d & String)) {
7b262e90 3011 struct read_cache *rc = &ctxt->decode.io_read;
d9271123 3012 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
7b262e90
GN		 3013 /*
3014 * Re-enter guest when pio read ahead buffer is empty or,
3015 * if it is not used, after each 1024 iteration.
3016 */
3017 if ((rc->end == 0 && !(c->regs[VCPU_REGS_RCX] & 0x3ff)) ||
3018 (rc->end != 0 && rc->end == rc->pos))
5cd21917
GN		 3019 ctxt->restart = false;
3020 }
9de41573
GN		 3021 /*
3022 * reset read cache here in case string instruction is restared
3023 * without decoding
3024 */
3025 ctxt->decode.mem_read.end = 0;
95c55886 3026 ctxt->eip = c->eip;
018a98db
AK		 3027
3028done:
cb404fe0 3029 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
6aa8b732
AK		 3030
3031twobyte_insn:
e4e03ded 3032 switch (c->b) {
6aa8b732 3033 case 0x01: /* lgdt, lidt, lmsw */
e4e03ded 3034 switch (c->modrm_reg) {
6aa8b732
AK		 3035 u16 size;
3036 unsigned long address;
3037
aca7f966 3038 case 0: /* vmcall */
e4e03ded 3039 if (c->modrm_mod != 3 || c->modrm_rm != 1)
aca7f966
AL		 3040 goto cannot_emulate;
3041
7aa81cc0 3042 rc = kvm_fix_hypercall(ctxt->vcpu);
1b30eaa8 3043 if (rc != X86EMUL_CONTINUE)
7aa81cc0
AL		 3044 goto done;
3045
33e3885d 3046 /* Let the processor re-execute the fixed hypercall */
063db061 3047 c->eip = ctxt->eip;
16286d08
AK		 3048 /* Disable writeback. */
3049 c->dst.type = OP_NONE;
aca7f966 3050 break;
6aa8b732 3051 case 2: /* lgdt */
e4e03ded
LV		 3052 rc = read_descriptor(ctxt, ops, c->src.ptr,
3053 &size, &address, c->op_bytes);
1b30eaa8 3054 if (rc != X86EMUL_CONTINUE)
6aa8b732
AK		 3055 goto done;
3056 realmode_lgdt(ctxt->vcpu, size, address);
16286d08
AK		 3057 /* Disable writeback. */
3058 c->dst.type = OP_NONE;
6aa8b732 3059 break;
aca7f966 3060 case 3: /* lidt/vmmcall */
2b3d2a20
AK		 3061 if (c->modrm_mod == 3) {
3062 switch (c->modrm_rm) {
3063 case 1:
3064 rc = kvm_fix_hypercall(ctxt->vcpu);
1b30eaa8 3065 if (rc != X86EMUL_CONTINUE)
2b3d2a20
AK		 3066 goto done;
3067 break;
3068 default:
3069 goto cannot_emulate;
3070 }
aca7f966 3071 } else {
e4e03ded 3072 rc = read_descriptor(ctxt, ops, c->src.ptr,
aca7f966 3073 &size, &address,
e4e03ded 3074 c->op_bytes);
1b30eaa8 3075 if (rc != X86EMUL_CONTINUE)
aca7f966
AL		 3076 goto done;
3077 realmode_lidt(ctxt->vcpu, size, address);
3078 }
16286d08
AK		 3079 /* Disable writeback. */
3080 c->dst.type = OP_NONE;
6aa8b732
AK		 3081 break;
3082 case 4: /* smsw */
16286d08 3083 c->dst.bytes = 2;
52a46617 3084 c->dst.val = ops->get_cr(0, ctxt->vcpu);
6aa8b732
AK		 3085 break;
3086 case 6: /* lmsw */
93a152be
GN		 3087 ops->set_cr(0, (ops->get_cr(0, ctxt->vcpu) & ~0x0ful) |
3088 (c->src.val & 0x0f), ctxt->vcpu);
dc7457ea 3089 c->dst.type = OP_NONE;
6aa8b732 3090 break;
6e1e5ffe 3091 case 5: /* not defined */
54b8486f 3092 emulate_ud(ctxt);
6e1e5ffe 3093 goto done;
6aa8b732 3094 case 7: /* invlpg*/
69f55cb1 3095 emulate_invlpg(ctxt->vcpu, c->modrm_ea);
16286d08
AK		 3096 /* Disable writeback. */
3097 c->dst.type = OP_NONE;
6aa8b732
AK		 3098 break;
3099 default:
3100 goto cannot_emulate;
3101 }
3102 break;
e99f0507 3103 case 0x05: /* syscall */
3fb1b5db 3104 rc = emulate_syscall(ctxt, ops);
e54cfa97
TY		 3105 if (rc != X86EMUL_CONTINUE)
3106 goto done;
e66bb2cc
AP		 3107 else
3108 goto writeback;
e99f0507 3109 break;
018a98db
AK		 3110 case 0x06:
3111 emulate_clts(ctxt->vcpu);
3112 c->dst.type = OP_NONE;
3113 break;
018a98db 3114 case 0x09: /* wbinvd */
f5f48ee1
SY		 3115 kvm_emulate_wbinvd(ctxt->vcpu);
3116 c->dst.type = OP_NONE;
3117 break;
3118 case 0x08: /* invd */
018a98db
AK		 3119 case 0x0d: /* GrpP (prefetch) */
3120 case 0x18: /* Grp16 (prefetch/nop) */
3121 c->dst.type = OP_NONE;
3122 break;
3123 case 0x20: /* mov cr, reg */
6aebfa6e
GN		 3124 switch (c->modrm_reg) {
3125 case 1:
3126 case 5 ... 7:
3127 case 9 ... 15:
54b8486f 3128 emulate_ud(ctxt);
6aebfa6e
GN		 3129 goto done;
3130 }
52a46617 3131 c->regs[c->modrm_rm] = ops->get_cr(c->modrm_reg, ctxt->vcpu);
018a98db
AK		 3132 c->dst.type = OP_NONE; /* no writeback */
3133 break;
6aa8b732 3134 case 0x21: /* mov from dr to reg */
1e470be5
GN		 3135 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3136 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
54b8486f 3137 emulate_ud(ctxt);
1e470be5
GN		 3138 goto done;
3139 }
35aa5375 3140 ops->get_dr(c->modrm_reg, &c->regs[c->modrm_rm], ctxt->vcpu);
a01af5ec 3141 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3142 break;
018a98db 3143 case 0x22: /* mov reg, cr */
0f12244f 3144 if (ops->set_cr(c->modrm_reg, c->modrm_val, ctxt->vcpu)) {
54b8486f 3145 emulate_gp(ctxt, 0);
0f12244f
GN		 3146 goto done;
3147 }
018a98db
AK		 3148 c->dst.type = OP_NONE;
3149 break;
6aa8b732 3150 case 0x23: /* mov from reg to dr */
1e470be5
GN		 3151 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3152 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
54b8486f 3153 emulate_ud(ctxt);
1e470be5
GN		 3154 goto done;
3155 }
35aa5375 3156
338dbc97
GN		 3157 if (ops->set_dr(c->modrm_reg, c->regs[c->modrm_rm] &
3158 ((ctxt->mode == X86EMUL_MODE_PROT64) ?
3159 ~0ULL : ~0U), ctxt->vcpu) < 0) {
3160 /* #UD condition is already handled by the code above */
54b8486f 3161 emulate_gp(ctxt, 0);
338dbc97
GN		 3162 goto done;
3163 }
3164
a01af5ec 3165 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3166 break;
018a98db
AK		 3167 case 0x30:
3168 /* wrmsr */
3169 msr_data = (u32)c->regs[VCPU_REGS_RAX]
3170 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
3fb1b5db 3171 if (ops->set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data)) {
54b8486f 3172 emulate_gp(ctxt, 0);
fd525365 3173 goto done;
018a98db
AK		 3174 }
3175 rc = X86EMUL_CONTINUE;
3176 c->dst.type = OP_NONE;
3177 break;
3178 case 0x32:
3179 /* rdmsr */
3fb1b5db 3180 if (ops->get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data)) {
54b8486f 3181 emulate_gp(ctxt, 0);
fd525365 3182 goto done;
018a98db
AK		 3183 } else {
3184 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
3185 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
3186 }
3187 rc = X86EMUL_CONTINUE;
3188 c->dst.type = OP_NONE;
3189 break;
e99f0507 3190 case 0x34: /* sysenter */
3fb1b5db 3191 rc = emulate_sysenter(ctxt, ops);
e54cfa97
TY		 3192 if (rc != X86EMUL_CONTINUE)
3193 goto done;
8c604352
AP		 3194 else
3195 goto writeback;
e99f0507
AP		 3196 break;
3197 case 0x35: /* sysexit */
3fb1b5db 3198 rc = emulate_sysexit(ctxt, ops);
e54cfa97
TY		 3199 if (rc != X86EMUL_CONTINUE)
3200 goto done;
4668f050
AP		 3201 else
3202 goto writeback;
e99f0507 3203 break;
6aa8b732 3204 case 0x40 ... 0x4f: /* cmov */
e4e03ded 3205 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 3206 if (!test_cc(c->b, ctxt->eflags))
3207 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3208 break;
b2833e3c 3209 case 0x80 ... 0x8f: /* jnz rel, etc*/
018a98db 3210 if (test_cc(c->b, ctxt->eflags))
b2833e3c 3211 jmp_rel(c, c->src.val);
018a98db
AK		 3212 c->dst.type = OP_NONE;
3213 break;
0934ac9d 3214 case 0xa0: /* push fs */
79168fd1 3215 emulate_push_sreg(ctxt, ops, VCPU_SREG_FS);
0934ac9d
MG		 3216 break;
3217 case 0xa1: /* pop fs */
3218 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
1b30eaa8 3219 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 3220 goto done;
3221 break;
7de75248
NK		 3222 case 0xa3:
3223 bt: /* bt */
e4f8e039 3224 c->dst.type = OP_NONE;
e4e03ded
LV		 3225 /* only subword offset */
3226 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3227 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248 3228 break;
9bf8ea42
GT		 3229 case 0xa4: /* shld imm8, r, r/m */
3230 case 0xa5: /* shld cl, r, r/m */
3231 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
3232 break;
0934ac9d 3233 case 0xa8: /* push gs */
79168fd1 3234 emulate_push_sreg(ctxt, ops, VCPU_SREG_GS);
0934ac9d
MG		 3235 break;
3236 case 0xa9: /* pop gs */
3237 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
1b30eaa8 3238 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 3239 goto done;
3240 break;
7de75248
NK		 3241 case 0xab:
3242 bts: /* bts */
e4e03ded
LV		 3243 /* only subword offset */
3244 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3245 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 3246 break;
9bf8ea42
GT		 3247 case 0xac: /* shrd imm8, r, r/m */
3248 case 0xad: /* shrd cl, r, r/m */
3249 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
3250 break;
2a7c5b8b
GC		 3251 case 0xae: /* clflush */
3252 break;
6aa8b732
AK		 3253 case 0xb0 ... 0xb1: /* cmpxchg */
3254 /*
3255 * Save real source value, then compare EAX against
3256 * destination.
3257 */
e4e03ded
LV		 3258 c->src.orig_val = c->src.val;
3259 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 3260 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
3261 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 3262 /* Success: write back to memory. */
e4e03ded 3263 c->dst.val = c->src.orig_val;
6aa8b732
AK		 3264 } else {
3265 /* Failure: write the value we saw to EAX. */
e4e03ded
LV		 3266 c->dst.type = OP_REG;
3267 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 3268 }
3269 break;
6aa8b732
AK		 3270 case 0xb3:
3271 btr: /* btr */
e4e03ded
LV		 3272 /* only subword offset */
3273 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3274 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 3275 break;
6aa8b732 3276 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 3277 c->dst.bytes = c->op_bytes;
3278 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
3279 : (u16) c->src.val;
6aa8b732 3280 break;
6aa8b732 3281 case 0xba: /* Grp8 */
e4e03ded 3282 switch (c->modrm_reg & 3) {
6aa8b732
AK		 3283 case 0:
3284 goto bt;
3285 case 1:
3286 goto bts;
3287 case 2:
3288 goto btr;
3289 case 3:
3290 goto btc;
3291 }
3292 break;
7de75248
NK		 3293 case 0xbb:
3294 btc: /* btc */
e4e03ded
LV		 3295 /* only subword offset */
3296 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3297 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 3298 break;
6aa8b732 3299 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 3300 c->dst.bytes = c->op_bytes;
3301 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
3302 (s16) c->src.val;
6aa8b732 3303 break;
a012e65a 3304 case 0xc3: /* movnti */
e4e03ded
LV		 3305 c->dst.bytes = c->op_bytes;
3306 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
3307 (u64) c->src.val;
a012e65a 3308 break;
6aa8b732 3309 case 0xc7: /* Grp9 (cmpxchg8b) */
69f55cb1 3310 rc = emulate_grp9(ctxt, ops);
1b30eaa8 3311 if (rc != X86EMUL_CONTINUE)
8cdbd2c9
LV		 3312 goto done;
3313 break;
91269b8f
AK		 3314 default:
3315 goto cannot_emulate;
6aa8b732
AK		 3316 }
3317 goto writeback;
3318
3319cannot_emulate:
e4e03ded 3320 DPRINTF("Cannot emulate %02x\n", c->b);
6aa8b732
AK		 3321 return -1;
3322}
Linux 6.x block layer and io_uring tree(s)