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KVM: x86: emulator: update the emulation mode after CR0 write
[linux-2.6-block.git] / arch / x86 / kvm / emulate.c
CommitLineData
20c8ccb1 1// SPDX-License-Identifier: GPL-2.0-only
6aa8b732 2/******************************************************************************
56e82318 3 * emulate.c
6aa8b732
AK		 4 *
5 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
6 *
7 * Copyright (c) 2005 Keir Fraser
8 *
9 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 10 * privileged instructions:
6aa8b732
AK		 11 *
12 * Copyright (C) 2006 Qumranet
9611c187 13 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 14 *
15 * Avi Kivity <avi@qumranet.com>
16 * Yaniv Kamay <yaniv@qumranet.com>
17 *
6aa8b732
AK		 18 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
19 */
20
edf88417 21#include <linux/kvm_host.h>
5fdbf976 22#include "kvm_cache_regs.h"
2f728d66 23#include "kvm_emulate.h"
b7d491e7 24#include <linux/stringify.h>
3db176d5 25#include <asm/debugreg.h>
1a29b5b7 26#include <asm/nospec-branch.h>
3986f65d 27#include <asm/ibt.h>
6aa8b732 28
3eeb3288 29#include "x86.h"
38ba30ba 30#include "tss.h"
d1cd3ce9 31#include "mmu.h"
2d7921c4 32#include "pmu.h"
e99f0507 33
a9945549
AK		 34/*
35 * Operand types
36 */
b1ea50b2
AK		 37#define OpNone 0ull
38#define OpImplicit 1ull /* No generic decode */
39#define OpReg 2ull /* Register */
40#define OpMem 3ull /* Memory */
41#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
42#define OpDI 5ull /* ES:DI/EDI/RDI */
43#define OpMem64 6ull /* Memory, 64-bit */
44#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
45#define OpDX 8ull /* DX register */
4dd6a57d
AK		 46#define OpCL 9ull /* CL register (for shifts) */
47#define OpImmByte 10ull /* 8-bit sign extended immediate */
48#define OpOne 11ull /* Implied 1 */
5e2c6883 49#define OpImm 12ull /* Sign extended up to 32-bit immediate */
0fe59128
AK		 50#define OpMem16 13ull /* Memory operand (16-bit). */
51#define OpMem32 14ull /* Memory operand (32-bit). */
52#define OpImmU 15ull /* Immediate operand, zero extended */
53#define OpSI 16ull /* SI/ESI/RSI */
54#define OpImmFAddr 17ull /* Immediate far address */
55#define OpMemFAddr 18ull /* Far address in memory */
56#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 57#define OpES 20ull /* ES */
58#define OpCS 21ull /* CS */
59#define OpSS 22ull /* SS */
60#define OpDS 23ull /* DS */
61#define OpFS 24ull /* FS */
62#define OpGS 25ull /* GS */
28867cee 63#define OpMem8 26ull /* 8-bit zero extended memory operand */
5e2c6883 64#define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
7fa57952 65#define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */
820207c8
AK		 66#define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */
67#define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */
0fe59128
AK		 68
69#define OpBits 5 /* Width of operand field */
b1ea50b2 70#define OpMask ((1ull << OpBits) - 1)
a9945549 71
6aa8b732
AK		 72/*
73 * Opcode effective-address decode tables.
74 * Note that we only emulate instructions that have at least one memory
75 * operand (excluding implicit stack references). We assume that stack
76 * references and instruction fetches will never occur in special memory
77 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
78 * not be handled.
79 */
80
81/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 82#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 83/* Destination operand type. */
a9945549
AK		 84#define DstShift 1
85#define ImplicitOps (OpImplicit << DstShift)
86#define DstReg (OpReg << DstShift)
87#define DstMem (OpMem << DstShift)
88#define DstAcc (OpAcc << DstShift)
89#define DstDI (OpDI << DstShift)
90#define DstMem64 (OpMem64 << DstShift)
16bebefe 91#define DstMem16 (OpMem16 << DstShift)
a9945549
AK		 92#define DstImmUByte (OpImmUByte << DstShift)
93#define DstDX (OpDX << DstShift)
820207c8 94#define DstAccLo (OpAccLo << DstShift)
a9945549 95#define DstMask (OpMask << DstShift)
6aa8b732 96/* Source operand type. */
0fe59128
AK		 97#define SrcShift 6
98#define SrcNone (OpNone << SrcShift)
99#define SrcReg (OpReg << SrcShift)
100#define SrcMem (OpMem << SrcShift)
101#define SrcMem16 (OpMem16 << SrcShift)
102#define SrcMem32 (OpMem32 << SrcShift)
103#define SrcImm (OpImm << SrcShift)
104#define SrcImmByte (OpImmByte << SrcShift)
105#define SrcOne (OpOne << SrcShift)
106#define SrcImmUByte (OpImmUByte << SrcShift)
107#define SrcImmU (OpImmU << SrcShift)
108#define SrcSI (OpSI << SrcShift)
7fa57952 109#define SrcXLat (OpXLat << SrcShift)
0fe59128
AK		 110#define SrcImmFAddr (OpImmFAddr << SrcShift)
111#define SrcMemFAddr (OpMemFAddr << SrcShift)
112#define SrcAcc (OpAcc << SrcShift)
113#define SrcImmU16 (OpImmU16 << SrcShift)
5e2c6883 114#define SrcImm64 (OpImm64 << SrcShift)
0fe59128 115#define SrcDX (OpDX << SrcShift)
28867cee 116#define SrcMem8 (OpMem8 << SrcShift)
820207c8 117#define SrcAccHi (OpAccHi << SrcShift)
0fe59128 118#define SrcMask (OpMask << SrcShift)
221192bd
MT		 119#define BitOp (1<<11)
120#define MemAbs (1<<12) /* Memory operand is absolute displacement */
121#define String (1<<13) /* String instruction (rep capable) */
122#define Stack (1<<14) /* Stack instruction (push/pop) */
123#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
124#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
125#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
126#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
127#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
045a282c 128#define Escape (5<<15) /* Escape to coprocessor instruction */
39f062ff 129#define InstrDual (6<<15) /* Alternate instruction decoding of mod == 3 */
2276b511 130#define ModeDual (7<<15) /* Different instruction for 32/64 bit */
221192bd 131#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 132/* Generic ModRM decode. */
133#define ModRM (1<<19)
134/* Destination is only written; never read. */
135#define Mov (1<<20)
d8769fed 136/* Misc flags */
8ea7d6ae 137#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
b51e974f 138#define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */
5a506b12 139#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 140#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 141#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 142#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 143#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 144#define No64 (1<<28)
d5ae7ce8 145#define PageTable (1 << 29) /* instruction used to write page table */
0b789eee 146#define NotImpl (1 << 30) /* instruction is not implemented */
0dc8d10f 147/* Source 2 operand type */
0b789eee 148#define Src2Shift (31)
4dd6a57d 149#define Src2None (OpNone << Src2Shift)
ab2c5ce6 150#define Src2Mem (OpMem << Src2Shift)
4dd6a57d
AK		 151#define Src2CL (OpCL << Src2Shift)
152#define Src2ImmByte (OpImmByte << Src2Shift)
153#define Src2One (OpOne << Src2Shift)
154#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 155#define Src2ES (OpES << Src2Shift)
156#define Src2CS (OpCS << Src2Shift)
157#define Src2SS (OpSS << Src2Shift)
158#define Src2DS (OpDS << Src2Shift)
159#define Src2FS (OpFS << Src2Shift)
160#define Src2GS (OpGS << Src2Shift)
4dd6a57d 161#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 162#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
48520187 163#define AlignMask ((u64)7 << 41)
1c11b376 164#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
48520187
RK		 165#define Unaligned ((u64)2 << 41) /* Explicitly unaligned (e.g. MOVDQU) */
166#define Avx ((u64)3 << 41) /* Advanced Vector Extensions */
167#define Aligned16 ((u64)4 << 41) /* Aligned to 16 byte boundary (e.g. FXSAVE) */
e28bbd44 168#define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
b6744dc3 169#define NoWrite ((u64)1 << 45) /* No writeback */
fb32b1ed 170#define SrcWrite ((u64)1 << 46) /* Write back src operand */
9b88ae99 171#define NoMod ((u64)1 << 47) /* Mod field is ignored */
d40a6898
PB		 172#define Intercept ((u64)1 << 48) /* Has valid intercept field */
173#define CheckPerm ((u64)1 << 49) /* Has valid check_perm field */
68efa764 174#define PrivUD ((u64)1 << 51) /* #UD instead of #GP on CPL > 0 */
58b7075d 175#define NearBranch ((u64)1 << 52) /* Near branches */
ed9aad21 176#define No16 ((u64)1 << 53) /* No 16 bit operand */
ab708099 177#define IncSP ((u64)1 << 54) /* SP is incremented before ModRM calc */
0f89b207 178#define TwoMemOp ((u64)1 << 55) /* Instruction has two memory operand */
018d70ff 179#define IsBranch ((u64)1 << 56) /* Instruction is considered a branch. */
6aa8b732 180
820207c8 181#define DstXacc (DstAccLo | SrcAccHi | SrcWrite)
6aa8b732 182
d0e53325
AK		 183#define X2(x...) x, x
184#define X3(x...) X2(x), x
185#define X4(x...) X2(x), X2(x)
186#define X5(x...) X4(x), x
187#define X6(x...) X4(x), X2(x)
188#define X7(x...) X4(x), X3(x)
189#define X8(x...) X4(x), X4(x)
190#define X16(x...) X8(x), X8(x)
83babbca 191
d65b1dee 192struct opcode {
018d70ff
EH		 193 u64 flags;
194 u8 intercept;
195 u8 pad[7];
120df890 196 union {
ef65c889 197 int (*execute)(struct x86_emulate_ctxt *ctxt);
fd0a0d82
MK		 198 const struct opcode *group;
199 const struct group_dual *gdual;
200 const struct gprefix *gprefix;
045a282c 201 const struct escape *esc;
39f062ff 202 const struct instr_dual *idual;
2276b511 203 const struct mode_dual *mdual;
e28bbd44 204 void (*fastop)(struct fastop *fake);
120df890 205 } u;
d09beabd 206 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 207};
208
209struct group_dual {
210 struct opcode mod012[8];
211 struct opcode mod3[8];
d65b1dee
AK		 212};
213
0d7cdee8
AK		 214struct gprefix {
215 struct opcode pfx_no;
216 struct opcode pfx_66;
217 struct opcode pfx_f2;
218 struct opcode pfx_f3;
219};
220
045a282c
GN		 221struct escape {
222 struct opcode op[8];
223 struct opcode high[64];
224};
225
39f062ff
NA		 226struct instr_dual {
227 struct opcode mod012;
228 struct opcode mod3;
229};
230
2276b511
NA		 231struct mode_dual {
232 struct opcode mode32;
233 struct opcode mode64;
234};
235
62bd430e 236#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
62bd430e 237
3dc4bc4f
NA		 238enum x86_transfer_type {
239 X86_TRANSFER_NONE,
240 X86_TRANSFER_CALL_JMP,
241 X86_TRANSFER_RET,
242 X86_TRANSFER_TASK_SWITCH,
243};
244
dd856efa
AK		 245static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
246{
1cca2f8c 247 if (KVM_EMULATOR_BUG_ON(nr >= NR_EMULATOR_GPRS, ctxt))
a5ba67b4 248 nr &= NR_EMULATOR_GPRS - 1;
dfe21e6b 249
dd856efa
AK		 250 if (!(ctxt->regs_valid & (1 << nr))) {
251 ctxt->regs_valid |= 1 << nr;
252 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
253 }
254 return ctxt->_regs[nr];
255}
256
257static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
258{
1cca2f8c 259 if (KVM_EMULATOR_BUG_ON(nr >= NR_EMULATOR_GPRS, ctxt))
a5ba67b4 260 nr &= NR_EMULATOR_GPRS - 1;
dfe21e6b 261
0cbc60d4
SC		 262 BUILD_BUG_ON(sizeof(ctxt->regs_dirty) * BITS_PER_BYTE < NR_EMULATOR_GPRS);
263 BUILD_BUG_ON(sizeof(ctxt->regs_valid) * BITS_PER_BYTE < NR_EMULATOR_GPRS);
264
dd856efa
AK		 265 ctxt->regs_valid |= 1 << nr;
266 ctxt->regs_dirty |= 1 << nr;
267 return &ctxt->_regs[nr];
268}
269
270static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
271{
272 reg_read(ctxt, nr);
273 return reg_write(ctxt, nr);
274}
275
276static void writeback_registers(struct x86_emulate_ctxt *ctxt)
277{
61d9c412 278 unsigned long dirty = ctxt->regs_dirty;
dd856efa
AK		 279 unsigned reg;
280
a5ba67b4 281 for_each_set_bit(reg, &dirty, NR_EMULATOR_GPRS)
dd856efa
AK		 282 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
283}
284
285static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
286{
287 ctxt->regs_dirty = 0;
288 ctxt->regs_valid = 0;
289}
290
6aa8b732
AK		 291/*
292 * These EFLAGS bits are restored from saved value during emulation, and
293 * any changes are written back to the saved value after emulation.
294 */
0efb0440
NA		 295#define EFLAGS_MASK (X86_EFLAGS_OF|X86_EFLAGS_SF|X86_EFLAGS_ZF|X86_EFLAGS_AF|\
296 X86_EFLAGS_PF|X86_EFLAGS_CF)
6aa8b732 297
dda96d8f
AK		 298#ifdef CONFIG_X86_64
299#define ON64(x) x
300#else
301#define ON64(x)
302#endif
303
b78a8552
QC		 304/*
305 * fastop functions have a special calling convention:
306 *
307 * dst: rax (in/out)
308 * src: rdx (in/out)
309 * src2: rcx (in)
310 * flags: rflags (in/out)
311 * ex: rsi (in:fastop pointer, out:zero if exception)
312 *
313 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
314 * different operand sizes can be reached by calculation, rather than a jump
315 * table (which would be bigger than the code).
79629181
PB		 316 *
317 * The 16 byte alignment, considering 5 bytes for the RET thunk, 3 for ENDBR
318 * and 1 for the straight line speculation INT3, leaves 7 bytes for the
319 * body of the function. Currently none is larger than 4.
b78a8552 320 */
3009afc6 321static int fastop(struct x86_emulate_ctxt *ctxt, fastop_t fop);
4d758349 322
79629181
PB		 323#define FASTOP_SIZE 16
324
d99a6ce7 325#define __FOP_FUNC(name) \
1482a082
JP		 326 ".align " __stringify(FASTOP_SIZE) " \n\t" \
327 ".type " name ", @function \n\t" \
6649fa87 328 name ":\n\t" \
3d9606b0
JP		 329 ASM_ENDBR \
330 IBT_NOSEAL(name)
1482a082 331
d99a6ce7
JP		 332#define FOP_FUNC(name) \
333 __FOP_FUNC(#name)
334
335#define __FOP_RET(name) \
c9a34c3f 336 "11: " ASM_RET \
d99a6ce7
JP		 337 ".size " name ", .-" name "\n\t"
338
339#define FOP_RET(name) \
340 __FOP_RET(#name)
b7d491e7 341
af2e140f 342#define __FOP_START(op, align) \
b7d491e7
AK		 343 extern void em_##op(struct fastop *fake); \
344 asm(".pushsection .text, \"ax\" \n\t" \
345 ".global em_" #op " \n\t" \
af2e140f 346 ".align " __stringify(align) " \n\t" \
d99a6ce7 347 "em_" #op ":\n\t"
b7d491e7 348
af2e140f
PZ		 349#define FOP_START(op) __FOP_START(op, FASTOP_SIZE)
350
b7d491e7
AK		 351#define FOP_END \
352 ".popsection")
353
d99a6ce7
JP		 354#define __FOPNOP(name) \
355 __FOP_FUNC(name) \
356 __FOP_RET(name)
357
1482a082 358#define FOPNOP() \
d99a6ce7 359 __FOPNOP(__stringify(__UNIQUE_ID(nop)))
0bdea068 360
b7d491e7 361#define FOP1E(op, dst) \
d99a6ce7
JP		 362 __FOP_FUNC(#op "_" #dst) \
363 "10: " #op " %" #dst " \n\t" \
364 __FOP_RET(#op "_" #dst)
b8c0b6ae
AK		 365
366#define FOP1EEX(op, dst) \
c9a34c3f 367 FOP1E(op, dst) _ASM_EXTABLE_TYPE_REG(10b, 11b, EX_TYPE_ZERO_REG, %%esi)
b7d491e7
AK		 368
369#define FASTOP1(op) \
370 FOP_START(op) \
371 FOP1E(op##b, al) \
372 FOP1E(op##w, ax) \
373 FOP1E(op##l, eax) \
374 ON64(FOP1E(op##q, rax)) \
375 FOP_END
376
b9fa409b
AK		 377/* 1-operand, using src2 (for MUL/DIV r/m) */
378#define FASTOP1SRC2(op, name) \
379 FOP_START(name) \
380 FOP1E(op, cl) \
381 FOP1E(op, cx) \
382 FOP1E(op, ecx) \
383 ON64(FOP1E(op, rcx)) \
384 FOP_END
385
b8c0b6ae
AK		 386/* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */
387#define FASTOP1SRC2EX(op, name) \
388 FOP_START(name) \
389 FOP1EEX(op, cl) \
390 FOP1EEX(op, cx) \
391 FOP1EEX(op, ecx) \
392 ON64(FOP1EEX(op, rcx)) \
393 FOP_END
394
f7857f35 395#define FOP2E(op, dst, src) \
d99a6ce7
JP		 396 __FOP_FUNC(#op "_" #dst "_" #src) \
397 #op " %" #src ", %" #dst " \n\t" \
398 __FOP_RET(#op "_" #dst "_" #src)
f7857f35
AK		 399
400#define FASTOP2(op) \
401 FOP_START(op) \
017da7b6
AK		 402 FOP2E(op##b, al, dl) \
403 FOP2E(op##w, ax, dx) \
404 FOP2E(op##l, eax, edx) \
405 ON64(FOP2E(op##q, rax, rdx)) \
f7857f35
AK		 406 FOP_END
407
11c363ba
AK		 408/* 2 operand, word only */
409#define FASTOP2W(op) \
410 FOP_START(op) \
411 FOPNOP() \
017da7b6
AK		 412 FOP2E(op##w, ax, dx) \
413 FOP2E(op##l, eax, edx) \
414 ON64(FOP2E(op##q, rax, rdx)) \
11c363ba
AK		 415 FOP_END
416
007a3b54
AK		 417/* 2 operand, src is CL */
418#define FASTOP2CL(op) \
419 FOP_START(op) \
420 FOP2E(op##b, al, cl) \
421 FOP2E(op##w, ax, cl) \
422 FOP2E(op##l, eax, cl) \
423 ON64(FOP2E(op##q, rax, cl)) \
424 FOP_END
425
5aca3722
NA		 426/* 2 operand, src and dest are reversed */
427#define FASTOP2R(op, name) \
428 FOP_START(name) \
429 FOP2E(op##b, dl, al) \
430 FOP2E(op##w, dx, ax) \
431 FOP2E(op##l, edx, eax) \
432 ON64(FOP2E(op##q, rdx, rax)) \
433 FOP_END
434
0bdea068 435#define FOP3E(op, dst, src, src2) \
d99a6ce7
JP		 436 __FOP_FUNC(#op "_" #dst "_" #src "_" #src2) \
437 #op " %" #src2 ", %" #src ", %" #dst " \n\t"\
438 __FOP_RET(#op "_" #dst "_" #src "_" #src2)
0bdea068
AK		 439
440/* 3-operand, word-only, src2=cl */
441#define FASTOP3WCL(op) \
442 FOP_START(op) \
443 FOPNOP() \
017da7b6
AK		 444 FOP3E(op##w, ax, dx, cl) \
445 FOP3E(op##l, eax, edx, cl) \
446 ON64(FOP3E(op##q, rax, rdx, cl)) \
0bdea068
AK		 447 FOP_END
448
9ae9feba 449/* Special case for SETcc - 1 instruction per cc */
1482a082 450#define FOP_SETCC(op) \
22472d12 451 FOP_FUNC(op) \
1482a082 452 #op " %al \n\t" \
22472d12 453 FOP_RET(op)
9ae9feba 454
22472d12 455FOP_START(setcc)
9ae9feba
AK		 456FOP_SETCC(seto)
457FOP_SETCC(setno)
458FOP_SETCC(setc)
459FOP_SETCC(setnc)
460FOP_SETCC(setz)
461FOP_SETCC(setnz)
462FOP_SETCC(setbe)
463FOP_SETCC(setnbe)
464FOP_SETCC(sets)
465FOP_SETCC(setns)
466FOP_SETCC(setp)
467FOP_SETCC(setnp)
468FOP_SETCC(setl)
469FOP_SETCC(setnl)
470FOP_SETCC(setle)
471FOP_SETCC(setnle)
472FOP_END;
473
d99a6ce7
JP		 474FOP_START(salc)
475FOP_FUNC(salc)
476"pushf; sbb %al, %al; popf \n\t"
477FOP_RET(salc)
326f578f
PB		 478FOP_END;
479
aabba3c6
RK		 480/*
481 * XXX: inoutclob user must know where the argument is being expanded.
a0a12c3e 482 * Using asm goto would allow us to remove _fault.
aabba3c6
RK		 483 */
484#define asm_safe(insn, inoutclob...) \
485({ \
486 int _fault = 0; \
487 \
488 asm volatile("1:" insn "\n" \
489 "2:\n" \
c9a34c3f
PZ		 490 _ASM_EXTABLE_TYPE_REG(1b, 2b, EX_TYPE_ONE_REG, %[_fault]) \
491 : [_fault] "+r"(_fault) inoutclob ); \
aabba3c6
RK		 492 \
493 _fault ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE; \
494})
495
8a76d7f2
JR		 496static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
497 enum x86_intercept intercept,
498 enum x86_intercept_stage stage)
499{
500 struct x86_instruction_info info = {
501 .intercept = intercept,
9dac77fa
AK		 502 .rep_prefix = ctxt->rep_prefix,
503 .modrm_mod = ctxt->modrm_mod,
504 .modrm_reg = ctxt->modrm_reg,
505 .modrm_rm = ctxt->modrm_rm,
506 .src_val = ctxt->src.val64,
6cbc5f5a 507 .dst_val = ctxt->dst.val64,
9dac77fa
AK		 508 .src_bytes = ctxt->src.bytes,
509 .dst_bytes = ctxt->dst.bytes,
510 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 511 .next_rip = ctxt->eip,
512 };
513
2953538e 514 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 515}
516
f47cfa31
AK		 517static void assign_masked(ulong *dest, ulong src, ulong mask)
518{
519 *dest = (*dest & ~mask) | (src & mask);
520}
521
6fd8e127
NA		 522static void assign_register(unsigned long *reg, u64 val, int bytes)
523{
524 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
525 switch (bytes) {
526 case 1:
527 *(u8 *)reg = (u8)val;
528 break;
529 case 2:
530 *(u16 *)reg = (u16)val;
531 break;
532 case 4:
533 *reg = (u32)val;
534 break; /* 64b: zero-extend */
535 case 8:
536 *reg = val;
537 break;
538 }
539}
540
9dac77fa 541static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 542{
9dac77fa 543 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 544}
545
f47cfa31
AK		 546static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
547{
548 u16 sel;
549 struct desc_struct ss;
550
551 if (ctxt->mode == X86EMUL_MODE_PROT64)
552 return ~0UL;
553 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
554 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
555}
556
612e89f0
AK		 557static int stack_size(struct x86_emulate_ctxt *ctxt)
558{
559 return (__fls(stack_mask(ctxt)) + 1) >> 3;
560}
561
6aa8b732 562/* Access/update address held in a register, based on addressing mode. */
e4706772 563static inline unsigned long
9dac77fa 564address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 565{
9dac77fa 566 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 567 return reg;
568 else
9dac77fa 569 return reg & ad_mask(ctxt);
e4706772
HH		 570}
571
572static inline unsigned long
01485a22 573register_address(struct x86_emulate_ctxt *ctxt, int reg)
e4706772 574{
01485a22 575 return address_mask(ctxt, reg_read(ctxt, reg));
e4706772
HH		 576}
577
5ad105e5
AK		 578static void masked_increment(ulong *reg, ulong mask, int inc)
579{
580 assign_masked(reg, *reg + inc, mask);
581}
582
7a957275 583static inline void
01485a22 584register_address_increment(struct x86_emulate_ctxt *ctxt, int reg, int inc)
7a957275 585{
ee122a71 586 ulong *preg = reg_rmw(ctxt, reg);
5ad105e5 587
ee122a71 588 assign_register(preg, *preg + inc, ctxt->ad_bytes);
5ad105e5
AK		 589}
590
591static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
592{
dd856efa 593 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
7a957275 594}
6aa8b732 595
56697687
AK		 596static u32 desc_limit_scaled(struct desc_struct *desc)
597{
598 u32 limit = get_desc_limit(desc);
599
600 return desc->g ? (limit << 12) | 0xfff : limit;
601}
602
7b105ca2 603static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 604{
605 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
606 return 0;
607
7b105ca2 608 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 609}
610
35d3d4a1
AK		 611static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
612 u32 error, bool valid)
54b8486f 613{
49a1431d
SC		 614 if (KVM_EMULATOR_BUG_ON(vec > 0x1f, ctxt))
615 return X86EMUL_UNHANDLEABLE;
616
da9cb575
AK		 617 ctxt->exception.vector = vec;
618 ctxt->exception.error_code = error;
619 ctxt->exception.error_code_valid = valid;
35d3d4a1 620 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 621}
622
3b88e41a
JR		 623static int emulate_db(struct x86_emulate_ctxt *ctxt)
624{
625 return emulate_exception(ctxt, DB_VECTOR, 0, false);
626}
627
35d3d4a1 628static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 629{
35d3d4a1 630 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 631}
632
618ff15d
AK		 633static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
634{
635 return emulate_exception(ctxt, SS_VECTOR, err, true);
636}
637
35d3d4a1 638static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 639{
35d3d4a1 640 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 641}
642
35d3d4a1 643static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 644{
35d3d4a1 645 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 646}
647
34d1f490
AK		 648static int emulate_de(struct x86_emulate_ctxt *ctxt)
649{
35d3d4a1 650 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 651}
652
1253791d
AK		 653static int emulate_nm(struct x86_emulate_ctxt *ctxt)
654{
655 return emulate_exception(ctxt, NM_VECTOR, 0, false);
656}
657
1aa36616
AK		 658static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
659{
660 u16 selector;
661 struct desc_struct desc;
662
663 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
664 return selector;
665}
666
667static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
668 unsigned seg)
669{
670 u16 dummy;
671 u32 base3;
672 struct desc_struct desc;
673
674 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
675 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
676}
677
f0ed4760
SC		 678static inline u8 ctxt_virt_addr_bits(struct x86_emulate_ctxt *ctxt)
679{
680 return (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_LA57) ? 57 : 48;
681}
682
683static inline bool emul_is_noncanonical_address(u64 la,
684 struct x86_emulate_ctxt *ctxt)
685{
1fb85d06 686 return !__is_canonical_address(la, ctxt_virt_addr_bits(ctxt));
f0ed4760
SC		 687}
688
1c11b376
AK		 689/*
690 * x86 defines three classes of vector instructions: explicitly
691 * aligned, explicitly unaligned, and the rest, which change behaviour
692 * depending on whether they're AVX encoded or not.
693 *
694 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
d3fe959f
RK		 695 * subject to the same check. FXSAVE and FXRSTOR are checked here too as their
696 * 512 bytes of data must be aligned to a 16 byte boundary.
1c11b376 697 */
d3fe959f 698static unsigned insn_alignment(struct x86_emulate_ctxt *ctxt, unsigned size)
1c11b376 699{
48520187 700 u64 alignment = ctxt->d & AlignMask;
1c11b376 701
1c11b376 702 if (likely(size < 16))
d3fe959f 703 return 1;
1c11b376 704
48520187
RK		 705 switch (alignment) {
706 case Unaligned:
707 case Avx:
d3fe959f 708 return 1;
48520187 709 case Aligned16:
d3fe959f 710 return 16;
48520187
RK		 711 case Aligned:
712 default:
d3fe959f 713 return size;
48520187 714 }
1c11b376
AK		 715}
716
d09155d2
PB		 717static __always_inline int __linearize(struct x86_emulate_ctxt *ctxt,
718 struct segmented_address addr,
719 unsigned *max_size, unsigned size,
720 bool write, bool fetch,
d50eaa18 721 enum x86emul_mode mode, ulong *linear)
52fd8b44 722{
618ff15d
AK		 723 struct desc_struct desc;
724 bool usable;
52fd8b44 725 ulong la;
618ff15d 726 u32 lim;
1aa36616 727 u16 sel;
fd8cb433 728 u8 va_bits;
52fd8b44 729
7b105ca2 730 la = seg_base(ctxt, addr.seg) + addr.ea;
fd56e154 731 *max_size = 0;
d50eaa18 732 switch (mode) {
618ff15d 733 case X86EMUL_MODE_PROT64:
0c1d77f4 734 *linear = la;
fd8cb433 735 va_bits = ctxt_virt_addr_bits(ctxt);
1fb85d06 736 if (!__is_canonical_address(la, va_bits))
abc7d8a4 737 goto bad;
fd56e154 738
fd8cb433 739 *max_size = min_t(u64, ~0u, (1ull << va_bits) - la);
fd56e154
PB		 740 if (size > *max_size)
741 goto bad;
618ff15d
AK		 742 break;
743 default:
0c1d77f4 744 *linear = la = (u32)la;
1aa36616
AK		 745 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
746 addr.seg);
618ff15d
AK		 747 if (!usable)
748 goto bad;
58b7825b
GN		 749 /* code segment in protected mode or read-only data segment */
750 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
751 || !(desc.type & 2)) && write)
618ff15d
AK		 752 goto bad;
753 /* unreadable code segment */
3d9b938e 754 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 755 goto bad;
756 lim = desc_limit_scaled(&desc);
997b0412 757 if (!(desc.type & 8) && (desc.type & 4)) {
fc058680 758 /* expand-down segment */
fd56e154 759 if (addr.ea <= lim)
618ff15d
AK		 760 goto bad;
761 lim = desc.d ? 0xffffffff : 0xffff;
618ff15d 762 }
997b0412
PB		 763 if (addr.ea > lim)
764 goto bad;
bac15531
NA		 765 if (lim == 0xffffffff)
766 *max_size = ~0u;
767 else {
768 *max_size = (u64)lim + 1 - addr.ea;
769 if (size > *max_size)
770 goto bad;
771 }
618ff15d
AK		 772 break;
773 }
d3fe959f 774 if (la & (insn_alignment(ctxt, size) - 1))
1c11b376 775 return emulate_gp(ctxt, 0);
52fd8b44 776 return X86EMUL_CONTINUE;
618ff15d
AK		 777bad:
778 if (addr.seg == VCPU_SREG_SS)
3606189f 779 return emulate_ss(ctxt, 0);
618ff15d 780 else
3606189f 781 return emulate_gp(ctxt, 0);
52fd8b44
AK		 782}
783
3d9b938e
NE		 784static int linearize(struct x86_emulate_ctxt *ctxt,
785 struct segmented_address addr,
786 unsigned size, bool write,
787 ulong *linear)
788{
fd56e154 789 unsigned max_size;
d50eaa18
NA		 790 return __linearize(ctxt, addr, &max_size, size, write, false,
791 ctxt->mode, linear);
3d9b938e
NE		 792}
793
d087e0f7 794static inline int assign_eip(struct x86_emulate_ctxt *ctxt, ulong dst)
d50eaa18
NA		 795{
796 ulong linear;
797 int rc;
798 unsigned max_size;
799 struct segmented_address addr = { .seg = VCPU_SREG_CS,
800 .ea = dst };
801
802 if (ctxt->op_bytes != sizeof(unsigned long))
803 addr.ea = dst & ((1UL << (ctxt->op_bytes << 3)) - 1);
d087e0f7 804 rc = __linearize(ctxt, addr, &max_size, 1, false, true, ctxt->mode, &linear);
d50eaa18
NA		 805 if (rc == X86EMUL_CONTINUE)
806 ctxt->_eip = addr.ea;
807 return rc;
808}
809
d087e0f7
ML		 810static inline int emulator_recalc_and_set_mode(struct x86_emulate_ctxt *ctxt)
811{
812 u64 efer;
813 struct desc_struct cs;
814 u16 selector;
815 u32 base3;
816
817 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
818
819 if (!(ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PE)) {
820 /* Real mode. cpu must not have long mode active */
821 if (efer & EFER_LMA)
822 return X86EMUL_UNHANDLEABLE;
823 ctxt->mode = X86EMUL_MODE_REAL;
824 return X86EMUL_CONTINUE;
825 }
826
827 if (ctxt->eflags & X86_EFLAGS_VM) {
828 /* Protected/VM86 mode. cpu must not have long mode active */
829 if (efer & EFER_LMA)
830 return X86EMUL_UNHANDLEABLE;
831 ctxt->mode = X86EMUL_MODE_VM86;
832 return X86EMUL_CONTINUE;
833 }
834
835 if (!ctxt->ops->get_segment(ctxt, &selector, &cs, &base3, VCPU_SREG_CS))
836 return X86EMUL_UNHANDLEABLE;
837
838 if (efer & EFER_LMA) {
839 if (cs.l) {
840 /* Proper long mode */
841 ctxt->mode = X86EMUL_MODE_PROT64;
842 } else if (cs.d) {
843 /* 32 bit compatibility mode*/
844 ctxt->mode = X86EMUL_MODE_PROT32;
845 } else {
846 ctxt->mode = X86EMUL_MODE_PROT16;
847 }
848 } else {
849 /* Legacy 32 bit / 16 bit mode */
850 ctxt->mode = cs.d ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
851 }
852
853 return X86EMUL_CONTINUE;
854}
855
d50eaa18
NA		 856static inline int assign_eip_near(struct x86_emulate_ctxt *ctxt, ulong dst)
857{
d087e0f7 858 return assign_eip(ctxt, dst);
3d9b938e
NE		 859}
860
d087e0f7 861static int assign_eip_far(struct x86_emulate_ctxt *ctxt, ulong dst)
d50eaa18 862{
d087e0f7 863 int rc = emulator_recalc_and_set_mode(ctxt);
d50eaa18 864
d087e0f7
ML		 865 if (rc != X86EMUL_CONTINUE)
866 return rc;
d50eaa18 867
d087e0f7 868 return assign_eip(ctxt, dst);
d50eaa18
NA		 869}
870
871static inline int jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
872{
873 return assign_eip_near(ctxt, ctxt->_eip + rel);
874}
3d9b938e 875
79367a65
PB		 876static int linear_read_system(struct x86_emulate_ctxt *ctxt, ulong linear,
877 void *data, unsigned size)
878{
3c9fa24c 879 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception, true);
79367a65
PB		 880}
881
882static int linear_write_system(struct x86_emulate_ctxt *ctxt,
883 ulong linear, void *data,
884 unsigned int size)
885{
3c9fa24c 886 return ctxt->ops->write_std(ctxt, linear, data, size, &ctxt->exception, true);
79367a65
PB		 887}
888
3ca3ac4d
AK		 889static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
890 struct segmented_address addr,
891 void *data,
892 unsigned size)
893{
9fa088f4
AK		 894 int rc;
895 ulong linear;
896
83b8795a 897 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 898 if (rc != X86EMUL_CONTINUE)
899 return rc;
3c9fa24c 900 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception, false);
3ca3ac4d
AK		 901}
902
129a72a0
SR		 903static int segmented_write_std(struct x86_emulate_ctxt *ctxt,
904 struct segmented_address addr,
905 void *data,
906 unsigned int size)
907{
908 int rc;
909 ulong linear;
910
911 rc = linearize(ctxt, addr, size, true, &linear);
912 if (rc != X86EMUL_CONTINUE)
913 return rc;
3c9fa24c 914 return ctxt->ops->write_std(ctxt, linear, data, size, &ctxt->exception, false);
129a72a0
SR		 915}
916
807941b1 917/*
285ca9e9 918 * Prefetch the remaining bytes of the instruction without crossing page
807941b1
TY		 919 * boundary if they are not in fetch_cache yet.
920 */
9506d57d 921static int __do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, int op_size)
62266869 922{
62266869 923 int rc;
fd56e154 924 unsigned size, max_size;
285ca9e9 925 unsigned long linear;
17052f16 926 int cur_size = ctxt->fetch.end - ctxt->fetch.data;
285ca9e9 927 struct segmented_address addr = { .seg = VCPU_SREG_CS,
17052f16
PB		 928 .ea = ctxt->eip + cur_size };
929
fd56e154
PB		 930 /*
931 * We do not know exactly how many bytes will be needed, and
932 * __linearize is expensive, so fetch as much as possible. We
933 * just have to avoid going beyond the 15 byte limit, the end
934 * of the segment, or the end of the page.
935 *
936 * __linearize is called with size 0 so that it does not do any
937 * boundary check itself. Instead, we use max_size to check
938 * against op_size.
939 */
d50eaa18
NA		 940 rc = __linearize(ctxt, addr, &max_size, 0, false, true, ctxt->mode,
941 &linear);
719d5a9b
PB		 942 if (unlikely(rc != X86EMUL_CONTINUE))
943 return rc;
944
fd56e154 945 size = min_t(unsigned, 15UL ^ cur_size, max_size);
719d5a9b 946 size = min_t(unsigned, size, PAGE_SIZE - offset_in_page(linear));
5cfc7e0f
PB		 947
948 /*
949 * One instruction can only straddle two pages,
950 * and one has been loaded at the beginning of
951 * x86_decode_insn. So, if not enough bytes
952 * still, we must have hit the 15-byte boundary.
953 */
954 if (unlikely(size < op_size))
fd56e154
PB		 955 return emulate_gp(ctxt, 0);
956
17052f16 957 rc = ctxt->ops->fetch(ctxt, linear, ctxt->fetch.end,
285ca9e9
PB		 958 size, &ctxt->exception);
959 if (unlikely(rc != X86EMUL_CONTINUE))
960 return rc;
17052f16 961 ctxt->fetch.end += size;
3e2815e9 962 return X86EMUL_CONTINUE;
62266869
AK		 963}
964
9506d57d
PB		 965static __always_inline int do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt,
966 unsigned size)
62266869 967{
08da44ae
NA		 968 unsigned done_size = ctxt->fetch.end - ctxt->fetch.ptr;
969
970 if (unlikely(done_size < size))
971 return __do_insn_fetch_bytes(ctxt, size - done_size);
9506d57d
PB		 972 else
973 return X86EMUL_CONTINUE;
62266869
AK		 974}
975
67cbc90d 976/* Fetch next part of the instruction being emulated. */
e85a1085 977#define insn_fetch(_type, _ctxt) \
9506d57d 978({ _type _x; \
9506d57d
PB		 979 \
980 rc = do_insn_fetch_bytes(_ctxt, sizeof(_type)); \
67cbc90d
TY		 981 if (rc != X86EMUL_CONTINUE) \
982 goto done; \
9506d57d 983 ctxt->_eip += sizeof(_type); \
8616abc2 984 memcpy(&_x, ctxt->fetch.ptr, sizeof(_type)); \
17052f16 985 ctxt->fetch.ptr += sizeof(_type); \
9506d57d 986 _x; \
67cbc90d
TY		 987})
988
807941b1 989#define insn_fetch_arr(_arr, _size, _ctxt) \
9506d57d 990({ \
9506d57d 991 rc = do_insn_fetch_bytes(_ctxt, _size); \
67cbc90d
TY		 992 if (rc != X86EMUL_CONTINUE) \
993 goto done; \
9506d57d 994 ctxt->_eip += (_size); \
17052f16
PB		 995 memcpy(_arr, ctxt->fetch.ptr, _size); \
996 ctxt->fetch.ptr += (_size); \
67cbc90d
TY		 997})
998
1e3c5cb0
RR		 999/*
1000 * Given the 'reg' portion of a ModRM byte, and a register block, return a
1001 * pointer into the block that addresses the relevant register.
1002 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
1003 */
dd856efa 1004static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
aa9ac1a6 1005 int byteop)
6aa8b732
AK		 1006{
1007 void *p;
aa9ac1a6 1008 int highbyte_regs = (ctxt->rex_prefix == 0) && byteop;
6aa8b732 1009
6aa8b732 1010 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
dd856efa
AK		 1011 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
1012 else
1013 p = reg_rmw(ctxt, modrm_reg);
6aa8b732
AK		 1014 return p;
1015}
1016
1017static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 1018 struct segmented_address addr,
6aa8b732
AK		 1019 u16 *size, unsigned long *address, int op_bytes)
1020{
1021 int rc;
1022
1023 if (op_bytes == 2)
1024 op_bytes = 3;
1025 *address = 0;
3ca3ac4d 1026 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 1027 if (rc != X86EMUL_CONTINUE)
6aa8b732 1028 return rc;
30b31ab6 1029 addr.ea += 2;
3ca3ac4d 1030 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 1031 return rc;
1032}
1033
34b77652
AK		 1034FASTOP2(add);
1035FASTOP2(or);
1036FASTOP2(adc);
1037FASTOP2(sbb);
1038FASTOP2(and);
1039FASTOP2(sub);
1040FASTOP2(xor);
1041FASTOP2(cmp);
1042FASTOP2(test);
1043
b9fa409b
AK		 1044FASTOP1SRC2(mul, mul_ex);
1045FASTOP1SRC2(imul, imul_ex);
b8c0b6ae
AK		 1046FASTOP1SRC2EX(div, div_ex);
1047FASTOP1SRC2EX(idiv, idiv_ex);
b9fa409b 1048
34b77652
AK		 1049FASTOP3WCL(shld);
1050FASTOP3WCL(shrd);
1051
1052FASTOP2W(imul);
1053
1054FASTOP1(not);
1055FASTOP1(neg);
1056FASTOP1(inc);
1057FASTOP1(dec);
1058
1059FASTOP2CL(rol);
1060FASTOP2CL(ror);
1061FASTOP2CL(rcl);
1062FASTOP2CL(rcr);
1063FASTOP2CL(shl);
1064FASTOP2CL(shr);
1065FASTOP2CL(sar);
1066
1067FASTOP2W(bsf);
1068FASTOP2W(bsr);
1069FASTOP2W(bt);
1070FASTOP2W(bts);
1071FASTOP2W(btr);
1072FASTOP2W(btc);
1073
e47a5f5f
AK		 1074FASTOP2(xadd);
1075
5aca3722
NA		 1076FASTOP2R(cmp, cmp_r);
1077
900efe20
NA		 1078static int em_bsf_c(struct x86_emulate_ctxt *ctxt)
1079{
1080 /* If src is zero, do not writeback, but update flags */
1081 if (ctxt->src.val == 0)
1082 ctxt->dst.type = OP_NONE;
1083 return fastop(ctxt, em_bsf);
1084}
1085
1086static int em_bsr_c(struct x86_emulate_ctxt *ctxt)
1087{
1088 /* If src is zero, do not writeback, but update flags */
1089 if (ctxt->src.val == 0)
1090 ctxt->dst.type = OP_NONE;
1091 return fastop(ctxt, em_bsr);
1092}
1093
cb7390fe 1094static __always_inline u8 test_cc(unsigned int condition, unsigned long flags)
bbe9abbd 1095{
9ae9feba 1096 u8 rc;
22472d12 1097 void (*fop)(void) = (void *)em_setcc + FASTOP_SIZE * (condition & 0xf);
bbe9abbd 1098
9ae9feba 1099 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
1a29b5b7
PZ		 1100 asm("push %[flags]; popf; " CALL_NOSPEC
1101 : "=a"(rc) : [thunk_target]"r"(fop), [flags]"r"(flags));
9ae9feba 1102 return rc;
bbe9abbd
NK		 1103}
1104
91ff3cb4
AK		 1105static void fetch_register_operand(struct operand *op)
1106{
1107 switch (op->bytes) {
1108 case 1:
1109 op->val = *(u8 *)op->addr.reg;
1110 break;
1111 case 2:
1112 op->val = *(u16 *)op->addr.reg;
1113 break;
1114 case 4:
1115 op->val = *(u32 *)op->addr.reg;
1116 break;
1117 case 8:
1118 op->val = *(u64 *)op->addr.reg;
1119 break;
1120 }
1121}
1122
045a282c
GN		 1123static int em_fninit(struct x86_emulate_ctxt *ctxt)
1124{
1125 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1126 return emulate_nm(ctxt);
1127
43e51464 1128 kvm_fpu_get();
045a282c 1129 asm volatile("fninit");
43e51464 1130 kvm_fpu_put();
045a282c
GN		 1131 return X86EMUL_CONTINUE;
1132}
1133
1134static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
1135{
1136 u16 fcw;
1137
1138 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1139 return emulate_nm(ctxt);
1140
43e51464 1141 kvm_fpu_get();
045a282c 1142 asm volatile("fnstcw %0": "+m"(fcw));
43e51464 1143 kvm_fpu_put();
045a282c 1144
045a282c
GN		 1145 ctxt->dst.val = fcw;
1146
1147 return X86EMUL_CONTINUE;
1148}
1149
1150static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
1151{
1152 u16 fsw;
1153
1154 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1155 return emulate_nm(ctxt);
1156
43e51464 1157 kvm_fpu_get();
045a282c 1158 asm volatile("fnstsw %0": "+m"(fsw));
43e51464 1159 kvm_fpu_put();
045a282c 1160
045a282c
GN		 1161 ctxt->dst.val = fsw;
1162
1163 return X86EMUL_CONTINUE;
1164}
1165
1253791d 1166static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 1167 struct operand *op)
3c118e24 1168{
e390f4d6 1169 unsigned int reg;
33615aa9 1170
e390f4d6
LN		 1171 if (ctxt->d & ModRM)
1172 reg = ctxt->modrm_reg;
1173 else
9dac77fa 1174 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 1175
9dac77fa 1176 if (ctxt->d & Sse) {
1253791d
AK		 1177 op->type = OP_XMM;
1178 op->bytes = 16;
1179 op->addr.xmm = reg;
43e51464 1180 kvm_read_sse_reg(reg, &op->vec_val);
1253791d
AK		 1181 return;
1182 }
cbe2c9d3
AK		 1183 if (ctxt->d & Mmx) {
1184 reg &= 7;
1185 op->type = OP_MM;
1186 op->bytes = 8;
1187 op->addr.mm = reg;
1188 return;
1189 }
1253791d 1190
3c118e24 1191 op->type = OP_REG;
6d4d85ec
GN		 1192 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1193 op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp);
1194
91ff3cb4 1195 fetch_register_operand(op);
3c118e24
AK		 1196 op->orig_val = op->val;
1197}
1198
a6e3407b
AK		 1199static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1200{
1201 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1202 ctxt->modrm_seg = VCPU_SREG_SS;
1203}
1204
1c73ef66 1205static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1206 struct operand *op)
1c73ef66 1207{
1c73ef66 1208 u8 sib;
02357bdc 1209 int index_reg, base_reg, scale;
3e2815e9 1210 int rc = X86EMUL_CONTINUE;
2dbd0dd7 1211 ulong modrm_ea = 0;
1c73ef66 1212
02357bdc
BD		 1213 ctxt->modrm_reg = ((ctxt->rex_prefix << 1) & 8); /* REX.R */
1214 index_reg = (ctxt->rex_prefix << 2) & 8; /* REX.X */
1215 base_reg = (ctxt->rex_prefix << 3) & 8; /* REX.B */
1c73ef66 1216
02357bdc 1217 ctxt->modrm_mod = (ctxt->modrm & 0xc0) >> 6;
9dac77fa 1218 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
02357bdc 1219 ctxt->modrm_rm = base_reg | (ctxt->modrm & 0x07);
9dac77fa 1220 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 1221
9b88ae99 1222 if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) {
2dbd0dd7 1223 op->type = OP_REG;
9dac77fa 1224 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
8acb4207 1225 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm,
aa9ac1a6 1226 ctxt->d & ByteOp);
9dac77fa 1227 if (ctxt->d & Sse) {
1253791d
AK		 1228 op->type = OP_XMM;
1229 op->bytes = 16;
9dac77fa 1230 op->addr.xmm = ctxt->modrm_rm;
43e51464 1231 kvm_read_sse_reg(ctxt->modrm_rm, &op->vec_val);
1253791d
AK		 1232 return rc;
1233 }
cbe2c9d3
AK		 1234 if (ctxt->d & Mmx) {
1235 op->type = OP_MM;
1236 op->bytes = 8;
bdc90722 1237 op->addr.mm = ctxt->modrm_rm & 7;
cbe2c9d3
AK		 1238 return rc;
1239 }
2dbd0dd7 1240 fetch_register_operand(op);
1c73ef66
AK		 1241 return rc;
1242 }
1243
2dbd0dd7
AK		 1244 op->type = OP_MEM;
1245
9dac77fa 1246 if (ctxt->ad_bytes == 2) {
dd856efa
AK		 1247 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1248 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1249 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1250 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1c73ef66
AK		 1251
1252 /* 16-bit ModR/M decode. */
9dac77fa 1253 switch (ctxt->modrm_mod) {
1c73ef66 1254 case 0:
9dac77fa 1255 if (ctxt->modrm_rm == 6)
e85a1085 1256 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1257 break;
1258 case 1:
e85a1085 1259 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1260 break;
1261 case 2:
e85a1085 1262 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1263 break;
1264 }
9dac77fa 1265 switch (ctxt->modrm_rm) {
1c73ef66 1266 case 0:
2dbd0dd7 1267 modrm_ea += bx + si;
1c73ef66
AK		 1268 break;
1269 case 1:
2dbd0dd7 1270 modrm_ea += bx + di;
1c73ef66
AK		 1271 break;
1272 case 2:
2dbd0dd7 1273 modrm_ea += bp + si;
1c73ef66
AK		 1274 break;
1275 case 3:
2dbd0dd7 1276 modrm_ea += bp + di;
1c73ef66
AK		 1277 break;
1278 case 4:
2dbd0dd7 1279 modrm_ea += si;
1c73ef66
AK		 1280 break;
1281 case 5:
2dbd0dd7 1282 modrm_ea += di;
1c73ef66
AK		 1283 break;
1284 case 6:
9dac77fa 1285 if (ctxt->modrm_mod != 0)
2dbd0dd7 1286 modrm_ea += bp;
1c73ef66
AK		 1287 break;
1288 case 7:
2dbd0dd7 1289 modrm_ea += bx;
1c73ef66
AK		 1290 break;
1291 }
9dac77fa
AK		 1292 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1293 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1294 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1295 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1296 } else {
1297 /* 32/64-bit ModR/M decode. */
9dac77fa 1298 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1299 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1300 index_reg |= (sib >> 3) & 7;
1301 base_reg |= sib & 7;
1302 scale = sib >> 6;
1303
9dac77fa 1304 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1305 modrm_ea += insn_fetch(s32, ctxt);
a6e3407b 1306 else {
dd856efa 1307 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b 1308 adjust_modrm_seg(ctxt, base_reg);
ab708099
NA		 1309 /* Increment ESP on POP [ESP] */
1310 if ((ctxt->d & IncSP) &&
1311 base_reg == VCPU_REGS_RSP)
1312 modrm_ea += ctxt->op_bytes;
a6e3407b 1313 }
dc71d0f1 1314 if (index_reg != 4)
dd856efa 1315 modrm_ea += reg_read(ctxt, index_reg) << scale;
9dac77fa 1316 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
5b38ab87 1317 modrm_ea += insn_fetch(s32, ctxt);
84411d85 1318 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1319 ctxt->rip_relative = 1;
a6e3407b
AK		 1320 } else {
1321 base_reg = ctxt->modrm_rm;
dd856efa 1322 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1323 adjust_modrm_seg(ctxt, base_reg);
1324 }
9dac77fa 1325 switch (ctxt->modrm_mod) {
1c73ef66 1326 case 1:
e85a1085 1327 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1328 break;
1329 case 2:
e85a1085 1330 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1331 break;
1332 }
1333 }
90de84f5 1334 op->addr.mem.ea = modrm_ea;
41061cdb
BD		 1335 if (ctxt->ad_bytes != 8)
1336 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
1337
1c73ef66
AK		 1338done:
1339 return rc;
1340}
1341
1342static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1343 struct operand *op)
1c73ef66 1344{
3e2815e9 1345 int rc = X86EMUL_CONTINUE;
1c73ef66 1346
2dbd0dd7 1347 op->type = OP_MEM;
9dac77fa 1348 switch (ctxt->ad_bytes) {
1c73ef66 1349 case 2:
e85a1085 1350 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1351 break;
1352 case 4:
e85a1085 1353 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1354 break;
1355 case 8:
e85a1085 1356 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1357 break;
1358 }
1359done:
1360 return rc;
1361}
1362
9dac77fa 1363static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1364{
7129eeca 1365 long sv = 0, mask;
35c843c4 1366
9dac77fa 1367 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
7dec5603 1368 mask = ~((long)ctxt->dst.bytes * 8 - 1);
35c843c4 1369
9dac77fa
AK		 1370 if (ctxt->src.bytes == 2)
1371 sv = (s16)ctxt->src.val & (s16)mask;
1372 else if (ctxt->src.bytes == 4)
1373 sv = (s32)ctxt->src.val & (s32)mask;
7dec5603
NA		 1374 else
1375 sv = (s64)ctxt->src.val & (s64)mask;
35c843c4 1376
1c1c35ae
NA		 1377 ctxt->dst.addr.mem.ea = address_mask(ctxt,
1378 ctxt->dst.addr.mem.ea + (sv >> 3));
35c843c4 1379 }
ba7ff2b7
WY		 1380
1381 /* only subword offset */
9dac77fa 1382 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1383}
1384
dde7e6d1 1385static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1386 unsigned long addr, void *dest, unsigned size)
6aa8b732 1387{
dde7e6d1 1388 int rc;
9dac77fa 1389 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1390
f23b070e
XG		 1391 if (mc->pos < mc->end)
1392 goto read_cached;
6aa8b732 1393
d38ea957
SC		 1394 if (KVM_EMULATOR_BUG_ON((mc->end + size) >= sizeof(mc->data), ctxt))
1395 return X86EMUL_UNHANDLEABLE;
f23b070e
XG		 1396
1397 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1398 &ctxt->exception);
1399 if (rc != X86EMUL_CONTINUE)
1400 return rc;
1401
1402 mc->end += size;
1403
1404read_cached:
1405 memcpy(dest, mc->data + mc->pos, size);
1406 mc->pos += size;
dde7e6d1
AK		 1407 return X86EMUL_CONTINUE;
1408}
6aa8b732 1409
3ca3ac4d
AK		 1410static int segmented_read(struct x86_emulate_ctxt *ctxt,
1411 struct segmented_address addr,
1412 void *data,
1413 unsigned size)
1414{
9fa088f4
AK		 1415 int rc;
1416 ulong linear;
1417
83b8795a 1418 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1419 if (rc != X86EMUL_CONTINUE)
1420 return rc;
7b105ca2 1421 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1422}
1423
1424static int segmented_write(struct x86_emulate_ctxt *ctxt,
1425 struct segmented_address addr,
1426 const void *data,
1427 unsigned size)
1428{
9fa088f4
AK		 1429 int rc;
1430 ulong linear;
1431
83b8795a 1432 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1433 if (rc != X86EMUL_CONTINUE)
1434 return rc;
0f65dd70
AK		 1435 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1436 &ctxt->exception);
3ca3ac4d
AK		 1437}
1438
1439static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1440 struct segmented_address addr,
1441 const void *orig_data, const void *data,
1442 unsigned size)
1443{
9fa088f4
AK		 1444 int rc;
1445 ulong linear;
1446
83b8795a 1447 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1448 if (rc != X86EMUL_CONTINUE)
1449 return rc;
0f65dd70
AK		 1450 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1451 size, &ctxt->exception);
3ca3ac4d
AK		 1452}
1453
dde7e6d1 1454static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1455 unsigned int size, unsigned short port,
1456 void *dest)
1457{
9dac77fa 1458 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1459
dde7e6d1 1460 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1461 unsigned int in_page, n;
9dac77fa 1462 unsigned int count = ctxt->rep_prefix ?
dd856efa 1463 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
0efb0440 1464 in_page = (ctxt->eflags & X86_EFLAGS_DF) ?
dd856efa
AK		 1465 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1466 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
b55a8144 1467 n = min3(in_page, (unsigned int)sizeof(rc->data) / size, count);
dde7e6d1
AK		 1468 if (n == 0)
1469 n = 1;
1470 rc->pos = rc->end = 0;
7b105ca2 1471 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1472 return 0;
1473 rc->end = n * size;
6aa8b732
AK		 1474 }
1475
e6e39f04 1476 if (ctxt->rep_prefix && (ctxt->d & String) &&
0efb0440 1477 !(ctxt->eflags & X86_EFLAGS_DF)) {
b3356bf0
GN		 1478 ctxt->dst.data = rc->data + rc->pos;
1479 ctxt->dst.type = OP_MEM_STR;
1480 ctxt->dst.count = (rc->end - rc->pos) / size;
1481 rc->pos = rc->end;
1482 } else {
1483 memcpy(dest, rc->data + rc->pos, size);
1484 rc->pos += size;
1485 }
dde7e6d1
AK		 1486 return 1;
1487}
6aa8b732 1488
7f3d35fd
KW		 1489static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1490 u16 index, struct desc_struct *desc)
1491{
1492 struct desc_ptr dt;
1493 ulong addr;
1494
1495 ctxt->ops->get_idt(ctxt, &dt);
1496
1497 if (dt.size < index * 8 + 7)
1498 return emulate_gp(ctxt, index << 3 | 0x2);
1499
1500 addr = dt.address + index * 8;
0e96f31e 1501 return linear_read_system(ctxt, addr, desc, sizeof(*desc));
7f3d35fd
KW		 1502}
1503
dde7e6d1 1504static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1505 u16 selector, struct desc_ptr *dt)
1506{
0225fb50 1507 const struct x86_emulate_ops *ops = ctxt->ops;
2eedcac8 1508 u32 base3 = 0;
7b105ca2 1509
dde7e6d1
AK		 1510 if (selector & 1 << 2) {
1511 struct desc_struct desc;
1aa36616
AK		 1512 u16 sel;
1513
0e96f31e 1514 memset(dt, 0, sizeof(*dt));
2eedcac8
NA		 1515 if (!ops->get_segment(ctxt, &sel, &desc, &base3,
1516 VCPU_SREG_LDTR))
dde7e6d1 1517 return;
e09d082c 1518
dde7e6d1 1519 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
2eedcac8 1520 dt->address = get_desc_base(&desc) | ((u64)base3 << 32);
dde7e6d1 1521 } else
4bff1e86 1522 ops->get_gdt(ctxt, dt);
dde7e6d1 1523}
120df890 1524
edccda7c
NA		 1525static int get_descriptor_ptr(struct x86_emulate_ctxt *ctxt,
1526 u16 selector, ulong *desc_addr_p)
dde7e6d1
AK		 1527{
1528 struct desc_ptr dt;
1529 u16 index = selector >> 3;
dde7e6d1 1530 ulong addr;
120df890 1531
7b105ca2 1532 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1533
35d3d4a1
AK		 1534 if (dt.size < index * 8 + 7)
1535 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1536
edccda7c
NA		 1537 addr = dt.address + index * 8;
1538
1539#ifdef CONFIG_X86_64
1540 if (addr >> 32 != 0) {
1541 u64 efer = 0;
1542
1543 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
1544 if (!(efer & EFER_LMA))
1545 addr &= (u32)-1;
1546 }
1547#endif
1548
1549 *desc_addr_p = addr;
1550 return X86EMUL_CONTINUE;
1551}
1552
1553/* allowed just for 8 bytes segments */
1554static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1555 u16 selector, struct desc_struct *desc,
1556 ulong *desc_addr_p)
1557{
1558 int rc;
1559
1560 rc = get_descriptor_ptr(ctxt, selector, desc_addr_p);
1561 if (rc != X86EMUL_CONTINUE)
1562 return rc;
1563
79367a65 1564 return linear_read_system(ctxt, *desc_addr_p, desc, sizeof(*desc));
dde7e6d1 1565}
ef65c889 1566
dde7e6d1
AK		 1567/* allowed just for 8 bytes segments */
1568static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1569 u16 selector, struct desc_struct *desc)
1570{
edccda7c 1571 int rc;
dde7e6d1 1572 ulong addr;
6aa8b732 1573
edccda7c
NA		 1574 rc = get_descriptor_ptr(ctxt, selector, &addr);
1575 if (rc != X86EMUL_CONTINUE)
1576 return rc;
6aa8b732 1577
0e96f31e 1578 return linear_write_system(ctxt, addr, desc, sizeof(*desc));
dde7e6d1 1579}
c7e75a3d 1580
2356aaeb 1581static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
d1442d85 1582 u16 selector, int seg, u8 cpl,
3dc4bc4f 1583 enum x86_transfer_type transfer,
d1442d85 1584 struct desc_struct *desc)
dde7e6d1 1585{
869be99c 1586 struct desc_struct seg_desc, old_desc;
2356aaeb 1587 u8 dpl, rpl;
dde7e6d1
AK		 1588 unsigned err_vec = GP_VECTOR;
1589 u32 err_code = 0;
1590 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
e919464b 1591 ulong desc_addr;
dde7e6d1 1592 int ret;
03ebebeb 1593 u16 dummy;
e37a75a1 1594 u32 base3 = 0;
69f55cb1 1595
0e96f31e 1596 memset(&seg_desc, 0, sizeof(seg_desc));
69f55cb1 1597
f8da94e9
KW		 1598 if (ctxt->mode == X86EMUL_MODE_REAL) {
1599 /* set real mode segment descriptor (keep limit etc. for
1600 * unreal mode) */
03ebebeb 1601 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
dde7e6d1 1602 set_desc_base(&seg_desc, selector << 4);
dde7e6d1 1603 goto load;
f8da94e9
KW		 1604 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
1605 /* VM86 needs a clean new segment descriptor */
1606 set_desc_base(&seg_desc, selector << 4);
1607 set_desc_limit(&seg_desc, 0xffff);
1608 seg_desc.type = 3;
1609 seg_desc.p = 1;
1610 seg_desc.s = 1;
1611 seg_desc.dpl = 3;
1612 goto load;
dde7e6d1
AK		 1613 }
1614
79d5b4c3 1615 rpl = selector & 3;
79d5b4c3 1616
dde7e6d1
AK		 1617 /* TR should be in GDT only */
1618 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1619 goto exception;
1620
33ab9110
PB		 1621 /* NULL selector is not valid for TR, CS and (except for long mode) SS */
1622 if (null_selector) {
1623 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_TR)
1624 goto exception;
1625
1626 if (seg == VCPU_SREG_SS) {
1627 if (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl)
1628 goto exception;
1629
1630 /*
1631 * ctxt->ops->set_segment expects the CPL to be in
1632 * SS.DPL, so fake an expand-up 32-bit data segment.
1633 */
1634 seg_desc.type = 3;
1635 seg_desc.p = 1;
1636 seg_desc.s = 1;
1637 seg_desc.dpl = cpl;
1638 seg_desc.d = 1;
1639 seg_desc.g = 1;
1640 }
1641
1642 /* Skip all following checks */
dde7e6d1 1643 goto load;
33ab9110 1644 }
dde7e6d1 1645
e919464b 1646 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
dde7e6d1
AK		 1647 if (ret != X86EMUL_CONTINUE)
1648 return ret;
1649
1650 err_code = selector & 0xfffc;
3dc4bc4f
NA		 1651 err_vec = (transfer == X86_TRANSFER_TASK_SWITCH) ? TS_VECTOR :
1652 GP_VECTOR;
dde7e6d1 1653
fc058680 1654 /* can't load system descriptor into segment selector */
3dc4bc4f
NA		 1655 if (seg <= VCPU_SREG_GS && !seg_desc.s) {
1656 if (transfer == X86_TRANSFER_CALL_JMP)
1657 return X86EMUL_UNHANDLEABLE;
dde7e6d1 1658 goto exception;
3dc4bc4f 1659 }
dde7e6d1 1660
dde7e6d1 1661 dpl = seg_desc.dpl;
dde7e6d1
AK		 1662
1663 switch (seg) {
1664 case VCPU_SREG_SS:
1665 /*
1666 * segment is not a writable data segment or segment
1667 * selector's RPL != CPL or segment selector's RPL != CPL
1668 */
1669 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1670 goto exception;
6aa8b732 1671 break;
dde7e6d1
AK		 1672 case VCPU_SREG_CS:
1673 if (!(seg_desc.type & 8))
1674 goto exception;
1675
1e326ad4
HW		 1676 if (transfer == X86_TRANSFER_RET) {
1677 /* RET can never return to an inner privilege level. */
1678 if (rpl < cpl)
dde7e6d1 1679 goto exception;
1e326ad4
HW		 1680 /* Outer-privilege level return is not implemented */
1681 if (rpl > cpl)
1682 return X86EMUL_UNHANDLEABLE;
1683 }
31c66dab
HW		 1684 if (transfer == X86_TRANSFER_RET || transfer == X86_TRANSFER_TASK_SWITCH) {
1685 if (seg_desc.type & 4) {
1686 /* conforming */
1687 if (dpl > rpl)
1688 goto exception;
1689 } else {
1690 /* nonconforming */
1691 if (dpl != rpl)
1692 goto exception;
1693 }
1694 } else { /* X86_TRANSFER_CALL_JMP */
1695 if (seg_desc.type & 4) {
1696 /* conforming */
1697 if (dpl > cpl)
1698 goto exception;
1699 } else {
1700 /* nonconforming */
1701 if (rpl > cpl || dpl != cpl)
1702 goto exception;
1703 }
dde7e6d1 1704 }
040c8dc8
NA		 1705 /* in long-mode d/b must be clear if l is set */
1706 if (seg_desc.d && seg_desc.l) {
1707 u64 efer = 0;
1708
1709 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
1710 if (efer & EFER_LMA)
1711 goto exception;
1712 }
1713
dde7e6d1
AK		 1714 /* CS(RPL) <- CPL */
1715 selector = (selector & 0xfffc) | cpl;
6aa8b732 1716 break;
dde7e6d1
AK		 1717 case VCPU_SREG_TR:
1718 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1719 goto exception;
1720 break;
1721 case VCPU_SREG_LDTR:
1722 if (seg_desc.s || seg_desc.type != 2)
1723 goto exception;
1724 break;
1725 default: /* DS, ES, FS, or GS */
4e62417b 1726 /*
dde7e6d1
AK		 1727 * segment is not a data or readable code segment or
1728 * ((segment is a data or nonconforming code segment)
1729 * and (both RPL and CPL > DPL))
4e62417b 1730 */
dde7e6d1
AK		 1731 if ((seg_desc.type & 0xa) == 0x8 ||
1732 (((seg_desc.type & 0xc) != 0xc) &&
1733 (rpl > dpl && cpl > dpl)))
1734 goto exception;
6aa8b732 1735 break;
dde7e6d1
AK		 1736 }
1737
ca85f002
HW		 1738 if (!seg_desc.p) {
1739 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1740 goto exception;
1741 }
1742
dde7e6d1
AK		 1743 if (seg_desc.s) {
1744 /* mark segment as accessed */
e2cefa74
NA		 1745 if (!(seg_desc.type & 1)) {
1746 seg_desc.type |= 1;
1747 ret = write_segment_descriptor(ctxt, selector,
1748 &seg_desc);
1749 if (ret != X86EMUL_CONTINUE)
1750 return ret;
1751 }
e37a75a1 1752 } else if (ctxt->mode == X86EMUL_MODE_PROT64) {
79367a65 1753 ret = linear_read_system(ctxt, desc_addr+8, &base3, sizeof(base3));
e37a75a1
NA		 1754 if (ret != X86EMUL_CONTINUE)
1755 return ret;
fd8cb433 1756 if (emul_is_noncanonical_address(get_desc_base(&seg_desc) |
26262069
SC		 1757 ((u64)base3 << 32), ctxt))
1758 return emulate_gp(ctxt, err_code);
dde7e6d1 1759 }
ec6e4d86
SC		 1760
1761 if (seg == VCPU_SREG_TR) {
1762 old_desc = seg_desc;
1763 seg_desc.type |= 2; /* busy */
1764 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1765 sizeof(seg_desc), &ctxt->exception);
1766 if (ret != X86EMUL_CONTINUE)
1767 return ret;
dde7e6d1
AK		 1768 }
1769load:
e37a75a1 1770 ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg);
d1442d85
NA		 1771 if (desc)
1772 *desc = seg_desc;
dde7e6d1
AK		 1773 return X86EMUL_CONTINUE;
1774exception:
592f0858 1775 return emulate_exception(ctxt, err_vec, err_code, true);
dde7e6d1
AK		 1776}
1777
2356aaeb
PB		 1778static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1779 u16 selector, int seg)
1780{
1781 u8 cpl = ctxt->ops->cpl(ctxt);
33ab9110
PB		 1782
1783 /*
1784 * None of MOV, POP and LSS can load a NULL selector in CPL=3, but
1785 * they can load it at CPL<3 (Intel's manual says only LSS can,
1786 * but it's wrong).
1787 *
1788 * However, the Intel manual says that putting IST=1/DPL=3 in
1789 * an interrupt gate will result in SS=3 (the AMD manual instead
1790 * says it doesn't), so allow SS=3 in __load_segment_descriptor
1791 * and only forbid it here.
1792 */
1793 if (seg == VCPU_SREG_SS && selector == 3 &&
1794 ctxt->mode == X86EMUL_MODE_PROT64)
1795 return emulate_exception(ctxt, GP_VECTOR, 0, true);
1796
3dc4bc4f
NA		 1797 return __load_segment_descriptor(ctxt, selector, seg, cpl,
1798 X86_TRANSFER_NONE, NULL);
2356aaeb
PB		 1799}
1800
31be40b3
WY		 1801static void write_register_operand(struct operand *op)
1802{
6fd8e127 1803 return assign_register(op->addr.reg, op->val, op->bytes);
31be40b3
WY		 1804}
1805
fb32b1ed 1806static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
dde7e6d1 1807{
fb32b1ed 1808 switch (op->type) {
dde7e6d1 1809 case OP_REG:
fb32b1ed 1810 write_register_operand(op);
6aa8b732 1811 break;
dde7e6d1 1812 case OP_MEM:
9dac77fa 1813 if (ctxt->lock_prefix)
f5f87dfb
PB		 1814 return segmented_cmpxchg(ctxt,
1815 op->addr.mem,
1816 &op->orig_val,
1817 &op->val,
1818 op->bytes);
1819 else
1820 return segmented_write(ctxt,
fb32b1ed 1821 op->addr.mem,
fb32b1ed
AK		 1822 &op->val,
1823 op->bytes);
a682e354 1824 break;
b3356bf0 1825 case OP_MEM_STR:
f5f87dfb
PB		 1826 return segmented_write(ctxt,
1827 op->addr.mem,
1828 op->data,
1829 op->bytes * op->count);
b3356bf0 1830 break;
1253791d 1831 case OP_XMM:
43e51464 1832 kvm_write_sse_reg(op->addr.xmm, &op->vec_val);
1253791d 1833 break;
cbe2c9d3 1834 case OP_MM:
43e51464 1835 kvm_write_mmx_reg(op->addr.mm, &op->mm_val);
cbe2c9d3 1836 break;
dde7e6d1
AK		 1837 case OP_NONE:
1838 /* no writeback */
414e6277 1839 break;
dde7e6d1 1840 default:
414e6277 1841 break;
6aa8b732 1842 }
dde7e6d1
AK		 1843 return X86EMUL_CONTINUE;
1844}
6aa8b732 1845
51ddff50 1846static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
dde7e6d1 1847{
4179bb02 1848 struct segmented_address addr;
0dc8d10f 1849
5ad105e5 1850 rsp_increment(ctxt, -bytes);
dd856efa 1851 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
4179bb02
TY		 1852 addr.seg = VCPU_SREG_SS;
1853
51ddff50
AK		 1854 return segmented_write(ctxt, addr, data, bytes);
1855}
1856
1857static int em_push(struct x86_emulate_ctxt *ctxt)
1858{
4179bb02 1859 /* Disable writeback. */
9dac77fa 1860 ctxt->dst.type = OP_NONE;
51ddff50 1861 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1862}
69f55cb1 1863
dde7e6d1 1864static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1865 void *dest, int len)
1866{
dde7e6d1 1867 int rc;
90de84f5 1868 struct segmented_address addr;
8b4caf66 1869
dd856efa 1870 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
90de84f5 1871 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1872 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1873 if (rc != X86EMUL_CONTINUE)
1874 return rc;
1875
5ad105e5 1876 rsp_increment(ctxt, len);
dde7e6d1 1877 return rc;
8b4caf66
LV		 1878}
1879
c54fe504
TY		 1880static int em_pop(struct x86_emulate_ctxt *ctxt)
1881{
9dac77fa 1882 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1883}
1884
dde7e6d1 1885static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1886 void *dest, int len)
9de41573
GN		 1887{
1888 int rc;
dde7e6d1 1889 unsigned long val, change_mask;
0efb0440 1890 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> X86_EFLAGS_IOPL_BIT;
7b105ca2 1891 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1892
3b9be3bf 1893 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1894 if (rc != X86EMUL_CONTINUE)
1895 return rc;
9de41573 1896
0efb0440
NA		 1897 change_mask = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
1898 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF |
1899 X86_EFLAGS_TF | X86_EFLAGS_DF | X86_EFLAGS_NT |
1900 X86_EFLAGS_AC | X86_EFLAGS_ID;
9de41573 1901
dde7e6d1
AK		 1902 switch(ctxt->mode) {
1903 case X86EMUL_MODE_PROT64:
1904 case X86EMUL_MODE_PROT32:
1905 case X86EMUL_MODE_PROT16:
1906 if (cpl == 0)
0efb0440 1907 change_mask |= X86_EFLAGS_IOPL;
dde7e6d1 1908 if (cpl <= iopl)
0efb0440 1909 change_mask |= X86_EFLAGS_IF;
dde7e6d1
AK		 1910 break;
1911 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1912 if (iopl < 3)
1913 return emulate_gp(ctxt, 0);
0efb0440 1914 change_mask |= X86_EFLAGS_IF;
dde7e6d1
AK		 1915 break;
1916 default: /* real mode */
0efb0440 1917 change_mask |= (X86_EFLAGS_IOPL | X86_EFLAGS_IF);
dde7e6d1 1918 break;
9de41573 1919 }
dde7e6d1
AK		 1920
1921 *(unsigned long *)dest =
1922 (ctxt->eflags & ~change_mask) | (val & change_mask);
1923
1924 return rc;
9de41573
GN		 1925}
1926
62aaa2f0
TY		 1927static int em_popf(struct x86_emulate_ctxt *ctxt)
1928{
9dac77fa
AK		 1929 ctxt->dst.type = OP_REG;
1930 ctxt->dst.addr.reg = &ctxt->eflags;
1931 ctxt->dst.bytes = ctxt->op_bytes;
1932 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1933}
1934
612e89f0
AK		 1935static int em_enter(struct x86_emulate_ctxt *ctxt)
1936{
1937 int rc;
1938 unsigned frame_size = ctxt->src.val;
1939 unsigned nesting_level = ctxt->src2.val & 31;
dd856efa 1940 ulong rbp;
612e89f0
AK		 1941
1942 if (nesting_level)
1943 return X86EMUL_UNHANDLEABLE;
1944
dd856efa
AK		 1945 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1946 rc = push(ctxt, &rbp, stack_size(ctxt));
612e89f0
AK		 1947 if (rc != X86EMUL_CONTINUE)
1948 return rc;
dd856efa 1949 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
612e89f0 1950 stack_mask(ctxt));
dd856efa
AK		 1951 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1952 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
612e89f0
AK		 1953 stack_mask(ctxt));
1954 return X86EMUL_CONTINUE;
1955}
1956
f47cfa31
AK		 1957static int em_leave(struct x86_emulate_ctxt *ctxt)
1958{
dd856efa 1959 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
f47cfa31 1960 stack_mask(ctxt));
dd856efa 1961 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
f47cfa31
AK		 1962}
1963
1cd196ea 1964static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1965{
1cd196ea
AK		 1966 int seg = ctxt->src2.val;
1967
9dac77fa 1968 ctxt->src.val = get_segment_selector(ctxt, seg);
0fcc207c
NA		 1969 if (ctxt->op_bytes == 4) {
1970 rsp_increment(ctxt, -2);
1971 ctxt->op_bytes = 2;
1972 }
7b262e90 1973
4487b3b4 1974 return em_push(ctxt);
7b262e90
GN		 1975}
1976
1cd196ea 1977static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1978{
1cd196ea 1979 int seg = ctxt->src2.val;
dde7e6d1
AK		 1980 unsigned long selector;
1981 int rc;
38ba30ba 1982
3313bc4e 1983 rc = emulate_pop(ctxt, &selector, 2);
dde7e6d1
AK		 1984 if (rc != X86EMUL_CONTINUE)
1985 return rc;
1986
6aa5c47c 1987 if (seg == VCPU_SREG_SS)
a5457e7b 1988 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3313bc4e
NA		 1989 if (ctxt->op_bytes > 2)
1990 rsp_increment(ctxt, ctxt->op_bytes - 2);
a5457e7b 1991
7b105ca2 1992 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1993 return rc;
38ba30ba
GN		 1994}
1995
b96a7fad 1996static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1997{
dd856efa 1998 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
dde7e6d1
AK		 1999 int rc = X86EMUL_CONTINUE;
2000 int reg = VCPU_REGS_RAX;
38ba30ba 2001
dde7e6d1
AK		 2002 while (reg <= VCPU_REGS_RDI) {
2003 (reg == VCPU_REGS_RSP) ?
dd856efa 2004 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
38ba30ba 2005
4487b3b4 2006 rc = em_push(ctxt);
dde7e6d1
AK		 2007 if (rc != X86EMUL_CONTINUE)
2008 return rc;
38ba30ba 2009
dde7e6d1 2010 ++reg;
38ba30ba 2011 }
38ba30ba 2012
dde7e6d1 2013 return rc;
38ba30ba
GN		 2014}
2015
62aaa2f0
TY		 2016static int em_pushf(struct x86_emulate_ctxt *ctxt)
2017{
0efb0440 2018 ctxt->src.val = (unsigned long)ctxt->eflags & ~X86_EFLAGS_VM;
62aaa2f0
TY		 2019 return em_push(ctxt);
2020}
2021
b96a7fad 2022static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 2023{
dde7e6d1
AK		 2024 int rc = X86EMUL_CONTINUE;
2025 int reg = VCPU_REGS_RDI;
6fd8e127 2026 u32 val;
38ba30ba 2027
dde7e6d1
AK		 2028 while (reg >= VCPU_REGS_RAX) {
2029 if (reg == VCPU_REGS_RSP) {
5ad105e5 2030 rsp_increment(ctxt, ctxt->op_bytes);
dde7e6d1
AK		 2031 --reg;
2032 }
38ba30ba 2033
6fd8e127 2034 rc = emulate_pop(ctxt, &val, ctxt->op_bytes);
dde7e6d1
AK		 2035 if (rc != X86EMUL_CONTINUE)
2036 break;
6fd8e127 2037 assign_register(reg_rmw(ctxt, reg), val, ctxt->op_bytes);
dde7e6d1 2038 --reg;
38ba30ba 2039 }
dde7e6d1 2040 return rc;
38ba30ba
GN		 2041}
2042
dd856efa 2043static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 2044{
0225fb50 2045 const struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 2046 int rc;
6e154e56
MG		 2047 struct desc_ptr dt;
2048 gva_t cs_addr;
2049 gva_t eip_addr;
2050 u16 cs, eip;
6e154e56
MG		 2051
2052 /* TODO: Add limit checks */
9dac77fa 2053 ctxt->src.val = ctxt->eflags;
4487b3b4 2054 rc = em_push(ctxt);
5c56e1cf
AK		 2055 if (rc != X86EMUL_CONTINUE)
2056 return rc;
6e154e56 2057
0efb0440 2058 ctxt->eflags &= ~(X86_EFLAGS_IF | X86_EFLAGS_TF | X86_EFLAGS_AC);
6e154e56 2059
9dac77fa 2060 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 2061 rc = em_push(ctxt);
5c56e1cf
AK		 2062 if (rc != X86EMUL_CONTINUE)
2063 return rc;
6e154e56 2064
9dac77fa 2065 ctxt->src.val = ctxt->_eip;
4487b3b4 2066 rc = em_push(ctxt);
5c56e1cf
AK		 2067 if (rc != X86EMUL_CONTINUE)
2068 return rc;
2069
4bff1e86 2070 ops->get_idt(ctxt, &dt);
6e154e56
MG		 2071
2072 eip_addr = dt.address + (irq << 2);
2073 cs_addr = dt.address + (irq << 2) + 2;
2074
79367a65 2075 rc = linear_read_system(ctxt, cs_addr, &cs, 2);
6e154e56
MG		 2076 if (rc != X86EMUL_CONTINUE)
2077 return rc;
2078
79367a65 2079 rc = linear_read_system(ctxt, eip_addr, &eip, 2);
6e154e56
MG		 2080 if (rc != X86EMUL_CONTINUE)
2081 return rc;
2082
7b105ca2 2083 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 2084 if (rc != X86EMUL_CONTINUE)
2085 return rc;
2086
9dac77fa 2087 ctxt->_eip = eip;
6e154e56
MG		 2088
2089 return rc;
2090}
2091
dd856efa
AK		 2092int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
2093{
2094 int rc;
2095
2096 invalidate_registers(ctxt);
2097 rc = __emulate_int_real(ctxt, irq);
2098 if (rc == X86EMUL_CONTINUE)
2099 writeback_registers(ctxt);
2100 return rc;
2101}
2102
7b105ca2 2103static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 2104{
2105 switch(ctxt->mode) {
2106 case X86EMUL_MODE_REAL:
dd856efa 2107 return __emulate_int_real(ctxt, irq);
6e154e56
MG		 2108 case X86EMUL_MODE_VM86:
2109 case X86EMUL_MODE_PROT16:
2110 case X86EMUL_MODE_PROT32:
2111 case X86EMUL_MODE_PROT64:
2112 default:
2113 /* Protected mode interrupts unimplemented yet */
2114 return X86EMUL_UNHANDLEABLE;
2115 }
2116}
2117
7b105ca2 2118static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 2119{
dde7e6d1
AK		 2120 int rc = X86EMUL_CONTINUE;
2121 unsigned long temp_eip = 0;
2122 unsigned long temp_eflags = 0;
2123 unsigned long cs = 0;
0efb0440
NA		 2124 unsigned long mask = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
2125 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_TF |
2126 X86_EFLAGS_IF | X86_EFLAGS_DF | X86_EFLAGS_OF |
2127 X86_EFLAGS_IOPL | X86_EFLAGS_NT | X86_EFLAGS_RF |
2128 X86_EFLAGS_AC | X86_EFLAGS_ID |
35fd68a3 2129 X86_EFLAGS_FIXED;
0efb0440
NA		 2130 unsigned long vm86_mask = X86_EFLAGS_VM | X86_EFLAGS_VIF |
2131 X86_EFLAGS_VIP;
38ba30ba 2132
dde7e6d1 2133 /* TODO: Add stack limit check */
38ba30ba 2134
9dac77fa 2135 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 2136
dde7e6d1
AK		 2137 if (rc != X86EMUL_CONTINUE)
2138 return rc;
38ba30ba 2139
35d3d4a1
AK		 2140 if (temp_eip & ~0xffff)
2141 return emulate_gp(ctxt, 0);
38ba30ba 2142
9dac77fa 2143 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 2144
dde7e6d1
AK		 2145 if (rc != X86EMUL_CONTINUE)
2146 return rc;
38ba30ba 2147
9dac77fa 2148 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 2149
dde7e6d1
AK		 2150 if (rc != X86EMUL_CONTINUE)
2151 return rc;
38ba30ba 2152
7b105ca2 2153 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 2154
dde7e6d1
AK		 2155 if (rc != X86EMUL_CONTINUE)
2156 return rc;
38ba30ba 2157
9dac77fa 2158 ctxt->_eip = temp_eip;
38ba30ba 2159
9dac77fa 2160 if (ctxt->op_bytes == 4)
dde7e6d1 2161 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 2162 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 2163 ctxt->eflags &= ~0xffff;
2164 ctxt->eflags |= temp_eflags;
38ba30ba 2165 }
dde7e6d1
AK		 2166
2167 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
35fd68a3 2168 ctxt->eflags |= X86_EFLAGS_FIXED;
801806d9 2169 ctxt->ops->set_nmi_mask(ctxt, false);
dde7e6d1
AK		 2170
2171 return rc;
38ba30ba
GN		 2172}
2173
e01991e7 2174static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 2175{
dde7e6d1
AK		 2176 switch(ctxt->mode) {
2177 case X86EMUL_MODE_REAL:
7b105ca2 2178 return emulate_iret_real(ctxt);
dde7e6d1
AK		 2179 case X86EMUL_MODE_VM86:
2180 case X86EMUL_MODE_PROT16:
2181 case X86EMUL_MODE_PROT32:
2182 case X86EMUL_MODE_PROT64:
c37eda13 2183 default:
dde7e6d1
AK		 2184 /* iret from protected mode unimplemented yet */
2185 return X86EMUL_UNHANDLEABLE;
c37eda13 2186 }
c37eda13
WY		 2187}
2188
d2f62766
TY		 2189static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
2190{
d2f62766 2191 int rc;
2117d539
RK		 2192 unsigned short sel;
2193 struct desc_struct new_desc;
d1442d85
NA		 2194 u8 cpl = ctxt->ops->cpl(ctxt);
2195
9dac77fa 2196 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 2197
3dc4bc4f
NA		 2198 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl,
2199 X86_TRANSFER_CALL_JMP,
d1442d85 2200 &new_desc);
d2f62766
TY		 2201 if (rc != X86EMUL_CONTINUE)
2202 return rc;
2203
d087e0f7 2204 rc = assign_eip_far(ctxt, ctxt->src.val);
2117d539
RK		 2205 /* Error handling is not implemented. */
2206 if (rc != X86EMUL_CONTINUE)
2207 return X86EMUL_UNHANDLEABLE;
2208
d1442d85 2209 return rc;
d2f62766
TY		 2210}
2211
f7784046 2212static int em_jmp_abs(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2213{
f7784046
NA		 2214 return assign_eip_near(ctxt, ctxt->src.val);
2215}
8cdbd2c9 2216
f7784046
NA		 2217static int em_call_near_abs(struct x86_emulate_ctxt *ctxt)
2218{
2219 int rc;
2220 long int old_eip;
2221
2222 old_eip = ctxt->_eip;
2223 rc = assign_eip_near(ctxt, ctxt->src.val);
2224 if (rc != X86EMUL_CONTINUE)
2225 return rc;
2226 ctxt->src.val = old_eip;
2227 rc = em_push(ctxt);
4179bb02 2228 return rc;
8cdbd2c9
LV		 2229}
2230
e0dac408 2231static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2232{
9dac77fa 2233 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 2234
aaa05f24
NA		 2235 if (ctxt->dst.bytes == 16)
2236 return X86EMUL_UNHANDLEABLE;
2237
dd856efa
AK		 2238 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
2239 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
2240 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
2241 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
0efb0440 2242 ctxt->eflags &= ~X86_EFLAGS_ZF;
8cdbd2c9 2243 } else {
dd856efa
AK		 2244 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2245 (u32) reg_read(ctxt, VCPU_REGS_RBX);
8cdbd2c9 2246
0efb0440 2247 ctxt->eflags |= X86_EFLAGS_ZF;
8cdbd2c9 2248 }
1b30eaa8 2249 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2250}
2251
ebda02c2
TY		 2252static int em_ret(struct x86_emulate_ctxt *ctxt)
2253{
234f3ce4
NA		 2254 int rc;
2255 unsigned long eip;
2256
2257 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
2258 if (rc != X86EMUL_CONTINUE)
2259 return rc;
2260
2261 return assign_eip_near(ctxt, eip);
ebda02c2
TY		 2262}
2263
e01991e7 2264static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 2265{
a77ab5ea 2266 int rc;
d1442d85 2267 unsigned long eip, cs;
9e8919ae 2268 int cpl = ctxt->ops->cpl(ctxt);
2117d539 2269 struct desc_struct new_desc;
a77ab5ea 2270
d1442d85 2271 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
1b30eaa8 2272 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2273 return rc;
9dac77fa 2274 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 2275 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2276 return rc;
3dc4bc4f
NA		 2277 rc = __load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS, cpl,
2278 X86_TRANSFER_RET,
d1442d85
NA		 2279 &new_desc);
2280 if (rc != X86EMUL_CONTINUE)
2281 return rc;
d087e0f7 2282 rc = assign_eip_far(ctxt, eip);
2117d539
RK		 2283 /* Error handling is not implemented. */
2284 if (rc != X86EMUL_CONTINUE)
2285 return X86EMUL_UNHANDLEABLE;
2286
a77ab5ea
AK		 2287 return rc;
2288}
2289
3261107e
BR		 2290static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt)
2291{
2292 int rc;
2293
2294 rc = em_ret_far(ctxt);
2295 if (rc != X86EMUL_CONTINUE)
2296 return rc;
2297 rsp_increment(ctxt, ctxt->src.val);
2298 return X86EMUL_CONTINUE;
2299}
2300
e940b5c2
TY		 2301static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2302{
2303 /* Save real source value, then compare EAX against destination. */
37c564f2
NA		 2304 ctxt->dst.orig_val = ctxt->dst.val;
2305 ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX);
e940b5c2 2306 ctxt->src.orig_val = ctxt->src.val;
37c564f2 2307 ctxt->src.val = ctxt->dst.orig_val;
158de57f 2308 fastop(ctxt, em_cmp);
e940b5c2 2309
0efb0440 2310 if (ctxt->eflags & X86_EFLAGS_ZF) {
2fcf5c8a
NA		 2311 /* Success: write back to memory; no update of EAX */
2312 ctxt->src.type = OP_NONE;
e940b5c2
TY		 2313 ctxt->dst.val = ctxt->src.orig_val;
2314 } else {
2315 /* Failure: write the value we saw to EAX. */
2fcf5c8a
NA		 2316 ctxt->src.type = OP_REG;
2317 ctxt->src.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
2318 ctxt->src.val = ctxt->dst.orig_val;
2319 /* Create write-cycle to dest by writing the same value */
37c564f2 2320 ctxt->dst.val = ctxt->dst.orig_val;
e940b5c2
TY		 2321 }
2322 return X86EMUL_CONTINUE;
2323}
2324
d4b4325f 2325static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 2326{
d4b4325f 2327 int seg = ctxt->src2.val;
09b5f4d3
WY		 2328 unsigned short sel;
2329 int rc;
2330
9dac77fa 2331 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 2332
7b105ca2 2333 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 2334 if (rc != X86EMUL_CONTINUE)
2335 return rc;
2336
9dac77fa 2337 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 2338 return rc;
2339}
2340
660a5d51
PB		 2341static int emulator_has_longmode(struct x86_emulate_ctxt *ctxt)
2342{
b68f3cc7 2343#ifdef CONFIG_X86_64
5ae78e95 2344 return ctxt->ops->guest_has_long_mode(ctxt);
b68f3cc7
SC		 2345#else
2346 return false;
2347#endif
660a5d51
PB		 2348}
2349
660a5d51
PB		 2350static void rsm_set_desc_flags(struct desc_struct *desc, u32 flags)
2351{
2352 desc->g = (flags >> 23) & 1;
2353 desc->d = (flags >> 22) & 1;
2354 desc->l = (flags >> 21) & 1;
2355 desc->avl = (flags >> 20) & 1;
2356 desc->p = (flags >> 15) & 1;
2357 desc->dpl = (flags >> 13) & 3;
2358 desc->s = (flags >> 12) & 1;
2359 desc->type = (flags >> 8) & 15;
2360}
2361
ed19321f
SC		 2362static int rsm_load_seg_32(struct x86_emulate_ctxt *ctxt, const char *smstate,
2363 int n)
660a5d51
PB		 2364{
2365 struct desc_struct desc;
2366 int offset;
2367 u16 selector;
2368
ed19321f 2369 selector = GET_SMSTATE(u32, smstate, 0x7fa8 + n * 4);
660a5d51
PB		 2370
2371 if (n < 3)
2372 offset = 0x7f84 + n * 12;
2373 else
2374 offset = 0x7f2c + (n - 3) * 12;
2375
ed19321f
SC		 2376 set_desc_base(&desc, GET_SMSTATE(u32, smstate, offset + 8));
2377 set_desc_limit(&desc, GET_SMSTATE(u32, smstate, offset + 4));
2378 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smstate, offset));
660a5d51
PB		 2379 ctxt->ops->set_segment(ctxt, selector, &desc, 0, n);
2380 return X86EMUL_CONTINUE;
2381}
2382
b68f3cc7 2383#ifdef CONFIG_X86_64
ed19321f
SC		 2384static int rsm_load_seg_64(struct x86_emulate_ctxt *ctxt, const char *smstate,
2385 int n)
660a5d51
PB		 2386{
2387 struct desc_struct desc;
2388 int offset;
2389 u16 selector;
2390 u32 base3;
2391
2392 offset = 0x7e00 + n * 16;
2393
ed19321f
SC		 2394 selector = GET_SMSTATE(u16, smstate, offset);
2395 rsm_set_desc_flags(&desc, GET_SMSTATE(u16, smstate, offset + 2) << 8);
2396 set_desc_limit(&desc, GET_SMSTATE(u32, smstate, offset + 4));
2397 set_desc_base(&desc, GET_SMSTATE(u32, smstate, offset + 8));
2398 base3 = GET_SMSTATE(u32, smstate, offset + 12);
660a5d51
PB		 2399
2400 ctxt->ops->set_segment(ctxt, selector, &desc, base3, n);
2401 return X86EMUL_CONTINUE;
2402}
b68f3cc7 2403#endif
660a5d51
PB		 2404
2405static int rsm_enter_protected_mode(struct x86_emulate_ctxt *ctxt,
fae1a3e7 2406 u64 cr0, u64 cr3, u64 cr4)
660a5d51
PB		 2407{
2408 int bad;
fae1a3e7
PB		 2409 u64 pcid;
2410
2411 /* In order to later set CR4.PCIDE, CR3[11:0] must be zero. */
2412 pcid = 0;
2413 if (cr4 & X86_CR4_PCIDE) {
2414 pcid = cr3 & 0xfff;
2415 cr3 &= ~0xfff;
2416 }
2417
2418 bad = ctxt->ops->set_cr(ctxt, 3, cr3);
2419 if (bad)
2420 return X86EMUL_UNHANDLEABLE;
660a5d51
PB		 2421
2422 /*
2423 * First enable PAE, long mode needs it before CR0.PG = 1 is set.
2424 * Then enable protected mode. However, PCID cannot be enabled
2425 * if EFER.LMA=0, so set it separately.
2426 */
2427 bad = ctxt->ops->set_cr(ctxt, 4, cr4 & ~X86_CR4_PCIDE);
2428 if (bad)
2429 return X86EMUL_UNHANDLEABLE;
2430
2431 bad = ctxt->ops->set_cr(ctxt, 0, cr0);
2432 if (bad)
2433 return X86EMUL_UNHANDLEABLE;
2434
2435 if (cr4 & X86_CR4_PCIDE) {
2436 bad = ctxt->ops->set_cr(ctxt, 4, cr4);
2437 if (bad)
2438 return X86EMUL_UNHANDLEABLE;
fae1a3e7
PB		 2439 if (pcid) {
2440 bad = ctxt->ops->set_cr(ctxt, 3, cr3 | pcid);
2441 if (bad)
2442 return X86EMUL_UNHANDLEABLE;
2443 }
2444
660a5d51
PB		 2445 }
2446
2447 return X86EMUL_CONTINUE;
2448}
2449
ed19321f
SC		 2450static int rsm_load_state_32(struct x86_emulate_ctxt *ctxt,
2451 const char *smstate)
660a5d51
PB		 2452{
2453 struct desc_struct desc;
2454 struct desc_ptr dt;
2455 u16 selector;
fae1a3e7 2456 u32 val, cr0, cr3, cr4;
660a5d51
PB		 2457 int i;
2458
ed19321f
SC		 2459 cr0 = GET_SMSTATE(u32, smstate, 0x7ffc);
2460 cr3 = GET_SMSTATE(u32, smstate, 0x7ff8);
2461 ctxt->eflags = GET_SMSTATE(u32, smstate, 0x7ff4) | X86_EFLAGS_FIXED;
2462 ctxt->_eip = GET_SMSTATE(u32, smstate, 0x7ff0);
660a5d51 2463
b443183a 2464 for (i = 0; i < NR_EMULATOR_GPRS; i++)
ed19321f 2465 *reg_write(ctxt, i) = GET_SMSTATE(u32, smstate, 0x7fd0 + i * 4);
660a5d51 2466
ed19321f 2467 val = GET_SMSTATE(u32, smstate, 0x7fcc);
37f66bbe 2468
16d5163f 2469 if (ctxt->ops->set_dr(ctxt, 6, val))
37f66bbe
ML		 2470 return X86EMUL_UNHANDLEABLE;
2471
ed19321f 2472 val = GET_SMSTATE(u32, smstate, 0x7fc8);
37f66bbe 2473
16d5163f 2474 if (ctxt->ops->set_dr(ctxt, 7, val))
37f66bbe 2475 return X86EMUL_UNHANDLEABLE;
660a5d51 2476
ed19321f
SC		 2477 selector = GET_SMSTATE(u32, smstate, 0x7fc4);
2478 set_desc_base(&desc, GET_SMSTATE(u32, smstate, 0x7f64));
2479 set_desc_limit(&desc, GET_SMSTATE(u32, smstate, 0x7f60));
2480 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smstate, 0x7f5c));
660a5d51
PB		 2481 ctxt->ops->set_segment(ctxt, selector, &desc, 0, VCPU_SREG_TR);
2482
ed19321f
SC		 2483 selector = GET_SMSTATE(u32, smstate, 0x7fc0);
2484 set_desc_base(&desc, GET_SMSTATE(u32, smstate, 0x7f80));
2485 set_desc_limit(&desc, GET_SMSTATE(u32, smstate, 0x7f7c));
2486 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smstate, 0x7f78));
660a5d51
PB		 2487 ctxt->ops->set_segment(ctxt, selector, &desc, 0, VCPU_SREG_LDTR);
2488
ed19321f
SC		 2489 dt.address = GET_SMSTATE(u32, smstate, 0x7f74);
2490 dt.size = GET_SMSTATE(u32, smstate, 0x7f70);
660a5d51
PB		 2491 ctxt->ops->set_gdt(ctxt, &dt);
2492
ed19321f
SC		 2493 dt.address = GET_SMSTATE(u32, smstate, 0x7f58);
2494 dt.size = GET_SMSTATE(u32, smstate, 0x7f54);
660a5d51
PB		 2495 ctxt->ops->set_idt(ctxt, &dt);
2496
2497 for (i = 0; i < 6; i++) {
ed19321f 2498 int r = rsm_load_seg_32(ctxt, smstate, i);
660a5d51
PB		 2499 if (r != X86EMUL_CONTINUE)
2500 return r;
2501 }
2502
ed19321f 2503 cr4 = GET_SMSTATE(u32, smstate, 0x7f14);
660a5d51 2504
ed19321f 2505 ctxt->ops->set_smbase(ctxt, GET_SMSTATE(u32, smstate, 0x7ef8));
660a5d51 2506
fae1a3e7 2507 return rsm_enter_protected_mode(ctxt, cr0, cr3, cr4);
660a5d51
PB		 2508}
2509
b68f3cc7 2510#ifdef CONFIG_X86_64
ed19321f
SC		 2511static int rsm_load_state_64(struct x86_emulate_ctxt *ctxt,
2512 const char *smstate)
660a5d51
PB		 2513{
2514 struct desc_struct desc;
2515 struct desc_ptr dt;
fae1a3e7 2516 u64 val, cr0, cr3, cr4;
660a5d51
PB		 2517 u32 base3;
2518 u16 selector;
b10d92a5 2519 int i, r;
660a5d51 2520
b443183a 2521 for (i = 0; i < NR_EMULATOR_GPRS; i++)
ed19321f 2522 *reg_write(ctxt, i) = GET_SMSTATE(u64, smstate, 0x7ff8 - i * 8);
660a5d51 2523
ed19321f
SC		 2524 ctxt->_eip = GET_SMSTATE(u64, smstate, 0x7f78);
2525 ctxt->eflags = GET_SMSTATE(u32, smstate, 0x7f70) | X86_EFLAGS_FIXED;
660a5d51 2526
26443120 2527 val = GET_SMSTATE(u64, smstate, 0x7f68);
37f66bbe 2528
16d5163f 2529 if (ctxt->ops->set_dr(ctxt, 6, val))
37f66bbe
ML		 2530 return X86EMUL_UNHANDLEABLE;
2531
26443120 2532 val = GET_SMSTATE(u64, smstate, 0x7f60);
37f66bbe 2533
16d5163f 2534 if (ctxt->ops->set_dr(ctxt, 7, val))
37f66bbe 2535 return X86EMUL_UNHANDLEABLE;
660a5d51 2536
ed19321f
SC		 2537 cr0 = GET_SMSTATE(u64, smstate, 0x7f58);
2538 cr3 = GET_SMSTATE(u64, smstate, 0x7f50);
2539 cr4 = GET_SMSTATE(u64, smstate, 0x7f48);
2540 ctxt->ops->set_smbase(ctxt, GET_SMSTATE(u32, smstate, 0x7f00));
2541 val = GET_SMSTATE(u64, smstate, 0x7ed0);
37f66bbe
ML		 2542
2543 if (ctxt->ops->set_msr(ctxt, MSR_EFER, val & ~EFER_LMA))
2544 return X86EMUL_UNHANDLEABLE;
660a5d51 2545
ed19321f
SC		 2546 selector = GET_SMSTATE(u32, smstate, 0x7e90);
2547 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smstate, 0x7e92) << 8);
2548 set_desc_limit(&desc, GET_SMSTATE(u32, smstate, 0x7e94));
2549 set_desc_base(&desc, GET_SMSTATE(u32, smstate, 0x7e98));
2550 base3 = GET_SMSTATE(u32, smstate, 0x7e9c);
660a5d51
PB		 2551 ctxt->ops->set_segment(ctxt, selector, &desc, base3, VCPU_SREG_TR);
2552
ed19321f
SC		 2553 dt.size = GET_SMSTATE(u32, smstate, 0x7e84);
2554 dt.address = GET_SMSTATE(u64, smstate, 0x7e88);
660a5d51
PB		 2555 ctxt->ops->set_idt(ctxt, &dt);
2556
ed19321f
SC		 2557 selector = GET_SMSTATE(u32, smstate, 0x7e70);
2558 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smstate, 0x7e72) << 8);
2559 set_desc_limit(&desc, GET_SMSTATE(u32, smstate, 0x7e74));
2560 set_desc_base(&desc, GET_SMSTATE(u32, smstate, 0x7e78));
2561 base3 = GET_SMSTATE(u32, smstate, 0x7e7c);
660a5d51
PB		 2562 ctxt->ops->set_segment(ctxt, selector, &desc, base3, VCPU_SREG_LDTR);
2563
ed19321f
SC		 2564 dt.size = GET_SMSTATE(u32, smstate, 0x7e64);
2565 dt.address = GET_SMSTATE(u64, smstate, 0x7e68);
660a5d51
PB		 2566 ctxt->ops->set_gdt(ctxt, &dt);
2567
fae1a3e7 2568 r = rsm_enter_protected_mode(ctxt, cr0, cr3, cr4);
b10d92a5
PB		 2569 if (r != X86EMUL_CONTINUE)
2570 return r;
2571
660a5d51 2572 for (i = 0; i < 6; i++) {
ed19321f 2573 r = rsm_load_seg_64(ctxt, smstate, i);
660a5d51
PB		 2574 if (r != X86EMUL_CONTINUE)
2575 return r;
2576 }
2577
b10d92a5 2578 return X86EMUL_CONTINUE;
660a5d51 2579}
b68f3cc7 2580#endif
660a5d51 2581
64d60670
PB		 2582static int em_rsm(struct x86_emulate_ctxt *ctxt)
2583{
660a5d51 2584 unsigned long cr0, cr4, efer;
ed19321f 2585 char buf[512];
660a5d51
PB		 2586 u64 smbase;
2587 int ret;
2588
6ed071f0 2589 if ((ctxt->ops->get_hflags(ctxt) & X86EMUL_SMM_MASK) == 0)
64d60670
PB		 2590 return emulate_ud(ctxt);
2591
ed19321f
SC		 2592 smbase = ctxt->ops->get_smbase(ctxt);
2593
2594 ret = ctxt->ops->read_phys(ctxt, smbase + 0xfe00, buf, sizeof(buf));
2595 if (ret != X86EMUL_CONTINUE)
2596 return X86EMUL_UNHANDLEABLE;
2597
9ec19493
SC		 2598 if ((ctxt->ops->get_hflags(ctxt) & X86EMUL_SMM_INSIDE_NMI_MASK) == 0)
2599 ctxt->ops->set_nmi_mask(ctxt, false);
2600
edce4654 2601 ctxt->ops->exiting_smm(ctxt);
9ec19493 2602
660a5d51
PB		 2603 /*
2604 * Get back to real mode, to prepare a safe state in which to load
89651a3d
PB		 2605 * CR0/CR3/CR4/EFER. It's all a bit more complicated if the vCPU
2606 * supports long mode.
660a5d51 2607 */
89651a3d
PB		 2608 if (emulator_has_longmode(ctxt)) {
2609 struct desc_struct cs_desc;
2610
2611 /* Zero CR4.PCIDE before CR0.PG. */
8f4dc2e7
SC		 2612 cr4 = ctxt->ops->get_cr(ctxt, 4);
2613 if (cr4 & X86_CR4_PCIDE)
89651a3d 2614 ctxt->ops->set_cr(ctxt, 4, cr4 & ~X86_CR4_PCIDE);
89651a3d
PB		 2615
2616 /* A 32-bit code segment is required to clear EFER.LMA. */
2617 memset(&cs_desc, 0, sizeof(cs_desc));
2618 cs_desc.type = 0xb;
2619 cs_desc.s = cs_desc.g = cs_desc.p = 1;
2620 ctxt->ops->set_segment(ctxt, 0, &cs_desc, 0, VCPU_SREG_CS);
2621 }
2622
2623 /* For the 64-bit case, this will clear EFER.LMA. */
660a5d51
PB		 2624 cr0 = ctxt->ops->get_cr(ctxt, 0);
2625 if (cr0 & X86_CR0_PE)
2626 ctxt->ops->set_cr(ctxt, 0, cr0 & ~(X86_CR0_PG | X86_CR0_PE));
89651a3d 2627
8f4dc2e7
SC		 2628 if (emulator_has_longmode(ctxt)) {
2629 /* Clear CR4.PAE before clearing EFER.LME. */
2630 cr4 = ctxt->ops->get_cr(ctxt, 4);
2631 if (cr4 & X86_CR4_PAE)
2632 ctxt->ops->set_cr(ctxt, 4, cr4 & ~X86_CR4_PAE);
2633
2634 /* And finally go back to 32-bit mode. */
2635 efer = 0;
2636 ctxt->ops->set_msr(ctxt, MSR_EFER, efer);
2637 }
660a5d51 2638
0234bf88 2639 /*
ecc513e5
SC		 2640 * Give leave_smm() a chance to make ISA-specific changes to the vCPU
2641 * state (e.g. enter guest mode) before loading state from the SMM
0234bf88
LP		 2642 * state-save area.
2643 */
ecc513e5 2644 if (ctxt->ops->leave_smm(ctxt, buf))
25b17226 2645 goto emulate_shutdown;
0234bf88 2646
b68f3cc7 2647#ifdef CONFIG_X86_64
660a5d51 2648 if (emulator_has_longmode(ctxt))
ed19321f 2649 ret = rsm_load_state_64(ctxt, buf);
660a5d51 2650 else
b68f3cc7 2651#endif
ed19321f 2652 ret = rsm_load_state_32(ctxt, buf);
660a5d51 2653
25b17226
SC		 2654 if (ret != X86EMUL_CONTINUE)
2655 goto emulate_shutdown;
660a5d51 2656
01281165
SC		 2657 /*
2658 * Note, the ctxt->ops callbacks are responsible for handling side
2659 * effects when writing MSRs and CRs, e.g. MMU context resets, CPUID
2660 * runtime updates, etc... If that changes, e.g. this flow is moved
2661 * out of the emulator to make it look more like enter_smm(), then
2662 * those side effects need to be explicitly handled for both success
2663 * and shutdown.
2664 */
055f37f8 2665 return emulator_recalc_and_set_mode(ctxt);
25b17226
SC		 2666
2667emulate_shutdown:
2668 ctxt->ops->triple_fault(ctxt);
2669 return X86EMUL_CONTINUE;
64d60670
PB		 2670}
2671
7b105ca2 2672static void
09d9423d 2673setup_syscalls_segments(struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 2674{
e66bb2cc 2675 cs->l = 0; /* will be adjusted later */
79168fd1 2676 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 2677 cs->g = 1; /* 4kb granularity */
79168fd1 2678 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2679 cs->type = 0x0b; /* Read, Execute, Accessed */
2680 cs->s = 1;
2681 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 2682 cs->p = 1;
2683 cs->d = 1;
99245b50 2684 cs->avl = 0;
e66bb2cc 2685
79168fd1
GN		 2686 set_desc_base(ss, 0); /* flat segment */
2687 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2688 ss->g = 1; /* 4kb granularity */
2689 ss->s = 1;
2690 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2691 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2692 ss->dpl = 0;
79168fd1 2693 ss->p = 1;
99245b50
GN		 2694 ss->l = 0;
2695 ss->avl = 0;
e66bb2cc
AP		 2696}
2697
1a18a69b
AK		 2698static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2699{
2700 u32 eax, ebx, ecx, edx;
2701
2702 eax = ecx = 0;
f91af517 2703 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, true);
15608ed0 2704 return is_guest_vendor_intel(ebx, ecx, edx);
1a18a69b
AK		 2705}
2706
c2226fc9
SB		 2707static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2708{
0225fb50 2709 const struct x86_emulate_ops *ops = ctxt->ops;
c2226fc9
SB		 2710 u32 eax, ebx, ecx, edx;
2711
2712 /*
2713 * syscall should always be enabled in longmode - so only become
2714 * vendor specific (cpuid) if other modes are active...
2715 */
2716 if (ctxt->mode == X86EMUL_MODE_PROT64)
2717 return true;
2718
2719 eax = 0x00000000;
2720 ecx = 0x00000000;
f91af517 2721 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, true);
0017f93a 2722 /*
15608ed0
SC		 2723 * remark: Intel CPUs only support "syscall" in 64bit longmode. Also a
2724 * 64bit guest with a 32bit compat-app running will #UD !! While this
2725 * behaviour can be fixed (by emulating) into AMD response - CPUs of
2726 * AMD can't behave like Intel.
0017f93a 2727 */
15608ed0 2728 if (is_guest_vendor_intel(ebx, ecx, edx))
0017f93a
AK		 2729 return false;
2730
15608ed0
SC		 2731 if (is_guest_vendor_amd(ebx, ecx, edx) ||
2732 is_guest_vendor_hygon(ebx, ecx, edx))
b8f4abb6
PW		 2733 return true;
2734
2735 /*
2736 * default: (not Intel, not AMD, not Hygon), apply Intel's
2737 * stricter rules...
2738 */
c2226fc9
SB		 2739 return false;
2740}
2741
e01991e7 2742static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2743{
0225fb50 2744 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2745 struct desc_struct cs, ss;
e66bb2cc 2746 u64 msr_data;
79168fd1 2747 u16 cs_sel, ss_sel;
c2ad2bb3 2748 u64 efer = 0;
e66bb2cc
AP		 2749
2750 /* syscall is not available in real mode */
2e901c4c 2751 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2752 ctxt->mode == X86EMUL_MODE_VM86)
2753 return emulate_ud(ctxt);
e66bb2cc 2754
c2226fc9
SB		 2755 if (!(em_syscall_is_enabled(ctxt)))
2756 return emulate_ud(ctxt);
2757
c2ad2bb3 2758 ops->get_msr(ctxt, MSR_EFER, &efer);
c2226fc9
SB		 2759 if (!(efer & EFER_SCE))
2760 return emulate_ud(ctxt);
2761
09d9423d 2762 setup_syscalls_segments(&cs, &ss);
717746e3 2763 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2764 msr_data >>= 32;
79168fd1
GN		 2765 cs_sel = (u16)(msr_data & 0xfffc);
2766 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2767
c2ad2bb3 2768 if (efer & EFER_LMA) {
79168fd1 2769 cs.d = 0;
e66bb2cc
AP		 2770 cs.l = 1;
2771 }
1aa36616
AK		 2772 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2773 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2774
dd856efa 2775 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
c2ad2bb3 2776 if (efer & EFER_LMA) {
e66bb2cc 2777#ifdef CONFIG_X86_64
6c6cb69b 2778 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags;
e66bb2cc 2779
717746e3 2780 ops->get_msr(ctxt,
3fb1b5db
GN		 2781 ctxt->mode == X86EMUL_MODE_PROT64 ?
2782 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2783 ctxt->_eip = msr_data;
e66bb2cc 2784
717746e3 2785 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
6c6cb69b 2786 ctxt->eflags &= ~msr_data;
35fd68a3 2787 ctxt->eflags |= X86_EFLAGS_FIXED;
e66bb2cc
AP		 2788#endif
2789 } else {
2790 /* legacy mode */
717746e3 2791 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2792 ctxt->_eip = (u32)msr_data;
e66bb2cc 2793
0efb0440 2794 ctxt->eflags &= ~(X86_EFLAGS_VM | X86_EFLAGS_IF);
e66bb2cc
AP		 2795 }
2796
c8401dda 2797 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
e54cfa97 2798 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2799}
2800
e01991e7 2801static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2802{
0225fb50 2803 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2804 struct desc_struct cs, ss;
8c604352 2805 u64 msr_data;
79168fd1 2806 u16 cs_sel, ss_sel;
c2ad2bb3 2807 u64 efer = 0;
8c604352 2808
7b105ca2 2809 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2810 /* inject #GP if in real mode */
35d3d4a1
AK		 2811 if (ctxt->mode == X86EMUL_MODE_REAL)
2812 return emulate_gp(ctxt, 0);
8c604352 2813
1a18a69b
AK		 2814 /*
2815 * Not recognized on AMD in compat mode (but is recognized in legacy
2816 * mode).
2817 */
f3747379 2818 if ((ctxt->mode != X86EMUL_MODE_PROT64) && (efer & EFER_LMA)
1a18a69b
AK		 2819 && !vendor_intel(ctxt))
2820 return emulate_ud(ctxt);
2821
b2c9d43e 2822 /* sysenter/sysexit have not been tested in 64bit mode. */
35d3d4a1 2823 if (ctxt->mode == X86EMUL_MODE_PROT64)
b2c9d43e 2824 return X86EMUL_UNHANDLEABLE;
8c604352 2825
717746e3 2826 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
f3747379
NA		 2827 if ((msr_data & 0xfffc) == 0x0)
2828 return emulate_gp(ctxt, 0);
8c604352 2829
09d9423d 2830 setup_syscalls_segments(&cs, &ss);
0efb0440 2831 ctxt->eflags &= ~(X86_EFLAGS_VM | X86_EFLAGS_IF);
b32a9918 2832 cs_sel = (u16)msr_data & ~SEGMENT_RPL_MASK;
79168fd1 2833 ss_sel = cs_sel + 8;
f3747379 2834 if (efer & EFER_LMA) {
79168fd1 2835 cs.d = 0;
8c604352
AP		 2836 cs.l = 1;
2837 }
2838
1aa36616
AK		 2839 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2840 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2841
717746e3 2842 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
f3747379 2843 ctxt->_eip = (efer & EFER_LMA) ? msr_data : (u32)msr_data;
8c604352 2844
717746e3 2845 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
f3747379
NA		 2846 *reg_write(ctxt, VCPU_REGS_RSP) = (efer & EFER_LMA) ? msr_data :
2847 (u32)msr_data;
943dea8a
SC		 2848 if (efer & EFER_LMA)
2849 ctxt->mode = X86EMUL_MODE_PROT64;
8c604352 2850
e54cfa97 2851 return X86EMUL_CONTINUE;
8c604352
AP		 2852}
2853
e01991e7 2854static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2855{
0225fb50 2856 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2857 struct desc_struct cs, ss;
234f3ce4 2858 u64 msr_data, rcx, rdx;
4668f050 2859 int usermode;
1249b96e 2860 u16 cs_sel = 0, ss_sel = 0;
4668f050 2861
a0044755
GN		 2862 /* inject #GP if in real mode or Virtual 8086 mode */
2863 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2864 ctxt->mode == X86EMUL_MODE_VM86)
2865 return emulate_gp(ctxt, 0);
4668f050 2866
09d9423d 2867 setup_syscalls_segments(&cs, &ss);
4668f050 2868
9dac77fa 2869 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2870 usermode = X86EMUL_MODE_PROT64;
2871 else
2872 usermode = X86EMUL_MODE_PROT32;
2873
234f3ce4
NA		 2874 rcx = reg_read(ctxt, VCPU_REGS_RCX);
2875 rdx = reg_read(ctxt, VCPU_REGS_RDX);
2876
4668f050
AP		 2877 cs.dpl = 3;
2878 ss.dpl = 3;
717746e3 2879 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2880 switch (usermode) {
2881 case X86EMUL_MODE_PROT32:
79168fd1 2882 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2883 if ((msr_data & 0xfffc) == 0x0)
2884 return emulate_gp(ctxt, 0);
79168fd1 2885 ss_sel = (u16)(msr_data + 24);
bf0b682c
NA		 2886 rcx = (u32)rcx;
2887 rdx = (u32)rdx;
4668f050
AP		 2888 break;
2889 case X86EMUL_MODE_PROT64:
79168fd1 2890 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2891 if (msr_data == 0x0)
2892 return emulate_gp(ctxt, 0);
79168fd1
GN		 2893 ss_sel = cs_sel + 8;
2894 cs.d = 0;
4668f050 2895 cs.l = 1;
fd8cb433
YZ		 2896 if (emul_is_noncanonical_address(rcx, ctxt) ||
2897 emul_is_noncanonical_address(rdx, ctxt))
234f3ce4 2898 return emulate_gp(ctxt, 0);
4668f050
AP		 2899 break;
2900 }
b32a9918
NA		 2901 cs_sel |= SEGMENT_RPL_MASK;
2902 ss_sel |= SEGMENT_RPL_MASK;
4668f050 2903
1aa36616
AK		 2904 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2905 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2906
234f3ce4 2907 ctxt->_eip = rdx;
5015bb89 2908 ctxt->mode = usermode;
234f3ce4 2909 *reg_write(ctxt, VCPU_REGS_RSP) = rcx;
4668f050 2910
e54cfa97 2911 return X86EMUL_CONTINUE;
4668f050
AP		 2912}
2913
7b105ca2 2914static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2915{
2916 int iopl;
2917 if (ctxt->mode == X86EMUL_MODE_REAL)
2918 return false;
2919 if (ctxt->mode == X86EMUL_MODE_VM86)
2920 return true;
0efb0440 2921 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> X86_EFLAGS_IOPL_BIT;
7b105ca2 2922 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2923}
2924
9a29d449
LA		 2925#define VMWARE_PORT_VMPORT (0x5658)
2926#define VMWARE_PORT_VMRPC (0x5659)
2927
f850e2e6 2928static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2929 u16 port, u16 len)
2930{
0225fb50 2931 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2932 struct desc_struct tr_seg;
5601d05b 2933 u32 base3;
f850e2e6 2934 int r;
1aa36616 2935 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2936 unsigned mask = (1 << len) - 1;
5601d05b 2937 unsigned long base;
f850e2e6 2938
9a29d449
LA		 2939 /*
2940 * VMware allows access to these ports even if denied
2941 * by TSS I/O permission bitmap. Mimic behavior.
2942 */
2943 if (enable_vmware_backdoor &&
2944 ((port == VMWARE_PORT_VMPORT) || (port == VMWARE_PORT_VMRPC)))
2945 return true;
2946
1aa36616 2947 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2948 if (!tr_seg.p)
f850e2e6 2949 return false;
79168fd1 2950 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2951 return false;
5601d05b
GN		 2952 base = get_desc_base(&tr_seg);
2953#ifdef CONFIG_X86_64
2954 base |= ((u64)base3) << 32;
2955#endif
3c9fa24c 2956 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL, true);
f850e2e6
GN		 2957 if (r != X86EMUL_CONTINUE)
2958 return false;
79168fd1 2959 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2960 return false;
3c9fa24c 2961 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL, true);
f850e2e6
GN		 2962 if (r != X86EMUL_CONTINUE)
2963 return false;
2964 if ((perm >> bit_idx) & mask)
2965 return false;
2966 return true;
2967}
2968
2969static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2970 u16 port, u16 len)
2971{
4fc40f07
GN		 2972 if (ctxt->perm_ok)
2973 return true;
2974
7b105ca2
TY		 2975 if (emulator_bad_iopl(ctxt))
2976 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2977 return false;
4fc40f07
GN		 2978
2979 ctxt->perm_ok = true;
2980
f850e2e6
GN		 2981 return true;
2982}
2983
428e3d08
NA		 2984static void string_registers_quirk(struct x86_emulate_ctxt *ctxt)
2985{
2986 /*
2987 * Intel CPUs mask the counter and pointers in quite strange
2988 * manner when ECX is zero due to REP-string optimizations.
2989 */
2990#ifdef CONFIG_X86_64
2991 if (ctxt->ad_bytes != 4 || !vendor_intel(ctxt))
2992 return;
2993
2994 *reg_write(ctxt, VCPU_REGS_RCX) = 0;
2995
2996 switch (ctxt->b) {
2997 case 0xa4: /* movsb */
2998 case 0xa5: /* movsd/w */
2999 *reg_rmw(ctxt, VCPU_REGS_RSI) &= (u32)-1;
df561f66 3000 fallthrough;
428e3d08
NA		 3001 case 0xaa: /* stosb */
3002 case 0xab: /* stosd/w */
3003 *reg_rmw(ctxt, VCPU_REGS_RDI) &= (u32)-1;
3004 }
3005#endif
3006}
3007
38ba30ba 3008static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 3009 struct tss_segment_16 *tss)
3010{
9dac77fa 3011 tss->ip = ctxt->_eip;
38ba30ba 3012 tss->flag = ctxt->eflags;
dd856efa
AK		 3013 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
3014 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
3015 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
3016 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
3017 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
3018 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
3019 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
3020 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 3021
1aa36616
AK		 3022 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
3023 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
3024 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
3025 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
3026 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 3027}
3028
3029static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 3030 struct tss_segment_16 *tss)
3031{
38ba30ba 3032 int ret;
2356aaeb 3033 u8 cpl;
38ba30ba 3034
9dac77fa 3035 ctxt->_eip = tss->ip;
38ba30ba 3036 ctxt->eflags = tss->flag | 2;
dd856efa
AK		 3037 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
3038 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
3039 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
3040 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
3041 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
3042 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
3043 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
3044 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
38ba30ba
GN		 3045
3046 /*
3047 * SDM says that segment selectors are loaded before segment
3048 * descriptors
3049 */
1aa36616
AK		 3050 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
3051 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
3052 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
3053 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
3054 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba 3055
2356aaeb
PB		 3056 cpl = tss->cs & 3;
3057
38ba30ba 3058 /*
fc058680 3059 * Now load segment descriptors. If fault happens at this stage
38ba30ba
GN		 3060 * it is handled in a context of new task
3061 */
d1442d85 3062 ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl,
3dc4bc4f 3063 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3064 if (ret != X86EMUL_CONTINUE)
3065 return ret;
d1442d85 3066 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
3dc4bc4f 3067 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3068 if (ret != X86EMUL_CONTINUE)
3069 return ret;
d1442d85 3070 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
3dc4bc4f 3071 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3072 if (ret != X86EMUL_CONTINUE)
3073 return ret;
d1442d85 3074 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
3dc4bc4f 3075 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3076 if (ret != X86EMUL_CONTINUE)
3077 return ret;
d1442d85 3078 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
3dc4bc4f 3079 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3080 if (ret != X86EMUL_CONTINUE)
3081 return ret;
3082
3083 return X86EMUL_CONTINUE;
3084}
3085
7127fd36 3086static int task_switch_16(struct x86_emulate_ctxt *ctxt, u16 old_tss_sel,
38ba30ba
GN		 3087 ulong old_tss_base, struct desc_struct *new_desc)
3088{
3089 struct tss_segment_16 tss_seg;
3090 int ret;
bcc55cba 3091 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 3092
0e96f31e 3093 ret = linear_read_system(ctxt, old_tss_base, &tss_seg, sizeof(tss_seg));
db297e3d 3094 if (ret != X86EMUL_CONTINUE)
38ba30ba 3095 return ret;
38ba30ba 3096
7b105ca2 3097 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 3098
0e96f31e 3099 ret = linear_write_system(ctxt, old_tss_base, &tss_seg, sizeof(tss_seg));
db297e3d 3100 if (ret != X86EMUL_CONTINUE)
38ba30ba 3101 return ret;
38ba30ba 3102
0e96f31e 3103 ret = linear_read_system(ctxt, new_tss_base, &tss_seg, sizeof(tss_seg));
db297e3d 3104 if (ret != X86EMUL_CONTINUE)
38ba30ba 3105 return ret;
38ba30ba
GN		 3106
3107 if (old_tss_sel != 0xffff) {
3108 tss_seg.prev_task_link = old_tss_sel;
3109
79367a65
PB		 3110 ret = linear_write_system(ctxt, new_tss_base,
3111 &tss_seg.prev_task_link,
0e96f31e 3112 sizeof(tss_seg.prev_task_link));
db297e3d 3113 if (ret != X86EMUL_CONTINUE)
38ba30ba 3114 return ret;
38ba30ba
GN		 3115 }
3116
7b105ca2 3117 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 3118}
3119
3120static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 3121 struct tss_segment_32 *tss)
3122{
5c7411e2 3123 /* CR3 and ldt selector are not saved intentionally */
9dac77fa 3124 tss->eip = ctxt->_eip;
38ba30ba 3125 tss->eflags = ctxt->eflags;
dd856efa
AK		 3126 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
3127 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
3128 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
3129 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
3130 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
3131 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
3132 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
3133 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 3134
1aa36616
AK		 3135 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
3136 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
3137 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
3138 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
3139 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
3140 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
38ba30ba
GN		 3141}
3142
3143static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 3144 struct tss_segment_32 *tss)
3145{
38ba30ba 3146 int ret;
2356aaeb 3147 u8 cpl;
38ba30ba 3148
7b105ca2 3149 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 3150 return emulate_gp(ctxt, 0);
9dac77fa 3151 ctxt->_eip = tss->eip;
38ba30ba 3152 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 3153
3154 /* General purpose registers */
dd856efa
AK		 3155 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
3156 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
3157 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
3158 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
3159 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
3160 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
3161 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
3162 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
38ba30ba
GN		 3163
3164 /*
3165 * SDM says that segment selectors are loaded before segment
2356aaeb
PB		 3166 * descriptors. This is important because CPL checks will
3167 * use CS.RPL.
38ba30ba 3168 */
1aa36616
AK		 3169 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
3170 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
3171 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
3172 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
3173 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
3174 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
3175 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 3176
4cee4798
KW		 3177 /*
3178 * If we're switching between Protected Mode and VM86, we need to make
3179 * sure to update the mode before loading the segment descriptors so
3180 * that the selectors are interpreted correctly.
4cee4798 3181 */
2356aaeb 3182 if (ctxt->eflags & X86_EFLAGS_VM) {
4cee4798 3183 ctxt->mode = X86EMUL_MODE_VM86;
2356aaeb
PB		 3184 cpl = 3;
3185 } else {
4cee4798 3186 ctxt->mode = X86EMUL_MODE_PROT32;
2356aaeb
PB		 3187 cpl = tss->cs & 3;
3188 }
4cee4798 3189
38ba30ba 3190 /*
d9f6e12f 3191 * Now load segment descriptors. If fault happens at this stage
38ba30ba
GN		 3192 * it is handled in a context of new task
3193 */
d1442d85 3194 ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR,
3dc4bc4f 3195 cpl, X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3196 if (ret != X86EMUL_CONTINUE)
3197 return ret;
d1442d85 3198 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
3dc4bc4f 3199 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3200 if (ret != X86EMUL_CONTINUE)
3201 return ret;
d1442d85 3202 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
3dc4bc4f 3203 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3204 if (ret != X86EMUL_CONTINUE)
3205 return ret;
d1442d85 3206 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
3dc4bc4f 3207 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3208 if (ret != X86EMUL_CONTINUE)
3209 return ret;
d1442d85 3210 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
3dc4bc4f 3211 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3212 if (ret != X86EMUL_CONTINUE)
3213 return ret;
d1442d85 3214 ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl,
3dc4bc4f 3215 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3216 if (ret != X86EMUL_CONTINUE)
3217 return ret;
d1442d85 3218 ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl,
3dc4bc4f 3219 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba 3220
2f729b10 3221 return ret;
38ba30ba
GN		 3222}
3223
7127fd36 3224static int task_switch_32(struct x86_emulate_ctxt *ctxt, u16 old_tss_sel,
38ba30ba
GN		 3225 ulong old_tss_base, struct desc_struct *new_desc)
3226{
3227 struct tss_segment_32 tss_seg;
3228 int ret;
bcc55cba 3229 u32 new_tss_base = get_desc_base(new_desc);
5c7411e2
NA		 3230 u32 eip_offset = offsetof(struct tss_segment_32, eip);
3231 u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector);
38ba30ba 3232
0e96f31e 3233 ret = linear_read_system(ctxt, old_tss_base, &tss_seg, sizeof(tss_seg));
db297e3d 3234 if (ret != X86EMUL_CONTINUE)
38ba30ba 3235 return ret;
38ba30ba 3236
7b105ca2 3237 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 3238
5c7411e2 3239 /* Only GP registers and segment selectors are saved */
79367a65
PB		 3240 ret = linear_write_system(ctxt, old_tss_base + eip_offset, &tss_seg.eip,
3241 ldt_sel_offset - eip_offset);
db297e3d 3242 if (ret != X86EMUL_CONTINUE)
38ba30ba 3243 return ret;
38ba30ba 3244
0e96f31e 3245 ret = linear_read_system(ctxt, new_tss_base, &tss_seg, sizeof(tss_seg));
db297e3d 3246 if (ret != X86EMUL_CONTINUE)
38ba30ba 3247 return ret;
38ba30ba
GN		 3248
3249 if (old_tss_sel != 0xffff) {
3250 tss_seg.prev_task_link = old_tss_sel;
3251
79367a65
PB		 3252 ret = linear_write_system(ctxt, new_tss_base,
3253 &tss_seg.prev_task_link,
0e96f31e 3254 sizeof(tss_seg.prev_task_link));
db297e3d 3255 if (ret != X86EMUL_CONTINUE)
38ba30ba 3256 return ret;
38ba30ba
GN		 3257 }
3258
7b105ca2 3259 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 3260}
3261
3262static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 3263 u16 tss_selector, int idt_index, int reason,
e269fb21 3264 bool has_error_code, u32 error_code)
38ba30ba 3265{
0225fb50 3266 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 3267 struct desc_struct curr_tss_desc, next_tss_desc;
3268 int ret;
1aa36616 3269 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 3270 ulong old_tss_base =
4bff1e86 3271 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 3272 u32 desc_limit;
3db176d5 3273 ulong desc_addr, dr7;
38ba30ba
GN		 3274
3275 /* FIXME: old_tss_base == ~0 ? */
3276
e919464b 3277 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
38ba30ba
GN		 3278 if (ret != X86EMUL_CONTINUE)
3279 return ret;
e919464b 3280 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
38ba30ba
GN		 3281 if (ret != X86EMUL_CONTINUE)
3282 return ret;
3283
3284 /* FIXME: check that next_tss_desc is tss */
3285
7f3d35fd
KW		 3286 /*
3287 * Check privileges. The three cases are task switch caused by...
3288 *
3289 * 1. jmp/call/int to task gate: Check against DPL of the task gate
3290 * 2. Exception/IRQ/iret: No check is performed
2c2ca2d1
NA		 3291 * 3. jmp/call to TSS/task-gate: No check is performed since the
3292 * hardware checks it before exiting.
7f3d35fd
KW		 3293 */
3294 if (reason == TASK_SWITCH_GATE) {
3295 if (idt_index != -1) {
3296 /* Software interrupts */
3297 struct desc_struct task_gate_desc;
3298 int dpl;
3299
3300 ret = read_interrupt_descriptor(ctxt, idt_index,
3301 &task_gate_desc);
3302 if (ret != X86EMUL_CONTINUE)
3303 return ret;
3304
3305 dpl = task_gate_desc.dpl;
3306 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
3307 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
3308 }
38ba30ba
GN		 3309 }
3310
ceffb459
GN		 3311 desc_limit = desc_limit_scaled(&next_tss_desc);
3312 if (!next_tss_desc.p ||
3313 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
3314 desc_limit < 0x2b)) {
592f0858 3315 return emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 3316 }
3317
3318 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3319 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 3320 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 3321 }
3322
3323 if (reason == TASK_SWITCH_IRET)
3324 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
3325
3326 /* set back link to prev task only if NT bit is set in eflags
fc058680 3327 note that old_tss_sel is not used after this point */
38ba30ba
GN		 3328 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
3329 old_tss_sel = 0xffff;
3330
3331 if (next_tss_desc.type & 8)
7127fd36 3332 ret = task_switch_32(ctxt, old_tss_sel, old_tss_base, &next_tss_desc);
38ba30ba 3333 else
7127fd36 3334 ret = task_switch_16(ctxt, old_tss_sel,
38ba30ba 3335 old_tss_base, &next_tss_desc);
0760d448
JK		 3336 if (ret != X86EMUL_CONTINUE)
3337 return ret;
38ba30ba
GN		 3338
3339 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
3340 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
3341
3342 if (reason != TASK_SWITCH_IRET) {
3343 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 3344 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 3345 }
3346
717746e3 3347 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 3348 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 3349
e269fb21 3350 if (has_error_code) {
9dac77fa
AK		 3351 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
3352 ctxt->lock_prefix = 0;
3353 ctxt->src.val = (unsigned long) error_code;
4487b3b4 3354 ret = em_push(ctxt);
e269fb21
JK		 3355 }
3356
3db176d5
NA		 3357 ops->get_dr(ctxt, 7, &dr7);
3358 ops->set_dr(ctxt, 7, dr7 & ~(DR_LOCAL_ENABLE_MASK | DR_LOCAL_SLOWDOWN));
3359
38ba30ba
GN		 3360 return ret;
3361}
3362
3363int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 3364 u16 tss_selector, int idt_index, int reason,
e269fb21 3365 bool has_error_code, u32 error_code)
38ba30ba 3366{
38ba30ba
GN		 3367 int rc;
3368
dd856efa 3369 invalidate_registers(ctxt);
9dac77fa
AK		 3370 ctxt->_eip = ctxt->eip;
3371 ctxt->dst.type = OP_NONE;
38ba30ba 3372
7f3d35fd 3373 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 3374 has_error_code, error_code);
38ba30ba 3375
dd856efa 3376 if (rc == X86EMUL_CONTINUE) {
9dac77fa 3377 ctxt->eip = ctxt->_eip;
dd856efa
AK		 3378 writeback_registers(ctxt);
3379 }
38ba30ba 3380
a0c0ab2f 3381 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 3382}
3383
f3bd64c6
GN		 3384static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
3385 struct operand *op)
a682e354 3386{
0efb0440 3387 int df = (ctxt->eflags & X86_EFLAGS_DF) ? -op->count : op->count;
a682e354 3388
01485a22
PB		 3389 register_address_increment(ctxt, reg, df * op->bytes);
3390 op->addr.mem.ea = register_address(ctxt, reg);
a682e354
GN		 3391}
3392
7af04fc0
AK		 3393static int em_das(struct x86_emulate_ctxt *ctxt)
3394{
7af04fc0
AK		 3395 u8 al, old_al;
3396 bool af, cf, old_cf;
3397
3398 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 3399 al = ctxt->dst.val;
7af04fc0
AK		 3400
3401 old_al = al;
3402 old_cf = cf;
3403 cf = false;
3404 af = ctxt->eflags & X86_EFLAGS_AF;
3405 if ((al & 0x0f) > 9 || af) {
3406 al -= 6;
3407 cf = old_cf | (al >= 250);
3408 af = true;
3409 } else {
3410 af = false;
3411 }
3412 if (old_al > 0x99 || old_cf) {
3413 al -= 0x60;
3414 cf = true;
3415 }
3416
9dac77fa 3417 ctxt->dst.val = al;
7af04fc0 3418 /* Set PF, ZF, SF */
9dac77fa
AK		 3419 ctxt->src.type = OP_IMM;
3420 ctxt->src.val = 0;
3421 ctxt->src.bytes = 1;
158de57f 3422 fastop(ctxt, em_or);
7af04fc0
AK		 3423 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
3424 if (cf)
3425 ctxt->eflags |= X86_EFLAGS_CF;
3426 if (af)
3427 ctxt->eflags |= X86_EFLAGS_AF;
3428 return X86EMUL_CONTINUE;
3429}
3430
a035d5c6
PB		 3431static int em_aam(struct x86_emulate_ctxt *ctxt)
3432{
3433 u8 al, ah;
3434
3435 if (ctxt->src.val == 0)
3436 return emulate_de(ctxt);
3437
3438 al = ctxt->dst.val & 0xff;
3439 ah = al / ctxt->src.val;
3440 al %= ctxt->src.val;
3441
3442 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);
3443
3444 /* Set PF, ZF, SF */
3445 ctxt->src.type = OP_IMM;
3446 ctxt->src.val = 0;
3447 ctxt->src.bytes = 1;
3448 fastop(ctxt, em_or);
3449
3450 return X86EMUL_CONTINUE;
3451}
3452
7f662273
GN		 3453static int em_aad(struct x86_emulate_ctxt *ctxt)
3454{
3455 u8 al = ctxt->dst.val & 0xff;
3456 u8 ah = (ctxt->dst.val >> 8) & 0xff;
3457
3458 al = (al + (ah * ctxt->src.val)) & 0xff;
3459
3460 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
3461
f583c29b
GN		 3462 /* Set PF, ZF, SF */
3463 ctxt->src.type = OP_IMM;
3464 ctxt->src.val = 0;
3465 ctxt->src.bytes = 1;
3466 fastop(ctxt, em_or);
7f662273
GN		 3467
3468 return X86EMUL_CONTINUE;
3469}
3470
d4ddafcd
TY		 3471static int em_call(struct x86_emulate_ctxt *ctxt)
3472{
234f3ce4 3473 int rc;
d4ddafcd
TY		 3474 long rel = ctxt->src.val;
3475
3476 ctxt->src.val = (unsigned long)ctxt->_eip;
234f3ce4
NA		 3477 rc = jmp_rel(ctxt, rel);
3478 if (rc != X86EMUL_CONTINUE)
3479 return rc;
d4ddafcd
TY		 3480 return em_push(ctxt);
3481}
3482
0ef753b8
AK		 3483static int em_call_far(struct x86_emulate_ctxt *ctxt)
3484{
0ef753b8
AK		 3485 u16 sel, old_cs;
3486 ulong old_eip;
3487 int rc;
d1442d85
NA		 3488 struct desc_struct old_desc, new_desc;
3489 const struct x86_emulate_ops *ops = ctxt->ops;
3490 int cpl = ctxt->ops->cpl(ctxt);
82268083 3491 enum x86emul_mode prev_mode = ctxt->mode;
0ef753b8 3492
9dac77fa 3493 old_eip = ctxt->_eip;
d1442d85 3494 ops->get_segment(ctxt, &old_cs, &old_desc, NULL, VCPU_SREG_CS);
0ef753b8 3495
9dac77fa 3496 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
3dc4bc4f
NA		 3497 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl,
3498 X86_TRANSFER_CALL_JMP, &new_desc);
d1442d85 3499 if (rc != X86EMUL_CONTINUE)
80976dbb 3500 return rc;
0ef753b8 3501
d087e0f7 3502 rc = assign_eip_far(ctxt, ctxt->src.val);
d1442d85
NA		 3503 if (rc != X86EMUL_CONTINUE)
3504 goto fail;
0ef753b8 3505
9dac77fa 3506 ctxt->src.val = old_cs;
4487b3b4 3507 rc = em_push(ctxt);
0ef753b8 3508 if (rc != X86EMUL_CONTINUE)
d1442d85 3509 goto fail;
0ef753b8 3510
9dac77fa 3511 ctxt->src.val = old_eip;
d1442d85
NA		 3512 rc = em_push(ctxt);
3513 /* If we failed, we tainted the memory, but the very least we should
3514 restore cs */
82268083
NA		 3515 if (rc != X86EMUL_CONTINUE) {
3516 pr_warn_once("faulting far call emulation tainted memory\n");
d1442d85 3517 goto fail;
82268083 3518 }
d1442d85
NA		 3519 return rc;
3520fail:
3521 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
82268083 3522 ctxt->mode = prev_mode;
d1442d85
NA		 3523 return rc;
3524
0ef753b8
AK		 3525}
3526
40ece7c7
AK		 3527static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
3528{
40ece7c7 3529 int rc;
234f3ce4 3530 unsigned long eip;
40ece7c7 3531
234f3ce4
NA		 3532 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
3533 if (rc != X86EMUL_CONTINUE)
3534 return rc;
3535 rc = assign_eip_near(ctxt, eip);
40ece7c7
AK		 3536 if (rc != X86EMUL_CONTINUE)
3537 return rc;
5ad105e5 3538 rsp_increment(ctxt, ctxt->src.val);
40ece7c7
AK		 3539 return X86EMUL_CONTINUE;
3540}
3541
e4f973ae
TY		 3542static int em_xchg(struct x86_emulate_ctxt *ctxt)
3543{
e4f973ae 3544 /* Write back the register source. */
9dac77fa
AK		 3545 ctxt->src.val = ctxt->dst.val;
3546 write_register_operand(&ctxt->src);
e4f973ae
TY		 3547
3548 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 3549 ctxt->dst.val = ctxt->src.orig_val;
3550 ctxt->lock_prefix = 1;
e4f973ae
TY		 3551 return X86EMUL_CONTINUE;
3552}
3553
5c82aa29
AK		 3554static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
3555{
9dac77fa 3556 ctxt->dst.val = ctxt->src2.val;
4d758349 3557 return fastop(ctxt, em_imul);
5c82aa29
AK		 3558}
3559
61429142
AK		 3560static int em_cwd(struct x86_emulate_ctxt *ctxt)
3561{
9dac77fa
AK		 3562 ctxt->dst.type = OP_REG;
3563 ctxt->dst.bytes = ctxt->src.bytes;
dd856efa 3564 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
9dac77fa 3565 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 3566
3567 return X86EMUL_CONTINUE;
3568}
3569
fb6d4d34
PB		 3570static int em_rdpid(struct x86_emulate_ctxt *ctxt)
3571{
3572 u64 tsc_aux = 0;
3573
a836839c 3574 if (!ctxt->ops->guest_has_rdpid(ctxt))
a9e2e0ae 3575 return emulate_ud(ctxt);
a836839c
HW		 3576
3577 ctxt->ops->get_msr(ctxt, MSR_TSC_AUX, &tsc_aux);
fb6d4d34
PB		 3578 ctxt->dst.val = tsc_aux;
3579 return X86EMUL_CONTINUE;
3580}
3581
48bb5d3c
AK		 3582static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
3583{
48bb5d3c
AK		 3584 u64 tsc = 0;
3585
717746e3 3586 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
dd856efa
AK		 3587 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
3588 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
48bb5d3c
AK		 3589 return X86EMUL_CONTINUE;
3590}
3591
222d21aa
AK		 3592static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
3593{
3594 u64 pmc;
3595
dd856efa 3596 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
222d21aa 3597 return emulate_gp(ctxt, 0);
dd856efa
AK		 3598 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
3599 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
222d21aa
AK		 3600 return X86EMUL_CONTINUE;
3601}
3602
b9eac5f4
AK		 3603static int em_mov(struct x86_emulate_ctxt *ctxt)
3604{
54cfdb3e 3605 memcpy(ctxt->dst.valptr, ctxt->src.valptr, sizeof(ctxt->src.valptr));
b9eac5f4
AK		 3606 return X86EMUL_CONTINUE;
3607}
3608
84cffe49
BP		 3609static int em_movbe(struct x86_emulate_ctxt *ctxt)
3610{
84cffe49
BP		 3611 u16 tmp;
3612
5ae78e95 3613 if (!ctxt->ops->guest_has_movbe(ctxt))
84cffe49
BP		 3614 return emulate_ud(ctxt);
3615
3616 switch (ctxt->op_bytes) {
3617 case 2:
3618 /*
3619 * From MOVBE definition: "...When the operand size is 16 bits,
3620 * the upper word of the destination register remains unchanged
3621 * ..."
3622 *
3623 * Both casting ->valptr and ->val to u16 breaks strict aliasing
3624 * rules so we have to do the operation almost per hand.
3625 */
3626 tmp = (u16)ctxt->src.val;
3627 ctxt->dst.val &= ~0xffffUL;
3628 ctxt->dst.val |= (unsigned long)swab16(tmp);
3629 break;
3630 case 4:
3631 ctxt->dst.val = swab32((u32)ctxt->src.val);
3632 break;
3633 case 8:
3634 ctxt->dst.val = swab64(ctxt->src.val);
3635 break;
3636 default:
592f0858 3637 BUG();
84cffe49
BP		 3638 }
3639 return X86EMUL_CONTINUE;
3640}
3641
bc00f8d2
TY		 3642static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3643{
ad8f9e69
ML		 3644 int cr_num = ctxt->modrm_reg;
3645 int r;
3646
3647 if (ctxt->ops->set_cr(ctxt, cr_num, ctxt->src.val))
bc00f8d2
TY		 3648 return emulate_gp(ctxt, 0);
3649
3650 /* Disable writeback. */
3651 ctxt->dst.type = OP_NONE;
ad8f9e69
ML		 3652
3653 if (cr_num == 0) {
3654 /*
3655 * CR0 write might have updated CR0.PE and/or CR0.PG
3656 * which can affect the cpu's execution mode.
3657 */
3658 r = emulator_recalc_and_set_mode(ctxt);
3659 if (r != X86EMUL_CONTINUE)
3660 return r;
3661 }
3662
bc00f8d2
TY		 3663 return X86EMUL_CONTINUE;
3664}
3665
3666static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3667{
3668 unsigned long val;
3669
3670 if (ctxt->mode == X86EMUL_MODE_PROT64)
3671 val = ctxt->src.val & ~0ULL;
3672 else
3673 val = ctxt->src.val & ~0U;
3674
3675 /* #UD condition is already handled. */
3676 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3677 return emulate_gp(ctxt, 0);
3678
3679 /* Disable writeback. */
3680 ctxt->dst.type = OP_NONE;
3681 return X86EMUL_CONTINUE;
3682}
3683
e1e210b0
TY		 3684static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3685{
1ae09954 3686 u64 msr_index = reg_read(ctxt, VCPU_REGS_RCX);
e1e210b0 3687 u64 msr_data;
1ae09954 3688 int r;
e1e210b0 3689
dd856efa
AK		 3690 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3691 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
ac8d6cad 3692 r = ctxt->ops->set_msr_with_filter(ctxt, msr_index, msr_data);
1ae09954 3693
36d546d5 3694 if (r == X86EMUL_PROPAGATE_FAULT)
e1e210b0
TY		 3695 return emulate_gp(ctxt, 0);
3696
36d546d5 3697 return r;
e1e210b0
TY		 3698}
3699
3700static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3701{
1ae09954 3702 u64 msr_index = reg_read(ctxt, VCPU_REGS_RCX);
e1e210b0 3703 u64 msr_data;
1ae09954
AG		 3704 int r;
3705
ac8d6cad 3706 r = ctxt->ops->get_msr_with_filter(ctxt, msr_index, &msr_data);
1ae09954 3707
36d546d5 3708 if (r == X86EMUL_PROPAGATE_FAULT)
e1e210b0
TY		 3709 return emulate_gp(ctxt, 0);
3710
36d546d5
HW		 3711 if (r == X86EMUL_CONTINUE) {
3712 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3713 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
3714 }
3715 return r;
e1e210b0
TY		 3716}
3717
dd307d01 3718static int em_store_sreg(struct x86_emulate_ctxt *ctxt, int segment)
1bd5f469 3719{
dd307d01
PB		 3720 if (segment > VCPU_SREG_GS &&
3721 (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_UMIP) &&
3722 ctxt->ops->cpl(ctxt) > 0)
3723 return emulate_gp(ctxt, 0);
1bd5f469 3724
dd307d01 3725 ctxt->dst.val = get_segment_selector(ctxt, segment);
b5bbf10e
NA		 3726 if (ctxt->dst.bytes == 4 && ctxt->dst.type == OP_MEM)
3727 ctxt->dst.bytes = 2;
1bd5f469
TY		 3728 return X86EMUL_CONTINUE;
3729}
3730
dd307d01
PB		 3731static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3732{
3733 if (ctxt->modrm_reg > VCPU_SREG_GS)
3734 return emulate_ud(ctxt);
3735
3736 return em_store_sreg(ctxt, ctxt->modrm_reg);
3737}
3738
1bd5f469
TY		 3739static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3740{
9dac77fa 3741 u16 sel = ctxt->src.val;
1bd5f469 3742
9dac77fa 3743 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3744 return emulate_ud(ctxt);
3745
9dac77fa 3746 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 3747 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3748
3749 /* Disable writeback. */
9dac77fa
AK		 3750 ctxt->dst.type = OP_NONE;
3751 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 3752}
3753
dd307d01
PB		 3754static int em_sldt(struct x86_emulate_ctxt *ctxt)
3755{
3756 return em_store_sreg(ctxt, VCPU_SREG_LDTR);
3757}
3758
a14e579f
AK		 3759static int em_lldt(struct x86_emulate_ctxt *ctxt)
3760{
3761 u16 sel = ctxt->src.val;
3762
3763 /* Disable writeback. */
3764 ctxt->dst.type = OP_NONE;
3765 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3766}
3767
dd307d01
PB		 3768static int em_str(struct x86_emulate_ctxt *ctxt)
3769{
3770 return em_store_sreg(ctxt, VCPU_SREG_TR);
3771}
3772
80890006
AK		 3773static int em_ltr(struct x86_emulate_ctxt *ctxt)
3774{
3775 u16 sel = ctxt->src.val;
3776
3777 /* Disable writeback. */
3778 ctxt->dst.type = OP_NONE;
3779 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3780}
3781
38503911
AK		 3782static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3783{
9fa088f4
AK		 3784 int rc;
3785 ulong linear;
3786
9dac77fa 3787 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 3788 if (rc == X86EMUL_CONTINUE)
3cb16fe7 3789 ctxt->ops->invlpg(ctxt, linear);
38503911 3790 /* Disable writeback. */
9dac77fa 3791 ctxt->dst.type = OP_NONE;
38503911
AK		 3792 return X86EMUL_CONTINUE;
3793}
3794
2d04a05b
AK		 3795static int em_clts(struct x86_emulate_ctxt *ctxt)
3796{
3797 ulong cr0;
3798
3799 cr0 = ctxt->ops->get_cr(ctxt, 0);
3800 cr0 &= ~X86_CR0_TS;
3801 ctxt->ops->set_cr(ctxt, 0, cr0);
3802 return X86EMUL_CONTINUE;
3803}
3804
b34a8051 3805static int em_hypercall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3806{
0f54a321 3807 int rc = ctxt->ops->fix_hypercall(ctxt);
26d05cc7 3808
26d05cc7
AK		 3809 if (rc != X86EMUL_CONTINUE)
3810 return rc;
3811
3812 /* Let the processor re-execute the fixed hypercall */
9dac77fa 3813 ctxt->_eip = ctxt->eip;
26d05cc7 3814 /* Disable writeback. */
9dac77fa 3815 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3816 return X86EMUL_CONTINUE;
3817}
3818
96051572
AK		 3819static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3820 void (*get)(struct x86_emulate_ctxt *ctxt,
3821 struct desc_ptr *ptr))
3822{
3823 struct desc_ptr desc_ptr;
3824
ae3e61e1
PB		 3825 if ((ctxt->ops->get_cr(ctxt, 4) & X86_CR4_UMIP) &&
3826 ctxt->ops->cpl(ctxt) > 0)
3827 return emulate_gp(ctxt, 0);
3828
96051572
AK		 3829 if (ctxt->mode == X86EMUL_MODE_PROT64)
3830 ctxt->op_bytes = 8;
3831 get(ctxt, &desc_ptr);
3832 if (ctxt->op_bytes == 2) {
3833 ctxt->op_bytes = 4;
3834 desc_ptr.address &= 0x00ffffff;
3835 }
3836 /* Disable writeback. */
3837 ctxt->dst.type = OP_NONE;
129a72a0
SR		 3838 return segmented_write_std(ctxt, ctxt->dst.addr.mem,
3839 &desc_ptr, 2 + ctxt->op_bytes);
96051572
AK		 3840}
3841
3842static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3843{
3844 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3845}
3846
3847static int em_sidt(struct x86_emulate_ctxt *ctxt)
3848{
3849 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3850}
3851
5b7f6a1e 3852static int em_lgdt_lidt(struct x86_emulate_ctxt *ctxt, bool lgdt)
26d05cc7 3853{
26d05cc7
AK		 3854 struct desc_ptr desc_ptr;
3855 int rc;
3856
510425ff
AK		 3857 if (ctxt->mode == X86EMUL_MODE_PROT64)
3858 ctxt->op_bytes = 8;
9dac77fa 3859 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3860 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3861 ctxt->op_bytes);
26d05cc7
AK		 3862 if (rc != X86EMUL_CONTINUE)
3863 return rc;
9a9abf6b 3864 if (ctxt->mode == X86EMUL_MODE_PROT64 &&
fd8cb433 3865 emul_is_noncanonical_address(desc_ptr.address, ctxt))
9a9abf6b 3866 return emulate_gp(ctxt, 0);
5b7f6a1e
NA		 3867 if (lgdt)
3868 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3869 else
3870 ctxt->ops->set_idt(ctxt, &desc_ptr);
26d05cc7 3871 /* Disable writeback. */
9dac77fa 3872 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3873 return X86EMUL_CONTINUE;
3874}
3875
5b7f6a1e
NA		 3876static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3877{
3878 return em_lgdt_lidt(ctxt, true);
3879}
3880
26d05cc7
AK		 3881static int em_lidt(struct x86_emulate_ctxt *ctxt)
3882{
5b7f6a1e 3883 return em_lgdt_lidt(ctxt, false);
26d05cc7
AK		 3884}
3885
3886static int em_smsw(struct x86_emulate_ctxt *ctxt)
3887{
ae3e61e1
PB		 3888 if ((ctxt->ops->get_cr(ctxt, 4) & X86_CR4_UMIP) &&
3889 ctxt->ops->cpl(ctxt) > 0)
3890 return emulate_gp(ctxt, 0);
3891
32e94d06
NA		 3892 if (ctxt->dst.type == OP_MEM)
3893 ctxt->dst.bytes = 2;
9dac77fa 3894 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3895 return X86EMUL_CONTINUE;
3896}
3897
3898static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3899{
26d05cc7 3900 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3901 | (ctxt->src.val & 0x0f));
3902 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3903 return X86EMUL_CONTINUE;
3904}
3905
d06e03ad
TY		 3906static int em_loop(struct x86_emulate_ctxt *ctxt)
3907{
234f3ce4
NA		 3908 int rc = X86EMUL_CONTINUE;
3909
01485a22 3910 register_address_increment(ctxt, VCPU_REGS_RCX, -1);
dd856efa 3911 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
9dac77fa 3912 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
234f3ce4 3913 rc = jmp_rel(ctxt, ctxt->src.val);
d06e03ad 3914
234f3ce4 3915 return rc;
d06e03ad
TY		 3916}
3917
3918static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3919{
234f3ce4
NA		 3920 int rc = X86EMUL_CONTINUE;
3921
dd856efa 3922 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
234f3ce4 3923 rc = jmp_rel(ctxt, ctxt->src.val);
d06e03ad 3924
234f3ce4 3925 return rc;
d06e03ad
TY		 3926}
3927
d7841a4b
TY		 3928static int em_in(struct x86_emulate_ctxt *ctxt)
3929{
3930 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3931 &ctxt->dst.val))
3932 return X86EMUL_IO_NEEDED;
3933
3934 return X86EMUL_CONTINUE;
3935}
3936
3937static int em_out(struct x86_emulate_ctxt *ctxt)
3938{
3939 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3940 &ctxt->src.val, 1);
3941 /* Disable writeback. */
3942 ctxt->dst.type = OP_NONE;
3943 return X86EMUL_CONTINUE;
3944}
3945
f411e6cd
TY		 3946static int em_cli(struct x86_emulate_ctxt *ctxt)
3947{
3948 if (emulator_bad_iopl(ctxt))
3949 return emulate_gp(ctxt, 0);
3950
3951 ctxt->eflags &= ~X86_EFLAGS_IF;
3952 return X86EMUL_CONTINUE;
3953}
3954
3955static int em_sti(struct x86_emulate_ctxt *ctxt)
3956{
3957 if (emulator_bad_iopl(ctxt))
3958 return emulate_gp(ctxt, 0);
3959
3960 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3961 ctxt->eflags |= X86_EFLAGS_IF;
3962 return X86EMUL_CONTINUE;
3963}
3964
6d6eede4
AK		 3965static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3966{
3967 u32 eax, ebx, ecx, edx;
db2336a8
KH		 3968 u64 msr = 0;
3969
3970 ctxt->ops->get_msr(ctxt, MSR_MISC_FEATURES_ENABLES, &msr);
3971 if (msr & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
3972 ctxt->ops->cpl(ctxt)) {
3973 return emulate_gp(ctxt, 0);
3974 }
6d6eede4 3975
dd856efa
AK		 3976 eax = reg_read(ctxt, VCPU_REGS_RAX);
3977 ecx = reg_read(ctxt, VCPU_REGS_RCX);
f91af517 3978 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, false);
dd856efa
AK		 3979 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3980 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3981 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3982 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
6d6eede4
AK		 3983 return X86EMUL_CONTINUE;
3984}
3985
98f73630
PB		 3986static int em_sahf(struct x86_emulate_ctxt *ctxt)
3987{
3988 u32 flags;
3989
0efb0440
NA		 3990 flags = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
3991 X86_EFLAGS_SF;
98f73630
PB		 3992 flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8;
3993
3994 ctxt->eflags &= ~0xffUL;
3995 ctxt->eflags |= flags | X86_EFLAGS_FIXED;
3996 return X86EMUL_CONTINUE;
3997}
3998
2dd7caa0
AK		 3999static int em_lahf(struct x86_emulate_ctxt *ctxt)
4000{
dd856efa
AK		 4001 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
4002 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
2dd7caa0
AK		 4003 return X86EMUL_CONTINUE;
4004}
4005
9299836e
AK		 4006static int em_bswap(struct x86_emulate_ctxt *ctxt)
4007{
4008 switch (ctxt->op_bytes) {
4009#ifdef CONFIG_X86_64
4010 case 8:
4011 asm("bswap %0" : "+r"(ctxt->dst.val));
4012 break;
4013#endif
4014 default:
4015 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
4016 break;
4017 }
4018 return X86EMUL_CONTINUE;
4019}
4020
13e457e0
NA		 4021static int em_clflush(struct x86_emulate_ctxt *ctxt)
4022{
4023 /* emulating clflush regardless of cpuid */
4024 return X86EMUL_CONTINUE;
4025}
4026
51b958e5
DE		 4027static int em_clflushopt(struct x86_emulate_ctxt *ctxt)
4028{
4029 /* emulating clflushopt regardless of cpuid */
4030 return X86EMUL_CONTINUE;
4031}
4032
2276b511
NA		 4033static int em_movsxd(struct x86_emulate_ctxt *ctxt)
4034{
4035 ctxt->dst.val = (s32) ctxt->src.val;
4036 return X86EMUL_CONTINUE;
4037}
4038
283c95d0
RK		 4039static int check_fxsr(struct x86_emulate_ctxt *ctxt)
4040{
5ae78e95 4041 if (!ctxt->ops->guest_has_fxsr(ctxt))
283c95d0
RK		 4042 return emulate_ud(ctxt);
4043
4044 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
4045 return emulate_nm(ctxt);
4046
4047 /*
4048 * Don't emulate a case that should never be hit, instead of working
4049 * around a lack of fxsave64/fxrstor64 on old compilers.
4050 */
4051 if (ctxt->mode >= X86EMUL_MODE_PROT64)
4052 return X86EMUL_UNHANDLEABLE;
4053
4054 return X86EMUL_CONTINUE;
4055}
4056
9d643f63
ND		 4057/*
4058 * Hardware doesn't save and restore XMM 0-7 without CR4.OSFXSR, but does save
4059 * and restore MXCSR.
4060 */
4061static size_t __fxstate_size(int nregs)
4062{
4063 return offsetof(struct fxregs_state, xmm_space[0]) + nregs * 16;
4064}
4065
4066static inline size_t fxstate_size(struct x86_emulate_ctxt *ctxt)
4067{
4068 bool cr4_osfxsr;
4069 if (ctxt->mode == X86EMUL_MODE_PROT64)
4070 return __fxstate_size(16);
4071
4072 cr4_osfxsr = ctxt->ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR;
4073 return __fxstate_size(cr4_osfxsr ? 8 : 0);
4074}
4075
283c95d0
RK		 4076/*
4077 * FXSAVE and FXRSTOR have 4 different formats depending on execution mode,
4078 * 1) 16 bit mode
4079 * 2) 32 bit mode
4080 * - like (1), but FIP and FDP (foo) are only 16 bit. At least Intel CPUs
4081 * preserve whole 32 bit values, though, so (1) and (2) are the same wrt.
4082 * save and restore
4083 * 3) 64-bit mode with REX.W prefix
4084 * - like (2), but XMM 8-15 are being saved and restored
4085 * 4) 64-bit mode without REX.W prefix
4086 * - like (3), but FIP and FDP are 64 bit
4087 *
4088 * Emulation uses (3) for (1) and (2) and preserves XMM 8-15 to reach the
4089 * desired result. (4) is not emulated.
4090 *
4091 * Note: Guest and host CPUID.(EAX=07H,ECX=0H):EBX[bit 13] (deprecate FPU CS
4092 * and FPU DS) should match.
4093 */
4094static int em_fxsave(struct x86_emulate_ctxt *ctxt)
4095{
4096 struct fxregs_state fx_state;
283c95d0
RK		 4097 int rc;
4098
4099 rc = check_fxsr(ctxt);
4100 if (rc != X86EMUL_CONTINUE)
4101 return rc;
4102
43e51464 4103 kvm_fpu_get();
a7baead7 4104
283c95d0
RK		 4105 rc = asm_safe("fxsave %[fx]", , [fx] "+m"(fx_state));
4106
43e51464 4107 kvm_fpu_put();
a7baead7 4108
283c95d0
RK		 4109 if (rc != X86EMUL_CONTINUE)
4110 return rc;
4111
9d643f63
ND		 4112 return segmented_write_std(ctxt, ctxt->memop.addr.mem, &fx_state,
4113 fxstate_size(ctxt));
283c95d0
RK		 4114}
4115
4d772cb8
DH		 4116/*
4117 * FXRSTOR might restore XMM registers not provided by the guest. Fill
4118 * in the host registers (via FXSAVE) instead, so they won't be modified.
4119 * (preemption has to stay disabled until FXRSTOR).
4120 *
4121 * Use noinline to keep the stack for other functions called by callers small.
4122 */
4123static noinline int fxregs_fixup(struct fxregs_state *fx_state,
4124 const size_t used_size)
4125{
4126 struct fxregs_state fx_tmp;
4127 int rc;
4128
4129 rc = asm_safe("fxsave %[fx]", , [fx] "+m"(fx_tmp));
4130 memcpy((void *)fx_state + used_size, (void *)&fx_tmp + used_size,
4131 __fxstate_size(16) - used_size);
4132
4133 return rc;
4134}
4135
283c95d0
RK		 4136static int em_fxrstor(struct x86_emulate_ctxt *ctxt)
4137{
4138 struct fxregs_state fx_state;
4139 int rc;
9d643f63 4140 size_t size;
283c95d0
RK		 4141
4142 rc = check_fxsr(ctxt);
4143 if (rc != X86EMUL_CONTINUE)
4144 return rc;
4145
4d772cb8
DH		 4146 size = fxstate_size(ctxt);
4147 rc = segmented_read_std(ctxt, ctxt->memop.addr.mem, &fx_state, size);
4148 if (rc != X86EMUL_CONTINUE)
4149 return rc;
4150
43e51464 4151 kvm_fpu_get();
a7baead7 4152
9d643f63 4153 if (size < __fxstate_size(16)) {
4d772cb8 4154 rc = fxregs_fixup(&fx_state, size);
9d643f63
ND		 4155 if (rc != X86EMUL_CONTINUE)
4156 goto out;
4157 }
283c95d0 4158
9d643f63
ND		 4159 if (fx_state.mxcsr >> 16) {
4160 rc = emulate_gp(ctxt, 0);
4161 goto out;
4162 }
283c95d0
RK		 4163
4164 if (rc == X86EMUL_CONTINUE)
4165 rc = asm_safe("fxrstor %[fx]", : [fx] "m"(fx_state));
4166
9d643f63 4167out:
43e51464 4168 kvm_fpu_put();
a7baead7 4169
283c95d0
RK		 4170 return rc;
4171}
4172
02d4160f
VK		 4173static int em_xsetbv(struct x86_emulate_ctxt *ctxt)
4174{
4175 u32 eax, ecx, edx;
4176
50b2d49b
SC		 4177 if (!(ctxt->ops->get_cr(ctxt, 4) & X86_CR4_OSXSAVE))
4178 return emulate_ud(ctxt);
4179
02d4160f
VK		 4180 eax = reg_read(ctxt, VCPU_REGS_RAX);
4181 edx = reg_read(ctxt, VCPU_REGS_RDX);
4182 ecx = reg_read(ctxt, VCPU_REGS_RCX);
4183
4184 if (ctxt->ops->set_xcr(ctxt, ecx, ((u64)edx << 32) | eax))
4185 return emulate_gp(ctxt, 0);
4186
4187 return X86EMUL_CONTINUE;
4188}
4189
cfec82cb
JR		 4190static bool valid_cr(int nr)
4191{
4192 switch (nr) {
4193 case 0:
4194 case 2 ... 4:
4195 case 8:
4196 return true;
4197 default:
4198 return false;
4199 }
4200}
4201
d0fe7b64 4202static int check_cr_access(struct x86_emulate_ctxt *ctxt)
cfec82cb 4203{
9dac77fa 4204 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 4205 return emulate_ud(ctxt);
4206
4207 return X86EMUL_CONTINUE;
4208}
4209
3b88e41a
JR		 4210static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
4211{
4212 unsigned long dr7;
4213
717746e3 4214 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a 4215
0701ec90 4216 return dr7 & DR7_GD;
3b88e41a
JR		 4217}
4218
4219static int check_dr_read(struct x86_emulate_ctxt *ctxt)
4220{
9dac77fa 4221 int dr = ctxt->modrm_reg;
3b88e41a
JR		 4222 u64 cr4;
4223
4224 if (dr > 7)
4225 return emulate_ud(ctxt);
4226
717746e3 4227 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 4228 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
4229 return emulate_ud(ctxt);
4230
6d2a0526
NA		 4231 if (check_dr7_gd(ctxt)) {
4232 ulong dr6;
4233
4234 ctxt->ops->get_dr(ctxt, 6, &dr6);
1fc5d194 4235 dr6 &= ~DR_TRAP_BITS;
9a3ecd5e 4236 dr6 |= DR6_BD | DR6_ACTIVE_LOW;
6d2a0526 4237 ctxt->ops->set_dr(ctxt, 6, dr6);
3b88e41a 4238 return emulate_db(ctxt);
6d2a0526 4239 }
3b88e41a
JR		 4240
4241 return X86EMUL_CONTINUE;
4242}
4243
4244static int check_dr_write(struct x86_emulate_ctxt *ctxt)
4245{
9dac77fa
AK		 4246 u64 new_val = ctxt->src.val64;
4247 int dr = ctxt->modrm_reg;
3b88e41a
JR		 4248
4249 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
4250 return emulate_gp(ctxt, 0);
4251
4252 return check_dr_read(ctxt);
4253}
4254
01de8b09
JR		 4255static int check_svme(struct x86_emulate_ctxt *ctxt)
4256{
92ceb767 4257 u64 efer = 0;
01de8b09 4258
717746e3 4259 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 4260
4261 if (!(efer & EFER_SVME))
4262 return emulate_ud(ctxt);
4263
4264 return X86EMUL_CONTINUE;
4265}
4266
4267static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
4268{
dd856efa 4269 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
01de8b09
JR		 4270
4271 /* Valid physical address? */
d4224449 4272 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 4273 return emulate_gp(ctxt, 0);
4274
4275 return check_svme(ctxt);
4276}
4277
d7eb8203
JR		 4278static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
4279{
717746e3 4280 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 4281
717746e3 4282 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
e9337c84 4283 return emulate_gp(ctxt, 0);
d7eb8203
JR		 4284
4285 return X86EMUL_CONTINUE;
4286}
4287
8061252e
JR		 4288static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
4289{
717746e3 4290 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
dd856efa 4291 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
8061252e 4292
2d7921c4
AM		 4293 /*
4294 * VMware allows access to these Pseduo-PMCs even when read via RDPMC
4295 * in Ring3 when CR4.PCE=0.
4296 */
4297 if (enable_vmware_backdoor && is_vmware_backdoor_pmc(rcx))
4298 return X86EMUL_CONTINUE;
4299
9ae7f6c9
WL		 4300 /*
4301 * If CR4.PCE is set, the SDM requires CPL=0 or CR0.PE=0. The CR0.PE
4302 * check however is unnecessary because CPL is always 0 outside
4303 * protected mode.
4304 */
717746e3 4305 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
67f4d428 4306 ctxt->ops->check_pmc(ctxt, rcx))
8061252e
JR		 4307 return emulate_gp(ctxt, 0);
4308
4309 return X86EMUL_CONTINUE;
4310}
4311
f6511935
JR		 4312static int check_perm_in(struct x86_emulate_ctxt *ctxt)
4313{
9dac77fa
AK		 4314 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
4315 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 4316 return emulate_gp(ctxt, 0);
4317
4318 return X86EMUL_CONTINUE;
4319}
4320
4321static int check_perm_out(struct x86_emulate_ctxt *ctxt)
4322{
9dac77fa
AK		 4323 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
4324 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 4325 return emulate_gp(ctxt, 0);
4326
4327 return X86EMUL_CONTINUE;
4328}
4329
73fba5f4 4330#define D(_y) { .flags = (_y) }
d40a6898
PB		 4331#define DI(_y, _i) { .flags = (_y)|Intercept, .intercept = x86_intercept_##_i }
4332#define DIP(_y, _i, _p) { .flags = (_y)|Intercept|CheckPerm, \
4333 .intercept = x86_intercept_##_i, .check_perm = (_p) }
0b789eee 4334#define N D(NotImpl)
01de8b09 4335#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 4336#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
4337#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
39f062ff 4338#define ID(_f, _i) { .flags = ((_f) | InstrDual | ModRM), .u.idual = (_i) }
2276b511 4339#define MD(_f, _m) { .flags = ((_f) | ModeDual), .u.mdual = (_m) }
045a282c 4340#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
73fba5f4 4341#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
e28bbd44 4342#define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
c4f035c6 4343#define II(_f, _e, _i) \
d40a6898 4344 { .flags = (_f)|Intercept, .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd 4345#define IIP(_f, _e, _i, _p) \
d40a6898
PB		 4346 { .flags = (_f)|Intercept|CheckPerm, .u.execute = (_e), \
4347 .intercept = x86_intercept_##_i, .check_perm = (_p) }
aa97bb48 4348#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 4349
8d8f4e9f 4350#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 4351#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 4352#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
f7857f35 4353#define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e)
d7841a4b
TY		 4354#define I2bvIP(_f, _e, _i, _p) \
4355 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 4356
fb864fbc
AK		 4357#define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \
4358 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
4359 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 4360
0f54a321
NA		 4361static const struct opcode group7_rm0[] = {
4362 N,
b34a8051 4363 I(SrcNone | Priv | EmulateOnUD, em_hypercall),
0f54a321
NA		 4364 N, N, N, N, N, N,
4365};
4366
fd0a0d82 4367static const struct opcode group7_rm1[] = {
1c2545be
TY		 4368 DI(SrcNone | Priv, monitor),
4369 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 4370 N, N, N, N, N, N,
4371};
4372
02d4160f
VK		 4373static const struct opcode group7_rm2[] = {
4374 N,
4375 II(ImplicitOps | Priv, em_xsetbv, xsetbv),
4376 N, N, N, N, N, N,
4377};
4378
fd0a0d82 4379static const struct opcode group7_rm3[] = {
1c2545be 4380 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
b34a8051 4381 II(SrcNone | Prot | EmulateOnUD, em_hypercall, vmmcall),
1c2545be
TY		 4382 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
4383 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
4384 DIP(SrcNone | Prot | Priv, stgi, check_svme),
4385 DIP(SrcNone | Prot | Priv, clgi, check_svme),
4386 DIP(SrcNone | Prot | Priv, skinit, check_svme),
4387 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 4388};
6230f7fc 4389
fd0a0d82 4390static const struct opcode group7_rm7[] = {
d7eb8203 4391 N,
1c2545be 4392 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 4393 N, N, N, N, N, N,
4394};
d67fc27a 4395
fd0a0d82 4396static const struct opcode group1[] = {
fb864fbc
AK		 4397 F(Lock, em_add),
4398 F(Lock | PageTable, em_or),
4399 F(Lock, em_adc),
4400 F(Lock, em_sbb),
4401 F(Lock | PageTable, em_and),
4402 F(Lock, em_sub),
4403 F(Lock, em_xor),
4404 F(NoWrite, em_cmp),
73fba5f4
AK		 4405};
4406
fd0a0d82 4407static const struct opcode group1A[] = {
0f89b207 4408 I(DstMem | SrcNone | Mov | Stack | IncSP | TwoMemOp, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 4409};
4410
007a3b54
AK		 4411static const struct opcode group2[] = {
4412 F(DstMem | ModRM, em_rol),
4413 F(DstMem | ModRM, em_ror),
4414 F(DstMem | ModRM, em_rcl),
4415 F(DstMem | ModRM, em_rcr),
4416 F(DstMem | ModRM, em_shl),
4417 F(DstMem | ModRM, em_shr),
4418 F(DstMem | ModRM, em_shl),
4419 F(DstMem | ModRM, em_sar),
4420};
4421
fd0a0d82 4422static const struct opcode group3[] = {
fb864fbc
AK		 4423 F(DstMem | SrcImm | NoWrite, em_test),
4424 F(DstMem | SrcImm | NoWrite, em_test),
45a1467d
AK		 4425 F(DstMem | SrcNone | Lock, em_not),
4426 F(DstMem | SrcNone | Lock, em_neg),
b9fa409b
AK		 4427 F(DstXacc | Src2Mem, em_mul_ex),
4428 F(DstXacc | Src2Mem, em_imul_ex),
b8c0b6ae
AK		 4429 F(DstXacc | Src2Mem, em_div_ex),
4430 F(DstXacc | Src2Mem, em_idiv_ex),
73fba5f4
AK		 4431};
4432
fd0a0d82 4433static const struct opcode group4[] = {
95413dc4
AK		 4434 F(ByteOp | DstMem | SrcNone | Lock, em_inc),
4435 F(ByteOp | DstMem | SrcNone | Lock, em_dec),
73fba5f4
AK		 4436 N, N, N, N, N, N,
4437};
4438
fd0a0d82 4439static const struct opcode group5[] = {
95413dc4
AK		 4440 F(DstMem | SrcNone | Lock, em_inc),
4441 F(DstMem | SrcNone | Lock, em_dec),
018d70ff
EH		 4442 I(SrcMem | NearBranch | IsBranch, em_call_near_abs),
4443 I(SrcMemFAddr | ImplicitOps | IsBranch, em_call_far),
4444 I(SrcMem | NearBranch | IsBranch, em_jmp_abs),
4445 I(SrcMemFAddr | ImplicitOps | IsBranch, em_jmp_far),
0f89b207 4446 I(SrcMem | Stack | TwoMemOp, em_push), D(Undefined),
73fba5f4
AK		 4447};
4448
fd0a0d82 4449static const struct opcode group6[] = {
dd307d01
PB		 4450 II(Prot | DstMem, em_sldt, sldt),
4451 II(Prot | DstMem, em_str, str),
a14e579f 4452 II(Prot | Priv | SrcMem16, em_lldt, lldt),
80890006 4453 II(Prot | Priv | SrcMem16, em_ltr, ltr),
dee6bb70
JR		 4454 N, N, N, N,
4455};
4456
fd0a0d82 4457static const struct group_dual group7 = { {
606b1c3e
NA		 4458 II(Mov | DstMem, em_sgdt, sgdt),
4459 II(Mov | DstMem, em_sidt, sidt),
1c2545be
TY		 4460 II(SrcMem | Priv, em_lgdt, lgdt),
4461 II(SrcMem | Priv, em_lidt, lidt),
4462 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
4463 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
4464 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 4465}, {
0f54a321 4466 EXT(0, group7_rm0),
5ef39c71 4467 EXT(0, group7_rm1),
02d4160f
VK		 4468 EXT(0, group7_rm2),
4469 EXT(0, group7_rm3),
1c2545be
TY		 4470 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
4471 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
4472 EXT(0, group7_rm7),
73fba5f4
AK		 4473} };
4474
fd0a0d82 4475static const struct opcode group8[] = {
73fba5f4 4476 N, N, N, N,
11c363ba
AK		 4477 F(DstMem | SrcImmByte | NoWrite, em_bt),
4478 F(DstMem | SrcImmByte | Lock | PageTable, em_bts),
4479 F(DstMem | SrcImmByte | Lock, em_btr),
4480 F(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 4481};
4482
fb6d4d34
PB		 4483/*
4484 * The "memory" destination is actually always a register, since we come
4485 * from the register case of group9.
4486 */
4487static const struct gprefix pfx_0f_c7_7 = {
2183de41 4488 N, N, N, II(DstMem | ModRM | Op3264 | EmulateOnUD, em_rdpid, rdpid),
fb6d4d34
PB		 4489};
4490
4491
fd0a0d82 4492static const struct group_dual group9 = { {
1c2545be 4493 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4 4494}, {
fb6d4d34
PB		 4495 N, N, N, N, N, N, N,
4496 GP(0, &pfx_0f_c7_7),
73fba5f4
AK		 4497} };
4498
fd0a0d82 4499static const struct opcode group11[] = {
1c2545be 4500 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 4501 X7(D(Undefined)),
a4d4a7c1
AK		 4502};
4503
13e457e0 4504static const struct gprefix pfx_0f_ae_7 = {
51b958e5 4505 I(SrcMem | ByteOp, em_clflush), I(SrcMem | ByteOp, em_clflushopt), N, N,
13e457e0
NA		 4506};
4507
4508static const struct group_dual group15 = { {
283c95d0
RK		 4509 I(ModRM | Aligned16, em_fxsave),
4510 I(ModRM | Aligned16, em_fxrstor),
4511 N, N, N, N, N, GP(0, &pfx_0f_ae_7),
13e457e0
NA		 4512}, {
4513 N, N, N, N, N, N, N, N,
4514} };
4515
fd0a0d82 4516static const struct gprefix pfx_0f_6f_0f_7f = {
e5971755 4517 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 4518};
4519
39f062ff
NA		 4520static const struct instr_dual instr_dual_0f_2b = {
4521 I(0, em_mov), N
4522};
4523
d5b77069 4524static const struct gprefix pfx_0f_2b = {
39f062ff 4525 ID(0, &instr_dual_0f_2b), ID(0, &instr_dual_0f_2b), N, N,
3e114eb4
AK		 4526};
4527
29916968
SF		 4528static const struct gprefix pfx_0f_10_0f_11 = {
4529 I(Unaligned, em_mov), I(Unaligned, em_mov), N, N,
4530};
4531
27ce8258 4532static const struct gprefix pfx_0f_28_0f_29 = {
6fec27d8 4533 I(Aligned, em_mov), I(Aligned, em_mov), N, N,
27ce8258
IM		 4534};
4535
0a37027e
AW		 4536static const struct gprefix pfx_0f_e7 = {
4537 N, I(Sse, em_mov), N, N,
4538};
4539
045a282c 4540static const struct escape escape_d9 = { {
16bebefe 4541 N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstcw),
045a282c
GN		 4542}, {
4543 /* 0xC0 - 0xC7 */
4544 N, N, N, N, N, N, N, N,
4545 /* 0xC8 - 0xCF */
4546 N, N, N, N, N, N, N, N,
4547 /* 0xD0 - 0xC7 */
4548 N, N, N, N, N, N, N, N,
4549 /* 0xD8 - 0xDF */
4550 N, N, N, N, N, N, N, N,
4551 /* 0xE0 - 0xE7 */
4552 N, N, N, N, N, N, N, N,
4553 /* 0xE8 - 0xEF */
4554 N, N, N, N, N, N, N, N,
4555 /* 0xF0 - 0xF7 */
4556 N, N, N, N, N, N, N, N,
4557 /* 0xF8 - 0xFF */
4558 N, N, N, N, N, N, N, N,
4559} };
4560
4561static const struct escape escape_db = { {
4562 N, N, N, N, N, N, N, N,
4563}, {
4564 /* 0xC0 - 0xC7 */
4565 N, N, N, N, N, N, N, N,
4566 /* 0xC8 - 0xCF */
4567 N, N, N, N, N, N, N, N,
4568 /* 0xD0 - 0xC7 */
4569 N, N, N, N, N, N, N, N,
4570 /* 0xD8 - 0xDF */
4571 N, N, N, N, N, N, N, N,
4572 /* 0xE0 - 0xE7 */
4573 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
4574 /* 0xE8 - 0xEF */
4575 N, N, N, N, N, N, N, N,
4576 /* 0xF0 - 0xF7 */
4577 N, N, N, N, N, N, N, N,
4578 /* 0xF8 - 0xFF */
4579 N, N, N, N, N, N, N, N,
4580} };
4581
4582static const struct escape escape_dd = { {
16bebefe 4583 N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstsw),
045a282c
GN		 4584}, {
4585 /* 0xC0 - 0xC7 */
4586 N, N, N, N, N, N, N, N,
4587 /* 0xC8 - 0xCF */
4588 N, N, N, N, N, N, N, N,
4589 /* 0xD0 - 0xC7 */
4590 N, N, N, N, N, N, N, N,
4591 /* 0xD8 - 0xDF */
4592 N, N, N, N, N, N, N, N,
4593 /* 0xE0 - 0xE7 */
4594 N, N, N, N, N, N, N, N,
4595 /* 0xE8 - 0xEF */
4596 N, N, N, N, N, N, N, N,
4597 /* 0xF0 - 0xF7 */
4598 N, N, N, N, N, N, N, N,
4599 /* 0xF8 - 0xFF */
4600 N, N, N, N, N, N, N, N,
4601} };
4602
39f062ff
NA		 4603static const struct instr_dual instr_dual_0f_c3 = {
4604 I(DstMem | SrcReg | ModRM | No16 | Mov, em_mov), N
4605};
4606
2276b511
NA		 4607static const struct mode_dual mode_dual_63 = {
4608 N, I(DstReg | SrcMem32 | ModRM | Mov, em_movsxd)
4609};
4610
4ac5b423
ML		 4611static const struct instr_dual instr_dual_8d = {
4612 D(DstReg | SrcMem | ModRM | NoAccess), N
4613};
4614
fd0a0d82 4615static const struct opcode opcode_table[256] = {
73fba5f4 4616 /* 0x00 - 0x07 */
fb864fbc 4617 F6ALU(Lock, em_add),
1cd196ea
AK		 4618 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
4619 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 4620 /* 0x08 - 0x0F */
fb864fbc 4621 F6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 4622 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
4623 N,
73fba5f4 4624 /* 0x10 - 0x17 */
fb864fbc 4625 F6ALU(Lock, em_adc),
1cd196ea
AK		 4626 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
4627 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 4628 /* 0x18 - 0x1F */
fb864fbc 4629 F6ALU(Lock, em_sbb),
1cd196ea
AK		 4630 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
4631 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 4632 /* 0x20 - 0x27 */
fb864fbc 4633 F6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 4634 /* 0x28 - 0x2F */
fb864fbc 4635 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 4636 /* 0x30 - 0x37 */
fb864fbc 4637 F6ALU(Lock, em_xor), N, N,
73fba5f4 4638 /* 0x38 - 0x3F */
fb864fbc 4639 F6ALU(NoWrite, em_cmp), N, N,
73fba5f4 4640 /* 0x40 - 0x4F */
95413dc4 4641 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
73fba5f4 4642 /* 0x50 - 0x57 */
63540382 4643 X8(I(SrcReg | Stack, em_push)),
73fba5f4 4644 /* 0x58 - 0x5F */
c54fe504 4645 X8(I(DstReg | Stack, em_pop)),
73fba5f4 4646 /* 0x60 - 0x67 */
b96a7fad
TY		 4647 I(ImplicitOps | Stack | No64, em_pusha),
4648 I(ImplicitOps | Stack | No64, em_popa),
2276b511 4649 N, MD(ModRM, &mode_dual_63),
73fba5f4
AK		 4650 N, N, N, N,
4651 /* 0x68 - 0x6F */
d46164db
AK		 4652 I(SrcImm | Mov | Stack, em_push),
4653 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 4654 I(SrcImmByte | Mov | Stack, em_push),
4655 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
b3356bf0 4656 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
2b5e97e1 4657 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4 4658 /* 0x70 - 0x7F */
018d70ff 4659 X16(D(SrcImmByte | NearBranch | IsBranch)),
73fba5f4 4660 /* 0x80 - 0x87 */
1c2545be
TY		 4661 G(ByteOp | DstMem | SrcImm, group1),
4662 G(DstMem | SrcImm, group1),
4663 G(ByteOp | DstMem | SrcImm | No64, group1),
4664 G(DstMem | SrcImmByte, group1),
fb864fbc 4665 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
d5ae7ce8 4666 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 4667 /* 0x88 - 0x8F */
d5ae7ce8 4668 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 4669 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 4670 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
4ac5b423 4671 ID(0, &instr_dual_8d),
1bd5f469
TY		 4672 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
4673 G(0, group1A),
73fba5f4 4674 /* 0x90 - 0x97 */
bf608f88 4675 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 4676 /* 0x98 - 0x9F */
61429142 4677 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
018d70ff 4678 I(SrcImmFAddr | No64 | IsBranch, em_call_far), N,
62aaa2f0 4679 II(ImplicitOps | Stack, em_pushf, pushf),
98f73630
PB		 4680 II(ImplicitOps | Stack, em_popf, popf),
4681 I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf),
73fba5f4 4682 /* 0xA0 - 0xA7 */
b9eac5f4 4683 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 4684 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
0f89b207
TL		 4685 I2bv(SrcSI | DstDI | Mov | String | TwoMemOp, em_mov),
4686 F2bv(SrcSI | DstDI | String | NoWrite | TwoMemOp, em_cmp_r),
73fba5f4 4687 /* 0xA8 - 0xAF */
fb864fbc 4688 F2bv(DstAcc | SrcImm | NoWrite, em_test),
b9eac5f4
AK		 4689 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
4690 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
5aca3722 4691 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp_r),
73fba5f4 4692 /* 0xB0 - 0xB7 */
b9eac5f4 4693 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 4694 /* 0xB8 - 0xBF */
5e2c6883 4695 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
73fba5f4 4696 /* 0xC0 - 0xC7 */
007a3b54 4697 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
018d70ff
EH		 4698 I(ImplicitOps | NearBranch | SrcImmU16 | IsBranch, em_ret_near_imm),
4699 I(ImplicitOps | NearBranch | IsBranch, em_ret),
d4b4325f
AK		 4700 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
4701 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 4702 G(ByteOp, group11), G(0, group11),
73fba5f4 4703 /* 0xC8 - 0xCF */
018d70ff
EH		 4704 I(Stack | SrcImmU16 | Src2ImmByte | IsBranch, em_enter),
4705 I(Stack | IsBranch, em_leave),
4706 I(ImplicitOps | SrcImmU16 | IsBranch, em_ret_far_imm),
4707 I(ImplicitOps | IsBranch, em_ret_far),
4708 D(ImplicitOps | IsBranch), DI(SrcImmByte | IsBranch, intn),
4709 D(ImplicitOps | No64 | IsBranch),
4710 II(ImplicitOps | IsBranch, em_iret, iret),
73fba5f4 4711 /* 0xD0 - 0xD7 */
007a3b54
AK		 4712 G(Src2One | ByteOp, group2), G(Src2One, group2),
4713 G(Src2CL | ByteOp, group2), G(Src2CL, group2),
a035d5c6 4714 I(DstAcc | SrcImmUByte | No64, em_aam),
326f578f
PB		 4715 I(DstAcc | SrcImmUByte | No64, em_aad),
4716 F(DstAcc | ByteOp | No64, em_salc),
7fa57952 4717 I(DstAcc | SrcXLat | ByteOp, em_mov),
73fba5f4 4718 /* 0xD8 - 0xDF */
045a282c 4719 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
73fba5f4 4720 /* 0xE0 - 0xE7 */
018d70ff
EH		 4721 X3(I(SrcImmByte | NearBranch | IsBranch, em_loop)),
4722 I(SrcImmByte | NearBranch | IsBranch, em_jcxz),
d7841a4b
TY		 4723 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
4724 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 4725 /* 0xE8 - 0xEF */
018d70ff
EH		 4726 I(SrcImm | NearBranch | IsBranch, em_call),
4727 D(SrcImm | ImplicitOps | NearBranch | IsBranch),
4728 I(SrcImmFAddr | No64 | IsBranch, em_jmp_far),
4729 D(SrcImmByte | ImplicitOps | NearBranch | IsBranch),
d7841a4b
TY		 4730 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
4731 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 4732 /* 0xF0 - 0xF7 */
bf608f88 4733 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 4734 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
4735 G(ByteOp, group3), G(0, group3),
73fba5f4 4736 /* 0xF8 - 0xFF */
f411e6cd
TY		 4737 D(ImplicitOps), D(ImplicitOps),
4738 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 4739 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
4740};
4741
fd0a0d82 4742static const struct opcode twobyte_table[256] = {
73fba5f4 4743 /* 0x00 - 0x0F */
dee6bb70 4744 G(0, group6), GD(0, &group7), N, N,
018d70ff 4745 N, I(ImplicitOps | EmulateOnUD | IsBranch, em_syscall),
db5b0762 4746 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 4747 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
3f6f1480 4748 N, D(ImplicitOps | ModRM | SrcMem | NoAccess), N, N,
73fba5f4 4749 /* 0x10 - 0x1F */
29916968
SF		 4750 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_10_0f_11),
4751 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_10_0f_11),
4752 N, N, N, N, N, N,
34d2618d
PB		 4753 D(ImplicitOps | ModRM | SrcMem | NoAccess), /* 4 * prefetch + 4 * reserved NOP */
4754 D(ImplicitOps | ModRM | SrcMem | NoAccess), N, N,
4755 D(ImplicitOps | ModRM | SrcMem | NoAccess), /* 8 * reserved NOP */
4756 D(ImplicitOps | ModRM | SrcMem | NoAccess), /* 8 * reserved NOP */
4757 D(ImplicitOps | ModRM | SrcMem | NoAccess), /* 8 * reserved NOP */
4758 D(ImplicitOps | ModRM | SrcMem | NoAccess), /* NOP + 7 * reserved NOP */
73fba5f4 4759 /* 0x20 - 0x2F */
d0fe7b64 4760 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_access),
9b88ae99
NA		 4761 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read),
4762 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write,
d0fe7b64 4763 check_cr_access),
9b88ae99
NA		 4764 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write,
4765 check_dr_write),
73fba5f4 4766 N, N, N, N,
27ce8258
IM		 4767 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29),
4768 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29),
d5b77069 4769 N, GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_2b),
3e114eb4 4770 N, N, N, N,
73fba5f4 4771 /* 0x30 - 0x3F */
e1e210b0 4772 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 4773 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 4774 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 4775 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
018d70ff
EH		 4776 I(ImplicitOps | EmulateOnUD | IsBranch, em_sysenter),
4777 I(ImplicitOps | Priv | EmulateOnUD | IsBranch, em_sysexit),
d867162c 4778 N, N,
73fba5f4
AK		 4779 N, N, N, N, N, N, N, N,
4780 /* 0x40 - 0x4F */
140bad89 4781 X16(D(DstReg | SrcMem | ModRM)),
73fba5f4
AK		 4782 /* 0x50 - 0x5F */
4783 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4784 /* 0x60 - 0x6F */
aa97bb48
AK		 4785 N, N, N, N,
4786 N, N, N, N,
4787 N, N, N, N,
4788 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 4789 /* 0x70 - 0x7F */
aa97bb48
AK		 4790 N, N, N, N,
4791 N, N, N, N,
4792 N, N, N, N,
4793 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 4794 /* 0x80 - 0x8F */
018d70ff 4795 X16(D(SrcImm | NearBranch | IsBranch)),
73fba5f4 4796 /* 0x90 - 0x9F */
ee45b58e 4797 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 4798 /* 0xA0 - 0xA7 */
1cd196ea 4799 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
11c363ba
AK		 4800 II(ImplicitOps, em_cpuid, cpuid),
4801 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
0bdea068
AK		 4802 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
4803 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
73fba5f4 4804 /* 0xA8 - 0xAF */
1cd196ea 4805 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
89651a3d 4806 II(EmulateOnUD | ImplicitOps, em_rsm, rsm),
11c363ba 4807 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
0bdea068
AK		 4808 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
4809 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
13e457e0 4810 GD(0, &group15), F(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 4811 /* 0xB0 - 0xB7 */
2fcf5c8a 4812 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable | SrcWrite, em_cmpxchg),
d4b4325f 4813 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
11c363ba 4814 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 4815 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
4816 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 4817 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 4818 /* 0xB8 - 0xBF */
4819 N, N,
ce7faab2 4820 G(BitOp, group8),
11c363ba 4821 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
900efe20
NA		 4822 I(DstReg | SrcMem | ModRM, em_bsf_c),
4823 I(DstReg | SrcMem | ModRM, em_bsr_c),
2adb5ad9 4824 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
9299836e 4825 /* 0xC0 - 0xC7 */
e47a5f5f 4826 F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd),
39f062ff 4827 N, ID(0, &instr_dual_0f_c3),
73fba5f4 4828 N, N, N, GD(0, &group9),
9299836e
AK		 4829 /* 0xC8 - 0xCF */
4830 X8(I(DstReg, em_bswap)),
73fba5f4
AK		 4831 /* 0xD0 - 0xDF */
4832 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4833 /* 0xE0 - 0xEF */
0a37027e
AW		 4834 N, N, N, N, N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_e7),
4835 N, N, N, N, N, N, N, N,
73fba5f4
AK		 4836 /* 0xF0 - 0xFF */
4837 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
4838};
4839
39f062ff
NA		 4840static const struct instr_dual instr_dual_0f_38_f0 = {
4841 I(DstReg | SrcMem | Mov, em_movbe), N
4842};
4843
4844static const struct instr_dual instr_dual_0f_38_f1 = {
4845 I(DstMem | SrcReg | Mov, em_movbe), N
4846};
4847
0bc5eedb 4848static const struct gprefix three_byte_0f_38_f0 = {
39f062ff 4849 ID(0, &instr_dual_0f_38_f0), N, N, N
0bc5eedb
BP		 4850};
4851
4852static const struct gprefix three_byte_0f_38_f1 = {
39f062ff 4853 ID(0, &instr_dual_0f_38_f1), N, N, N
0bc5eedb
BP		 4854};
4855
4856/*
4857 * Insns below are selected by the prefix which indexed by the third opcode
4858 * byte.
4859 */
4860static const struct opcode opcode_map_0f_38[256] = {
4861 /* 0x00 - 0x7f */
4862 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
84cffe49
BP		 4863 /* 0x80 - 0xef */
4864 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
4865 /* 0xf0 - 0xf1 */
53bb4f78
NA		 4866 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f0),
4867 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f1),
84cffe49
BP		 4868 /* 0xf2 - 0xff */
4869 N, N, X4(N), X8(N)
0bc5eedb
BP		 4870};
4871
73fba5f4
AK		 4872#undef D
4873#undef N
4874#undef G
4875#undef GD
4876#undef I
aa97bb48 4877#undef GP
01de8b09 4878#undef EXT
2276b511 4879#undef MD
2b42fce6 4880#undef ID
73fba5f4 4881
8d8f4e9f 4882#undef D2bv
f6511935 4883#undef D2bvIP
8d8f4e9f 4884#undef I2bv
d7841a4b 4885#undef I2bvIP
d67fc27a 4886#undef I6ALU
8d8f4e9f 4887
9dac77fa 4888static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 4889{
4890 unsigned size;
4891
9dac77fa 4892 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 4893 if (size == 8)
4894 size = 4;
4895 return size;
4896}
4897
4898static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
4899 unsigned size, bool sign_extension)
4900{
39f21ee5
AK		 4901 int rc = X86EMUL_CONTINUE;
4902
4903 op->type = OP_IMM;
4904 op->bytes = size;
9dac77fa 4905 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 4906 /* NB. Immediates are sign-extended as necessary. */
4907 switch (op->bytes) {
4908 case 1:
e85a1085 4909 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 4910 break;
4911 case 2:
e85a1085 4912 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 4913 break;
4914 case 4:
e85a1085 4915 op->val = insn_fetch(s32, ctxt);
39f21ee5 4916 break;
5e2c6883
NA		 4917 case 8:
4918 op->val = insn_fetch(s64, ctxt);
4919 break;
39f21ee5
AK		 4920 }
4921 if (!sign_extension) {
4922 switch (op->bytes) {
4923 case 1:
4924 op->val &= 0xff;
4925 break;
4926 case 2:
4927 op->val &= 0xffff;
4928 break;
4929 case 4:
4930 op->val &= 0xffffffff;
4931 break;
4932 }
4933 }
4934done:
4935 return rc;
4936}
4937
a9945549
AK		 4938static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
4939 unsigned d)
4940{
4941 int rc = X86EMUL_CONTINUE;
4942
4943 switch (d) {
4944 case OpReg:
2adb5ad9 4945 decode_register_operand(ctxt, op);
a9945549
AK		 4946 break;
4947 case OpImmUByte:
608aabe3 4948 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 4949 break;
4950 case OpMem:
41ddf978 4951 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 4952 mem_common:
4953 *op = ctxt->memop;
4954 ctxt->memopp = op;
96888977 4955 if (ctxt->d & BitOp)
a9945549
AK		 4956 fetch_bit_operand(ctxt);
4957 op->orig_val = op->val;
4958 break;
41ddf978 4959 case OpMem64:
aaa05f24 4960 ctxt->memop.bytes = (ctxt->op_bytes == 8) ? 16 : 8;
41ddf978 4961 goto mem_common;
a9945549
AK		 4962 case OpAcc:
4963 op->type = OP_REG;
4964 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 4965 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
a9945549
AK		 4966 fetch_register_operand(op);
4967 op->orig_val = op->val;
4968 break;
820207c8
AK		 4969 case OpAccLo:
4970 op->type = OP_REG;
4971 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes;
4972 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4973 fetch_register_operand(op);
4974 op->orig_val = op->val;
4975 break;
4976 case OpAccHi:
4977 if (ctxt->d & ByteOp) {
4978 op->type = OP_NONE;
4979 break;
4980 }
4981 op->type = OP_REG;
4982 op->bytes = ctxt->op_bytes;
4983 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4984 fetch_register_operand(op);
4985 op->orig_val = op->val;
4986 break;
a9945549
AK		 4987 case OpDI:
4988 op->type = OP_MEM;
4989 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4990 op->addr.mem.ea =
01485a22 4991 register_address(ctxt, VCPU_REGS_RDI);
a9945549
AK		 4992 op->addr.mem.seg = VCPU_SREG_ES;
4993 op->val = 0;
b3356bf0 4994 op->count = 1;
a9945549
AK		 4995 break;
4996 case OpDX:
4997 op->type = OP_REG;
4998 op->bytes = 2;
dd856efa 4999 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
a9945549
AK		 5000 fetch_register_operand(op);
5001 break;
4dd6a57d 5002 case OpCL:
d29b9d7e 5003 op->type = OP_IMM;
4dd6a57d 5004 op->bytes = 1;
dd856efa 5005 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4dd6a57d
AK		 5006 break;
5007 case OpImmByte:
5008 rc = decode_imm(ctxt, op, 1, true);
5009 break;
5010 case OpOne:
d29b9d7e 5011 op->type = OP_IMM;
4dd6a57d
AK		 5012 op->bytes = 1;
5013 op->val = 1;
5014 break;
5015 case OpImm:
5016 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
5017 break;
5e2c6883
NA		 5018 case OpImm64:
5019 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
5020 break;
28867cee
AK		 5021 case OpMem8:
5022 ctxt->memop.bytes = 1;
660696d1 5023 if (ctxt->memop.type == OP_REG) {
aa9ac1a6
GN		 5024 ctxt->memop.addr.reg = decode_register(ctxt,
5025 ctxt->modrm_rm, true);
660696d1
GN		 5026 fetch_register_operand(&ctxt->memop);
5027 }
28867cee 5028 goto mem_common;
0fe59128
AK		 5029 case OpMem16:
5030 ctxt->memop.bytes = 2;
5031 goto mem_common;
5032 case OpMem32:
5033 ctxt->memop.bytes = 4;
5034 goto mem_common;
5035 case OpImmU16:
5036 rc = decode_imm(ctxt, op, 2, false);
5037 break;
5038 case OpImmU:
5039 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
5040 break;
5041 case OpSI:
5042 op->type = OP_MEM;
5043 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
5044 op->addr.mem.ea =
01485a22 5045 register_address(ctxt, VCPU_REGS_RSI);
573e80fe 5046 op->addr.mem.seg = ctxt->seg_override;
0fe59128 5047 op->val = 0;
b3356bf0 5048 op->count = 1;
0fe59128 5049 break;
7fa57952
PB		 5050 case OpXLat:
5051 op->type = OP_MEM;
5052 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
5053 op->addr.mem.ea =
01485a22 5054 address_mask(ctxt,
7fa57952
PB		 5055 reg_read(ctxt, VCPU_REGS_RBX) +
5056 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
573e80fe 5057 op->addr.mem.seg = ctxt->seg_override;
7fa57952
PB		 5058 op->val = 0;
5059 break;
0fe59128
AK		 5060 case OpImmFAddr:
5061 op->type = OP_IMM;
5062 op->addr.mem.ea = ctxt->_eip;
5063 op->bytes = ctxt->op_bytes + 2;
5064 insn_fetch_arr(op->valptr, op->bytes, ctxt);
5065 break;
5066 case OpMemFAddr:
5067 ctxt->memop.bytes = ctxt->op_bytes + 2;
5068 goto mem_common;
c191a7a0 5069 case OpES:
d29b9d7e 5070 op->type = OP_IMM;
c191a7a0
AK		 5071 op->val = VCPU_SREG_ES;
5072 break;
5073 case OpCS:
d29b9d7e 5074 op->type = OP_IMM;
c191a7a0
AK		 5075 op->val = VCPU_SREG_CS;
5076 break;
5077 case OpSS:
d29b9d7e 5078 op->type = OP_IMM;
c191a7a0
AK		 5079 op->val = VCPU_SREG_SS;
5080 break;
5081 case OpDS:
d29b9d7e 5082 op->type = OP_IMM;
c191a7a0
AK		 5083 op->val = VCPU_SREG_DS;
5084 break;
5085 case OpFS:
d29b9d7e 5086 op->type = OP_IMM;
c191a7a0
AK		 5087 op->val = VCPU_SREG_FS;
5088 break;
5089 case OpGS:
d29b9d7e 5090 op->type = OP_IMM;
c191a7a0
AK		 5091 op->val = VCPU_SREG_GS;
5092 break;
a9945549
AK		 5093 case OpImplicit:
5094 /* Special instructions do their own operand decoding. */
5095 default:
5096 op->type = OP_NONE; /* Disable writeback. */
5097 break;
5098 }
5099
5100done:
5101 return rc;
5102}
5103
b35491e6 5104int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len, int emulation_type)
dde7e6d1 5105{
dde7e6d1
AK		 5106 int rc = X86EMUL_CONTINUE;
5107 int mode = ctxt->mode;
46561646 5108 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 5109 bool op_prefix = false;
573e80fe 5110 bool has_seg_override = false;
46561646 5111 struct opcode opcode;
3853be26
WL		 5112 u16 dummy;
5113 struct desc_struct desc;
dde7e6d1 5114
f09ed83e
AK		 5115 ctxt->memop.type = OP_NONE;
5116 ctxt->memopp = NULL;
9dac77fa 5117 ctxt->_eip = ctxt->eip;
17052f16
PB		 5118 ctxt->fetch.ptr = ctxt->fetch.data;
5119 ctxt->fetch.end = ctxt->fetch.data + insn_len;
1ce19dc1 5120 ctxt->opcode_len = 1;
342993f9 5121 ctxt->intercept = x86_intercept_none;
dc25e89e 5122 if (insn_len > 0)
9dac77fa 5123 memcpy(ctxt->fetch.data, insn, insn_len);
285ca9e9 5124 else {
9506d57d 5125 rc = __do_insn_fetch_bytes(ctxt, 1);
285ca9e9 5126 if (rc != X86EMUL_CONTINUE)
016cd759 5127 goto done;
285ca9e9 5128 }
dde7e6d1
AK		 5129
5130 switch (mode) {
5131 case X86EMUL_MODE_REAL:
5132 case X86EMUL_MODE_VM86:
3853be26
WL		 5133 def_op_bytes = def_ad_bytes = 2;
5134 ctxt->ops->get_segment(ctxt, &dummy, &desc, NULL, VCPU_SREG_CS);
5135 if (desc.d)
5136 def_op_bytes = def_ad_bytes = 4;
5137 break;
dde7e6d1
AK		 5138 case X86EMUL_MODE_PROT16:
5139 def_op_bytes = def_ad_bytes = 2;
5140 break;
5141 case X86EMUL_MODE_PROT32:
5142 def_op_bytes = def_ad_bytes = 4;
5143 break;
5144#ifdef CONFIG_X86_64
5145 case X86EMUL_MODE_PROT64:
5146 def_op_bytes = 4;
5147 def_ad_bytes = 8;
5148 break;
5149#endif
5150 default:
1d2887e2 5151 return EMULATION_FAILED;
dde7e6d1
AK		 5152 }
5153
9dac77fa
AK		 5154 ctxt->op_bytes = def_op_bytes;
5155 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 5156
5157 /* Legacy prefixes. */
5158 for (;;) {
e85a1085 5159 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 5160 case 0x66: /* operand-size override */
0d7cdee8 5161 op_prefix = true;
dde7e6d1 5162 /* switch between 2/4 bytes */
9dac77fa 5163 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 5164 break;
5165 case 0x67: /* address-size override */
5166 if (mode == X86EMUL_MODE_PROT64)
5167 /* switch between 4/8 bytes */
9dac77fa 5168 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 5169 else
5170 /* switch between 2/4 bytes */
9dac77fa 5171 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 5172 break;
5173 case 0x26: /* ES override */
125ffc5e
MP		 5174 has_seg_override = true;
5175 ctxt->seg_override = VCPU_SREG_ES;
5176 break;
dde7e6d1 5177 case 0x2e: /* CS override */
125ffc5e
MP		 5178 has_seg_override = true;
5179 ctxt->seg_override = VCPU_SREG_CS;
5180 break;
dde7e6d1 5181 case 0x36: /* SS override */
125ffc5e
MP		 5182 has_seg_override = true;
5183 ctxt->seg_override = VCPU_SREG_SS;
5184 break;
dde7e6d1 5185 case 0x3e: /* DS override */
573e80fe 5186 has_seg_override = true;
125ffc5e 5187 ctxt->seg_override = VCPU_SREG_DS;
dde7e6d1
AK		 5188 break;
5189 case 0x64: /* FS override */
125ffc5e
MP		 5190 has_seg_override = true;
5191 ctxt->seg_override = VCPU_SREG_FS;
5192 break;
dde7e6d1 5193 case 0x65: /* GS override */
573e80fe 5194 has_seg_override = true;
125ffc5e 5195 ctxt->seg_override = VCPU_SREG_GS;
dde7e6d1
AK		 5196 break;
5197 case 0x40 ... 0x4f: /* REX */
5198 if (mode != X86EMUL_MODE_PROT64)
5199 goto done_prefixes;
9dac77fa 5200 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 5201 continue;
5202 case 0xf0: /* LOCK */
9dac77fa 5203 ctxt->lock_prefix = 1;
dde7e6d1
AK		 5204 break;
5205 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 5206 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 5207 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 5208 break;
5209 default:
5210 goto done_prefixes;
5211 }
5212
5213 /* Any legacy prefix after a REX prefix nullifies its effect. */
5214
9dac77fa 5215 ctxt->rex_prefix = 0;
dde7e6d1
AK		 5216 }
5217
5218done_prefixes:
5219
5220 /* REX prefix. */
9dac77fa
AK		 5221 if (ctxt->rex_prefix & 8)
5222 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 5223
5224 /* Opcode byte(s). */
9dac77fa 5225 opcode = opcode_table[ctxt->b];
d3ad6243 5226 /* Two-byte opcode? */
9dac77fa 5227 if (ctxt->b == 0x0f) {
1ce19dc1 5228 ctxt->opcode_len = 2;
e85a1085 5229 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 5230 opcode = twobyte_table[ctxt->b];
0bc5eedb
BP		 5231
5232 /* 0F_38 opcode map */
5233 if (ctxt->b == 0x38) {
5234 ctxt->opcode_len = 3;
5235 ctxt->b = insn_fetch(u8, ctxt);
5236 opcode = opcode_map_0f_38[ctxt->b];
5237 }
dde7e6d1 5238 }
9dac77fa 5239 ctxt->d = opcode.flags;
dde7e6d1 5240
9f4260e7
TY		 5241 if (ctxt->d & ModRM)
5242 ctxt->modrm = insn_fetch(u8, ctxt);
5243
7fe864dc
NA		 5244 /* vex-prefix instructions are not implemented */
5245 if (ctxt->opcode_len == 1 && (ctxt->b == 0xc5 || ctxt->b == 0xc4) &&
d14cb5df 5246 (mode == X86EMUL_MODE_PROT64 || (ctxt->modrm & 0xc0) == 0xc0)) {
7fe864dc
NA		 5247 ctxt->d = NotImpl;
5248 }
5249
9dac77fa
AK		 5250 while (ctxt->d & GroupMask) {
5251 switch (ctxt->d & GroupMask) {
46561646 5252 case Group:
9dac77fa 5253 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 5254 opcode = opcode.u.group[goffset];
5255 break;
5256 case GroupDual:
9dac77fa
AK		 5257 goffset = (ctxt->modrm >> 3) & 7;
5258 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 5259 opcode = opcode.u.gdual->mod3[goffset];
5260 else
5261 opcode = opcode.u.gdual->mod012[goffset];
5262 break;
5263 case RMExt:
9dac77fa 5264 goffset = ctxt->modrm & 7;
01de8b09 5265 opcode = opcode.u.group[goffset];
46561646
AK		 5266 break;
5267 case Prefix:
9dac77fa 5268 if (ctxt->rep_prefix && op_prefix)
1d2887e2 5269 return EMULATION_FAILED;
9dac77fa 5270 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 5271 switch (simd_prefix) {
5272 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
5273 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
5274 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
5275 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
5276 }
5277 break;
045a282c 5278 case Escape:
3c9053a2
MP		 5279 if (ctxt->modrm > 0xbf) {
5280 size_t size = ARRAY_SIZE(opcode.u.esc->high);
5281 u32 index = array_index_nospec(
5282 ctxt->modrm - 0xc0, size);
5283
5284 opcode = opcode.u.esc->high[index];
5285 } else {
045a282c 5286 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
3c9053a2 5287 }
045a282c 5288 break;
39f062ff
NA		 5289 case InstrDual:
5290 if ((ctxt->modrm >> 6) == 3)
5291 opcode = opcode.u.idual->mod3;
5292 else
5293 opcode = opcode.u.idual->mod012;
5294 break;
2276b511
NA		 5295 case ModeDual:
5296 if (ctxt->mode == X86EMUL_MODE_PROT64)
5297 opcode = opcode.u.mdual->mode64;
5298 else
5299 opcode = opcode.u.mdual->mode32;
5300 break;
46561646 5301 default:
1d2887e2 5302 return EMULATION_FAILED;
0d7cdee8 5303 }
46561646 5304
b1ea50b2 5305 ctxt->d &= ~(u64)GroupMask;
9dac77fa 5306 ctxt->d |= opcode.flags;
0d7cdee8
AK		 5307 }
5308
018d70ff
EH		 5309 ctxt->is_branch = opcode.flags & IsBranch;
5310
e24186e0
PB		 5311 /* Unrecognised? */
5312 if (ctxt->d == 0)
5313 return EMULATION_FAILED;
5314
9dac77fa 5315 ctxt->execute = opcode.u.execute;
dde7e6d1 5316
b35491e6
WL		 5317 if (unlikely(emulation_type & EMULTYPE_TRAP_UD) &&
5318 likely(!(ctxt->d & EmulateOnUD)))
3a6095a0
NA		 5319 return EMULATION_FAILED;
5320
d40a6898 5321 if (unlikely(ctxt->d &
ed9aad21
NA		 5322 (NotImpl|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm|NearBranch|
5323 No16))) {
d40a6898
PB		 5324 /*
5325 * These are copied unconditionally here, and checked unconditionally
5326 * in x86_emulate_insn.
5327 */
5328 ctxt->check_perm = opcode.check_perm;
5329 ctxt->intercept = opcode.intercept;
dde7e6d1 5330
d40a6898
PB		 5331 if (ctxt->d & NotImpl)
5332 return EMULATION_FAILED;
d867162c 5333
58b7075d
NA		 5334 if (mode == X86EMUL_MODE_PROT64) {
5335 if (ctxt->op_bytes == 4 && (ctxt->d & Stack))
5336 ctxt->op_bytes = 8;
5337 else if (ctxt->d & NearBranch)
5338 ctxt->op_bytes = 8;
5339 }
7f9b4b75 5340
d40a6898
PB		 5341 if (ctxt->d & Op3264) {
5342 if (mode == X86EMUL_MODE_PROT64)
5343 ctxt->op_bytes = 8;
5344 else
5345 ctxt->op_bytes = 4;
5346 }
5347
ed9aad21
NA		 5348 if ((ctxt->d & No16) && ctxt->op_bytes == 2)
5349 ctxt->op_bytes = 4;
5350
d40a6898
PB		 5351 if (ctxt->d & Sse)
5352 ctxt->op_bytes = 16;
5353 else if (ctxt->d & Mmx)
5354 ctxt->op_bytes = 8;
5355 }
1253791d 5356
dde7e6d1 5357 /* ModRM and SIB bytes. */
9dac77fa 5358 if (ctxt->d & ModRM) {
f09ed83e 5359 rc = decode_modrm(ctxt, &ctxt->memop);
573e80fe
BD		 5360 if (!has_seg_override) {
5361 has_seg_override = true;
5362 ctxt->seg_override = ctxt->modrm_seg;
5363 }
9dac77fa 5364 } else if (ctxt->d & MemAbs)
f09ed83e 5365 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 5366 if (rc != X86EMUL_CONTINUE)
5367 goto done;
5368
573e80fe
BD		 5369 if (!has_seg_override)
5370 ctxt->seg_override = VCPU_SREG_DS;
dde7e6d1 5371
573e80fe 5372 ctxt->memop.addr.mem.seg = ctxt->seg_override;
dde7e6d1 5373
dde7e6d1
AK		 5374 /*
5375 * Decode and fetch the source operand: register, memory
5376 * or immediate.
5377 */
0fe59128 5378 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 5379 if (rc != X86EMUL_CONTINUE)
5380 goto done;
5381
dde7e6d1
AK		 5382 /*
5383 * Decode and fetch the second source operand: register, memory
5384 * or immediate.
5385 */
4dd6a57d 5386 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 5387 if (rc != X86EMUL_CONTINUE)
5388 goto done;
5389
dde7e6d1 5390 /* Decode and fetch the destination operand: register or memory. */
a9945549 5391 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1 5392
d9092f52 5393 if (ctxt->rip_relative && likely(ctxt->memopp))
1c1c35ae
NA		 5394 ctxt->memopp->addr.mem.ea = address_mask(ctxt,
5395 ctxt->memopp->addr.mem.ea + ctxt->_eip);
cb16c348 5396
a430c916 5397done:
c8848cee
JD		 5398 if (rc == X86EMUL_PROPAGATE_FAULT)
5399 ctxt->have_exception = true;
1d2887e2 5400 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 5401}
5402
1cb3f3ae
XG		 5403bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
5404{
5405 return ctxt->d & PageTable;
5406}
5407
3e2f65d5
GN		 5408static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
5409{
3e2f65d5
GN		 5410 /* The second termination condition only applies for REPE
5411 * and REPNE. Test if the repeat string operation prefix is
5412 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
5413 * corresponding termination condition according to:
5414 * - if REPE/REPZ and ZF = 0 then done
5415 * - if REPNE/REPNZ and ZF = 1 then done
5416 */
9dac77fa
AK		 5417 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
5418 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
5419 && (((ctxt->rep_prefix == REPE_PREFIX) &&
0efb0440 5420 ((ctxt->eflags & X86_EFLAGS_ZF) == 0))
9dac77fa 5421 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
0efb0440 5422 ((ctxt->eflags & X86_EFLAGS_ZF) == X86_EFLAGS_ZF))))
3e2f65d5
GN		 5423 return true;
5424
5425 return false;
5426}
5427
cbe2c9d3
AK		 5428static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
5429{
aabba3c6 5430 int rc;
cbe2c9d3 5431
43e51464 5432 kvm_fpu_get();
aabba3c6 5433 rc = asm_safe("fwait");
43e51464 5434 kvm_fpu_put();
cbe2c9d3 5435
aabba3c6 5436 if (unlikely(rc != X86EMUL_CONTINUE))
cbe2c9d3
AK		 5437 return emulate_exception(ctxt, MF_VECTOR, 0, false);
5438
5439 return X86EMUL_CONTINUE;
5440}
5441
c0a21c3f 5442static void fetch_possible_mmx_operand(struct operand *op)
cbe2c9d3
AK		 5443{
5444 if (op->type == OP_MM)
43e51464 5445 kvm_read_mmx_reg(op->addr.mm, &op->mm_val);
cbe2c9d3
AK		 5446}
5447
3009afc6 5448static int fastop(struct x86_emulate_ctxt *ctxt, fastop_t fop)
e28bbd44
AK		 5449{
5450 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
4548f63e 5451
b9fa409b
AK		 5452 if (!(ctxt->d & ByteOp))
5453 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
4548f63e 5454
1a29b5b7 5455 asm("push %[flags]; popf; " CALL_NOSPEC " ; pushf; pop %[flags]\n"
b8c0b6ae 5456 : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags),
1a29b5b7 5457 [thunk_target]"+S"(fop), ASM_CALL_CONSTRAINT
b8c0b6ae 5458 : "c"(ctxt->src2.val));
4548f63e 5459
e28bbd44 5460 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
b8c0b6ae
AK		 5461 if (!fop) /* exception is returned in fop variable */
5462 return emulate_de(ctxt);
e28bbd44
AK		 5463 return X86EMUL_CONTINUE;
5464}
dd856efa 5465
1498507a
BD		 5466void init_decode_cache(struct x86_emulate_ctxt *ctxt)
5467{
73ab4a35
SC		 5468 /* Clear fields that are set conditionally but read without a guard. */
5469 ctxt->rip_relative = false;
5470 ctxt->rex_prefix = 0;
5471 ctxt->lock_prefix = 0;
5472 ctxt->rep_prefix = 0;
5473 ctxt->regs_valid = 0;
5474 ctxt->regs_dirty = 0;
1498507a 5475
1498507a
BD		 5476 ctxt->io_read.pos = 0;
5477 ctxt->io_read.end = 0;
1498507a
BD		 5478 ctxt->mem_read.end = 0;
5479}
5480
7b105ca2 5481int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 5482{
0225fb50 5483 const struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 5484 int rc = X86EMUL_CONTINUE;
9dac77fa 5485 int saved_dst_type = ctxt->dst.type;
6ed071f0 5486 unsigned emul_flags;
8b4caf66 5487
9dac77fa 5488 ctxt->mem_read.pos = 0;
310b5d30 5489
e24186e0
PB		 5490 /* LOCK prefix is allowed only with some instructions */
5491 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 5492 rc = emulate_ud(ctxt);
1161624f
GN		 5493 goto done;
5494 }
5495
e24186e0 5496 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 5497 rc = emulate_ud(ctxt);
d380a5e4
GN		 5498 goto done;
5499 }
5500
6ed071f0 5501 emul_flags = ctxt->ops->get_hflags(ctxt);
d40a6898
PB		 5502 if (unlikely(ctxt->d &
5503 (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) {
5504 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
5505 (ctxt->d & Undefined)) {
5506 rc = emulate_ud(ctxt);
5507 goto done;
5508 }
1253791d 5509
d40a6898
PB		 5510 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
5511 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
5512 rc = emulate_ud(ctxt);
cbe2c9d3 5513 goto done;
d40a6898 5514 }
cbe2c9d3 5515
d40a6898
PB		 5516 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
5517 rc = emulate_nm(ctxt);
c4f035c6 5518 goto done;
d40a6898 5519 }
c4f035c6 5520
d40a6898
PB		 5521 if (ctxt->d & Mmx) {
5522 rc = flush_pending_x87_faults(ctxt);
5523 if (rc != X86EMUL_CONTINUE)
5524 goto done;
5525 /*
5526 * Now that we know the fpu is exception safe, we can fetch
5527 * operands from it.
5528 */
c0a21c3f
SC		 5529 fetch_possible_mmx_operand(&ctxt->src);
5530 fetch_possible_mmx_operand(&ctxt->src2);
d40a6898 5531 if (!(ctxt->d & Mov))
c0a21c3f 5532 fetch_possible_mmx_operand(&ctxt->dst);
d40a6898 5533 }
e92805ac 5534
6ed071f0 5535 if (unlikely(emul_flags & X86EMUL_GUEST_MASK) && ctxt->intercept) {
d40a6898
PB		 5536 rc = emulator_check_intercept(ctxt, ctxt->intercept,
5537 X86_ICPT_PRE_EXCEPT);
5538 if (rc != X86EMUL_CONTINUE)
5539 goto done;
5540 }
8ea7d6ae 5541
64a38292
NA		 5542 /* Instruction can only be executed in protected mode */
5543 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
5544 rc = emulate_ud(ctxt);
5545 goto done;
5546 }
5547
d40a6898
PB		 5548 /* Privileged instruction can be executed only in CPL=0 */
5549 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
68efa764
NA		 5550 if (ctxt->d & PrivUD)
5551 rc = emulate_ud(ctxt);
5552 else
5553 rc = emulate_gp(ctxt, 0);
d09beabd 5554 goto done;
d40a6898 5555 }
d09beabd 5556
d40a6898 5557 /* Do instruction specific permission checks */
685bbf4a 5558 if (ctxt->d & CheckPerm) {
d40a6898
PB		 5559 rc = ctxt->check_perm(ctxt);
5560 if (rc != X86EMUL_CONTINUE)
5561 goto done;
5562 }
5563
6ed071f0 5564 if (unlikely(emul_flags & X86EMUL_GUEST_MASK) && (ctxt->d & Intercept)) {
d40a6898
PB		 5565 rc = emulator_check_intercept(ctxt, ctxt->intercept,
5566 X86_ICPT_POST_EXCEPT);
5567 if (rc != X86EMUL_CONTINUE)
5568 goto done;
5569 }
5570
5571 if (ctxt->rep_prefix && (ctxt->d & String)) {
5572 /* All REP prefixes have the same first termination condition */
5573 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
428e3d08 5574 string_registers_quirk(ctxt);
d40a6898 5575 ctxt->eip = ctxt->_eip;
0efb0440 5576 ctxt->eflags &= ~X86_EFLAGS_RF;
d40a6898
PB		 5577 goto done;
5578 }
b9fa9d6b 5579 }
b9fa9d6b
AK		 5580 }
5581
9dac77fa
AK		 5582 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
5583 rc = segmented_read(ctxt, ctxt->src.addr.mem,
5584 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 5585 if (rc != X86EMUL_CONTINUE)
8b4caf66 5586 goto done;
9dac77fa 5587 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 5588 }
5589
9dac77fa
AK		 5590 if (ctxt->src2.type == OP_MEM) {
5591 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
5592 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 5593 if (rc != X86EMUL_CONTINUE)
5594 goto done;
5595 }
5596
9dac77fa 5597 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 5598 goto special_insn;
5599
5600
9dac77fa 5601 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 5602 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 5603 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
5604 &ctxt->dst.val, ctxt->dst.bytes);
c205fb7d 5605 if (rc != X86EMUL_CONTINUE) {
d44e1212
PB		 5606 if (!(ctxt->d & NoWrite) &&
5607 rc == X86EMUL_PROPAGATE_FAULT &&
c205fb7d
NA		 5608 ctxt->exception.vector == PF_VECTOR)
5609 ctxt->exception.error_code |= PFERR_WRITE_MASK;
69f55cb1 5610 goto done;
c205fb7d 5611 }
038e51de 5612 }
4ff6f8e6
PB		 5613 /* Copy full 64-bit value for CMPXCHG8B. */
5614 ctxt->dst.orig_val64 = ctxt->dst.val64;
038e51de 5615
018a98db
AK		 5616special_insn:
5617
6ed071f0 5618 if (unlikely(emul_flags & X86EMUL_GUEST_MASK) && (ctxt->d & Intercept)) {
9dac77fa 5619 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 5620 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 5621 if (rc != X86EMUL_CONTINUE)
5622 goto done;
5623 }
5624
b9a1ecb9 5625 if (ctxt->rep_prefix && (ctxt->d & String))
0efb0440 5626 ctxt->eflags |= X86_EFLAGS_RF;
b9a1ecb9 5627 else
0efb0440 5628 ctxt->eflags &= ~X86_EFLAGS_RF;
4467c3f1 5629
9dac77fa 5630 if (ctxt->execute) {
3009afc6 5631 if (ctxt->d & Fastop)
b78a8552 5632 rc = fastop(ctxt, ctxt->fop);
3009afc6 5633 else
52db3698 5634 rc = ctxt->execute(ctxt);
ef65c889
AK		 5635 if (rc != X86EMUL_CONTINUE)
5636 goto done;
5637 goto writeback;
5638 }
5639
1ce19dc1 5640 if (ctxt->opcode_len == 2)
6aa8b732 5641 goto twobyte_insn;
0bc5eedb
BP		 5642 else if (ctxt->opcode_len == 3)
5643 goto threebyte_insn;
6aa8b732 5644
9dac77fa 5645 switch (ctxt->b) {
b2833e3c 5646 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa 5647 if (test_cc(ctxt->b, ctxt->eflags))
234f3ce4 5648 rc = jmp_rel(ctxt, ctxt->src.val);
018a98db 5649 break;
7e0b54b1 5650 case 0x8d: /* lea r16/r32, m */
9dac77fa 5651 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 5652 break;
3d9e77df 5653 case 0x90 ... 0x97: /* nop / xchg reg, rax */
dd856efa 5654 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
a825f5cc
NA		 5655 ctxt->dst.type = OP_NONE;
5656 else
5657 rc = em_xchg(ctxt);
e4f973ae 5658 break;
e8b6fa70 5659 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 5660 switch (ctxt->op_bytes) {
5661 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
5662 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
5663 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 5664 }
5665 break;
6e154e56 5666 case 0xcc: /* int3 */
5c5df76b
TY		 5667 rc = emulate_int(ctxt, 3);
5668 break;
6e154e56 5669 case 0xcd: /* int n */
9dac77fa 5670 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 5671 break;
5672 case 0xce: /* into */
0efb0440 5673 if (ctxt->eflags & X86_EFLAGS_OF)
5c5df76b 5674 rc = emulate_int(ctxt, 4);
6e154e56 5675 break;
1a52e051 5676 case 0xe9: /* jmp rel */
db5b0762 5677 case 0xeb: /* jmp rel short */
234f3ce4 5678 rc = jmp_rel(ctxt, ctxt->src.val);
9dac77fa 5679 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 5680 break;
111de5d6 5681 case 0xf4: /* hlt */
6c3287f7 5682 ctxt->ops->halt(ctxt);
19fdfa0d 5683 break;
111de5d6
AK		 5684 case 0xf5: /* cmc */
5685 /* complement carry flag from eflags reg */
0efb0440 5686 ctxt->eflags ^= X86_EFLAGS_CF;
111de5d6
AK		 5687 break;
5688 case 0xf8: /* clc */
0efb0440 5689 ctxt->eflags &= ~X86_EFLAGS_CF;
111de5d6 5690 break;
8744aa9a 5691 case 0xf9: /* stc */
0efb0440 5692 ctxt->eflags |= X86_EFLAGS_CF;
8744aa9a 5693 break;
fb4616f4 5694 case 0xfc: /* cld */
0efb0440 5695 ctxt->eflags &= ~X86_EFLAGS_DF;
fb4616f4
MG		 5696 break;
5697 case 0xfd: /* std */
0efb0440 5698 ctxt->eflags |= X86_EFLAGS_DF;
fb4616f4 5699 break;
91269b8f
AK		 5700 default:
5701 goto cannot_emulate;
6aa8b732 5702 }
018a98db 5703
7d9ddaed
AK		 5704 if (rc != X86EMUL_CONTINUE)
5705 goto done;
5706
018a98db 5707writeback:
fb32b1ed
AK		 5708 if (ctxt->d & SrcWrite) {
5709 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR);
5710 rc = writeback(ctxt, &ctxt->src);
5711 if (rc != X86EMUL_CONTINUE)
5712 goto done;
5713 }
ee212297
NA		 5714 if (!(ctxt->d & NoWrite)) {
5715 rc = writeback(ctxt, &ctxt->dst);
5716 if (rc != X86EMUL_CONTINUE)
5717 goto done;
5718 }
018a98db 5719
5cd21917
GN		 5720 /*
5721 * restore dst type in case the decoding will be reused
5722 * (happens for string instruction )
5723 */
9dac77fa 5724 ctxt->dst.type = saved_dst_type;
5cd21917 5725
9dac77fa 5726 if ((ctxt->d & SrcMask) == SrcSI)
f3bd64c6 5727 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
a682e354 5728
9dac77fa 5729 if ((ctxt->d & DstMask) == DstDI)
f3bd64c6 5730 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
d9271123 5731
9dac77fa 5732 if (ctxt->rep_prefix && (ctxt->d & String)) {
b3356bf0 5733 unsigned int count;
9dac77fa 5734 struct read_cache *r = &ctxt->io_read;
b3356bf0
GN		 5735 if ((ctxt->d & SrcMask) == SrcSI)
5736 count = ctxt->src.count;
5737 else
5738 count = ctxt->dst.count;
01485a22 5739 register_address_increment(ctxt, VCPU_REGS_RCX, -count);
3e2f65d5 5740
d2ddd1c4
GN		 5741 if (!string_insn_completed(ctxt)) {
5742 /*
5743 * Re-enter guest when pio read ahead buffer is empty
5744 * or, if it is not used, after each 1024 iteration.
5745 */
dd856efa 5746 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
d2ddd1c4
GN		 5747 (r->end == 0 || r->end != r->pos)) {
5748 /*
5749 * Reset read cache. Usually happens before
5750 * decode, but since instruction is restarted
5751 * we have to do it here.
5752 */
9dac77fa 5753 ctxt->mem_read.end = 0;
dd856efa 5754 writeback_registers(ctxt);
d2ddd1c4
GN		 5755 return EMULATION_RESTART;
5756 }
5757 goto done; /* skip rip writeback */
0fa6ccbd 5758 }
0efb0440 5759 ctxt->eflags &= ~X86_EFLAGS_RF;
5cd21917 5760 }
d2ddd1c4 5761
9dac77fa 5762 ctxt->eip = ctxt->_eip;
fede8076
PB		 5763 if (ctxt->mode != X86EMUL_MODE_PROT64)
5764 ctxt->eip = (u32)ctxt->_eip;
018a98db
AK		 5765
5766done:
e0ad0b47 5767 if (rc == X86EMUL_PROPAGATE_FAULT) {
49a1431d
SC		 5768 if (KVM_EMULATOR_BUG_ON(ctxt->exception.vector > 0x1f, ctxt))
5769 return EMULATION_FAILED;
da9cb575 5770 ctxt->have_exception = true;
e0ad0b47 5771 }
775fde86
JR		 5772 if (rc == X86EMUL_INTERCEPTED)
5773 return EMULATION_INTERCEPTED;
5774
dd856efa
AK		 5775 if (rc == X86EMUL_CONTINUE)
5776 writeback_registers(ctxt);
5777
d2ddd1c4 5778 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 5779
5780twobyte_insn:
9dac77fa 5781 switch (ctxt->b) {
018a98db 5782 case 0x09: /* wbinvd */
cfb22375 5783 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 5784 break;
5785 case 0x08: /* invd */
018a98db
AK		 5786 case 0x0d: /* GrpP (prefetch) */
5787 case 0x18: /* Grp16 (prefetch/nop) */
103f98ea 5788 case 0x1f: /* nop */
018a98db
AK		 5789 break;
5790 case 0x20: /* mov cr, reg */
9dac77fa 5791 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 5792 break;
6aa8b732 5793 case 0x21: /* mov from dr to reg */
9dac77fa 5794 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 5795 break;
6aa8b732 5796 case 0x40 ... 0x4f: /* cmov */
140bad89
NA		 5797 if (test_cc(ctxt->b, ctxt->eflags))
5798 ctxt->dst.val = ctxt->src.val;
b91aa14d 5799 else if (ctxt->op_bytes != 4)
9dac77fa 5800 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 5801 break;
b2833e3c 5802 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa 5803 if (test_cc(ctxt->b, ctxt->eflags))
234f3ce4 5804 rc = jmp_rel(ctxt, ctxt->src.val);
018a98db 5805 break;
ee45b58e 5806 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 5807 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 5808 break;
6aa8b732 5809 case 0xb6 ... 0xb7: /* movzx */
9dac77fa 5810 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 5811 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
9dac77fa 5812 : (u16) ctxt->src.val;
6aa8b732 5813 break;
6aa8b732 5814 case 0xbe ... 0xbf: /* movsx */
9dac77fa 5815 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 5816 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
9dac77fa 5817 (s16) ctxt->src.val;
6aa8b732 5818 break;
91269b8f
AK		 5819 default:
5820 goto cannot_emulate;
6aa8b732 5821 }
7d9ddaed 5822
0bc5eedb
BP		 5823threebyte_insn:
5824
7d9ddaed
AK		 5825 if (rc != X86EMUL_CONTINUE)
5826 goto done;
5827
6aa8b732
AK		 5828 goto writeback;
5829
5830cannot_emulate:
a0c0ab2f 5831 return EMULATION_FAILED;
6aa8b732 5832}
dd856efa
AK		 5833
5834void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
5835{
5836 invalidate_registers(ctxt);
5837}
5838
5839void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
5840{
5841 writeback_registers(ctxt);
5842}
0f89b207
TL		 5843
5844bool emulator_can_use_gpa(struct x86_emulate_ctxt *ctxt)
5845{
5846 if (ctxt->rep_prefix && (ctxt->d & String))
5847 return false;
5848
5849 if (ctxt->d & TwoMemOp)
5850 return false;
5851
5852 return true;
5853}
Linux 6.x block layer and io_uring tree(s)