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KVM: MMU: Track page fault data in struct vcpu
[linux-2.6-block.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
221d059d 12 * Copyright 2010 Red Hat, Inc. and/or its affilates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
23#ifndef __KERNEL__
24#include <stdio.h>
25#include <stdint.h>
26#include <public/xen.h>
d77c26fc 27#define DPRINTF(_f, _a ...) printf(_f , ## _a)
6aa8b732 28#else
edf88417 29#include <linux/kvm_host.h>
5fdbf976 30#include "kvm_cache_regs.h"
6aa8b732
AK		 31#define DPRINTF(x...) do {} while (0)
32#endif
6aa8b732 33#include <linux/module.h>
56e82318 34#include <asm/kvm_emulate.h>
6aa8b732 35
3eeb3288 36#include "x86.h"
38ba30ba 37#include "tss.h"
e99f0507 38
6aa8b732
AK		 39/*
40 * Opcode effective-address decode tables.
41 * Note that we only emulate instructions that have at least one memory
42 * operand (excluding implicit stack references). We assume that stack
43 * references and instruction fetches will never occur in special memory
44 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
45 * not be handled.
46 */
47
48/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 49#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 50/* Destination operand type. */
ab85b12b
AK		 51#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
52#define DstReg (2<<1) /* Register operand. */
53#define DstMem (3<<1) /* Memory operand. */
54#define DstAcc (4<<1) /* Destination Accumulator */
55#define DstDI (5<<1) /* Destination is in ES:(E)DI */
56#define DstMem64 (6<<1) /* 64bit memory operand */
943858e2 57#define DstImmUByte (7<<1) /* 8-bit unsigned immediate operand */
ab85b12b 58#define DstMask (7<<1)
6aa8b732 59/* Source operand type. */
9c9fddd0 60#define SrcNone (0<<4) /* No source operand. */
9c9fddd0
GT		 61#define SrcReg (1<<4) /* Register operand. */
62#define SrcMem (2<<4) /* Memory operand. */
63#define SrcMem16 (3<<4) /* Memory operand (16-bit). */
64#define SrcMem32 (4<<4) /* Memory operand (32-bit). */
65#define SrcImm (5<<4) /* Immediate operand. */
66#define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
bfcadf83 67#define SrcOne (7<<4) /* Implied '1' */
341de7e3 68#define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
c9eaf20f 69#define SrcImmU (9<<4) /* Immediate operand, unsigned */
a682e354 70#define SrcSI (0xa<<4) /* Source is in the DS:RSI */
414e6277
GN		 71#define SrcImmFAddr (0xb<<4) /* Source is immediate far address */
72#define SrcMemFAddr (0xc<<4) /* Source is far address in memory */
5d55f299 73#define SrcAcc (0xd<<4) /* Source Accumulator */
b250e605 74#define SrcImmU16 (0xe<<4) /* Immediate operand, unsigned, 16 bits */
341de7e3 75#define SrcMask (0xf<<4)
6aa8b732 76/* Generic ModRM decode. */
341de7e3 77#define ModRM (1<<8)
6aa8b732 78/* Destination is only written; never read. */
341de7e3
GN		 79#define Mov (1<<9)
80#define BitOp (1<<10)
81#define MemAbs (1<<11) /* Memory operand is absolute displacement */
9c9fddd0
GT		 82#define String (1<<12) /* String instruction (rep capable) */
83#define Stack (1<<13) /* Stack instruction (push/pop) */
e09d082c
AK		 84#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
85#define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
d8769fed 86/* Misc flags */
5a506b12 87#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 88#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 89#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 90#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 91#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 92#define No64 (1<<28)
0dc8d10f
GT		 93/* Source 2 operand type */
94#define Src2None (0<<29)
95#define Src2CL (1<<29)
96#define Src2ImmByte (2<<29)
97#define Src2One (3<<29)
7db41eb7 98#define Src2Imm (4<<29)
0dc8d10f 99#define Src2Mask (7<<29)
6aa8b732 100
d0e53325
AK		 101#define X2(x...) x, x
102#define X3(x...) X2(x), x
103#define X4(x...) X2(x), X2(x)
104#define X5(x...) X4(x), x
105#define X6(x...) X4(x), X2(x)
106#define X7(x...) X4(x), X3(x)
107#define X8(x...) X4(x), X4(x)
108#define X16(x...) X8(x), X8(x)
83babbca 109
d65b1dee
AK		 110struct opcode {
111 u32 flags;
120df890 112 union {
ef65c889 113 int (*execute)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 114 struct opcode *group;
115 struct group_dual *gdual;
116 } u;
117};
118
119struct group_dual {
120 struct opcode mod012[8];
121 struct opcode mod3[8];
d65b1dee
AK		 122};
123
6aa8b732 124/* EFLAGS bit definitions. */
d4c6a154
GN		 125#define EFLG_ID (1<<21)
126#define EFLG_VIP (1<<20)
127#define EFLG_VIF (1<<19)
128#define EFLG_AC (1<<18)
b1d86143
AP		 129#define EFLG_VM (1<<17)
130#define EFLG_RF (1<<16)
d4c6a154
GN		 131#define EFLG_IOPL (3<<12)
132#define EFLG_NT (1<<14)
6aa8b732
AK		 133#define EFLG_OF (1<<11)
134#define EFLG_DF (1<<10)
b1d86143 135#define EFLG_IF (1<<9)
d4c6a154 136#define EFLG_TF (1<<8)
6aa8b732
AK		 137#define EFLG_SF (1<<7)
138#define EFLG_ZF (1<<6)
139#define EFLG_AF (1<<4)
140#define EFLG_PF (1<<2)
141#define EFLG_CF (1<<0)
142
62bd430e
MG		 143#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
144#define EFLG_RESERVED_ONE_MASK 2
145
6aa8b732
AK		 146/*
147 * Instruction emulation:
148 * Most instructions are emulated directly via a fragment of inline assembly
149 * code. This allows us to save/restore EFLAGS and thus very easily pick up
150 * any modified flags.
151 */
152
05b3e0c2 153#if defined(CONFIG_X86_64)
6aa8b732
AK		 154#define _LO32 "k" /* force 32-bit operand */
155#define _STK "%%rsp" /* stack pointer */
156#elif defined(__i386__)
157#define _LO32 "" /* force 32-bit operand */
158#define _STK "%%esp" /* stack pointer */
159#endif
160
161/*
162 * These EFLAGS bits are restored from saved value during emulation, and
163 * any changes are written back to the saved value after emulation.
164 */
165#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
166
167/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 168#define _PRE_EFLAGS(_sav, _msk, _tmp) \
169 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
170 "movl %"_sav",%"_LO32 _tmp"; " \
171 "push %"_tmp"; " \
172 "push %"_tmp"; " \
173 "movl %"_msk",%"_LO32 _tmp"; " \
174 "andl %"_LO32 _tmp",("_STK"); " \
175 "pushf; " \
176 "notl %"_LO32 _tmp"; " \
177 "andl %"_LO32 _tmp",("_STK"); " \
178 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
179 "pop %"_tmp"; " \
180 "orl %"_LO32 _tmp",("_STK"); " \
181 "popf; " \
182 "pop %"_sav"; "
6aa8b732
AK		 183
184/* After executing instruction: write-back necessary bits in EFLAGS. */
185#define _POST_EFLAGS(_sav, _msk, _tmp) \
186 /* _sav |= EFLAGS & _msk; */ \
187 "pushf; " \
188 "pop %"_tmp"; " \
189 "andl %"_msk",%"_LO32 _tmp"; " \
190 "orl %"_LO32 _tmp",%"_sav"; "
191
dda96d8f
AK		 192#ifdef CONFIG_X86_64
193#define ON64(x) x
194#else
195#define ON64(x)
196#endif
197
b3b3d25a 198#define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix, _dsttype) \
6b7ad61f
AK		 199 do { \
200 __asm__ __volatile__ ( \
201 _PRE_EFLAGS("0", "4", "2") \
202 _op _suffix " %"_x"3,%1; " \
203 _POST_EFLAGS("0", "4", "2") \
fb2c2641 204 : "=m" (_eflags), "+q" (*(_dsttype*)&(_dst).val),\
6b7ad61f
AK		 205 "=&r" (_tmp) \
206 : _y ((_src).val), "i" (EFLAGS_MASK)); \
f3fd92fb 207 } while (0)
6b7ad61f
AK		 208
209
6aa8b732
AK		 210/* Raw emulation: instruction has two explicit operands. */
211#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 212 do { \
213 unsigned long _tmp; \
214 \
215 switch ((_dst).bytes) { \
216 case 2: \
b3b3d25a 217 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w",u16);\
6b7ad61f
AK		 218 break; \
219 case 4: \
b3b3d25a 220 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l",u32);\
6b7ad61f
AK		 221 break; \
222 case 8: \
b3b3d25a 223 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q",u64)); \
6b7ad61f
AK		 224 break; \
225 } \
6aa8b732
AK		 226 } while (0)
227
228#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
229 do { \
6b7ad61f 230 unsigned long _tmp; \
d77c26fc 231 switch ((_dst).bytes) { \
6aa8b732 232 case 1: \
b3b3d25a 233 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b",u8); \
6aa8b732
AK		 234 break; \
235 default: \
236 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
237 _wx, _wy, _lx, _ly, _qx, _qy); \
238 break; \
239 } \
240 } while (0)
241
242/* Source operand is byte-sized and may be restricted to just %cl. */
243#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
244 __emulate_2op(_op, _src, _dst, _eflags, \
245 "b", "c", "b", "c", "b", "c", "b", "c")
246
247/* Source operand is byte, word, long or quad sized. */
248#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
249 __emulate_2op(_op, _src, _dst, _eflags, \
250 "b", "q", "w", "r", _LO32, "r", "", "r")
251
252/* Source operand is word, long or quad sized. */
253#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
254 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
255 "w", "r", _LO32, "r", "", "r")
256
d175226a
GT		 257/* Instruction has three operands and one operand is stored in ECX register */
258#define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
259 do { \
260 unsigned long _tmp; \
261 _type _clv = (_cl).val; \
262 _type _srcv = (_src).val; \
263 _type _dstv = (_dst).val; \
264 \
265 __asm__ __volatile__ ( \
266 _PRE_EFLAGS("0", "5", "2") \
267 _op _suffix " %4,%1 \n" \
268 _POST_EFLAGS("0", "5", "2") \
269 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
270 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
271 ); \
272 \
273 (_cl).val = (unsigned long) _clv; \
274 (_src).val = (unsigned long) _srcv; \
275 (_dst).val = (unsigned long) _dstv; \
276 } while (0)
277
278#define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
279 do { \
280 switch ((_dst).bytes) { \
281 case 2: \
282 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
283 "w", unsigned short); \
284 break; \
285 case 4: \
286 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
287 "l", unsigned int); \
288 break; \
289 case 8: \
290 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
291 "q", unsigned long)); \
292 break; \
293 } \
294 } while (0)
295
dda96d8f 296#define __emulate_1op(_op, _dst, _eflags, _suffix) \
6aa8b732
AK		 297 do { \
298 unsigned long _tmp; \
299 \
dda96d8f
AK		 300 __asm__ __volatile__ ( \
301 _PRE_EFLAGS("0", "3", "2") \
302 _op _suffix " %1; " \
303 _POST_EFLAGS("0", "3", "2") \
304 : "=m" (_eflags), "+m" ((_dst).val), \
305 "=&r" (_tmp) \
306 : "i" (EFLAGS_MASK)); \
307 } while (0)
308
309/* Instruction has only one explicit operand (no source operand). */
310#define emulate_1op(_op, _dst, _eflags) \
311 do { \
d77c26fc 312 switch ((_dst).bytes) { \
dda96d8f
AK		 313 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
314 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
315 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
316 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
6aa8b732
AK		 317 } \
318 } while (0)
319
3f9f53b0
MG		 320#define __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, _suffix) \
321 do { \
322 unsigned long _tmp; \
323 \
324 __asm__ __volatile__ ( \
325 _PRE_EFLAGS("0", "4", "1") \
326 _op _suffix " %5; " \
327 _POST_EFLAGS("0", "4", "1") \
328 : "=m" (_eflags), "=&r" (_tmp), \
329 "+a" (_rax), "+d" (_rdx) \
330 : "i" (EFLAGS_MASK), "m" ((_src).val), \
331 "a" (_rax), "d" (_rdx)); \
332 } while (0)
333
f6b3597b
AK		 334#define __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _suffix, _ex) \
335 do { \
336 unsigned long _tmp; \
337 \
338 __asm__ __volatile__ ( \
339 _PRE_EFLAGS("0", "5", "1") \
340 "1: \n\t" \
341 _op _suffix " %6; " \
342 "2: \n\t" \
343 _POST_EFLAGS("0", "5", "1") \
344 ".pushsection .fixup,\"ax\" \n\t" \
345 "3: movb $1, %4 \n\t" \
346 "jmp 2b \n\t" \
347 ".popsection \n\t" \
348 _ASM_EXTABLE(1b, 3b) \
349 : "=m" (_eflags), "=&r" (_tmp), \
350 "+a" (_rax), "+d" (_rdx), "+qm"(_ex) \
351 : "i" (EFLAGS_MASK), "m" ((_src).val), \
352 "a" (_rax), "d" (_rdx)); \
353 } while (0)
354
3f9f53b0
MG		 355/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
356#define emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags) \
357 do { \
358 switch((_src).bytes) { \
359 case 1: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "b"); break; \
360 case 2: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "w"); break; \
361 case 4: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "l"); break; \
362 case 8: ON64(__emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "q")); break; \
363 } \
364 } while (0)
365
f6b3597b
AK		 366#define emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _ex) \
367 do { \
368 switch((_src).bytes) { \
369 case 1: \
370 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
371 _eflags, "b", _ex); \
372 break; \
373 case 2: \
374 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
375 _eflags, "w", _ex); \
376 break; \
377 case 4: \
378 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
379 _eflags, "l", _ex); \
380 break; \
381 case 8: ON64( \
382 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
383 _eflags, "q", _ex)); \
384 break; \
385 } \
386 } while (0)
387
6aa8b732
AK		 388/* Fetch next part of the instruction being emulated. */
389#define insn_fetch(_type, _size, _eip) \
390({ unsigned long _x; \
62266869 391 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
af5b4f7f 392 if (rc != X86EMUL_CONTINUE) \
6aa8b732
AK		 393 goto done; \
394 (_eip) += (_size); \
395 (_type)_x; \
396})
397
414e6277
GN		 398#define insn_fetch_arr(_arr, _size, _eip) \
399({ rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size)); \
400 if (rc != X86EMUL_CONTINUE) \
401 goto done; \
402 (_eip) += (_size); \
403})
404
ddcb2885
HH		 405static inline unsigned long ad_mask(struct decode_cache *c)
406{
407 return (1UL << (c->ad_bytes << 3)) - 1;
408}
409
6aa8b732 410/* Access/update address held in a register, based on addressing mode. */
e4706772
HH		 411static inline unsigned long
412address_mask(struct decode_cache *c, unsigned long reg)
413{
414 if (c->ad_bytes == sizeof(unsigned long))
415 return reg;
416 else
417 return reg & ad_mask(c);
418}
419
420static inline unsigned long
421register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
422{
423 return base + address_mask(c, reg);
424}
425
7a957275
HH		 426static inline void
427register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
428{
429 if (c->ad_bytes == sizeof(unsigned long))
430 *reg += inc;
431 else
432 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
433}
6aa8b732 434
7a957275
HH		 435static inline void jmp_rel(struct decode_cache *c, int rel)
436{
437 register_address_increment(c, &c->eip, rel);
438}
098c937b 439
7a5b56df
AK		 440static void set_seg_override(struct decode_cache *c, int seg)
441{
442 c->has_seg_override = true;
443 c->seg_override = seg;
444}
445
79168fd1
GN		 446static unsigned long seg_base(struct x86_emulate_ctxt *ctxt,
447 struct x86_emulate_ops *ops, int seg)
7a5b56df
AK		 448{
449 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
450 return 0;
451
79168fd1 452 return ops->get_cached_segment_base(seg, ctxt->vcpu);
7a5b56df
AK		 453}
454
455static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt,
79168fd1 456 struct x86_emulate_ops *ops,
7a5b56df
AK		 457 struct decode_cache *c)
458{
459 if (!c->has_seg_override)
460 return 0;
461
79168fd1 462 return seg_base(ctxt, ops, c->seg_override);
7a5b56df
AK		 463}
464
79168fd1
GN		 465static unsigned long es_base(struct x86_emulate_ctxt *ctxt,
466 struct x86_emulate_ops *ops)
7a5b56df 467{
79168fd1 468 return seg_base(ctxt, ops, VCPU_SREG_ES);
7a5b56df
AK		 469}
470
79168fd1
GN		 471static unsigned long ss_base(struct x86_emulate_ctxt *ctxt,
472 struct x86_emulate_ops *ops)
7a5b56df 473{
79168fd1 474 return seg_base(ctxt, ops, VCPU_SREG_SS);
7a5b56df
AK		 475}
476
54b8486f
GN		 477static void emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
478 u32 error, bool valid)
479{
480 ctxt->exception = vec;
481 ctxt->error_code = error;
482 ctxt->error_code_valid = valid;
54b8486f
GN		 483}
484
485static void emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
486{
487 emulate_exception(ctxt, GP_VECTOR, err, true);
488}
489
8df25a32 490static void emulate_pf(struct x86_emulate_ctxt *ctxt)
54b8486f 491{
8df25a32 492 emulate_exception(ctxt, PF_VECTOR, 0, true);
54b8486f
GN		 493}
494
495static void emulate_ud(struct x86_emulate_ctxt *ctxt)
496{
497 emulate_exception(ctxt, UD_VECTOR, 0, false);
498}
499
500static void emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
501{
502 emulate_exception(ctxt, TS_VECTOR, err, true);
503}
504
34d1f490
AK		 505static int emulate_de(struct x86_emulate_ctxt *ctxt)
506{
507 emulate_exception(ctxt, DE_VECTOR, 0, false);
508 return X86EMUL_PROPAGATE_FAULT;
509}
510
62266869
AK		 511static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
512 struct x86_emulate_ops *ops,
2fb53ad8 513 unsigned long eip, u8 *dest)
62266869
AK		 514{
515 struct fetch_cache *fc = &ctxt->decode.fetch;
516 int rc;
2fb53ad8 517 int size, cur_size;
62266869 518
2fb53ad8
AK		 519 if (eip == fc->end) {
520 cur_size = fc->end - fc->start;
521 size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip));
522 rc = ops->fetch(ctxt->cs_base + eip, fc->data + cur_size,
523 size, ctxt->vcpu, NULL);
3e2815e9 524 if (rc != X86EMUL_CONTINUE)
62266869 525 return rc;
2fb53ad8 526 fc->end += size;
62266869 527 }
2fb53ad8 528 *dest = fc->data[eip - fc->start];
3e2815e9 529 return X86EMUL_CONTINUE;
62266869
AK		 530}
531
532static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
533 struct x86_emulate_ops *ops,
534 unsigned long eip, void *dest, unsigned size)
535{
3e2815e9 536 int rc;
62266869 537
eb3c79e6 538 /* x86 instructions are limited to 15 bytes. */
063db061 539 if (eip + size - ctxt->eip > 15)
eb3c79e6 540 return X86EMUL_UNHANDLEABLE;
62266869
AK		 541 while (size--) {
542 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
3e2815e9 543 if (rc != X86EMUL_CONTINUE)
62266869
AK		 544 return rc;
545 }
3e2815e9 546 return X86EMUL_CONTINUE;
62266869
AK		 547}
548
1e3c5cb0
RR		 549/*
550 * Given the 'reg' portion of a ModRM byte, and a register block, return a
551 * pointer into the block that addresses the relevant register.
552 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
553 */
554static void *decode_register(u8 modrm_reg, unsigned long *regs,
555 int highbyte_regs)
6aa8b732
AK		 556{
557 void *p;
558
559 p = &regs[modrm_reg];
560 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
561 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
562 return p;
563}
564
565static int read_descriptor(struct x86_emulate_ctxt *ctxt,
566 struct x86_emulate_ops *ops,
1a6440ae 567 ulong addr,
6aa8b732
AK		 568 u16 *size, unsigned long *address, int op_bytes)
569{
570 int rc;
571
572 if (op_bytes == 2)
573 op_bytes = 3;
574 *address = 0;
1a6440ae 575 rc = ops->read_std(addr, (unsigned long *)size, 2, ctxt->vcpu, NULL);
1b30eaa8 576 if (rc != X86EMUL_CONTINUE)
6aa8b732 577 return rc;
1a6440ae 578 rc = ops->read_std(addr + 2, address, op_bytes, ctxt->vcpu, NULL);
6aa8b732
AK		 579 return rc;
580}
581
bbe9abbd
NK		 582static int test_cc(unsigned int condition, unsigned int flags)
583{
584 int rc = 0;
585
586 switch ((condition & 15) >> 1) {
587 case 0: /* o */
588 rc |= (flags & EFLG_OF);
589 break;
590 case 1: /* b/c/nae */
591 rc |= (flags & EFLG_CF);
592 break;
593 case 2: /* z/e */
594 rc |= (flags & EFLG_ZF);
595 break;
596 case 3: /* be/na */
597 rc |= (flags & (EFLG_CF|EFLG_ZF));
598 break;
599 case 4: /* s */
600 rc |= (flags & EFLG_SF);
601 break;
602 case 5: /* p/pe */
603 rc |= (flags & EFLG_PF);
604 break;
605 case 7: /* le/ng */
606 rc |= (flags & EFLG_ZF);
607 /* fall through */
608 case 6: /* l/nge */
609 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
610 break;
611 }
612
613 /* Odd condition identifiers (lsb == 1) have inverted sense. */
614 return (!!rc ^ (condition & 1));
615}
616
91ff3cb4
AK		 617static void fetch_register_operand(struct operand *op)
618{
619 switch (op->bytes) {
620 case 1:
621 op->val = *(u8 *)op->addr.reg;
622 break;
623 case 2:
624 op->val = *(u16 *)op->addr.reg;
625 break;
626 case 4:
627 op->val = *(u32 *)op->addr.reg;
628 break;
629 case 8:
630 op->val = *(u64 *)op->addr.reg;
631 break;
632 }
633}
634
3c118e24
AK		 635static void decode_register_operand(struct operand *op,
636 struct decode_cache *c,
3c118e24
AK		 637 int inhibit_bytereg)
638{
33615aa9 639 unsigned reg = c->modrm_reg;
9f1ef3f8 640 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 641
642 if (!(c->d & ModRM))
643 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
3c118e24
AK		 644 op->type = OP_REG;
645 if ((c->d & ByteOp) && !inhibit_bytereg) {
1a6440ae 646 op->addr.reg = decode_register(reg, c->regs, highbyte_regs);
3c118e24
AK		 647 op->bytes = 1;
648 } else {
1a6440ae 649 op->addr.reg = decode_register(reg, c->regs, 0);
3c118e24 650 op->bytes = c->op_bytes;
3c118e24 651 }
91ff3cb4 652 fetch_register_operand(op);
3c118e24
AK		 653 op->orig_val = op->val;
654}
655
1c73ef66 656static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7
AK		 657 struct x86_emulate_ops *ops,
658 struct operand *op)
1c73ef66
AK		 659{
660 struct decode_cache *c = &ctxt->decode;
661 u8 sib;
f5b4edcd 662 int index_reg = 0, base_reg = 0, scale;
3e2815e9 663 int rc = X86EMUL_CONTINUE;
2dbd0dd7 664 ulong modrm_ea = 0;
1c73ef66
AK		 665
666 if (c->rex_prefix) {
667 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
668 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
669 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
670 }
671
672 c->modrm = insn_fetch(u8, 1, c->eip);
673 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
674 c->modrm_reg |= (c->modrm & 0x38) >> 3;
675 c->modrm_rm |= (c->modrm & 0x07);
09ee57cd 676 c->modrm_seg = VCPU_SREG_DS;
1c73ef66
AK		 677
678 if (c->modrm_mod == 3) {
2dbd0dd7
AK		 679 op->type = OP_REG;
680 op->bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
681 op->addr.reg = decode_register(c->modrm_rm,
107d6d2e 682 c->regs, c->d & ByteOp);
2dbd0dd7 683 fetch_register_operand(op);
1c73ef66
AK		 684 return rc;
685 }
686
2dbd0dd7
AK		 687 op->type = OP_MEM;
688
1c73ef66
AK		 689 if (c->ad_bytes == 2) {
690 unsigned bx = c->regs[VCPU_REGS_RBX];
691 unsigned bp = c->regs[VCPU_REGS_RBP];
692 unsigned si = c->regs[VCPU_REGS_RSI];
693 unsigned di = c->regs[VCPU_REGS_RDI];
694
695 /* 16-bit ModR/M decode. */
696 switch (c->modrm_mod) {
697 case 0:
698 if (c->modrm_rm == 6)
2dbd0dd7 699 modrm_ea += insn_fetch(u16, 2, c->eip);
1c73ef66
AK		 700 break;
701 case 1:
2dbd0dd7 702 modrm_ea += insn_fetch(s8, 1, c->eip);
1c73ef66
AK		 703 break;
704 case 2:
2dbd0dd7 705 modrm_ea += insn_fetch(u16, 2, c->eip);
1c73ef66
AK		 706 break;
707 }
708 switch (c->modrm_rm) {
709 case 0:
2dbd0dd7 710 modrm_ea += bx + si;
1c73ef66
AK		 711 break;
712 case 1:
2dbd0dd7 713 modrm_ea += bx + di;
1c73ef66
AK		 714 break;
715 case 2:
2dbd0dd7 716 modrm_ea += bp + si;
1c73ef66
AK		 717 break;
718 case 3:
2dbd0dd7 719 modrm_ea += bp + di;
1c73ef66
AK		 720 break;
721 case 4:
2dbd0dd7 722 modrm_ea += si;
1c73ef66
AK		 723 break;
724 case 5:
2dbd0dd7 725 modrm_ea += di;
1c73ef66
AK		 726 break;
727 case 6:
728 if (c->modrm_mod != 0)
2dbd0dd7 729 modrm_ea += bp;
1c73ef66
AK		 730 break;
731 case 7:
2dbd0dd7 732 modrm_ea += bx;
1c73ef66
AK		 733 break;
734 }
735 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
736 (c->modrm_rm == 6 && c->modrm_mod != 0))
09ee57cd 737 c->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 738 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 739 } else {
740 /* 32/64-bit ModR/M decode. */
84411d85 741 if ((c->modrm_rm & 7) == 4) {
1c73ef66
AK		 742 sib = insn_fetch(u8, 1, c->eip);
743 index_reg |= (sib >> 3) & 7;
744 base_reg |= sib & 7;
745 scale = sib >> 6;
746
dc71d0f1 747 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
2dbd0dd7 748 modrm_ea += insn_fetch(s32, 4, c->eip);
dc71d0f1 749 else
2dbd0dd7 750 modrm_ea += c->regs[base_reg];
dc71d0f1 751 if (index_reg != 4)
2dbd0dd7 752 modrm_ea += c->regs[index_reg] << scale;
84411d85
AK		 753 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
754 if (ctxt->mode == X86EMUL_MODE_PROT64)
f5b4edcd 755 c->rip_relative = 1;
84411d85 756 } else
2dbd0dd7 757 modrm_ea += c->regs[c->modrm_rm];
1c73ef66
AK		 758 switch (c->modrm_mod) {
759 case 0:
760 if (c->modrm_rm == 5)
2dbd0dd7 761 modrm_ea += insn_fetch(s32, 4, c->eip);
1c73ef66
AK		 762 break;
763 case 1:
2dbd0dd7 764 modrm_ea += insn_fetch(s8, 1, c->eip);
1c73ef66
AK		 765 break;
766 case 2:
2dbd0dd7 767 modrm_ea += insn_fetch(s32, 4, c->eip);
1c73ef66
AK		 768 break;
769 }
770 }
2dbd0dd7 771 op->addr.mem = modrm_ea;
1c73ef66
AK		 772done:
773 return rc;
774}
775
776static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7
AK		 777 struct x86_emulate_ops *ops,
778 struct operand *op)
1c73ef66
AK		 779{
780 struct decode_cache *c = &ctxt->decode;
3e2815e9 781 int rc = X86EMUL_CONTINUE;
1c73ef66 782
2dbd0dd7 783 op->type = OP_MEM;
1c73ef66
AK		 784 switch (c->ad_bytes) {
785 case 2:
2dbd0dd7 786 op->addr.mem = insn_fetch(u16, 2, c->eip);
1c73ef66
AK		 787 break;
788 case 4:
2dbd0dd7 789 op->addr.mem = insn_fetch(u32, 4, c->eip);
1c73ef66
AK		 790 break;
791 case 8:
2dbd0dd7 792 op->addr.mem = insn_fetch(u64, 8, c->eip);
1c73ef66
AK		 793 break;
794 }
795done:
796 return rc;
797}
798
35c843c4
WY		 799static void fetch_bit_operand(struct decode_cache *c)
800{
801 long sv, mask;
802
3885f18f 803 if (c->dst.type == OP_MEM && c->src.type == OP_REG) {
35c843c4
WY		 804 mask = ~(c->dst.bytes * 8 - 1);
805
806 if (c->src.bytes == 2)
807 sv = (s16)c->src.val & (s16)mask;
808 else if (c->src.bytes == 4)
809 sv = (s32)c->src.val & (s32)mask;
810
811 c->dst.addr.mem += (sv >> 3);
812 }
ba7ff2b7
WY		 813
814 /* only subword offset */
815 c->src.val &= (c->dst.bytes << 3) - 1;
35c843c4
WY		 816}
817
dde7e6d1
AK		 818static int read_emulated(struct x86_emulate_ctxt *ctxt,
819 struct x86_emulate_ops *ops,
820 unsigned long addr, void *dest, unsigned size)
6aa8b732 821{
dde7e6d1
AK		 822 int rc;
823 struct read_cache *mc = &ctxt->decode.mem_read;
824 u32 err;
6aa8b732 825
dde7e6d1
AK		 826 while (size) {
827 int n = min(size, 8u);
828 size -= n;
829 if (mc->pos < mc->end)
830 goto read_cached;
5cd21917 831
dde7e6d1
AK		 832 rc = ops->read_emulated(addr, mc->data + mc->end, n, &err,
833 ctxt->vcpu);
834 if (rc == X86EMUL_PROPAGATE_FAULT)
8df25a32 835 emulate_pf(ctxt);
dde7e6d1
AK		 836 if (rc != X86EMUL_CONTINUE)
837 return rc;
838 mc->end += n;
6aa8b732 839
dde7e6d1
AK		 840 read_cached:
841 memcpy(dest, mc->data + mc->pos, n);
842 mc->pos += n;
843 dest += n;
844 addr += n;
6aa8b732 845 }
dde7e6d1
AK		 846 return X86EMUL_CONTINUE;
847}
6aa8b732 848
dde7e6d1
AK		 849static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
850 struct x86_emulate_ops *ops,
851 unsigned int size, unsigned short port,
852 void *dest)
853{
854 struct read_cache *rc = &ctxt->decode.io_read;
b4c6abfe 855
dde7e6d1
AK		 856 if (rc->pos == rc->end) { /* refill pio read ahead */
857 struct decode_cache *c = &ctxt->decode;
858 unsigned int in_page, n;
859 unsigned int count = c->rep_prefix ?
860 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1;
861 in_page = (ctxt->eflags & EFLG_DF) ?
862 offset_in_page(c->regs[VCPU_REGS_RDI]) :
863 PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]);
864 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
865 count);
866 if (n == 0)
867 n = 1;
868 rc->pos = rc->end = 0;
869 if (!ops->pio_in_emulated(size, port, rc->data, n, ctxt->vcpu))
870 return 0;
871 rc->end = n * size;
6aa8b732
AK		 872 }
873
dde7e6d1
AK		 874 memcpy(dest, rc->data + rc->pos, size);
875 rc->pos += size;
876 return 1;
877}
6aa8b732 878
dde7e6d1
AK		 879static u32 desc_limit_scaled(struct desc_struct *desc)
880{
881 u32 limit = get_desc_limit(desc);
6aa8b732 882
dde7e6d1
AK		 883 return desc->g ? (limit << 12) | 0xfff : limit;
884}
6aa8b732 885
dde7e6d1
AK		 886static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
887 struct x86_emulate_ops *ops,
888 u16 selector, struct desc_ptr *dt)
889{
890 if (selector & 1 << 2) {
891 struct desc_struct desc;
892 memset (dt, 0, sizeof *dt);
893 if (!ops->get_cached_descriptor(&desc, VCPU_SREG_LDTR, ctxt->vcpu))
894 return;
e09d082c 895
dde7e6d1
AK		 896 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
897 dt->address = get_desc_base(&desc);
898 } else
899 ops->get_gdt(dt, ctxt->vcpu);
900}
120df890 901
dde7e6d1
AK		 902/* allowed just for 8 bytes segments */
903static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
904 struct x86_emulate_ops *ops,
905 u16 selector, struct desc_struct *desc)
906{
907 struct desc_ptr dt;
908 u16 index = selector >> 3;
909 int ret;
910 u32 err;
911 ulong addr;
120df890 912
dde7e6d1 913 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
120df890 914
dde7e6d1
AK		 915 if (dt.size < index * 8 + 7) {
916 emulate_gp(ctxt, selector & 0xfffc);
917 return X86EMUL_PROPAGATE_FAULT;
e09d082c 918 }
dde7e6d1
AK		 919 addr = dt.address + index * 8;
920 ret = ops->read_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
921 if (ret == X86EMUL_PROPAGATE_FAULT)
8df25a32 922 emulate_pf(ctxt);
e09d082c 923
dde7e6d1
AK		 924 return ret;
925}
ef65c889 926
dde7e6d1
AK		 927/* allowed just for 8 bytes segments */
928static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
929 struct x86_emulate_ops *ops,
930 u16 selector, struct desc_struct *desc)
931{
932 struct desc_ptr dt;
933 u16 index = selector >> 3;
934 u32 err;
935 ulong addr;
936 int ret;
6aa8b732 937
dde7e6d1 938 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
6e3d5dfb 939
dde7e6d1
AK		 940 if (dt.size < index * 8 + 7) {
941 emulate_gp(ctxt, selector & 0xfffc);
942 return X86EMUL_PROPAGATE_FAULT;
943 }
6aa8b732 944
dde7e6d1
AK		 945 addr = dt.address + index * 8;
946 ret = ops->write_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
947 if (ret == X86EMUL_PROPAGATE_FAULT)
8df25a32 948 emulate_pf(ctxt);
c7e75a3d 949
dde7e6d1
AK		 950 return ret;
951}
c7e75a3d 952
dde7e6d1
AK		 953static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
954 struct x86_emulate_ops *ops,
955 u16 selector, int seg)
956{
957 struct desc_struct seg_desc;
958 u8 dpl, rpl, cpl;
959 unsigned err_vec = GP_VECTOR;
960 u32 err_code = 0;
961 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
962 int ret;
69f55cb1 963
dde7e6d1 964 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 965
dde7e6d1
AK		 966 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
967 || ctxt->mode == X86EMUL_MODE_REAL) {
968 /* set real mode segment descriptor */
969 set_desc_base(&seg_desc, selector << 4);
970 set_desc_limit(&seg_desc, 0xffff);
971 seg_desc.type = 3;
972 seg_desc.p = 1;
973 seg_desc.s = 1;
974 goto load;
975 }
976
977 /* NULL selector is not valid for TR, CS and SS */
978 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
979 && null_selector)
980 goto exception;
981
982 /* TR should be in GDT only */
983 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
984 goto exception;
985
986 if (null_selector) /* for NULL selector skip all following checks */
987 goto load;
988
989 ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc);
990 if (ret != X86EMUL_CONTINUE)
991 return ret;
992
993 err_code = selector & 0xfffc;
994 err_vec = GP_VECTOR;
995
996 /* can't load system descriptor into segment selecor */
997 if (seg <= VCPU_SREG_GS && !seg_desc.s)
998 goto exception;
999
1000 if (!seg_desc.p) {
1001 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1002 goto exception;
1003 }
1004
1005 rpl = selector & 3;
1006 dpl = seg_desc.dpl;
1007 cpl = ops->cpl(ctxt->vcpu);
1008
1009 switch (seg) {
1010 case VCPU_SREG_SS:
1011 /*
1012 * segment is not a writable data segment or segment
1013 * selector's RPL != CPL or segment selector's RPL != CPL
1014 */
1015 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1016 goto exception;
6aa8b732 1017 break;
dde7e6d1
AK		 1018 case VCPU_SREG_CS:
1019 if (!(seg_desc.type & 8))
1020 goto exception;
1021
1022 if (seg_desc.type & 4) {
1023 /* conforming */
1024 if (dpl > cpl)
1025 goto exception;
1026 } else {
1027 /* nonconforming */
1028 if (rpl > cpl || dpl != cpl)
1029 goto exception;
1030 }
1031 /* CS(RPL) <- CPL */
1032 selector = (selector & 0xfffc) | cpl;
6aa8b732 1033 break;
dde7e6d1
AK		 1034 case VCPU_SREG_TR:
1035 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1036 goto exception;
1037 break;
1038 case VCPU_SREG_LDTR:
1039 if (seg_desc.s || seg_desc.type != 2)
1040 goto exception;
1041 break;
1042 default: /* DS, ES, FS, or GS */
4e62417b 1043 /*
dde7e6d1
AK		 1044 * segment is not a data or readable code segment or
1045 * ((segment is a data or nonconforming code segment)
1046 * and (both RPL and CPL > DPL))
4e62417b 1047 */
dde7e6d1
AK		 1048 if ((seg_desc.type & 0xa) == 0x8 ||
1049 (((seg_desc.type & 0xc) != 0xc) &&
1050 (rpl > dpl && cpl > dpl)))
1051 goto exception;
6aa8b732 1052 break;
dde7e6d1
AK		 1053 }
1054
1055 if (seg_desc.s) {
1056 /* mark segment as accessed */
1057 seg_desc.type |= 1;
1058 ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc);
1059 if (ret != X86EMUL_CONTINUE)
1060 return ret;
1061 }
1062load:
1063 ops->set_segment_selector(selector, seg, ctxt->vcpu);
1064 ops->set_cached_descriptor(&seg_desc, seg, ctxt->vcpu);
1065 return X86EMUL_CONTINUE;
1066exception:
1067 emulate_exception(ctxt, err_vec, err_code, true);
1068 return X86EMUL_PROPAGATE_FAULT;
1069}
1070
31be40b3
WY		 1071static void write_register_operand(struct operand *op)
1072{
1073 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1074 switch (op->bytes) {
1075 case 1:
1076 *(u8 *)op->addr.reg = (u8)op->val;
1077 break;
1078 case 2:
1079 *(u16 *)op->addr.reg = (u16)op->val;
1080 break;
1081 case 4:
1082 *op->addr.reg = (u32)op->val;
1083 break; /* 64b: zero-extend */
1084 case 8:
1085 *op->addr.reg = op->val;
1086 break;
1087 }
1088}
1089
dde7e6d1
AK		 1090static inline int writeback(struct x86_emulate_ctxt *ctxt,
1091 struct x86_emulate_ops *ops)
1092{
1093 int rc;
1094 struct decode_cache *c = &ctxt->decode;
1095 u32 err;
1096
1097 switch (c->dst.type) {
1098 case OP_REG:
31be40b3 1099 write_register_operand(&c->dst);
6aa8b732 1100 break;
dde7e6d1
AK		 1101 case OP_MEM:
1102 if (c->lock_prefix)
1103 rc = ops->cmpxchg_emulated(
1a6440ae 1104 c->dst.addr.mem,
dde7e6d1
AK		 1105 &c->dst.orig_val,
1106 &c->dst.val,
1107 c->dst.bytes,
1108 &err,
1109 ctxt->vcpu);
341de7e3 1110 else
dde7e6d1 1111 rc = ops->write_emulated(
1a6440ae 1112 c->dst.addr.mem,
dde7e6d1
AK		 1113 &c->dst.val,
1114 c->dst.bytes,
1115 &err,
1116 ctxt->vcpu);
1117 if (rc == X86EMUL_PROPAGATE_FAULT)
8df25a32 1118 emulate_pf(ctxt);
dde7e6d1
AK		 1119 if (rc != X86EMUL_CONTINUE)
1120 return rc;
a682e354 1121 break;
dde7e6d1
AK		 1122 case OP_NONE:
1123 /* no writeback */
414e6277 1124 break;
dde7e6d1 1125 default:
414e6277 1126 break;
6aa8b732 1127 }
dde7e6d1
AK		 1128 return X86EMUL_CONTINUE;
1129}
6aa8b732 1130
dde7e6d1
AK		 1131static inline void emulate_push(struct x86_emulate_ctxt *ctxt,
1132 struct x86_emulate_ops *ops)
1133{
1134 struct decode_cache *c = &ctxt->decode;
0dc8d10f 1135
dde7e6d1
AK		 1136 c->dst.type = OP_MEM;
1137 c->dst.bytes = c->op_bytes;
1138 c->dst.val = c->src.val;
1139 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
1a6440ae
AK		 1140 c->dst.addr.mem = register_address(c, ss_base(ctxt, ops),
1141 c->regs[VCPU_REGS_RSP]);
dde7e6d1 1142}
69f55cb1 1143
dde7e6d1
AK		 1144static int emulate_pop(struct x86_emulate_ctxt *ctxt,
1145 struct x86_emulate_ops *ops,
1146 void *dest, int len)
1147{
1148 struct decode_cache *c = &ctxt->decode;
1149 int rc;
8b4caf66 1150
dde7e6d1
AK		 1151 rc = read_emulated(ctxt, ops, register_address(c, ss_base(ctxt, ops),
1152 c->regs[VCPU_REGS_RSP]),
1153 dest, len);
1154 if (rc != X86EMUL_CONTINUE)
1155 return rc;
1156
1157 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
1158 return rc;
8b4caf66
LV		 1159}
1160
dde7e6d1
AK		 1161static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1162 struct x86_emulate_ops *ops,
1163 void *dest, int len)
9de41573
GN		 1164{
1165 int rc;
dde7e6d1
AK		 1166 unsigned long val, change_mask;
1167 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1168 int cpl = ops->cpl(ctxt->vcpu);
9de41573 1169
dde7e6d1
AK		 1170 rc = emulate_pop(ctxt, ops, &val, len);
1171 if (rc != X86EMUL_CONTINUE)
1172 return rc;
9de41573 1173
dde7e6d1
AK		 1174 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1175 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1176
dde7e6d1
AK		 1177 switch(ctxt->mode) {
1178 case X86EMUL_MODE_PROT64:
1179 case X86EMUL_MODE_PROT32:
1180 case X86EMUL_MODE_PROT16:
1181 if (cpl == 0)
1182 change_mask |= EFLG_IOPL;
1183 if (cpl <= iopl)
1184 change_mask |= EFLG_IF;
1185 break;
1186 case X86EMUL_MODE_VM86:
1187 if (iopl < 3) {
1188 emulate_gp(ctxt, 0);
1189 return X86EMUL_PROPAGATE_FAULT;
1190 }
1191 change_mask |= EFLG_IF;
1192 break;
1193 default: /* real mode */
1194 change_mask |= (EFLG_IOPL | EFLG_IF);
1195 break;
9de41573 1196 }
dde7e6d1
AK		 1197
1198 *(unsigned long *)dest =
1199 (ctxt->eflags & ~change_mask) | (val & change_mask);
1200
1201 return rc;
9de41573
GN		 1202}
1203
dde7e6d1
AK		 1204static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt,
1205 struct x86_emulate_ops *ops, int seg)
7b262e90 1206{
dde7e6d1 1207 struct decode_cache *c = &ctxt->decode;
7b262e90 1208
dde7e6d1 1209 c->src.val = ops->get_segment_selector(seg, ctxt->vcpu);
7b262e90 1210
dde7e6d1 1211 emulate_push(ctxt, ops);
7b262e90
GN		 1212}
1213
dde7e6d1
AK		 1214static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
1215 struct x86_emulate_ops *ops, int seg)
38ba30ba 1216{
dde7e6d1
AK		 1217 struct decode_cache *c = &ctxt->decode;
1218 unsigned long selector;
1219 int rc;
38ba30ba 1220
dde7e6d1
AK		 1221 rc = emulate_pop(ctxt, ops, &selector, c->op_bytes);
1222 if (rc != X86EMUL_CONTINUE)
1223 return rc;
1224
1225 rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg);
1226 return rc;
38ba30ba
GN		 1227}
1228
dde7e6d1
AK		 1229static int emulate_pusha(struct x86_emulate_ctxt *ctxt,
1230 struct x86_emulate_ops *ops)
38ba30ba 1231{
dde7e6d1
AK		 1232 struct decode_cache *c = &ctxt->decode;
1233 unsigned long old_esp = c->regs[VCPU_REGS_RSP];
1234 int rc = X86EMUL_CONTINUE;
1235 int reg = VCPU_REGS_RAX;
38ba30ba 1236
dde7e6d1
AK		 1237 while (reg <= VCPU_REGS_RDI) {
1238 (reg == VCPU_REGS_RSP) ?
1239 (c->src.val = old_esp) : (c->src.val = c->regs[reg]);
38ba30ba 1240
dde7e6d1 1241 emulate_push(ctxt, ops);
38ba30ba 1242
dde7e6d1
AK		 1243 rc = writeback(ctxt, ops);
1244 if (rc != X86EMUL_CONTINUE)
1245 return rc;
38ba30ba 1246
dde7e6d1 1247 ++reg;
38ba30ba 1248 }
38ba30ba 1249
dde7e6d1
AK		 1250 /* Disable writeback. */
1251 c->dst.type = OP_NONE;
1252
1253 return rc;
38ba30ba
GN		 1254}
1255
dde7e6d1
AK		 1256static int emulate_popa(struct x86_emulate_ctxt *ctxt,
1257 struct x86_emulate_ops *ops)
38ba30ba 1258{
dde7e6d1
AK		 1259 struct decode_cache *c = &ctxt->decode;
1260 int rc = X86EMUL_CONTINUE;
1261 int reg = VCPU_REGS_RDI;
38ba30ba 1262
dde7e6d1
AK		 1263 while (reg >= VCPU_REGS_RAX) {
1264 if (reg == VCPU_REGS_RSP) {
1265 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1266 c->op_bytes);
1267 --reg;
1268 }
38ba30ba 1269
dde7e6d1
AK		 1270 rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes);
1271 if (rc != X86EMUL_CONTINUE)
1272 break;
1273 --reg;
38ba30ba 1274 }
dde7e6d1 1275 return rc;
38ba30ba
GN		 1276}
1277
6e154e56
MG		 1278int emulate_int_real(struct x86_emulate_ctxt *ctxt,
1279 struct x86_emulate_ops *ops, int irq)
1280{
1281 struct decode_cache *c = &ctxt->decode;
5c56e1cf 1282 int rc;
6e154e56
MG		 1283 struct desc_ptr dt;
1284 gva_t cs_addr;
1285 gva_t eip_addr;
1286 u16 cs, eip;
1287 u32 err;
1288
1289 /* TODO: Add limit checks */
1290 c->src.val = ctxt->eflags;
1291 emulate_push(ctxt, ops);
5c56e1cf
AK		 1292 rc = writeback(ctxt, ops);
1293 if (rc != X86EMUL_CONTINUE)
1294 return rc;
6e154e56
MG		 1295
1296 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1297
1298 c->src.val = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
1299 emulate_push(ctxt, ops);
5c56e1cf
AK		 1300 rc = writeback(ctxt, ops);
1301 if (rc != X86EMUL_CONTINUE)
1302 return rc;
6e154e56
MG		 1303
1304 c->src.val = c->eip;
1305 emulate_push(ctxt, ops);
5c56e1cf
AK		 1306 rc = writeback(ctxt, ops);
1307 if (rc != X86EMUL_CONTINUE)
1308 return rc;
1309
1310 c->dst.type = OP_NONE;
6e154e56
MG		 1311
1312 ops->get_idt(&dt, ctxt->vcpu);
1313
1314 eip_addr = dt.address + (irq << 2);
1315 cs_addr = dt.address + (irq << 2) + 2;
1316
1317 rc = ops->read_std(cs_addr, &cs, 2, ctxt->vcpu, &err);
1318 if (rc != X86EMUL_CONTINUE)
1319 return rc;
1320
1321 rc = ops->read_std(eip_addr, &eip, 2, ctxt->vcpu, &err);
1322 if (rc != X86EMUL_CONTINUE)
1323 return rc;
1324
1325 rc = load_segment_descriptor(ctxt, ops, cs, VCPU_SREG_CS);
1326 if (rc != X86EMUL_CONTINUE)
1327 return rc;
1328
1329 c->eip = eip;
1330
1331 return rc;
1332}
1333
1334static int emulate_int(struct x86_emulate_ctxt *ctxt,
1335 struct x86_emulate_ops *ops, int irq)
1336{
1337 switch(ctxt->mode) {
1338 case X86EMUL_MODE_REAL:
1339 return emulate_int_real(ctxt, ops, irq);
1340 case X86EMUL_MODE_VM86:
1341 case X86EMUL_MODE_PROT16:
1342 case X86EMUL_MODE_PROT32:
1343 case X86EMUL_MODE_PROT64:
1344 default:
1345 /* Protected mode interrupts unimplemented yet */
1346 return X86EMUL_UNHANDLEABLE;
1347 }
1348}
1349
dde7e6d1
AK		 1350static int emulate_iret_real(struct x86_emulate_ctxt *ctxt,
1351 struct x86_emulate_ops *ops)
38ba30ba 1352{
dde7e6d1
AK		 1353 struct decode_cache *c = &ctxt->decode;
1354 int rc = X86EMUL_CONTINUE;
1355 unsigned long temp_eip = 0;
1356 unsigned long temp_eflags = 0;
1357 unsigned long cs = 0;
1358 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1359 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1360 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1361 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1362
dde7e6d1 1363 /* TODO: Add stack limit check */
38ba30ba 1364
dde7e6d1 1365 rc = emulate_pop(ctxt, ops, &temp_eip, c->op_bytes);
38ba30ba 1366
dde7e6d1
AK		 1367 if (rc != X86EMUL_CONTINUE)
1368 return rc;
38ba30ba 1369
dde7e6d1
AK		 1370 if (temp_eip & ~0xffff) {
1371 emulate_gp(ctxt, 0);
1372 return X86EMUL_PROPAGATE_FAULT;
1373 }
38ba30ba 1374
dde7e6d1 1375 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
38ba30ba 1376
dde7e6d1
AK		 1377 if (rc != X86EMUL_CONTINUE)
1378 return rc;
38ba30ba 1379
dde7e6d1 1380 rc = emulate_pop(ctxt, ops, &temp_eflags, c->op_bytes);
38ba30ba 1381
dde7e6d1
AK		 1382 if (rc != X86EMUL_CONTINUE)
1383 return rc;
38ba30ba 1384
dde7e6d1 1385 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
38ba30ba 1386
dde7e6d1
AK		 1387 if (rc != X86EMUL_CONTINUE)
1388 return rc;
38ba30ba 1389
dde7e6d1 1390 c->eip = temp_eip;
38ba30ba 1391
38ba30ba 1392
dde7e6d1
AK		 1393 if (c->op_bytes == 4)
1394 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
1395 else if (c->op_bytes == 2) {
1396 ctxt->eflags &= ~0xffff;
1397 ctxt->eflags |= temp_eflags;
38ba30ba 1398 }
dde7e6d1
AK		 1399
1400 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1401 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1402
1403 return rc;
38ba30ba
GN		 1404}
1405
dde7e6d1
AK		 1406static inline int emulate_iret(struct x86_emulate_ctxt *ctxt,
1407 struct x86_emulate_ops* ops)
c37eda13 1408{
dde7e6d1
AK		 1409 switch(ctxt->mode) {
1410 case X86EMUL_MODE_REAL:
1411 return emulate_iret_real(ctxt, ops);
1412 case X86EMUL_MODE_VM86:
1413 case X86EMUL_MODE_PROT16:
1414 case X86EMUL_MODE_PROT32:
1415 case X86EMUL_MODE_PROT64:
c37eda13 1416 default:
dde7e6d1
AK		 1417 /* iret from protected mode unimplemented yet */
1418 return X86EMUL_UNHANDLEABLE;
c37eda13 1419 }
c37eda13
WY		 1420}
1421
dde7e6d1 1422static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
79168fd1 1423 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1424{
1425 struct decode_cache *c = &ctxt->decode;
1426
dde7e6d1 1427 return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
8cdbd2c9
LV		 1428}
1429
dde7e6d1 1430static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1431{
05f086f8 1432 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1433 switch (c->modrm_reg) {
1434 case 0: /* rol */
05f086f8 1435 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1436 break;
1437 case 1: /* ror */
05f086f8 1438 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1439 break;
1440 case 2: /* rcl */
05f086f8 1441 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1442 break;
1443 case 3: /* rcr */
05f086f8 1444 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1445 break;
1446 case 4: /* sal/shl */
1447 case 6: /* sal/shl */
05f086f8 1448 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1449 break;
1450 case 5: /* shr */
05f086f8 1451 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1452 break;
1453 case 7: /* sar */
05f086f8 1454 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1455 break;
1456 }
1457}
1458
1459static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 1460 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1461{
1462 struct decode_cache *c = &ctxt->decode;
3f9f53b0
MG		 1463 unsigned long *rax = &c->regs[VCPU_REGS_RAX];
1464 unsigned long *rdx = &c->regs[VCPU_REGS_RDX];
34d1f490 1465 u8 de = 0;
8cdbd2c9
LV		 1466
1467 switch (c->modrm_reg) {
1468 case 0 ... 1: /* test */
05f086f8 1469 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1470 break;
1471 case 2: /* not */
1472 c->dst.val = ~c->dst.val;
1473 break;
1474 case 3: /* neg */
05f086f8 1475 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9 1476 break;
3f9f53b0
MG		 1477 case 4: /* mul */
1478 emulate_1op_rax_rdx("mul", c->src, *rax, *rdx, ctxt->eflags);
1479 break;
1480 case 5: /* imul */
1481 emulate_1op_rax_rdx("imul", c->src, *rax, *rdx, ctxt->eflags);
1482 break;
1483 case 6: /* div */
34d1f490
AK		 1484 emulate_1op_rax_rdx_ex("div", c->src, *rax, *rdx,
1485 ctxt->eflags, de);
3f9f53b0
MG		 1486 break;
1487 case 7: /* idiv */
34d1f490
AK		 1488 emulate_1op_rax_rdx_ex("idiv", c->src, *rax, *rdx,
1489 ctxt->eflags, de);
3f9f53b0 1490 break;
8cdbd2c9 1491 default:
8c5eee30 1492 return X86EMUL_UNHANDLEABLE;
8cdbd2c9 1493 }
34d1f490
AK		 1494 if (de)
1495 return emulate_de(ctxt);
8c5eee30 1496 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1497}
1498
1499static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
a01af5ec 1500 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1501{
1502 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1503
1504 switch (c->modrm_reg) {
1505 case 0: /* inc */
05f086f8 1506 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1507 break;
1508 case 1: /* dec */
05f086f8 1509 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9 1510 break;
d19292e4
MG		 1511 case 2: /* call near abs */ {
1512 long int old_eip;
1513 old_eip = c->eip;
1514 c->eip = c->src.val;
1515 c->src.val = old_eip;
79168fd1 1516 emulate_push(ctxt, ops);
d19292e4
MG		 1517 break;
1518 }
8cdbd2c9 1519 case 4: /* jmp abs */
fd60754e 1520 c->eip = c->src.val;
8cdbd2c9
LV		 1521 break;
1522 case 6: /* push */
79168fd1 1523 emulate_push(ctxt, ops);
8cdbd2c9 1524 break;
8cdbd2c9 1525 }
1b30eaa8 1526 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1527}
1528
1529static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
69f55cb1 1530 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1531{
1532 struct decode_cache *c = &ctxt->decode;
16518d5a 1533 u64 old = c->dst.orig_val64;
8cdbd2c9
LV		 1534
1535 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1536 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
8cdbd2c9
LV		 1537 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1538 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1539 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 1540 } else {
16518d5a
AK		 1541 c->dst.val64 = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1542 (u32) c->regs[VCPU_REGS_RBX];
8cdbd2c9 1543
05f086f8 1544 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 1545 }
1b30eaa8 1546 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1547}
1548
a77ab5ea
AK		 1549static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1550 struct x86_emulate_ops *ops)
1551{
1552 struct decode_cache *c = &ctxt->decode;
1553 int rc;
1554 unsigned long cs;
1555
1556 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1b30eaa8 1557 if (rc != X86EMUL_CONTINUE)
a77ab5ea
AK		 1558 return rc;
1559 if (c->op_bytes == 4)
1560 c->eip = (u32)c->eip;
1561 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1b30eaa8 1562 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1563 return rc;
2e873022 1564 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 1565 return rc;
1566}
1567
09b5f4d3
WY		 1568static int emulate_load_segment(struct x86_emulate_ctxt *ctxt,
1569 struct x86_emulate_ops *ops, int seg)
1570{
1571 struct decode_cache *c = &ctxt->decode;
1572 unsigned short sel;
1573 int rc;
1574
1575 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
1576
1577 rc = load_segment_descriptor(ctxt, ops, sel, seg);
1578 if (rc != X86EMUL_CONTINUE)
1579 return rc;
1580
1581 c->dst.val = c->src.val;
1582 return rc;
1583}
1584
e66bb2cc
AP		 1585static inline void
1586setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
79168fd1
GN		 1587 struct x86_emulate_ops *ops, struct desc_struct *cs,
1588 struct desc_struct *ss)
e66bb2cc 1589{
79168fd1
GN		 1590 memset(cs, 0, sizeof(struct desc_struct));
1591 ops->get_cached_descriptor(cs, VCPU_SREG_CS, ctxt->vcpu);
1592 memset(ss, 0, sizeof(struct desc_struct));
e66bb2cc
AP		 1593
1594 cs->l = 0; /* will be adjusted later */
79168fd1 1595 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 1596 cs->g = 1; /* 4kb granularity */
79168fd1 1597 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1598 cs->type = 0x0b; /* Read, Execute, Accessed */
1599 cs->s = 1;
1600 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 1601 cs->p = 1;
1602 cs->d = 1;
e66bb2cc 1603
79168fd1
GN		 1604 set_desc_base(ss, 0); /* flat segment */
1605 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1606 ss->g = 1; /* 4kb granularity */
1607 ss->s = 1;
1608 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 1609 ss->d = 1; /* 32bit stack segment */
e66bb2cc 1610 ss->dpl = 0;
79168fd1 1611 ss->p = 1;
e66bb2cc
AP		 1612}
1613
1614static int
3fb1b5db 1615emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
e66bb2cc
AP		 1616{
1617 struct decode_cache *c = &ctxt->decode;
79168fd1 1618 struct desc_struct cs, ss;
e66bb2cc 1619 u64 msr_data;
79168fd1 1620 u16 cs_sel, ss_sel;
e66bb2cc
AP		 1621
1622 /* syscall is not available in real mode */
2e901c4c
GN		 1623 if (ctxt->mode == X86EMUL_MODE_REAL ||
1624 ctxt->mode == X86EMUL_MODE_VM86) {
54b8486f 1625 emulate_ud(ctxt);
2e901c4c
GN		 1626 return X86EMUL_PROPAGATE_FAULT;
1627 }
e66bb2cc 1628
79168fd1 1629 setup_syscalls_segments(ctxt, ops, &cs, &ss);
e66bb2cc 1630
3fb1b5db 1631 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
e66bb2cc 1632 msr_data >>= 32;
79168fd1
GN		 1633 cs_sel = (u16)(msr_data & 0xfffc);
1634 ss_sel = (u16)(msr_data + 8);
e66bb2cc
AP		 1635
1636 if (is_long_mode(ctxt->vcpu)) {
79168fd1 1637 cs.d = 0;
e66bb2cc
AP		 1638 cs.l = 1;
1639 }
79168fd1
GN		 1640 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
1641 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
1642 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
1643 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
e66bb2cc
AP		 1644
1645 c->regs[VCPU_REGS_RCX] = c->eip;
1646 if (is_long_mode(ctxt->vcpu)) {
1647#ifdef CONFIG_X86_64
1648 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
1649
3fb1b5db
GN		 1650 ops->get_msr(ctxt->vcpu,
1651 ctxt->mode == X86EMUL_MODE_PROT64 ?
1652 MSR_LSTAR : MSR_CSTAR, &msr_data);
e66bb2cc
AP		 1653 c->eip = msr_data;
1654
3fb1b5db 1655 ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 1656 ctxt->eflags &= ~(msr_data | EFLG_RF);
1657#endif
1658 } else {
1659 /* legacy mode */
3fb1b5db 1660 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
e66bb2cc
AP		 1661 c->eip = (u32)msr_data;
1662
1663 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1664 }
1665
e54cfa97 1666 return X86EMUL_CONTINUE;
e66bb2cc
AP		 1667}
1668
8c604352 1669static int
3fb1b5db 1670emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8c604352
AP		 1671{
1672 struct decode_cache *c = &ctxt->decode;
79168fd1 1673 struct desc_struct cs, ss;
8c604352 1674 u64 msr_data;
79168fd1 1675 u16 cs_sel, ss_sel;
8c604352 1676
a0044755
GN		 1677 /* inject #GP if in real mode */
1678 if (ctxt->mode == X86EMUL_MODE_REAL) {
54b8486f 1679 emulate_gp(ctxt, 0);
2e901c4c 1680 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 1681 }
1682
1683 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1684 * Therefore, we inject an #UD.
1685 */
2e901c4c 1686 if (ctxt->mode == X86EMUL_MODE_PROT64) {
54b8486f 1687 emulate_ud(ctxt);
2e901c4c
GN		 1688 return X86EMUL_PROPAGATE_FAULT;
1689 }
8c604352 1690
79168fd1 1691 setup_syscalls_segments(ctxt, ops, &cs, &ss);
8c604352 1692
3fb1b5db 1693 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 1694 switch (ctxt->mode) {
1695 case X86EMUL_MODE_PROT32:
1696 if ((msr_data & 0xfffc) == 0x0) {
54b8486f 1697 emulate_gp(ctxt, 0);
e54cfa97 1698 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 1699 }
1700 break;
1701 case X86EMUL_MODE_PROT64:
1702 if (msr_data == 0x0) {
54b8486f 1703 emulate_gp(ctxt, 0);
e54cfa97 1704 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 1705 }
1706 break;
1707 }
1708
1709 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 1710 cs_sel = (u16)msr_data;
1711 cs_sel &= ~SELECTOR_RPL_MASK;
1712 ss_sel = cs_sel + 8;
1713 ss_sel &= ~SELECTOR_RPL_MASK;
8c604352
AP		 1714 if (ctxt->mode == X86EMUL_MODE_PROT64
1715 || is_long_mode(ctxt->vcpu)) {
79168fd1 1716 cs.d = 0;
8c604352
AP		 1717 cs.l = 1;
1718 }
1719
79168fd1
GN		 1720 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
1721 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
1722 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
1723 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
8c604352 1724
3fb1b5db 1725 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data);
8c604352
AP		 1726 c->eip = msr_data;
1727
3fb1b5db 1728 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data);
8c604352
AP		 1729 c->regs[VCPU_REGS_RSP] = msr_data;
1730
e54cfa97 1731 return X86EMUL_CONTINUE;
8c604352
AP		 1732}
1733
4668f050 1734static int
3fb1b5db 1735emulate_sysexit(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
4668f050
AP		 1736{
1737 struct decode_cache *c = &ctxt->decode;
79168fd1 1738 struct desc_struct cs, ss;
4668f050
AP		 1739 u64 msr_data;
1740 int usermode;
79168fd1 1741 u16 cs_sel, ss_sel;
4668f050 1742
a0044755
GN		 1743 /* inject #GP if in real mode or Virtual 8086 mode */
1744 if (ctxt->mode == X86EMUL_MODE_REAL ||
1745 ctxt->mode == X86EMUL_MODE_VM86) {
54b8486f 1746 emulate_gp(ctxt, 0);
2e901c4c 1747 return X86EMUL_PROPAGATE_FAULT;
4668f050
AP		 1748 }
1749
79168fd1 1750 setup_syscalls_segments(ctxt, ops, &cs, &ss);
4668f050
AP		 1751
1752 if ((c->rex_prefix & 0x8) != 0x0)
1753 usermode = X86EMUL_MODE_PROT64;
1754 else
1755 usermode = X86EMUL_MODE_PROT32;
1756
1757 cs.dpl = 3;
1758 ss.dpl = 3;
3fb1b5db 1759 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 1760 switch (usermode) {
1761 case X86EMUL_MODE_PROT32:
79168fd1 1762 cs_sel = (u16)(msr_data + 16);
4668f050 1763 if ((msr_data & 0xfffc) == 0x0) {
54b8486f 1764 emulate_gp(ctxt, 0);
e54cfa97 1765 return X86EMUL_PROPAGATE_FAULT;
4668f050 1766 }
79168fd1 1767 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 1768 break;
1769 case X86EMUL_MODE_PROT64:
79168fd1 1770 cs_sel = (u16)(msr_data + 32);
4668f050 1771 if (msr_data == 0x0) {
54b8486f 1772 emulate_gp(ctxt, 0);
e54cfa97 1773 return X86EMUL_PROPAGATE_FAULT;
4668f050 1774 }
79168fd1
GN		 1775 ss_sel = cs_sel + 8;
1776 cs.d = 0;
4668f050
AP		 1777 cs.l = 1;
1778 break;
1779 }
79168fd1
GN		 1780 cs_sel |= SELECTOR_RPL_MASK;
1781 ss_sel |= SELECTOR_RPL_MASK;
4668f050 1782
79168fd1
GN		 1783 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
1784 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
1785 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
1786 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
4668f050 1787
bdb475a3
GN		 1788 c->eip = c->regs[VCPU_REGS_RDX];
1789 c->regs[VCPU_REGS_RSP] = c->regs[VCPU_REGS_RCX];
4668f050 1790
e54cfa97 1791 return X86EMUL_CONTINUE;
4668f050
AP		 1792}
1793
9c537244
GN		 1794static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt,
1795 struct x86_emulate_ops *ops)
f850e2e6
GN		 1796{
1797 int iopl;
1798 if (ctxt->mode == X86EMUL_MODE_REAL)
1799 return false;
1800 if (ctxt->mode == X86EMUL_MODE_VM86)
1801 return true;
1802 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
9c537244 1803 return ops->cpl(ctxt->vcpu) > iopl;
f850e2e6
GN		 1804}
1805
1806static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
1807 struct x86_emulate_ops *ops,
1808 u16 port, u16 len)
1809{
79168fd1 1810 struct desc_struct tr_seg;
f850e2e6
GN		 1811 int r;
1812 u16 io_bitmap_ptr;
1813 u8 perm, bit_idx = port & 0x7;
1814 unsigned mask = (1 << len) - 1;
1815
79168fd1
GN		 1816 ops->get_cached_descriptor(&tr_seg, VCPU_SREG_TR, ctxt->vcpu);
1817 if (!tr_seg.p)
f850e2e6 1818 return false;
79168fd1 1819 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 1820 return false;
79168fd1
GN		 1821 r = ops->read_std(get_desc_base(&tr_seg) + 102, &io_bitmap_ptr, 2,
1822 ctxt->vcpu, NULL);
f850e2e6
GN		 1823 if (r != X86EMUL_CONTINUE)
1824 return false;
79168fd1 1825 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 1826 return false;
79168fd1
GN		 1827 r = ops->read_std(get_desc_base(&tr_seg) + io_bitmap_ptr + port/8,
1828 &perm, 1, ctxt->vcpu, NULL);
f850e2e6
GN		 1829 if (r != X86EMUL_CONTINUE)
1830 return false;
1831 if ((perm >> bit_idx) & mask)
1832 return false;
1833 return true;
1834}
1835
1836static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
1837 struct x86_emulate_ops *ops,
1838 u16 port, u16 len)
1839{
4fc40f07
GN		 1840 if (ctxt->perm_ok)
1841 return true;
1842
9c537244 1843 if (emulator_bad_iopl(ctxt, ops))
f850e2e6
GN		 1844 if (!emulator_io_port_access_allowed(ctxt, ops, port, len))
1845 return false;
4fc40f07
GN		 1846
1847 ctxt->perm_ok = true;
1848
f850e2e6
GN		 1849 return true;
1850}
1851
38ba30ba
GN		 1852static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
1853 struct x86_emulate_ops *ops,
1854 struct tss_segment_16 *tss)
1855{
1856 struct decode_cache *c = &ctxt->decode;
1857
1858 tss->ip = c->eip;
1859 tss->flag = ctxt->eflags;
1860 tss->ax = c->regs[VCPU_REGS_RAX];
1861 tss->cx = c->regs[VCPU_REGS_RCX];
1862 tss->dx = c->regs[VCPU_REGS_RDX];
1863 tss->bx = c->regs[VCPU_REGS_RBX];
1864 tss->sp = c->regs[VCPU_REGS_RSP];
1865 tss->bp = c->regs[VCPU_REGS_RBP];
1866 tss->si = c->regs[VCPU_REGS_RSI];
1867 tss->di = c->regs[VCPU_REGS_RDI];
1868
1869 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
1870 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
1871 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
1872 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
1873 tss->ldt = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
1874}
1875
1876static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
1877 struct x86_emulate_ops *ops,
1878 struct tss_segment_16 *tss)
1879{
1880 struct decode_cache *c = &ctxt->decode;
1881 int ret;
1882
1883 c->eip = tss->ip;
1884 ctxt->eflags = tss->flag | 2;
1885 c->regs[VCPU_REGS_RAX] = tss->ax;
1886 c->regs[VCPU_REGS_RCX] = tss->cx;
1887 c->regs[VCPU_REGS_RDX] = tss->dx;
1888 c->regs[VCPU_REGS_RBX] = tss->bx;
1889 c->regs[VCPU_REGS_RSP] = tss->sp;
1890 c->regs[VCPU_REGS_RBP] = tss->bp;
1891 c->regs[VCPU_REGS_RSI] = tss->si;
1892 c->regs[VCPU_REGS_RDI] = tss->di;
1893
1894 /*
1895 * SDM says that segment selectors are loaded before segment
1896 * descriptors
1897 */
1898 ops->set_segment_selector(tss->ldt, VCPU_SREG_LDTR, ctxt->vcpu);
1899 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
1900 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
1901 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
1902 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
1903
1904 /*
1905 * Now load segment descriptors. If fault happenes at this stage
1906 * it is handled in a context of new task
1907 */
1908 ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR);
1909 if (ret != X86EMUL_CONTINUE)
1910 return ret;
1911 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
1912 if (ret != X86EMUL_CONTINUE)
1913 return ret;
1914 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
1915 if (ret != X86EMUL_CONTINUE)
1916 return ret;
1917 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
1918 if (ret != X86EMUL_CONTINUE)
1919 return ret;
1920 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
1921 if (ret != X86EMUL_CONTINUE)
1922 return ret;
1923
1924 return X86EMUL_CONTINUE;
1925}
1926
1927static int task_switch_16(struct x86_emulate_ctxt *ctxt,
1928 struct x86_emulate_ops *ops,
1929 u16 tss_selector, u16 old_tss_sel,
1930 ulong old_tss_base, struct desc_struct *new_desc)
1931{
1932 struct tss_segment_16 tss_seg;
1933 int ret;
1934 u32 err, new_tss_base = get_desc_base(new_desc);
1935
1936 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
1937 &err);
1938 if (ret == X86EMUL_PROPAGATE_FAULT) {
1939 /* FIXME: need to provide precise fault address */
8df25a32 1940 emulate_pf(ctxt);
38ba30ba
GN		 1941 return ret;
1942 }
1943
1944 save_state_to_tss16(ctxt, ops, &tss_seg);
1945
1946 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
1947 &err);
1948 if (ret == X86EMUL_PROPAGATE_FAULT) {
1949 /* FIXME: need to provide precise fault address */
8df25a32 1950 emulate_pf(ctxt);
38ba30ba
GN		 1951 return ret;
1952 }
1953
1954 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
1955 &err);
1956 if (ret == X86EMUL_PROPAGATE_FAULT) {
1957 /* FIXME: need to provide precise fault address */
8df25a32 1958 emulate_pf(ctxt);
38ba30ba
GN		 1959 return ret;
1960 }
1961
1962 if (old_tss_sel != 0xffff) {
1963 tss_seg.prev_task_link = old_tss_sel;
1964
1965 ret = ops->write_std(new_tss_base,
1966 &tss_seg.prev_task_link,
1967 sizeof tss_seg.prev_task_link,
1968 ctxt->vcpu, &err);
1969 if (ret == X86EMUL_PROPAGATE_FAULT) {
1970 /* FIXME: need to provide precise fault address */
8df25a32 1971 emulate_pf(ctxt);
38ba30ba
GN		 1972 return ret;
1973 }
1974 }
1975
1976 return load_state_from_tss16(ctxt, ops, &tss_seg);
1977}
1978
1979static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
1980 struct x86_emulate_ops *ops,
1981 struct tss_segment_32 *tss)
1982{
1983 struct decode_cache *c = &ctxt->decode;
1984
1985 tss->cr3 = ops->get_cr(3, ctxt->vcpu);
1986 tss->eip = c->eip;
1987 tss->eflags = ctxt->eflags;
1988 tss->eax = c->regs[VCPU_REGS_RAX];
1989 tss->ecx = c->regs[VCPU_REGS_RCX];
1990 tss->edx = c->regs[VCPU_REGS_RDX];
1991 tss->ebx = c->regs[VCPU_REGS_RBX];
1992 tss->esp = c->regs[VCPU_REGS_RSP];
1993 tss->ebp = c->regs[VCPU_REGS_RBP];
1994 tss->esi = c->regs[VCPU_REGS_RSI];
1995 tss->edi = c->regs[VCPU_REGS_RDI];
1996
1997 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
1998 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
1999 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
2000 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
2001 tss->fs = ops->get_segment_selector(VCPU_SREG_FS, ctxt->vcpu);
2002 tss->gs = ops->get_segment_selector(VCPU_SREG_GS, ctxt->vcpu);
2003 tss->ldt_selector = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
2004}
2005
2006static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
2007 struct x86_emulate_ops *ops,
2008 struct tss_segment_32 *tss)
2009{
2010 struct decode_cache *c = &ctxt->decode;
2011 int ret;
2012
0f12244f 2013 if (ops->set_cr(3, tss->cr3, ctxt->vcpu)) {
54b8486f 2014 emulate_gp(ctxt, 0);
0f12244f
GN		 2015 return X86EMUL_PROPAGATE_FAULT;
2016 }
38ba30ba
GN		 2017 c->eip = tss->eip;
2018 ctxt->eflags = tss->eflags | 2;
2019 c->regs[VCPU_REGS_RAX] = tss->eax;
2020 c->regs[VCPU_REGS_RCX] = tss->ecx;
2021 c->regs[VCPU_REGS_RDX] = tss->edx;
2022 c->regs[VCPU_REGS_RBX] = tss->ebx;
2023 c->regs[VCPU_REGS_RSP] = tss->esp;
2024 c->regs[VCPU_REGS_RBP] = tss->ebp;
2025 c->regs[VCPU_REGS_RSI] = tss->esi;
2026 c->regs[VCPU_REGS_RDI] = tss->edi;
2027
2028 /*
2029 * SDM says that segment selectors are loaded before segment
2030 * descriptors
2031 */
2032 ops->set_segment_selector(tss->ldt_selector, VCPU_SREG_LDTR, ctxt->vcpu);
2033 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
2034 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
2035 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
2036 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
2037 ops->set_segment_selector(tss->fs, VCPU_SREG_FS, ctxt->vcpu);
2038 ops->set_segment_selector(tss->gs, VCPU_SREG_GS, ctxt->vcpu);
2039
2040 /*
2041 * Now load segment descriptors. If fault happenes at this stage
2042 * it is handled in a context of new task
2043 */
2044 ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR);
2045 if (ret != X86EMUL_CONTINUE)
2046 return ret;
2047 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2048 if (ret != X86EMUL_CONTINUE)
2049 return ret;
2050 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2051 if (ret != X86EMUL_CONTINUE)
2052 return ret;
2053 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2054 if (ret != X86EMUL_CONTINUE)
2055 return ret;
2056 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2057 if (ret != X86EMUL_CONTINUE)
2058 return ret;
2059 ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS);
2060 if (ret != X86EMUL_CONTINUE)
2061 return ret;
2062 ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS);
2063 if (ret != X86EMUL_CONTINUE)
2064 return ret;
2065
2066 return X86EMUL_CONTINUE;
2067}
2068
2069static int task_switch_32(struct x86_emulate_ctxt *ctxt,
2070 struct x86_emulate_ops *ops,
2071 u16 tss_selector, u16 old_tss_sel,
2072 ulong old_tss_base, struct desc_struct *new_desc)
2073{
2074 struct tss_segment_32 tss_seg;
2075 int ret;
2076 u32 err, new_tss_base = get_desc_base(new_desc);
2077
2078 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2079 &err);
2080 if (ret == X86EMUL_PROPAGATE_FAULT) {
2081 /* FIXME: need to provide precise fault address */
8df25a32 2082 emulate_pf(ctxt);
38ba30ba
GN		 2083 return ret;
2084 }
2085
2086 save_state_to_tss32(ctxt, ops, &tss_seg);
2087
2088 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2089 &err);
2090 if (ret == X86EMUL_PROPAGATE_FAULT) {
2091 /* FIXME: need to provide precise fault address */
8df25a32 2092 emulate_pf(ctxt);
38ba30ba
GN		 2093 return ret;
2094 }
2095
2096 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2097 &err);
2098 if (ret == X86EMUL_PROPAGATE_FAULT) {
2099 /* FIXME: need to provide precise fault address */
8df25a32 2100 emulate_pf(ctxt);
38ba30ba
GN		 2101 return ret;
2102 }
2103
2104 if (old_tss_sel != 0xffff) {
2105 tss_seg.prev_task_link = old_tss_sel;
2106
2107 ret = ops->write_std(new_tss_base,
2108 &tss_seg.prev_task_link,
2109 sizeof tss_seg.prev_task_link,
2110 ctxt->vcpu, &err);
2111 if (ret == X86EMUL_PROPAGATE_FAULT) {
2112 /* FIXME: need to provide precise fault address */
8df25a32 2113 emulate_pf(ctxt);
38ba30ba
GN		 2114 return ret;
2115 }
2116 }
2117
2118 return load_state_from_tss32(ctxt, ops, &tss_seg);
2119}
2120
2121static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2122 struct x86_emulate_ops *ops,
2123 u16 tss_selector, int reason,
2124 bool has_error_code, u32 error_code)
38ba30ba
GN		 2125{
2126 struct desc_struct curr_tss_desc, next_tss_desc;
2127 int ret;
2128 u16 old_tss_sel = ops->get_segment_selector(VCPU_SREG_TR, ctxt->vcpu);
2129 ulong old_tss_base =
5951c442 2130 ops->get_cached_segment_base(VCPU_SREG_TR, ctxt->vcpu);
ceffb459 2131 u32 desc_limit;
38ba30ba
GN		 2132
2133 /* FIXME: old_tss_base == ~0 ? */
2134
2135 ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc);
2136 if (ret != X86EMUL_CONTINUE)
2137 return ret;
2138 ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc);
2139 if (ret != X86EMUL_CONTINUE)
2140 return ret;
2141
2142 /* FIXME: check that next_tss_desc is tss */
2143
2144 if (reason != TASK_SWITCH_IRET) {
2145 if ((tss_selector & 3) > next_tss_desc.dpl ||
2146 ops->cpl(ctxt->vcpu) > next_tss_desc.dpl) {
54b8486f 2147 emulate_gp(ctxt, 0);
38ba30ba
GN		 2148 return X86EMUL_PROPAGATE_FAULT;
2149 }
2150 }
2151
ceffb459
GN		 2152 desc_limit = desc_limit_scaled(&next_tss_desc);
2153 if (!next_tss_desc.p ||
2154 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2155 desc_limit < 0x2b)) {
54b8486f 2156 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2157 return X86EMUL_PROPAGATE_FAULT;
2158 }
2159
2160 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2161 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2162 write_segment_descriptor(ctxt, ops, old_tss_sel,
2163 &curr_tss_desc);
2164 }
2165
2166 if (reason == TASK_SWITCH_IRET)
2167 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2168
2169 /* set back link to prev task only if NT bit is set in eflags
2170 note that old_tss_sel is not used afetr this point */
2171 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2172 old_tss_sel = 0xffff;
2173
2174 if (next_tss_desc.type & 8)
2175 ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel,
2176 old_tss_base, &next_tss_desc);
2177 else
2178 ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel,
2179 old_tss_base, &next_tss_desc);
0760d448
JK		 2180 if (ret != X86EMUL_CONTINUE)
2181 return ret;
38ba30ba
GN		 2182
2183 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2184 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2185
2186 if (reason != TASK_SWITCH_IRET) {
2187 next_tss_desc.type |= (1 << 1); /* set busy flag */
2188 write_segment_descriptor(ctxt, ops, tss_selector,
2189 &next_tss_desc);
2190 }
2191
2192 ops->set_cr(0, ops->get_cr(0, ctxt->vcpu) | X86_CR0_TS, ctxt->vcpu);
2193 ops->set_cached_descriptor(&next_tss_desc, VCPU_SREG_TR, ctxt->vcpu);
2194 ops->set_segment_selector(tss_selector, VCPU_SREG_TR, ctxt->vcpu);
2195
e269fb21
JK		 2196 if (has_error_code) {
2197 struct decode_cache *c = &ctxt->decode;
2198
2199 c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2200 c->lock_prefix = 0;
2201 c->src.val = (unsigned long) error_code;
79168fd1 2202 emulate_push(ctxt, ops);
e269fb21
JK		 2203 }
2204
38ba30ba
GN		 2205 return ret;
2206}
2207
2208int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2209 u16 tss_selector, int reason,
2210 bool has_error_code, u32 error_code)
38ba30ba 2211{
9aabc88f 2212 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2213 struct decode_cache *c = &ctxt->decode;
2214 int rc;
2215
38ba30ba 2216 c->eip = ctxt->eip;
e269fb21 2217 c->dst.type = OP_NONE;
38ba30ba 2218
e269fb21
JK		 2219 rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason,
2220 has_error_code, error_code);
38ba30ba
GN		 2221
2222 if (rc == X86EMUL_CONTINUE) {
e269fb21 2223 rc = writeback(ctxt, ops);
95c55886
GN		 2224 if (rc == X86EMUL_CONTINUE)
2225 ctxt->eip = c->eip;
38ba30ba
GN		 2226 }
2227
19d04437 2228 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
38ba30ba
GN		 2229}
2230
a682e354 2231static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned long base,
d9271123 2232 int reg, struct operand *op)
a682e354
GN		 2233{
2234 struct decode_cache *c = &ctxt->decode;
2235 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2236
d9271123 2237 register_address_increment(c, &c->regs[reg], df * op->bytes);
1a6440ae 2238 op->addr.mem = register_address(c, base, c->regs[reg]);
a682e354
GN		 2239}
2240
63540382
AK		 2241static int em_push(struct x86_emulate_ctxt *ctxt)
2242{
2243 emulate_push(ctxt, ctxt->ops);
2244 return X86EMUL_CONTINUE;
2245}
2246
7af04fc0
AK		 2247static int em_das(struct x86_emulate_ctxt *ctxt)
2248{
2249 struct decode_cache *c = &ctxt->decode;
2250 u8 al, old_al;
2251 bool af, cf, old_cf;
2252
2253 cf = ctxt->eflags & X86_EFLAGS_CF;
2254 al = c->dst.val;
2255
2256 old_al = al;
2257 old_cf = cf;
2258 cf = false;
2259 af = ctxt->eflags & X86_EFLAGS_AF;
2260 if ((al & 0x0f) > 9 || af) {
2261 al -= 6;
2262 cf = old_cf | (al >= 250);
2263 af = true;
2264 } else {
2265 af = false;
2266 }
2267 if (old_al > 0x99 || old_cf) {
2268 al -= 0x60;
2269 cf = true;
2270 }
2271
2272 c->dst.val = al;
2273 /* Set PF, ZF, SF */
2274 c->src.type = OP_IMM;
2275 c->src.val = 0;
2276 c->src.bytes = 1;
2277 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
2278 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2279 if (cf)
2280 ctxt->eflags |= X86_EFLAGS_CF;
2281 if (af)
2282 ctxt->eflags |= X86_EFLAGS_AF;
2283 return X86EMUL_CONTINUE;
2284}
2285
0ef753b8
AK		 2286static int em_call_far(struct x86_emulate_ctxt *ctxt)
2287{
2288 struct decode_cache *c = &ctxt->decode;
2289 u16 sel, old_cs;
2290 ulong old_eip;
2291 int rc;
2292
2293 old_cs = ctxt->ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2294 old_eip = c->eip;
2295
2296 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
2297 if (load_segment_descriptor(ctxt, ctxt->ops, sel, VCPU_SREG_CS))
2298 return X86EMUL_CONTINUE;
2299
2300 c->eip = 0;
2301 memcpy(&c->eip, c->src.valptr, c->op_bytes);
2302
2303 c->src.val = old_cs;
2304 emulate_push(ctxt, ctxt->ops);
2305 rc = writeback(ctxt, ctxt->ops);
2306 if (rc != X86EMUL_CONTINUE)
2307 return rc;
2308
2309 c->src.val = old_eip;
2310 emulate_push(ctxt, ctxt->ops);
2311 rc = writeback(ctxt, ctxt->ops);
2312 if (rc != X86EMUL_CONTINUE)
2313 return rc;
2314
2315 c->dst.type = OP_NONE;
2316
2317 return X86EMUL_CONTINUE;
2318}
2319
40ece7c7
AK		 2320static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2321{
2322 struct decode_cache *c = &ctxt->decode;
2323 int rc;
2324
2325 c->dst.type = OP_REG;
2326 c->dst.addr.reg = &c->eip;
2327 c->dst.bytes = c->op_bytes;
2328 rc = emulate_pop(ctxt, ctxt->ops, &c->dst.val, c->op_bytes);
2329 if (rc != X86EMUL_CONTINUE)
2330 return rc;
2331 register_address_increment(c, &c->regs[VCPU_REGS_RSP], c->src.val);
2332 return X86EMUL_CONTINUE;
2333}
2334
5c82aa29 2335static int em_imul(struct x86_emulate_ctxt *ctxt)
f3a1b9f4
AK		 2336{
2337 struct decode_cache *c = &ctxt->decode;
2338
f3a1b9f4
AK		 2339 emulate_2op_SrcV_nobyte("imul", c->src, c->dst, ctxt->eflags);
2340 return X86EMUL_CONTINUE;
2341}
2342
5c82aa29
AK		 2343static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2344{
2345 struct decode_cache *c = &ctxt->decode;
2346
2347 c->dst.val = c->src2.val;
2348 return em_imul(ctxt);
2349}
2350
61429142
AK		 2351static int em_cwd(struct x86_emulate_ctxt *ctxt)
2352{
2353 struct decode_cache *c = &ctxt->decode;
2354
2355 c->dst.type = OP_REG;
2356 c->dst.bytes = c->src.bytes;
2357 c->dst.addr.reg = &c->regs[VCPU_REGS_RDX];
2358 c->dst.val = ~((c->src.val >> (c->src.bytes * 8 - 1)) - 1);
2359
2360 return X86EMUL_CONTINUE;
2361}
2362
48bb5d3c
AK		 2363static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2364{
2365 unsigned cpl = ctxt->ops->cpl(ctxt->vcpu);
2366 struct decode_cache *c = &ctxt->decode;
2367 u64 tsc = 0;
2368
2369 if (cpl > 0 && (ctxt->ops->get_cr(4, ctxt->vcpu) & X86_CR4_TSD)) {
2370 emulate_gp(ctxt, 0);
2371 return X86EMUL_PROPAGATE_FAULT;
2372 }
2373 ctxt->ops->get_msr(ctxt->vcpu, MSR_IA32_TSC, &tsc);
2374 c->regs[VCPU_REGS_RAX] = (u32)tsc;
2375 c->regs[VCPU_REGS_RDX] = tsc >> 32;
2376 return X86EMUL_CONTINUE;
2377}
2378
b9eac5f4
AK		 2379static int em_mov(struct x86_emulate_ctxt *ctxt)
2380{
2381 struct decode_cache *c = &ctxt->decode;
2382 c->dst.val = c->src.val;
2383 return X86EMUL_CONTINUE;
2384}
2385
73fba5f4
AK		 2386#define D(_y) { .flags = (_y) }
2387#define N D(0)
2388#define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) }
2389#define GD(_f, _g) { .flags = ((_f) | Group | GroupDual), .u.gdual = (_g) }
2390#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
2391
8d8f4e9f
AK		 2392#define D2bv(_f) D((_f) | ByteOp), D(_f)
2393#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
2394
6230f7fc
AK		 2395#define D6ALU(_f) D2bv((_f) | DstMem | SrcReg | ModRM), \
2396 D2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock), \
2397 D2bv(((_f) & ~Lock) | DstAcc | SrcImm)
2398
2399
73fba5f4
AK		 2400static struct opcode group1[] = {
2401 X7(D(Lock)), N
2402};
2403
2404static struct opcode group1A[] = {
2405 D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N,
2406};
2407
2408static struct opcode group3[] = {
2409 D(DstMem | SrcImm | ModRM), D(DstMem | SrcImm | ModRM),
2410 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
3f9f53b0 2411 X4(D(SrcMem | ModRM)),
73fba5f4
AK		 2412};
2413
2414static struct opcode group4[] = {
2415 D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock),
2416 N, N, N, N, N, N,
2417};
2418
2419static struct opcode group5[] = {
2420 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
0ef753b8
AK		 2421 D(SrcMem | ModRM | Stack),
2422 I(SrcMemFAddr | ModRM | ImplicitOps | Stack, em_call_far),
73fba5f4
AK		 2423 D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps),
2424 D(SrcMem | ModRM | Stack), N,
2425};
2426
2427static struct group_dual group7 = { {
2428 N, N, D(ModRM | SrcMem | Priv), D(ModRM | SrcMem | Priv),
2429 D(SrcNone | ModRM | DstMem | Mov), N,
5a506b12
AK		 2430 D(SrcMem16 | ModRM | Mov | Priv),
2431 D(SrcMem | ModRM | ByteOp | Priv | NoAccess),
73fba5f4
AK		 2432}, {
2433 D(SrcNone | ModRM | Priv), N, N, D(SrcNone | ModRM | Priv),
2434 D(SrcNone | ModRM | DstMem | Mov), N,
2435 D(SrcMem16 | ModRM | Mov | Priv), N,
2436} };
2437
2438static struct opcode group8[] = {
2439 N, N, N, N,
2440 D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock),
2441 D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock),
2442};
2443
2444static struct group_dual group9 = { {
2445 N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N,
2446}, {
2447 N, N, N, N, N, N, N, N,
2448} };
2449
a4d4a7c1
AK		 2450static struct opcode group11[] = {
2451 I(DstMem | SrcImm | ModRM | Mov, em_mov), X7(D(Undefined)),
2452};
2453
73fba5f4
AK		 2454static struct opcode opcode_table[256] = {
2455 /* 0x00 - 0x07 */
6230f7fc 2456 D6ALU(Lock),
73fba5f4
AK		 2457 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2458 /* 0x08 - 0x0F */
6230f7fc 2459 D6ALU(Lock),
73fba5f4
AK		 2460 D(ImplicitOps | Stack | No64), N,
2461 /* 0x10 - 0x17 */
6230f7fc 2462 D6ALU(Lock),
73fba5f4
AK		 2463 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2464 /* 0x18 - 0x1F */
6230f7fc 2465 D6ALU(Lock),
73fba5f4
AK		 2466 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2467 /* 0x20 - 0x27 */
6230f7fc 2468 D6ALU(Lock), N, N,
73fba5f4 2469 /* 0x28 - 0x2F */
6230f7fc 2470 D6ALU(Lock), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 2471 /* 0x30 - 0x37 */
6230f7fc 2472 D6ALU(Lock), N, N,
73fba5f4 2473 /* 0x38 - 0x3F */
6230f7fc 2474 D6ALU(0), N, N,
73fba5f4
AK		 2475 /* 0x40 - 0x4F */
2476 X16(D(DstReg)),
2477 /* 0x50 - 0x57 */
63540382 2478 X8(I(SrcReg | Stack, em_push)),
73fba5f4
AK		 2479 /* 0x58 - 0x5F */
2480 X8(D(DstReg | Stack)),
2481 /* 0x60 - 0x67 */
2482 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2483 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
2484 N, N, N, N,
2485 /* 0x68 - 0x6F */
d46164db
AK		 2486 I(SrcImm | Mov | Stack, em_push),
2487 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 2488 I(SrcImmByte | Mov | Stack, em_push),
2489 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
48fe67b5
AK		 2490 D2bv(DstDI | Mov | String), /* insb, insw/insd */
2491 D2bv(SrcSI | ImplicitOps | String), /* outsb, outsw/outsd */
73fba5f4
AK		 2492 /* 0x70 - 0x7F */
2493 X16(D(SrcImmByte)),
2494 /* 0x80 - 0x87 */
2495 G(ByteOp | DstMem | SrcImm | ModRM | Group, group1),
2496 G(DstMem | SrcImm | ModRM | Group, group1),
2497 G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1),
2498 G(DstMem | SrcImmByte | ModRM | Group, group1),
76e8e68d 2499 D2bv(DstMem | SrcReg | ModRM), D2bv(DstMem | SrcReg | ModRM | Lock),
73fba5f4 2500 /* 0x88 - 0x8F */
b9eac5f4
AK		 2501 I2bv(DstMem | SrcReg | ModRM | Mov, em_mov),
2502 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
342fc630 2503 D(DstMem | SrcNone | ModRM | Mov), D(ModRM | SrcMem | NoAccess | DstReg),
73fba5f4
AK		 2504 D(ImplicitOps | SrcMem16 | ModRM), G(0, group1A),
2505 /* 0x90 - 0x97 */
3d9e77df 2506 X8(D(SrcAcc | DstReg)),
73fba5f4 2507 /* 0x98 - 0x9F */
61429142 2508 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 2509 I(SrcImmFAddr | No64, em_call_far), N,
73fba5f4
AK		 2510 D(ImplicitOps | Stack), D(ImplicitOps | Stack), N, N,
2511 /* 0xA0 - 0xA7 */
b9eac5f4
AK		 2512 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
2513 I2bv(DstMem | SrcAcc | Mov | MemAbs, em_mov),
2514 I2bv(SrcSI | DstDI | Mov | String, em_mov),
2515 D2bv(SrcSI | DstDI | String),
73fba5f4 2516 /* 0xA8 - 0xAF */
50748613 2517 D2bv(DstAcc | SrcImm),
b9eac5f4
AK		 2518 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
2519 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
48fe67b5 2520 D2bv(SrcAcc | DstDI | String),
73fba5f4 2521 /* 0xB0 - 0xB7 */
b9eac5f4 2522 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 2523 /* 0xB8 - 0xBF */
b9eac5f4 2524 X8(I(DstReg | SrcImm | Mov, em_mov)),
73fba5f4 2525 /* 0xC0 - 0xC7 */
d2c6c7ad 2526 D2bv(DstMem | SrcImmByte | ModRM),
40ece7c7
AK		 2527 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
2528 D(ImplicitOps | Stack),
09b5f4d3 2529 D(DstReg | SrcMemFAddr | ModRM | No64), D(DstReg | SrcMemFAddr | ModRM | No64),
a4d4a7c1 2530 G(ByteOp, group11), G(0, group11),
73fba5f4
AK		 2531 /* 0xC8 - 0xCF */
2532 N, N, N, D(ImplicitOps | Stack),
2533 D(ImplicitOps), D(SrcImmByte), D(ImplicitOps | No64), D(ImplicitOps),
2534 /* 0xD0 - 0xD7 */
d2c6c7ad 2535 D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM),
73fba5f4
AK		 2536 N, N, N, N,
2537 /* 0xD8 - 0xDF */
2538 N, N, N, N, N, N, N, N,
2539 /* 0xE0 - 0xE7 */
e4abac67 2540 X4(D(SrcImmByte)),
d269e396 2541 D2bv(SrcImmUByte | DstAcc), D2bv(SrcAcc | DstImmUByte),
73fba5f4
AK		 2542 /* 0xE8 - 0xEF */
2543 D(SrcImm | Stack), D(SrcImm | ImplicitOps),
2544 D(SrcImmFAddr | No64), D(SrcImmByte | ImplicitOps),
d269e396 2545 D2bv(SrcNone | DstAcc), D2bv(SrcAcc | ImplicitOps),
73fba5f4
AK		 2546 /* 0xF0 - 0xF7 */
2547 N, N, N, N,
2548 D(ImplicitOps | Priv), D(ImplicitOps), G(ByteOp, group3), G(0, group3),
2549 /* 0xF8 - 0xFF */
8744aa9a 2550 D(ImplicitOps), D(ImplicitOps), D(ImplicitOps), D(ImplicitOps),
73fba5f4
AK		 2551 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
2552};
2553
2554static struct opcode twobyte_table[256] = {
2555 /* 0x00 - 0x0F */
2556 N, GD(0, &group7), N, N,
2557 N, D(ImplicitOps), D(ImplicitOps | Priv), N,
2558 D(ImplicitOps | Priv), D(ImplicitOps | Priv), N, N,
2559 N, D(ImplicitOps | ModRM), N, N,
2560 /* 0x10 - 0x1F */
2561 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
2562 /* 0x20 - 0x2F */
b27f3856
AK		 2563 D(ModRM | DstMem | Priv | Op3264), D(ModRM | DstMem | Priv | Op3264),
2564 D(ModRM | SrcMem | Priv | Op3264), D(ModRM | SrcMem | Priv | Op3264),
73fba5f4
AK		 2565 N, N, N, N,
2566 N, N, N, N, N, N, N, N,
2567 /* 0x30 - 0x3F */
48bb5d3c
AK		 2568 D(ImplicitOps | Priv), I(ImplicitOps, em_rdtsc),
2569 D(ImplicitOps | Priv), N,
73fba5f4
AK		 2570 D(ImplicitOps), D(ImplicitOps | Priv), N, N,
2571 N, N, N, N, N, N, N, N,
2572 /* 0x40 - 0x4F */
2573 X16(D(DstReg | SrcMem | ModRM | Mov)),
2574 /* 0x50 - 0x5F */
2575 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2576 /* 0x60 - 0x6F */
2577 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2578 /* 0x70 - 0x7F */
2579 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2580 /* 0x80 - 0x8F */
2581 X16(D(SrcImm)),
2582 /* 0x90 - 0x9F */
ee45b58e 2583 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4
AK		 2584 /* 0xA0 - 0xA7 */
2585 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
2586 N, D(DstMem | SrcReg | ModRM | BitOp),
2587 D(DstMem | SrcReg | Src2ImmByte | ModRM),
2588 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
2589 /* 0xA8 - 0xAF */
2590 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
2591 N, D(DstMem | SrcReg | ModRM | BitOp | Lock),
2592 D(DstMem | SrcReg | Src2ImmByte | ModRM),
2593 D(DstMem | SrcReg | Src2CL | ModRM),
5c82aa29 2594 D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 2595 /* 0xB0 - 0xB7 */
739ae406 2596 D2bv(DstMem | SrcReg | ModRM | Lock),
09b5f4d3
WY		 2597 D(DstReg | SrcMemFAddr | ModRM), D(DstMem | SrcReg | ModRM | BitOp | Lock),
2598 D(DstReg | SrcMemFAddr | ModRM), D(DstReg | SrcMemFAddr | ModRM),
2599 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 2600 /* 0xB8 - 0xBF */
2601 N, N,
ba7ff2b7 2602 G(BitOp, group8), D(DstMem | SrcReg | ModRM | BitOp | Lock),
d9574a25
WY		 2603 D(DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2604 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4 2605 /* 0xC0 - 0xCF */
739ae406 2606 D2bv(DstMem | SrcReg | ModRM | Lock),
92f738a5 2607 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4
AK		 2608 N, N, N, GD(0, &group9),
2609 N, N, N, N, N, N, N, N,
2610 /* 0xD0 - 0xDF */
2611 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2612 /* 0xE0 - 0xEF */
2613 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2614 /* 0xF0 - 0xFF */
2615 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
2616};
2617
2618#undef D
2619#undef N
2620#undef G
2621#undef GD
2622#undef I
2623
8d8f4e9f
AK		 2624#undef D2bv
2625#undef I2bv
6230f7fc 2626#undef D6ALU
8d8f4e9f 2627
39f21ee5
AK		 2628static unsigned imm_size(struct decode_cache *c)
2629{
2630 unsigned size;
2631
2632 size = (c->d & ByteOp) ? 1 : c->op_bytes;
2633 if (size == 8)
2634 size = 4;
2635 return size;
2636}
2637
2638static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
2639 unsigned size, bool sign_extension)
2640{
2641 struct decode_cache *c = &ctxt->decode;
2642 struct x86_emulate_ops *ops = ctxt->ops;
2643 int rc = X86EMUL_CONTINUE;
2644
2645 op->type = OP_IMM;
2646 op->bytes = size;
2647 op->addr.mem = c->eip;
2648 /* NB. Immediates are sign-extended as necessary. */
2649 switch (op->bytes) {
2650 case 1:
2651 op->val = insn_fetch(s8, 1, c->eip);
2652 break;
2653 case 2:
2654 op->val = insn_fetch(s16, 2, c->eip);
2655 break;
2656 case 4:
2657 op->val = insn_fetch(s32, 4, c->eip);
2658 break;
2659 }
2660 if (!sign_extension) {
2661 switch (op->bytes) {
2662 case 1:
2663 op->val &= 0xff;
2664 break;
2665 case 2:
2666 op->val &= 0xffff;
2667 break;
2668 case 4:
2669 op->val &= 0xffffffff;
2670 break;
2671 }
2672 }
2673done:
2674 return rc;
2675}
2676
dde7e6d1
AK		 2677int
2678x86_decode_insn(struct x86_emulate_ctxt *ctxt)
2679{
2680 struct x86_emulate_ops *ops = ctxt->ops;
2681 struct decode_cache *c = &ctxt->decode;
2682 int rc = X86EMUL_CONTINUE;
2683 int mode = ctxt->mode;
2684 int def_op_bytes, def_ad_bytes, dual, goffset;
2685 struct opcode opcode, *g_mod012, *g_mod3;
2dbd0dd7 2686 struct operand memop = { .type = OP_NONE };
dde7e6d1 2687
dde7e6d1
AK		 2688 c->eip = ctxt->eip;
2689 c->fetch.start = c->fetch.end = c->eip;
2690 ctxt->cs_base = seg_base(ctxt, ops, VCPU_SREG_CS);
2691
2692 switch (mode) {
2693 case X86EMUL_MODE_REAL:
2694 case X86EMUL_MODE_VM86:
2695 case X86EMUL_MODE_PROT16:
2696 def_op_bytes = def_ad_bytes = 2;
2697 break;
2698 case X86EMUL_MODE_PROT32:
2699 def_op_bytes = def_ad_bytes = 4;
2700 break;
2701#ifdef CONFIG_X86_64
2702 case X86EMUL_MODE_PROT64:
2703 def_op_bytes = 4;
2704 def_ad_bytes = 8;
2705 break;
2706#endif
2707 default:
2708 return -1;
2709 }
2710
2711 c->op_bytes = def_op_bytes;
2712 c->ad_bytes = def_ad_bytes;
2713
2714 /* Legacy prefixes. */
2715 for (;;) {
2716 switch (c->b = insn_fetch(u8, 1, c->eip)) {
2717 case 0x66: /* operand-size override */
2718 /* switch between 2/4 bytes */
2719 c->op_bytes = def_op_bytes ^ 6;
2720 break;
2721 case 0x67: /* address-size override */
2722 if (mode == X86EMUL_MODE_PROT64)
2723 /* switch between 4/8 bytes */
2724 c->ad_bytes = def_ad_bytes ^ 12;
2725 else
2726 /* switch between 2/4 bytes */
2727 c->ad_bytes = def_ad_bytes ^ 6;
2728 break;
2729 case 0x26: /* ES override */
2730 case 0x2e: /* CS override */
2731 case 0x36: /* SS override */
2732 case 0x3e: /* DS override */
2733 set_seg_override(c, (c->b >> 3) & 3);
2734 break;
2735 case 0x64: /* FS override */
2736 case 0x65: /* GS override */
2737 set_seg_override(c, c->b & 7);
2738 break;
2739 case 0x40 ... 0x4f: /* REX */
2740 if (mode != X86EMUL_MODE_PROT64)
2741 goto done_prefixes;
2742 c->rex_prefix = c->b;
2743 continue;
2744 case 0xf0: /* LOCK */
2745 c->lock_prefix = 1;
2746 break;
2747 case 0xf2: /* REPNE/REPNZ */
2748 c->rep_prefix = REPNE_PREFIX;
2749 break;
2750 case 0xf3: /* REP/REPE/REPZ */
2751 c->rep_prefix = REPE_PREFIX;
2752 break;
2753 default:
2754 goto done_prefixes;
2755 }
2756
2757 /* Any legacy prefix after a REX prefix nullifies its effect. */
2758
2759 c->rex_prefix = 0;
2760 }
2761
2762done_prefixes:
2763
2764 /* REX prefix. */
1e87e3ef
AK		 2765 if (c->rex_prefix & 8)
2766 c->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 2767
2768 /* Opcode byte(s). */
2769 opcode = opcode_table[c->b];
d3ad6243
WY		 2770 /* Two-byte opcode? */
2771 if (c->b == 0x0f) {
2772 c->twobyte = 1;
2773 c->b = insn_fetch(u8, 1, c->eip);
2774 opcode = twobyte_table[c->b];
dde7e6d1
AK		 2775 }
2776 c->d = opcode.flags;
2777
2778 if (c->d & Group) {
2779 dual = c->d & GroupDual;
2780 c->modrm = insn_fetch(u8, 1, c->eip);
2781 --c->eip;
2782
2783 if (c->d & GroupDual) {
2784 g_mod012 = opcode.u.gdual->mod012;
2785 g_mod3 = opcode.u.gdual->mod3;
2786 } else
2787 g_mod012 = g_mod3 = opcode.u.group;
2788
2789 c->d &= ~(Group | GroupDual);
2790
2791 goffset = (c->modrm >> 3) & 7;
2792
2793 if ((c->modrm >> 6) == 3)
2794 opcode = g_mod3[goffset];
2795 else
2796 opcode = g_mod012[goffset];
2797 c->d |= opcode.flags;
2798 }
2799
2800 c->execute = opcode.u.execute;
2801
2802 /* Unrecognised? */
2803 if (c->d == 0 || (c->d & Undefined)) {
2804 DPRINTF("Cannot emulate %02x\n", c->b);
2805 return -1;
2806 }
2807
2808 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
2809 c->op_bytes = 8;
2810
7f9b4b75
AK		 2811 if (c->d & Op3264) {
2812 if (mode == X86EMUL_MODE_PROT64)
2813 c->op_bytes = 8;
2814 else
2815 c->op_bytes = 4;
2816 }
2817
dde7e6d1 2818 /* ModRM and SIB bytes. */
09ee57cd 2819 if (c->d & ModRM) {
2dbd0dd7 2820 rc = decode_modrm(ctxt, ops, &memop);
09ee57cd
AK		 2821 if (!c->has_seg_override)
2822 set_seg_override(c, c->modrm_seg);
2823 } else if (c->d & MemAbs)
2dbd0dd7 2824 rc = decode_abs(ctxt, ops, &memop);
dde7e6d1
AK		 2825 if (rc != X86EMUL_CONTINUE)
2826 goto done;
2827
2828 if (!c->has_seg_override)
2829 set_seg_override(c, VCPU_SREG_DS);
2830
2dbd0dd7
AK		 2831 if (memop.type == OP_MEM && !(!c->twobyte && c->b == 0x8d))
2832 memop.addr.mem += seg_override_base(ctxt, ops, c);
dde7e6d1 2833
2dbd0dd7
AK		 2834 if (memop.type == OP_MEM && c->ad_bytes != 8)
2835 memop.addr.mem = (u32)memop.addr.mem;
dde7e6d1 2836
2dbd0dd7
AK		 2837 if (memop.type == OP_MEM && c->rip_relative)
2838 memop.addr.mem += c->eip;
dde7e6d1
AK		 2839
2840 /*
2841 * Decode and fetch the source operand: register, memory
2842 * or immediate.
2843 */
2844 switch (c->d & SrcMask) {
2845 case SrcNone:
2846 break;
2847 case SrcReg:
2848 decode_register_operand(&c->src, c, 0);
2849 break;
2850 case SrcMem16:
2dbd0dd7 2851 memop.bytes = 2;
dde7e6d1
AK		 2852 goto srcmem_common;
2853 case SrcMem32:
2dbd0dd7 2854 memop.bytes = 4;
dde7e6d1
AK		 2855 goto srcmem_common;
2856 case SrcMem:
2dbd0dd7 2857 memop.bytes = (c->d & ByteOp) ? 1 :
dde7e6d1 2858 c->op_bytes;
dde7e6d1 2859 srcmem_common:
2dbd0dd7 2860 c->src = memop;
dde7e6d1 2861 break;
b250e605 2862 case SrcImmU16:
39f21ee5
AK		 2863 rc = decode_imm(ctxt, &c->src, 2, false);
2864 break;
dde7e6d1 2865 case SrcImm:
39f21ee5
AK		 2866 rc = decode_imm(ctxt, &c->src, imm_size(c), true);
2867 break;
dde7e6d1 2868 case SrcImmU:
39f21ee5 2869 rc = decode_imm(ctxt, &c->src, imm_size(c), false);
dde7e6d1
AK		 2870 break;
2871 case SrcImmByte:
39f21ee5
AK		 2872 rc = decode_imm(ctxt, &c->src, 1, true);
2873 break;
dde7e6d1 2874 case SrcImmUByte:
39f21ee5 2875 rc = decode_imm(ctxt, &c->src, 1, false);
dde7e6d1
AK		 2876 break;
2877 case SrcAcc:
2878 c->src.type = OP_REG;
2879 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1a6440ae 2880 c->src.addr.reg = &c->regs[VCPU_REGS_RAX];
91ff3cb4 2881 fetch_register_operand(&c->src);
dde7e6d1
AK		 2882 break;
2883 case SrcOne:
2884 c->src.bytes = 1;
2885 c->src.val = 1;
2886 break;
2887 case SrcSI:
2888 c->src.type = OP_MEM;
2889 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1a6440ae 2890 c->src.addr.mem =
dde7e6d1
AK		 2891 register_address(c, seg_override_base(ctxt, ops, c),
2892 c->regs[VCPU_REGS_RSI]);
2893 c->src.val = 0;
2894 break;
2895 case SrcImmFAddr:
2896 c->src.type = OP_IMM;
1a6440ae 2897 c->src.addr.mem = c->eip;
dde7e6d1
AK		 2898 c->src.bytes = c->op_bytes + 2;
2899 insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip);
2900 break;
2901 case SrcMemFAddr:
2dbd0dd7
AK		 2902 memop.bytes = c->op_bytes + 2;
2903 goto srcmem_common;
dde7e6d1
AK		 2904 break;
2905 }
2906
39f21ee5
AK		 2907 if (rc != X86EMUL_CONTINUE)
2908 goto done;
2909
dde7e6d1
AK		 2910 /*
2911 * Decode and fetch the second source operand: register, memory
2912 * or immediate.
2913 */
2914 switch (c->d & Src2Mask) {
2915 case Src2None:
2916 break;
2917 case Src2CL:
2918 c->src2.bytes = 1;
2919 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
2920 break;
2921 case Src2ImmByte:
39f21ee5 2922 rc = decode_imm(ctxt, &c->src2, 1, true);
dde7e6d1
AK		 2923 break;
2924 case Src2One:
2925 c->src2.bytes = 1;
2926 c->src2.val = 1;
2927 break;
7db41eb7
AK		 2928 case Src2Imm:
2929 rc = decode_imm(ctxt, &c->src2, imm_size(c), true);
2930 break;
dde7e6d1
AK		 2931 }
2932
39f21ee5
AK		 2933 if (rc != X86EMUL_CONTINUE)
2934 goto done;
2935
dde7e6d1
AK		 2936 /* Decode and fetch the destination operand: register or memory. */
2937 switch (c->d & DstMask) {
dde7e6d1
AK		 2938 case DstReg:
2939 decode_register_operand(&c->dst, c,
2940 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
2941 break;
943858e2
WY		 2942 case DstImmUByte:
2943 c->dst.type = OP_IMM;
2944 c->dst.addr.mem = c->eip;
2945 c->dst.bytes = 1;
2946 c->dst.val = insn_fetch(u8, 1, c->eip);
2947 break;
dde7e6d1
AK		 2948 case DstMem:
2949 case DstMem64:
2dbd0dd7 2950 c->dst = memop;
dde7e6d1
AK		 2951 if ((c->d & DstMask) == DstMem64)
2952 c->dst.bytes = 8;
2953 else
2954 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
35c843c4
WY		 2955 if (c->d & BitOp)
2956 fetch_bit_operand(c);
2dbd0dd7 2957 c->dst.orig_val = c->dst.val;
dde7e6d1
AK		 2958 break;
2959 case DstAcc:
2960 c->dst.type = OP_REG;
2961 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1a6440ae 2962 c->dst.addr.reg = &c->regs[VCPU_REGS_RAX];
91ff3cb4 2963 fetch_register_operand(&c->dst);
dde7e6d1
AK		 2964 c->dst.orig_val = c->dst.val;
2965 break;
2966 case DstDI:
2967 c->dst.type = OP_MEM;
2968 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1a6440ae 2969 c->dst.addr.mem =
dde7e6d1
AK		 2970 register_address(c, es_base(ctxt, ops),
2971 c->regs[VCPU_REGS_RDI]);
2972 c->dst.val = 0;
2973 break;
36089fed
WY		 2974 case ImplicitOps:
2975 /* Special instructions do their own operand decoding. */
2976 default:
2977 c->dst.type = OP_NONE; /* Disable writeback. */
2978 return 0;
dde7e6d1
AK		 2979 }
2980
2981done:
2982 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
2983}
2984
3e2f65d5
GN		 2985static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
2986{
2987 struct decode_cache *c = &ctxt->decode;
2988
2989 /* The second termination condition only applies for REPE
2990 * and REPNE. Test if the repeat string operation prefix is
2991 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
2992 * corresponding termination condition according to:
2993 * - if REPE/REPZ and ZF = 0 then done
2994 * - if REPNE/REPNZ and ZF = 1 then done
2995 */
2996 if (((c->b == 0xa6) || (c->b == 0xa7) ||
2997 (c->b == 0xae) || (c->b == 0xaf))
2998 && (((c->rep_prefix == REPE_PREFIX) &&
2999 ((ctxt->eflags & EFLG_ZF) == 0))
3000 || ((c->rep_prefix == REPNE_PREFIX) &&
3001 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
3002 return true;
3003
3004 return false;
3005}
3006
8b4caf66 3007int
9aabc88f 3008x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 3009{
9aabc88f 3010 struct x86_emulate_ops *ops = ctxt->ops;
8b4caf66 3011 u64 msr_data;
8b4caf66 3012 struct decode_cache *c = &ctxt->decode;
1b30eaa8 3013 int rc = X86EMUL_CONTINUE;
5cd21917 3014 int saved_dst_type = c->dst.type;
6e154e56 3015 int irq; /* Used for int 3, int, and into */
8b4caf66 3016
9de41573 3017 ctxt->decode.mem_read.pos = 0;
310b5d30 3018
1161624f 3019 if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
54b8486f 3020 emulate_ud(ctxt);
1161624f
GN		 3021 goto done;
3022 }
3023
d380a5e4 3024 /* LOCK prefix is allowed only with some instructions */
a41ffb75 3025 if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) {
54b8486f 3026 emulate_ud(ctxt);
d380a5e4
GN		 3027 goto done;
3028 }
3029
081bca0e
AK		 3030 if ((c->d & SrcMask) == SrcMemFAddr && c->src.type != OP_MEM) {
3031 emulate_ud(ctxt);
3032 goto done;
3033 }
3034
e92805ac 3035 /* Privileged instruction can be executed only in CPL=0 */
9c537244 3036 if ((c->d & Priv) && ops->cpl(ctxt->vcpu)) {
54b8486f 3037 emulate_gp(ctxt, 0);
e92805ac
GN		 3038 goto done;
3039 }
3040
b9fa9d6b
AK		 3041 if (c->rep_prefix && (c->d & String)) {
3042 /* All REP prefixes have the same first termination condition */
c73e197b 3043 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) {
95c55886 3044 ctxt->eip = c->eip;
b9fa9d6b
AK		 3045 goto done;
3046 }
b9fa9d6b
AK		 3047 }
3048
c483c02a 3049 if ((c->src.type == OP_MEM) && !(c->d & NoAccess)) {
1a6440ae 3050 rc = read_emulated(ctxt, ops, c->src.addr.mem,
414e6277 3051 c->src.valptr, c->src.bytes);
b60d513c 3052 if (rc != X86EMUL_CONTINUE)
8b4caf66 3053 goto done;
16518d5a 3054 c->src.orig_val64 = c->src.val64;
8b4caf66
LV		 3055 }
3056
e35b7b9c 3057 if (c->src2.type == OP_MEM) {
1a6440ae 3058 rc = read_emulated(ctxt, ops, c->src2.addr.mem,
9de41573 3059 &c->src2.val, c->src2.bytes);
e35b7b9c
GN		 3060 if (rc != X86EMUL_CONTINUE)
3061 goto done;
3062 }
3063
8b4caf66
LV		 3064 if ((c->d & DstMask) == ImplicitOps)
3065 goto special_insn;
3066
3067
69f55cb1
GN		 3068 if ((c->dst.type == OP_MEM) && !(c->d & Mov)) {
3069 /* optimisation - avoid slow emulated read if Mov */
1a6440ae 3070 rc = read_emulated(ctxt, ops, c->dst.addr.mem,
9de41573 3071 &c->dst.val, c->dst.bytes);
69f55cb1
GN		 3072 if (rc != X86EMUL_CONTINUE)
3073 goto done;
038e51de 3074 }
e4e03ded 3075 c->dst.orig_val = c->dst.val;
038e51de 3076
018a98db
AK		 3077special_insn:
3078
ef65c889
AK		 3079 if (c->execute) {
3080 rc = c->execute(ctxt);
3081 if (rc != X86EMUL_CONTINUE)
3082 goto done;
3083 goto writeback;
3084 }
3085
e4e03ded 3086 if (c->twobyte)
6aa8b732
AK		 3087 goto twobyte_insn;
3088
e4e03ded 3089 switch (c->b) {
6aa8b732
AK		 3090 case 0x00 ... 0x05:
3091 add: /* add */
05f086f8 3092 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
6aa8b732 3093 break;
0934ac9d 3094 case 0x06: /* push es */
79168fd1 3095 emulate_push_sreg(ctxt, ops, VCPU_SREG_ES);
0934ac9d
MG		 3096 break;
3097 case 0x07: /* pop es */
0934ac9d 3098 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
0934ac9d 3099 break;
6aa8b732
AK		 3100 case 0x08 ... 0x0d:
3101 or: /* or */
05f086f8 3102 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
6aa8b732 3103 break;
0934ac9d 3104 case 0x0e: /* push cs */
79168fd1 3105 emulate_push_sreg(ctxt, ops, VCPU_SREG_CS);
0934ac9d 3106 break;
6aa8b732
AK		 3107 case 0x10 ... 0x15:
3108 adc: /* adc */
05f086f8 3109 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
6aa8b732 3110 break;
0934ac9d 3111 case 0x16: /* push ss */
79168fd1 3112 emulate_push_sreg(ctxt, ops, VCPU_SREG_SS);
0934ac9d
MG		 3113 break;
3114 case 0x17: /* pop ss */
0934ac9d 3115 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
0934ac9d 3116 break;
6aa8b732
AK		 3117 case 0x18 ... 0x1d:
3118 sbb: /* sbb */
05f086f8 3119 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
6aa8b732 3120 break;
0934ac9d 3121 case 0x1e: /* push ds */
79168fd1 3122 emulate_push_sreg(ctxt, ops, VCPU_SREG_DS);
0934ac9d
MG		 3123 break;
3124 case 0x1f: /* pop ds */
0934ac9d 3125 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
0934ac9d 3126 break;
aa3a816b 3127 case 0x20 ... 0x25:
6aa8b732 3128 and: /* and */
05f086f8 3129 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 3130 break;
3131 case 0x28 ... 0x2d:
3132 sub: /* sub */
05f086f8 3133 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 3134 break;
3135 case 0x30 ... 0x35:
3136 xor: /* xor */
05f086f8 3137 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 3138 break;
3139 case 0x38 ... 0x3d:
3140 cmp: /* cmp */
05f086f8 3141 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
6aa8b732 3142 break;
33615aa9
AK		 3143 case 0x40 ... 0x47: /* inc r16/r32 */
3144 emulate_1op("inc", c->dst, ctxt->eflags);
3145 break;
3146 case 0x48 ... 0x4f: /* dec r16/r32 */
3147 emulate_1op("dec", c->dst, ctxt->eflags);
3148 break;
33615aa9
AK		 3149 case 0x58 ... 0x5f: /* pop reg */
3150 pop_instruction:
350f69dc 3151 rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes);
33615aa9 3152 break;
abcf14b5 3153 case 0x60: /* pusha */
c37eda13 3154 rc = emulate_pusha(ctxt, ops);
abcf14b5
MG		 3155 break;
3156 case 0x61: /* popa */
3157 rc = emulate_popa(ctxt, ops);
abcf14b5 3158 break;
6aa8b732 3159 case 0x63: /* movsxd */
8b4caf66 3160 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 3161 goto cannot_emulate;
e4e03ded 3162 c->dst.val = (s32) c->src.val;
6aa8b732 3163 break;
018a98db
AK		 3164 case 0x6c: /* insb */
3165 case 0x6d: /* insw/insd */
a13a63fa
WY		 3166 c->src.val = c->regs[VCPU_REGS_RDX];
3167 goto do_io_in;
018a98db
AK		 3168 case 0x6e: /* outsb */
3169 case 0x6f: /* outsw/outsd */
a13a63fa
WY		 3170 c->dst.val = c->regs[VCPU_REGS_RDX];
3171 goto do_io_out;
7972995b 3172 break;
b2833e3c 3173 case 0x70 ... 0x7f: /* jcc (short) */
018a98db 3174 if (test_cc(c->b, ctxt->eflags))
b2833e3c 3175 jmp_rel(c, c->src.val);
018a98db 3176 break;
6aa8b732 3177 case 0x80 ... 0x83: /* Grp1 */
e4e03ded 3178 switch (c->modrm_reg) {
6aa8b732
AK		 3179 case 0:
3180 goto add;
3181 case 1:
3182 goto or;
3183 case 2:
3184 goto adc;
3185 case 3:
3186 goto sbb;
3187 case 4:
3188 goto and;
3189 case 5:
3190 goto sub;
3191 case 6:
3192 goto xor;
3193 case 7:
3194 goto cmp;
3195 }
3196 break;
3197 case 0x84 ... 0x85:
dfb507c4 3198 test:
05f086f8 3199 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 3200 break;
3201 case 0x86 ... 0x87: /* xchg */
b13354f8 3202 xchg:
6aa8b732 3203 /* Write back the register source. */
31be40b3
WY		 3204 c->src.val = c->dst.val;
3205 write_register_operand(&c->src);
6aa8b732
AK		 3206 /*
3207 * Write back the memory destination with implicit LOCK
3208 * prefix.
3209 */
31be40b3 3210 c->dst.val = c->src.orig_val;
e4e03ded 3211 c->lock_prefix = 1;
6aa8b732 3212 break;
79168fd1
GN		 3213 case 0x8c: /* mov r/m, sreg */
3214 if (c->modrm_reg > VCPU_SREG_GS) {
54b8486f 3215 emulate_ud(ctxt);
5e3ae6c5 3216 goto done;
38d5bc6d 3217 }
79168fd1 3218 c->dst.val = ops->get_segment_selector(c->modrm_reg, ctxt->vcpu);
38d5bc6d 3219 break;
7e0b54b1 3220 case 0x8d: /* lea r16/r32, m */
342fc630 3221 c->dst.val = c->src.addr.mem;
7e0b54b1 3222 break;
4257198a
GT		 3223 case 0x8e: { /* mov seg, r/m16 */
3224 uint16_t sel;
4257198a
GT		 3225
3226 sel = c->src.val;
8b9f4414 3227
c697518a
GN		 3228 if (c->modrm_reg == VCPU_SREG_CS ||
3229 c->modrm_reg > VCPU_SREG_GS) {
54b8486f 3230 emulate_ud(ctxt);
8b9f4414
GN		 3231 goto done;
3232 }
3233
310b5d30 3234 if (c->modrm_reg == VCPU_SREG_SS)
95cb2295 3235 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
310b5d30 3236
2e873022 3237 rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg);
4257198a
GT		 3238
3239 c->dst.type = OP_NONE; /* Disable writeback. */
3240 break;
3241 }
6aa8b732 3242 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9 3243 rc = emulate_grp1a(ctxt, ops);
6aa8b732 3244 break;
3d9e77df
AK		 3245 case 0x90 ... 0x97: /* nop / xchg reg, rax */
3246 if (c->dst.addr.reg == &c->regs[VCPU_REGS_RAX])
34698d8c 3247 break;
b13354f8 3248 goto xchg;
e8b6fa70
WY		 3249 case 0x98: /* cbw/cwde/cdqe */
3250 switch (c->op_bytes) {
3251 case 2: c->dst.val = (s8)c->dst.val; break;
3252 case 4: c->dst.val = (s16)c->dst.val; break;
3253 case 8: c->dst.val = (s32)c->dst.val; break;
3254 }
3255 break;
fd2a7608 3256 case 0x9c: /* pushf */
05f086f8 3257 c->src.val = (unsigned long) ctxt->eflags;
79168fd1 3258 emulate_push(ctxt, ops);
8cdbd2c9 3259 break;
535eabcf 3260 case 0x9d: /* popf */
2b48cc75 3261 c->dst.type = OP_REG;
1a6440ae 3262 c->dst.addr.reg = &ctxt->eflags;
2b48cc75 3263 c->dst.bytes = c->op_bytes;
d4c6a154 3264 rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes);
d4c6a154 3265 break;
6aa8b732 3266 case 0xa6 ... 0xa7: /* cmps */
d7e5117a 3267 c->dst.type = OP_NONE; /* Disable writeback. */
1a6440ae 3268 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.addr.mem, c->dst.addr.mem);
a682e354 3269 goto cmp;
dfb507c4
MG		 3270 case 0xa8 ... 0xa9: /* test ax, imm */
3271 goto test;
6aa8b732 3272 case 0xae ... 0xaf: /* scas */
f6b33fc5 3273 goto cmp;
018a98db
AK		 3274 case 0xc0 ... 0xc1:
3275 emulate_grp2(ctxt);
3276 break;
111de5d6 3277 case 0xc3: /* ret */
cf5de4f8 3278 c->dst.type = OP_REG;
1a6440ae 3279 c->dst.addr.reg = &c->eip;
cf5de4f8 3280 c->dst.bytes = c->op_bytes;
111de5d6 3281 goto pop_instruction;
09b5f4d3
WY		 3282 case 0xc4: /* les */
3283 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_ES);
09b5f4d3
WY		 3284 break;
3285 case 0xc5: /* lds */
3286 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_DS);
09b5f4d3 3287 break;
a77ab5ea
AK		 3288 case 0xcb: /* ret far */
3289 rc = emulate_ret_far(ctxt, ops);
62bd430e 3290 break;
6e154e56
MG		 3291 case 0xcc: /* int3 */
3292 irq = 3;
3293 goto do_interrupt;
3294 case 0xcd: /* int n */
3295 irq = c->src.val;
3296 do_interrupt:
3297 rc = emulate_int(ctxt, ops, irq);
6e154e56
MG		 3298 break;
3299 case 0xce: /* into */
3300 if (ctxt->eflags & EFLG_OF) {
3301 irq = 4;
3302 goto do_interrupt;
3303 }
3304 break;
62bd430e
MG		 3305 case 0xcf: /* iret */
3306 rc = emulate_iret(ctxt, ops);
a77ab5ea 3307 break;
018a98db 3308 case 0xd0 ... 0xd1: /* Grp2 */
018a98db
AK		 3309 emulate_grp2(ctxt);
3310 break;
3311 case 0xd2 ... 0xd3: /* Grp2 */
3312 c->src.val = c->regs[VCPU_REGS_RCX];
3313 emulate_grp2(ctxt);
3314 break;
f2f31845
WY		 3315 case 0xe0 ... 0xe2: /* loop/loopz/loopnz */
3316 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
3317 if (address_mask(c, c->regs[VCPU_REGS_RCX]) != 0 &&
3318 (c->b == 0xe2 || test_cc(c->b ^ 0x5, ctxt->eflags)))
3319 jmp_rel(c, c->src.val);
3320 break;
e4abac67
WY		 3321 case 0xe3: /* jcxz/jecxz/jrcxz */
3322 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0)
3323 jmp_rel(c, c->src.val);
3324 break;
a6a3034c
MG		 3325 case 0xe4: /* inb */
3326 case 0xe5: /* in */
cf8f70bf 3327 goto do_io_in;
a6a3034c
MG		 3328 case 0xe6: /* outb */
3329 case 0xe7: /* out */
cf8f70bf 3330 goto do_io_out;
1a52e051 3331 case 0xe8: /* call (near) */ {
d53c4777 3332 long int rel = c->src.val;
e4e03ded 3333 c->src.val = (unsigned long) c->eip;
7a957275 3334 jmp_rel(c, rel);
79168fd1 3335 emulate_push(ctxt, ops);
8cdbd2c9 3336 break;
1a52e051
NK		 3337 }
3338 case 0xe9: /* jmp rel */
954cd36f 3339 goto jmp;
414e6277
GN		 3340 case 0xea: { /* jmp far */
3341 unsigned short sel;
ea79849d 3342 jump_far:
414e6277
GN		 3343 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
3344
3345 if (load_segment_descriptor(ctxt, ops, sel, VCPU_SREG_CS))
c697518a 3346 goto done;
954cd36f 3347
414e6277
GN		 3348 c->eip = 0;
3349 memcpy(&c->eip, c->src.valptr, c->op_bytes);
954cd36f 3350 break;
414e6277 3351 }
954cd36f
GT		 3352 case 0xeb:
3353 jmp: /* jmp rel short */
7a957275 3354 jmp_rel(c, c->src.val);
a01af5ec 3355 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 3356 break;
a6a3034c
MG		 3357 case 0xec: /* in al,dx */
3358 case 0xed: /* in (e/r)ax,dx */
cf8f70bf
GN		 3359 c->src.val = c->regs[VCPU_REGS_RDX];
3360 do_io_in:
3361 c->dst.bytes = min(c->dst.bytes, 4u);
3362 if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) {
54b8486f 3363 emulate_gp(ctxt, 0);
cf8f70bf
GN		 3364 goto done;
3365 }
7b262e90
GN		 3366 if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val,
3367 &c->dst.val))
cf8f70bf
GN		 3368 goto done; /* IO is needed */
3369 break;
ce7a0ad3
WY		 3370 case 0xee: /* out dx,al */
3371 case 0xef: /* out dx,(e/r)ax */
41167be5 3372 c->dst.val = c->regs[VCPU_REGS_RDX];
cf8f70bf 3373 do_io_out:
41167be5
WY		 3374 c->src.bytes = min(c->src.bytes, 4u);
3375 if (!emulator_io_permited(ctxt, ops, c->dst.val,
3376 c->src.bytes)) {
54b8486f 3377 emulate_gp(ctxt, 0);
f850e2e6
GN		 3378 goto done;
3379 }
41167be5
WY		 3380 ops->pio_out_emulated(c->src.bytes, c->dst.val,
3381 &c->src.val, 1, ctxt->vcpu);
cf8f70bf 3382 c->dst.type = OP_NONE; /* Disable writeback. */
e93f36bc 3383 break;
111de5d6 3384 case 0xf4: /* hlt */
ad312c7c 3385 ctxt->vcpu->arch.halt_request = 1;
19fdfa0d 3386 break;
111de5d6
AK		 3387 case 0xf5: /* cmc */
3388 /* complement carry flag from eflags reg */
3389 ctxt->eflags ^= EFLG_CF;
111de5d6 3390 break;
018a98db 3391 case 0xf6 ... 0xf7: /* Grp3 */
34d1f490 3392 rc = emulate_grp3(ctxt, ops);
018a98db 3393 break;
111de5d6
AK		 3394 case 0xf8: /* clc */
3395 ctxt->eflags &= ~EFLG_CF;
111de5d6 3396 break;
8744aa9a
MG		 3397 case 0xf9: /* stc */
3398 ctxt->eflags |= EFLG_CF;
3399 break;
111de5d6 3400 case 0xfa: /* cli */
07cbc6c1 3401 if (emulator_bad_iopl(ctxt, ops)) {
54b8486f 3402 emulate_gp(ctxt, 0);
07cbc6c1 3403 goto done;
36089fed 3404 } else
f850e2e6 3405 ctxt->eflags &= ~X86_EFLAGS_IF;
111de5d6
AK		 3406 break;
3407 case 0xfb: /* sti */
07cbc6c1 3408 if (emulator_bad_iopl(ctxt, ops)) {
54b8486f 3409 emulate_gp(ctxt, 0);
07cbc6c1
WY		 3410 goto done;
3411 } else {
95cb2295 3412 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
f850e2e6 3413 ctxt->eflags |= X86_EFLAGS_IF;
f850e2e6 3414 }
111de5d6 3415 break;
fb4616f4
MG		 3416 case 0xfc: /* cld */
3417 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 3418 break;
3419 case 0xfd: /* std */
3420 ctxt->eflags |= EFLG_DF;
fb4616f4 3421 break;
ea79849d
GN		 3422 case 0xfe: /* Grp4 */
3423 grp45:
018a98db 3424 rc = emulate_grp45(ctxt, ops);
018a98db 3425 break;
ea79849d
GN		 3426 case 0xff: /* Grp5 */
3427 if (c->modrm_reg == 5)
3428 goto jump_far;
3429 goto grp45;
91269b8f
AK		 3430 default:
3431 goto cannot_emulate;
6aa8b732 3432 }
018a98db 3433
7d9ddaed
AK		 3434 if (rc != X86EMUL_CONTINUE)
3435 goto done;
3436
018a98db
AK		 3437writeback:
3438 rc = writeback(ctxt, ops);
1b30eaa8 3439 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 3440 goto done;
3441
5cd21917
GN		 3442 /*
3443 * restore dst type in case the decoding will be reused
3444 * (happens for string instruction )
3445 */
3446 c->dst.type = saved_dst_type;
3447
a682e354 3448 if ((c->d & SrcMask) == SrcSI)
79168fd1
GN		 3449 string_addr_inc(ctxt, seg_override_base(ctxt, ops, c),
3450 VCPU_REGS_RSI, &c->src);
a682e354
GN		 3451
3452 if ((c->d & DstMask) == DstDI)
79168fd1
GN		 3453 string_addr_inc(ctxt, es_base(ctxt, ops), VCPU_REGS_RDI,
3454 &c->dst);
d9271123 3455
5cd21917 3456 if (c->rep_prefix && (c->d & String)) {
6e2fb2ca 3457 struct read_cache *r = &ctxt->decode.io_read;
d9271123 3458 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
3e2f65d5 3459
d2ddd1c4
GN		 3460 if (!string_insn_completed(ctxt)) {
3461 /*
3462 * Re-enter guest when pio read ahead buffer is empty
3463 * or, if it is not used, after each 1024 iteration.
3464 */
3465 if ((r->end != 0 || c->regs[VCPU_REGS_RCX] & 0x3ff) &&
3466 (r->end == 0 || r->end != r->pos)) {
3467 /*
3468 * Reset read cache. Usually happens before
3469 * decode, but since instruction is restarted
3470 * we have to do it here.
3471 */
3472 ctxt->decode.mem_read.end = 0;
3473 return EMULATION_RESTART;
3474 }
3475 goto done; /* skip rip writeback */
0fa6ccbd 3476 }
5cd21917 3477 }
d2ddd1c4
GN		 3478
3479 ctxt->eip = c->eip;
018a98db
AK		 3480
3481done:
d2ddd1c4 3482 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 3483
3484twobyte_insn:
e4e03ded 3485 switch (c->b) {
6aa8b732 3486 case 0x01: /* lgdt, lidt, lmsw */
e4e03ded 3487 switch (c->modrm_reg) {
6aa8b732
AK		 3488 u16 size;
3489 unsigned long address;
3490
aca7f966 3491 case 0: /* vmcall */
e4e03ded 3492 if (c->modrm_mod != 3 || c->modrm_rm != 1)
aca7f966
AL		 3493 goto cannot_emulate;
3494
7aa81cc0 3495 rc = kvm_fix_hypercall(ctxt->vcpu);
1b30eaa8 3496 if (rc != X86EMUL_CONTINUE)
7aa81cc0
AL		 3497 goto done;
3498
33e3885d 3499 /* Let the processor re-execute the fixed hypercall */
063db061 3500 c->eip = ctxt->eip;
16286d08
AK		 3501 /* Disable writeback. */
3502 c->dst.type = OP_NONE;
aca7f966 3503 break;
6aa8b732 3504 case 2: /* lgdt */
1a6440ae 3505 rc = read_descriptor(ctxt, ops, c->src.addr.mem,
e4e03ded 3506 &size, &address, c->op_bytes);
1b30eaa8 3507 if (rc != X86EMUL_CONTINUE)
6aa8b732
AK		 3508 goto done;
3509 realmode_lgdt(ctxt->vcpu, size, address);
16286d08
AK		 3510 /* Disable writeback. */
3511 c->dst.type = OP_NONE;
6aa8b732 3512 break;
aca7f966 3513 case 3: /* lidt/vmmcall */
2b3d2a20
AK		 3514 if (c->modrm_mod == 3) {
3515 switch (c->modrm_rm) {
3516 case 1:
3517 rc = kvm_fix_hypercall(ctxt->vcpu);
2b3d2a20
AK		 3518 break;
3519 default:
3520 goto cannot_emulate;
3521 }
aca7f966 3522 } else {
1a6440ae 3523 rc = read_descriptor(ctxt, ops, c->src.addr.mem,
aca7f966 3524 &size, &address,
e4e03ded 3525 c->op_bytes);
1b30eaa8 3526 if (rc != X86EMUL_CONTINUE)
aca7f966
AL		 3527 goto done;
3528 realmode_lidt(ctxt->vcpu, size, address);
3529 }
16286d08
AK		 3530 /* Disable writeback. */
3531 c->dst.type = OP_NONE;
6aa8b732
AK		 3532 break;
3533 case 4: /* smsw */
16286d08 3534 c->dst.bytes = 2;
52a46617 3535 c->dst.val = ops->get_cr(0, ctxt->vcpu);
6aa8b732
AK		 3536 break;
3537 case 6: /* lmsw */
9928ff60 3538 ops->set_cr(0, (ops->get_cr(0, ctxt->vcpu) & ~0x0eul) |
93a152be 3539 (c->src.val & 0x0f), ctxt->vcpu);
dc7457ea 3540 c->dst.type = OP_NONE;
6aa8b732 3541 break;
6e1e5ffe 3542 case 5: /* not defined */
54b8486f 3543 emulate_ud(ctxt);
6e1e5ffe 3544 goto done;
6aa8b732 3545 case 7: /* invlpg*/
1f6f0580 3546 emulate_invlpg(ctxt->vcpu, c->src.addr.mem);
16286d08
AK		 3547 /* Disable writeback. */
3548 c->dst.type = OP_NONE;
6aa8b732
AK		 3549 break;
3550 default:
3551 goto cannot_emulate;
3552 }
3553 break;
e99f0507 3554 case 0x05: /* syscall */
3fb1b5db 3555 rc = emulate_syscall(ctxt, ops);
e99f0507 3556 break;
018a98db
AK		 3557 case 0x06:
3558 emulate_clts(ctxt->vcpu);
018a98db 3559 break;
018a98db 3560 case 0x09: /* wbinvd */
f5f48ee1 3561 kvm_emulate_wbinvd(ctxt->vcpu);
f5f48ee1
SY		 3562 break;
3563 case 0x08: /* invd */
018a98db
AK		 3564 case 0x0d: /* GrpP (prefetch) */
3565 case 0x18: /* Grp16 (prefetch/nop) */
018a98db
AK		 3566 break;
3567 case 0x20: /* mov cr, reg */
6aebfa6e
GN		 3568 switch (c->modrm_reg) {
3569 case 1:
3570 case 5 ... 7:
3571 case 9 ... 15:
54b8486f 3572 emulate_ud(ctxt);
6aebfa6e
GN		 3573 goto done;
3574 }
1a0c7d44 3575 c->dst.val = ops->get_cr(c->modrm_reg, ctxt->vcpu);
018a98db 3576 break;
6aa8b732 3577 case 0x21: /* mov from dr to reg */
1e470be5
GN		 3578 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3579 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
54b8486f 3580 emulate_ud(ctxt);
1e470be5
GN		 3581 goto done;
3582 }
b27f3856 3583 ops->get_dr(c->modrm_reg, &c->dst.val, ctxt->vcpu);
6aa8b732 3584 break;
018a98db 3585 case 0x22: /* mov reg, cr */
1a0c7d44 3586 if (ops->set_cr(c->modrm_reg, c->src.val, ctxt->vcpu)) {
54b8486f 3587 emulate_gp(ctxt, 0);
0f12244f
GN		 3588 goto done;
3589 }
018a98db
AK		 3590 c->dst.type = OP_NONE;
3591 break;
6aa8b732 3592 case 0x23: /* mov from reg to dr */
1e470be5
GN		 3593 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3594 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
54b8486f 3595 emulate_ud(ctxt);
1e470be5
GN		 3596 goto done;
3597 }
35aa5375 3598
b27f3856 3599 if (ops->set_dr(c->modrm_reg, c->src.val &
338dbc97
GN		 3600 ((ctxt->mode == X86EMUL_MODE_PROT64) ?
3601 ~0ULL : ~0U), ctxt->vcpu) < 0) {
3602 /* #UD condition is already handled by the code above */
54b8486f 3603 emulate_gp(ctxt, 0);
338dbc97
GN		 3604 goto done;
3605 }
3606
a01af5ec 3607 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3608 break;
018a98db
AK		 3609 case 0x30:
3610 /* wrmsr */
3611 msr_data = (u32)c->regs[VCPU_REGS_RAX]
3612 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
3fb1b5db 3613 if (ops->set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data)) {
54b8486f 3614 emulate_gp(ctxt, 0);
fd525365 3615 goto done;
018a98db
AK		 3616 }
3617 rc = X86EMUL_CONTINUE;
018a98db
AK		 3618 break;
3619 case 0x32:
3620 /* rdmsr */
3fb1b5db 3621 if (ops->get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data)) {
54b8486f 3622 emulate_gp(ctxt, 0);
fd525365 3623 goto done;
018a98db
AK		 3624 } else {
3625 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
3626 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
3627 }
3628 rc = X86EMUL_CONTINUE;
018a98db 3629 break;
e99f0507 3630 case 0x34: /* sysenter */
3fb1b5db 3631 rc = emulate_sysenter(ctxt, ops);
e99f0507
AP		 3632 break;
3633 case 0x35: /* sysexit */
3fb1b5db 3634 rc = emulate_sysexit(ctxt, ops);
e99f0507 3635 break;
6aa8b732 3636 case 0x40 ... 0x4f: /* cmov */
e4e03ded 3637 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 3638 if (!test_cc(c->b, ctxt->eflags))
3639 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3640 break;
b2833e3c 3641 case 0x80 ... 0x8f: /* jnz rel, etc*/
018a98db 3642 if (test_cc(c->b, ctxt->eflags))
b2833e3c 3643 jmp_rel(c, c->src.val);
018a98db 3644 break;
ee45b58e
WY		 3645 case 0x90 ... 0x9f: /* setcc r/m8 */
3646 c->dst.val = test_cc(c->b, ctxt->eflags);
3647 break;
0934ac9d 3648 case 0xa0: /* push fs */
79168fd1 3649 emulate_push_sreg(ctxt, ops, VCPU_SREG_FS);
0934ac9d
MG		 3650 break;
3651 case 0xa1: /* pop fs */
3652 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
0934ac9d 3653 break;
7de75248
NK		 3654 case 0xa3:
3655 bt: /* bt */
e4f8e039 3656 c->dst.type = OP_NONE;
e4e03ded
LV		 3657 /* only subword offset */
3658 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3659 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248 3660 break;
9bf8ea42
GT		 3661 case 0xa4: /* shld imm8, r, r/m */
3662 case 0xa5: /* shld cl, r, r/m */
3663 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
3664 break;
0934ac9d 3665 case 0xa8: /* push gs */
79168fd1 3666 emulate_push_sreg(ctxt, ops, VCPU_SREG_GS);
0934ac9d
MG		 3667 break;
3668 case 0xa9: /* pop gs */
3669 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
0934ac9d 3670 break;
7de75248
NK		 3671 case 0xab:
3672 bts: /* bts */
05f086f8 3673 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 3674 break;
9bf8ea42
GT		 3675 case 0xac: /* shrd imm8, r, r/m */
3676 case 0xad: /* shrd cl, r, r/m */
3677 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
3678 break;
2a7c5b8b
GC		 3679 case 0xae: /* clflush */
3680 break;
6aa8b732
AK		 3681 case 0xb0 ... 0xb1: /* cmpxchg */
3682 /*
3683 * Save real source value, then compare EAX against
3684 * destination.
3685 */
e4e03ded
LV		 3686 c->src.orig_val = c->src.val;
3687 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 3688 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
3689 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 3690 /* Success: write back to memory. */
e4e03ded 3691 c->dst.val = c->src.orig_val;
6aa8b732
AK		 3692 } else {
3693 /* Failure: write the value we saw to EAX. */
e4e03ded 3694 c->dst.type = OP_REG;
1a6440ae 3695 c->dst.addr.reg = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 3696 }
3697 break;
09b5f4d3
WY		 3698 case 0xb2: /* lss */
3699 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_SS);
09b5f4d3 3700 break;
6aa8b732
AK		 3701 case 0xb3:
3702 btr: /* btr */
05f086f8 3703 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 3704 break;
09b5f4d3
WY		 3705 case 0xb4: /* lfs */
3706 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_FS);
09b5f4d3
WY		 3707 break;
3708 case 0xb5: /* lgs */
3709 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_GS);
09b5f4d3 3710 break;
6aa8b732 3711 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 3712 c->dst.bytes = c->op_bytes;
3713 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
3714 : (u16) c->src.val;
6aa8b732 3715 break;
6aa8b732 3716 case 0xba: /* Grp8 */
e4e03ded 3717 switch (c->modrm_reg & 3) {
6aa8b732
AK		 3718 case 0:
3719 goto bt;
3720 case 1:
3721 goto bts;
3722 case 2:
3723 goto btr;
3724 case 3:
3725 goto btc;
3726 }
3727 break;
7de75248
NK		 3728 case 0xbb:
3729 btc: /* btc */
05f086f8 3730 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 3731 break;
d9574a25
WY		 3732 case 0xbc: { /* bsf */
3733 u8 zf;
3734 __asm__ ("bsf %2, %0; setz %1"
3735 : "=r"(c->dst.val), "=q"(zf)
3736 : "r"(c->src.val));
3737 ctxt->eflags &= ~X86_EFLAGS_ZF;
3738 if (zf) {
3739 ctxt->eflags |= X86_EFLAGS_ZF;
3740 c->dst.type = OP_NONE; /* Disable writeback. */
3741 }
3742 break;
3743 }
3744 case 0xbd: { /* bsr */
3745 u8 zf;
3746 __asm__ ("bsr %2, %0; setz %1"
3747 : "=r"(c->dst.val), "=q"(zf)
3748 : "r"(c->src.val));
3749 ctxt->eflags &= ~X86_EFLAGS_ZF;
3750 if (zf) {
3751 ctxt->eflags |= X86_EFLAGS_ZF;
3752 c->dst.type = OP_NONE; /* Disable writeback. */
3753 }
3754 break;
3755 }
6aa8b732 3756 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 3757 c->dst.bytes = c->op_bytes;
3758 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
3759 (s16) c->src.val;
6aa8b732 3760 break;
92f738a5
WY		 3761 case 0xc0 ... 0xc1: /* xadd */
3762 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
3763 /* Write back the register source. */
3764 c->src.val = c->dst.orig_val;
3765 write_register_operand(&c->src);
3766 break;
a012e65a 3767 case 0xc3: /* movnti */
e4e03ded
LV		 3768 c->dst.bytes = c->op_bytes;
3769 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
3770 (u64) c->src.val;
a012e65a 3771 break;
6aa8b732 3772 case 0xc7: /* Grp9 (cmpxchg8b) */
69f55cb1 3773 rc = emulate_grp9(ctxt, ops);
8cdbd2c9 3774 break;
91269b8f
AK		 3775 default:
3776 goto cannot_emulate;
6aa8b732 3777 }
7d9ddaed
AK		 3778
3779 if (rc != X86EMUL_CONTINUE)
3780 goto done;
3781
6aa8b732
AK		 3782 goto writeback;
3783
3784cannot_emulate:
e4e03ded 3785 DPRINTF("Cannot emulate %02x\n", c->b);
6aa8b732
AK		 3786 return -1;
3787}
Linux 6.x block layer and io_uring tree(s)