projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
KVM: x86 emulator: Don't force #UD for 0F 01 /5
[linux-2.6-block.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
6aa8b732 27
3eeb3288 28#include "x86.h"
38ba30ba 29#include "tss.h"
e99f0507 30
6aa8b732
AK		 31/*
32 * Opcode effective-address decode tables.
33 * Note that we only emulate instructions that have at least one memory
34 * operand (excluding implicit stack references). We assume that stack
35 * references and instruction fetches will never occur in special memory
36 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
37 * not be handled.
38 */
39
40/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 41#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 42/* Destination operand type. */
ab85b12b
AK		 43#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
44#define DstReg (2<<1) /* Register operand. */
45#define DstMem (3<<1) /* Memory operand. */
46#define DstAcc (4<<1) /* Destination Accumulator */
47#define DstDI (5<<1) /* Destination is in ES:(E)DI */
48#define DstMem64 (6<<1) /* 64bit memory operand */
943858e2 49#define DstImmUByte (7<<1) /* 8-bit unsigned immediate operand */
ab85b12b 50#define DstMask (7<<1)
6aa8b732 51/* Source operand type. */
9c9fddd0 52#define SrcNone (0<<4) /* No source operand. */
9c9fddd0
GT		 53#define SrcReg (1<<4) /* Register operand. */
54#define SrcMem (2<<4) /* Memory operand. */
55#define SrcMem16 (3<<4) /* Memory operand (16-bit). */
56#define SrcMem32 (4<<4) /* Memory operand (32-bit). */
57#define SrcImm (5<<4) /* Immediate operand. */
58#define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
bfcadf83 59#define SrcOne (7<<4) /* Implied '1' */
341de7e3 60#define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
c9eaf20f 61#define SrcImmU (9<<4) /* Immediate operand, unsigned */
a682e354 62#define SrcSI (0xa<<4) /* Source is in the DS:RSI */
414e6277
GN		 63#define SrcImmFAddr (0xb<<4) /* Source is immediate far address */
64#define SrcMemFAddr (0xc<<4) /* Source is far address in memory */
5d55f299 65#define SrcAcc (0xd<<4) /* Source Accumulator */
b250e605 66#define SrcImmU16 (0xe<<4) /* Immediate operand, unsigned, 16 bits */
341de7e3 67#define SrcMask (0xf<<4)
6aa8b732 68/* Generic ModRM decode. */
341de7e3 69#define ModRM (1<<8)
6aa8b732 70/* Destination is only written; never read. */
341de7e3
GN		 71#define Mov (1<<9)
72#define BitOp (1<<10)
73#define MemAbs (1<<11) /* Memory operand is absolute displacement */
9c9fddd0
GT		 74#define String (1<<12) /* String instruction (rep capable) */
75#define Stack (1<<13) /* Stack instruction (push/pop) */
e09d082c
AK		 76#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
77#define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
0d7cdee8 78#define Prefix (1<<16) /* Instruction varies with 66/f2/f3 prefix */
1253791d 79#define Sse (1<<17) /* SSE Vector instruction */
01de8b09 80#define RMExt (1<<18) /* Opcode extension in ModRM r/m if mod == 3 */
d8769fed 81/* Misc flags */
8ea7d6ae 82#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
d867162c 83#define VendorSpecific (1<<22) /* Vendor specific instruction */
5a506b12 84#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 85#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 86#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 87#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 88#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 89#define No64 (1<<28)
0dc8d10f
GT		 90/* Source 2 operand type */
91#define Src2None (0<<29)
92#define Src2CL (1<<29)
93#define Src2ImmByte (2<<29)
94#define Src2One (3<<29)
7db41eb7 95#define Src2Imm (4<<29)
0dc8d10f 96#define Src2Mask (7<<29)
6aa8b732 97
d0e53325
AK		 98#define X2(x...) x, x
99#define X3(x...) X2(x), x
100#define X4(x...) X2(x), X2(x)
101#define X5(x...) X4(x), x
102#define X6(x...) X4(x), X2(x)
103#define X7(x...) X4(x), X3(x)
104#define X8(x...) X4(x), X4(x)
105#define X16(x...) X8(x), X8(x)
83babbca 106
d65b1dee
AK		 107struct opcode {
108 u32 flags;
c4f035c6 109 u8 intercept;
120df890 110 union {
ef65c889 111 int (*execute)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 112 struct opcode *group;
113 struct group_dual *gdual;
0d7cdee8 114 struct gprefix *gprefix;
120df890 115 } u;
d09beabd 116 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 117};
118
119struct group_dual {
120 struct opcode mod012[8];
121 struct opcode mod3[8];
d65b1dee
AK		 122};
123
0d7cdee8
AK		 124struct gprefix {
125 struct opcode pfx_no;
126 struct opcode pfx_66;
127 struct opcode pfx_f2;
128 struct opcode pfx_f3;
129};
130
6aa8b732 131/* EFLAGS bit definitions. */
d4c6a154
GN		 132#define EFLG_ID (1<<21)
133#define EFLG_VIP (1<<20)
134#define EFLG_VIF (1<<19)
135#define EFLG_AC (1<<18)
b1d86143
AP		 136#define EFLG_VM (1<<17)
137#define EFLG_RF (1<<16)
d4c6a154
GN		 138#define EFLG_IOPL (3<<12)
139#define EFLG_NT (1<<14)
6aa8b732
AK		 140#define EFLG_OF (1<<11)
141#define EFLG_DF (1<<10)
b1d86143 142#define EFLG_IF (1<<9)
d4c6a154 143#define EFLG_TF (1<<8)
6aa8b732
AK		 144#define EFLG_SF (1<<7)
145#define EFLG_ZF (1<<6)
146#define EFLG_AF (1<<4)
147#define EFLG_PF (1<<2)
148#define EFLG_CF (1<<0)
149
62bd430e
MG		 150#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
151#define EFLG_RESERVED_ONE_MASK 2
152
6aa8b732
AK		 153/*
154 * Instruction emulation:
155 * Most instructions are emulated directly via a fragment of inline assembly
156 * code. This allows us to save/restore EFLAGS and thus very easily pick up
157 * any modified flags.
158 */
159
05b3e0c2 160#if defined(CONFIG_X86_64)
6aa8b732
AK		 161#define _LO32 "k" /* force 32-bit operand */
162#define _STK "%%rsp" /* stack pointer */
163#elif defined(__i386__)
164#define _LO32 "" /* force 32-bit operand */
165#define _STK "%%esp" /* stack pointer */
166#endif
167
168/*
169 * These EFLAGS bits are restored from saved value during emulation, and
170 * any changes are written back to the saved value after emulation.
171 */
172#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
173
174/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 175#define _PRE_EFLAGS(_sav, _msk, _tmp) \
176 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
177 "movl %"_sav",%"_LO32 _tmp"; " \
178 "push %"_tmp"; " \
179 "push %"_tmp"; " \
180 "movl %"_msk",%"_LO32 _tmp"; " \
181 "andl %"_LO32 _tmp",("_STK"); " \
182 "pushf; " \
183 "notl %"_LO32 _tmp"; " \
184 "andl %"_LO32 _tmp",("_STK"); " \
185 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
186 "pop %"_tmp"; " \
187 "orl %"_LO32 _tmp",("_STK"); " \
188 "popf; " \
189 "pop %"_sav"; "
6aa8b732
AK		 190
191/* After executing instruction: write-back necessary bits in EFLAGS. */
192#define _POST_EFLAGS(_sav, _msk, _tmp) \
193 /* _sav |= EFLAGS & _msk; */ \
194 "pushf; " \
195 "pop %"_tmp"; " \
196 "andl %"_msk",%"_LO32 _tmp"; " \
197 "orl %"_LO32 _tmp",%"_sav"; "
198
dda96d8f
AK		 199#ifdef CONFIG_X86_64
200#define ON64(x) x
201#else
202#define ON64(x)
203#endif
204
b3b3d25a 205#define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix, _dsttype) \
6b7ad61f
AK		 206 do { \
207 __asm__ __volatile__ ( \
208 _PRE_EFLAGS("0", "4", "2") \
209 _op _suffix " %"_x"3,%1; " \
210 _POST_EFLAGS("0", "4", "2") \
fb2c2641 211 : "=m" (_eflags), "+q" (*(_dsttype*)&(_dst).val),\
6b7ad61f
AK		 212 "=&r" (_tmp) \
213 : _y ((_src).val), "i" (EFLAGS_MASK)); \
f3fd92fb 214 } while (0)
6b7ad61f
AK		 215
216
6aa8b732
AK		 217/* Raw emulation: instruction has two explicit operands. */
218#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 219 do { \
220 unsigned long _tmp; \
221 \
222 switch ((_dst).bytes) { \
223 case 2: \
b3b3d25a 224 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w",u16);\
6b7ad61f
AK		 225 break; \
226 case 4: \
b3b3d25a 227 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l",u32);\
6b7ad61f
AK		 228 break; \
229 case 8: \
b3b3d25a 230 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q",u64)); \
6b7ad61f
AK		 231 break; \
232 } \
6aa8b732
AK		 233 } while (0)
234
235#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
236 do { \
6b7ad61f 237 unsigned long _tmp; \
d77c26fc 238 switch ((_dst).bytes) { \
6aa8b732 239 case 1: \
b3b3d25a 240 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b",u8); \
6aa8b732
AK		 241 break; \
242 default: \
243 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
244 _wx, _wy, _lx, _ly, _qx, _qy); \
245 break; \
246 } \
247 } while (0)
248
249/* Source operand is byte-sized and may be restricted to just %cl. */
250#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
251 __emulate_2op(_op, _src, _dst, _eflags, \
252 "b", "c", "b", "c", "b", "c", "b", "c")
253
254/* Source operand is byte, word, long or quad sized. */
255#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
256 __emulate_2op(_op, _src, _dst, _eflags, \
257 "b", "q", "w", "r", _LO32, "r", "", "r")
258
259/* Source operand is word, long or quad sized. */
260#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
261 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
262 "w", "r", _LO32, "r", "", "r")
263
d175226a 264/* Instruction has three operands and one operand is stored in ECX register */
7295261c
AK		 265#define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
266 do { \
267 unsigned long _tmp; \
268 _type _clv = (_cl).val; \
269 _type _srcv = (_src).val; \
270 _type _dstv = (_dst).val; \
271 \
272 __asm__ __volatile__ ( \
273 _PRE_EFLAGS("0", "5", "2") \
274 _op _suffix " %4,%1 \n" \
275 _POST_EFLAGS("0", "5", "2") \
276 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
277 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
278 ); \
279 \
280 (_cl).val = (unsigned long) _clv; \
281 (_src).val = (unsigned long) _srcv; \
282 (_dst).val = (unsigned long) _dstv; \
d175226a
GT		 283 } while (0)
284
7295261c
AK		 285#define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
286 do { \
287 switch ((_dst).bytes) { \
288 case 2: \
289 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
290 "w", unsigned short); \
291 break; \
292 case 4: \
293 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
294 "l", unsigned int); \
295 break; \
296 case 8: \
297 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
298 "q", unsigned long)); \
299 break; \
300 } \
d175226a
GT		 301 } while (0)
302
dda96d8f 303#define __emulate_1op(_op, _dst, _eflags, _suffix) \
6aa8b732
AK		 304 do { \
305 unsigned long _tmp; \
306 \
dda96d8f
AK		 307 __asm__ __volatile__ ( \
308 _PRE_EFLAGS("0", "3", "2") \
309 _op _suffix " %1; " \
310 _POST_EFLAGS("0", "3", "2") \
311 : "=m" (_eflags), "+m" ((_dst).val), \
312 "=&r" (_tmp) \
313 : "i" (EFLAGS_MASK)); \
314 } while (0)
315
316/* Instruction has only one explicit operand (no source operand). */
317#define emulate_1op(_op, _dst, _eflags) \
318 do { \
d77c26fc 319 switch ((_dst).bytes) { \
dda96d8f
AK		 320 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
321 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
322 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
323 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
6aa8b732
AK		 324 } \
325 } while (0)
326
3f9f53b0
MG		 327#define __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, _suffix) \
328 do { \
329 unsigned long _tmp; \
330 \
331 __asm__ __volatile__ ( \
332 _PRE_EFLAGS("0", "4", "1") \
333 _op _suffix " %5; " \
334 _POST_EFLAGS("0", "4", "1") \
335 : "=m" (_eflags), "=&r" (_tmp), \
336 "+a" (_rax), "+d" (_rdx) \
337 : "i" (EFLAGS_MASK), "m" ((_src).val), \
338 "a" (_rax), "d" (_rdx)); \
339 } while (0)
340
f6b3597b
AK		 341#define __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _suffix, _ex) \
342 do { \
343 unsigned long _tmp; \
344 \
345 __asm__ __volatile__ ( \
346 _PRE_EFLAGS("0", "5", "1") \
347 "1: \n\t" \
348 _op _suffix " %6; " \
349 "2: \n\t" \
350 _POST_EFLAGS("0", "5", "1") \
351 ".pushsection .fixup,\"ax\" \n\t" \
352 "3: movb $1, %4 \n\t" \
353 "jmp 2b \n\t" \
354 ".popsection \n\t" \
355 _ASM_EXTABLE(1b, 3b) \
356 : "=m" (_eflags), "=&r" (_tmp), \
357 "+a" (_rax), "+d" (_rdx), "+qm"(_ex) \
358 : "i" (EFLAGS_MASK), "m" ((_src).val), \
359 "a" (_rax), "d" (_rdx)); \
360 } while (0)
361
3f9f53b0 362/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
7295261c
AK		 363#define emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags) \
364 do { \
365 switch((_src).bytes) { \
366 case 1: \
367 __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, \
368 _eflags, "b"); \
369 break; \
370 case 2: \
371 __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, \
372 _eflags, "w"); \
373 break; \
374 case 4: \
375 __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, \
376 _eflags, "l"); \
377 break; \
378 case 8: \
379 ON64(__emulate_1op_rax_rdx(_op, _src, _rax, _rdx, \
380 _eflags, "q")); \
381 break; \
3f9f53b0
MG		 382 } \
383 } while (0)
384
f6b3597b
AK		 385#define emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _ex) \
386 do { \
387 switch((_src).bytes) { \
388 case 1: \
389 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
390 _eflags, "b", _ex); \
391 break; \
392 case 2: \
393 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
394 _eflags, "w", _ex); \
395 break; \
396 case 4: \
397 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
398 _eflags, "l", _ex); \
399 break; \
400 case 8: ON64( \
401 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
402 _eflags, "q", _ex)); \
403 break; \
404 } \
405 } while (0)
406
6aa8b732
AK		 407/* Fetch next part of the instruction being emulated. */
408#define insn_fetch(_type, _size, _eip) \
409({ unsigned long _x; \
62266869 410 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
af5b4f7f 411 if (rc != X86EMUL_CONTINUE) \
6aa8b732
AK		 412 goto done; \
413 (_eip) += (_size); \
414 (_type)_x; \
415})
416
7295261c 417#define insn_fetch_arr(_arr, _size, _eip) \
414e6277
GN		 418({ rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size)); \
419 if (rc != X86EMUL_CONTINUE) \
420 goto done; \
421 (_eip) += (_size); \
422})
423
8a76d7f2
JR		 424static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
425 enum x86_intercept intercept,
426 enum x86_intercept_stage stage)
427{
428 struct x86_instruction_info info = {
429 .intercept = intercept,
430 .rep_prefix = ctxt->decode.rep_prefix,
431 .modrm_mod = ctxt->decode.modrm_mod,
432 .modrm_reg = ctxt->decode.modrm_reg,
433 .modrm_rm = ctxt->decode.modrm_rm,
434 .src_val = ctxt->decode.src.val64,
435 .src_bytes = ctxt->decode.src.bytes,
436 .dst_bytes = ctxt->decode.dst.bytes,
437 .ad_bytes = ctxt->decode.ad_bytes,
438 .next_rip = ctxt->eip,
439 };
440
2953538e 441 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 442}
443
ddcb2885
HH		 444static inline unsigned long ad_mask(struct decode_cache *c)
445{
446 return (1UL << (c->ad_bytes << 3)) - 1;
447}
448
6aa8b732 449/* Access/update address held in a register, based on addressing mode. */
e4706772
HH		 450static inline unsigned long
451address_mask(struct decode_cache *c, unsigned long reg)
452{
453 if (c->ad_bytes == sizeof(unsigned long))
454 return reg;
455 else
456 return reg & ad_mask(c);
457}
458
459static inline unsigned long
90de84f5 460register_address(struct decode_cache *c, unsigned long reg)
e4706772 461{
90de84f5 462 return address_mask(c, reg);
e4706772
HH		 463}
464
7a957275
HH		 465static inline void
466register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
467{
468 if (c->ad_bytes == sizeof(unsigned long))
469 *reg += inc;
470 else
471 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
472}
6aa8b732 473
7a957275
HH		 474static inline void jmp_rel(struct decode_cache *c, int rel)
475{
476 register_address_increment(c, &c->eip, rel);
477}
098c937b 478
56697687
AK		 479static u32 desc_limit_scaled(struct desc_struct *desc)
480{
481 u32 limit = get_desc_limit(desc);
482
483 return desc->g ? (limit << 12) | 0xfff : limit;
484}
485
7a5b56df
AK		 486static void set_seg_override(struct decode_cache *c, int seg)
487{
488 c->has_seg_override = true;
489 c->seg_override = seg;
490}
491
79168fd1
GN		 492static unsigned long seg_base(struct x86_emulate_ctxt *ctxt,
493 struct x86_emulate_ops *ops, int seg)
7a5b56df
AK		 494{
495 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
496 return 0;
497
4bff1e86 498 return ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 499}
500
90de84f5
AK		 501static unsigned seg_override(struct x86_emulate_ctxt *ctxt,
502 struct x86_emulate_ops *ops,
503 struct decode_cache *c)
7a5b56df
AK		 504{
505 if (!c->has_seg_override)
506 return 0;
507
90de84f5 508 return c->seg_override;
7a5b56df
AK		 509}
510
35d3d4a1
AK		 511static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
512 u32 error, bool valid)
54b8486f 513{
da9cb575
AK		 514 ctxt->exception.vector = vec;
515 ctxt->exception.error_code = error;
516 ctxt->exception.error_code_valid = valid;
35d3d4a1 517 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 518}
519
3b88e41a
JR		 520static int emulate_db(struct x86_emulate_ctxt *ctxt)
521{
522 return emulate_exception(ctxt, DB_VECTOR, 0, false);
523}
524
35d3d4a1 525static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 526{
35d3d4a1 527 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 528}
529
618ff15d
AK		 530static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
531{
532 return emulate_exception(ctxt, SS_VECTOR, err, true);
533}
534
35d3d4a1 535static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 536{
35d3d4a1 537 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 538}
539
35d3d4a1 540static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 541{
35d3d4a1 542 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 543}
544
34d1f490
AK		 545static int emulate_de(struct x86_emulate_ctxt *ctxt)
546{
35d3d4a1 547 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 548}
549
1253791d
AK		 550static int emulate_nm(struct x86_emulate_ctxt *ctxt)
551{
552 return emulate_exception(ctxt, NM_VECTOR, 0, false);
553}
554
3d9b938e 555static int __linearize(struct x86_emulate_ctxt *ctxt,
52fd8b44 556 struct segmented_address addr,
3d9b938e 557 unsigned size, bool write, bool fetch,
52fd8b44
AK		 558 ulong *linear)
559{
560 struct decode_cache *c = &ctxt->decode;
618ff15d
AK		 561 struct desc_struct desc;
562 bool usable;
52fd8b44 563 ulong la;
618ff15d
AK		 564 u32 lim;
565 unsigned cpl, rpl;
52fd8b44
AK		 566
567 la = seg_base(ctxt, ctxt->ops, addr.seg) + addr.ea;
618ff15d
AK		 568 switch (ctxt->mode) {
569 case X86EMUL_MODE_REAL:
570 break;
571 case X86EMUL_MODE_PROT64:
572 if (((signed long)la << 16) >> 16 != la)
573 return emulate_gp(ctxt, 0);
574 break;
575 default:
4bff1e86
AK		 576 usable = ctxt->ops->get_cached_descriptor(ctxt, &desc, NULL,
577 addr.seg);
618ff15d
AK		 578 if (!usable)
579 goto bad;
580 /* code segment or read-only data segment */
581 if (((desc.type & 8) || !(desc.type & 2)) && write)
582 goto bad;
583 /* unreadable code segment */
3d9b938e 584 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 585 goto bad;
586 lim = desc_limit_scaled(&desc);
587 if ((desc.type & 8) || !(desc.type & 4)) {
588 /* expand-up segment */
589 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
590 goto bad;
591 } else {
592 /* exapand-down segment */
593 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
594 goto bad;
595 lim = desc.d ? 0xffffffff : 0xffff;
596 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
597 goto bad;
598 }
717746e3 599 cpl = ctxt->ops->cpl(ctxt);
4bff1e86 600 rpl = ctxt->ops->get_segment_selector(ctxt, addr.seg) & 3;
618ff15d
AK		 601 cpl = max(cpl, rpl);
602 if (!(desc.type & 8)) {
603 /* data segment */
604 if (cpl > desc.dpl)
605 goto bad;
606 } else if ((desc.type & 8) && !(desc.type & 4)) {
607 /* nonconforming code segment */
608 if (cpl != desc.dpl)
609 goto bad;
610 } else if ((desc.type & 8) && (desc.type & 4)) {
611 /* conforming code segment */
612 if (cpl < desc.dpl)
613 goto bad;
614 }
615 break;
616 }
3d9b938e 617 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : c->ad_bytes != 8)
52fd8b44
AK		 618 la &= (u32)-1;
619 *linear = la;
620 return X86EMUL_CONTINUE;
618ff15d
AK		 621bad:
622 if (addr.seg == VCPU_SREG_SS)
623 return emulate_ss(ctxt, addr.seg);
624 else
625 return emulate_gp(ctxt, addr.seg);
52fd8b44
AK		 626}
627
3d9b938e
NE		 628static int linearize(struct x86_emulate_ctxt *ctxt,
629 struct segmented_address addr,
630 unsigned size, bool write,
631 ulong *linear)
632{
633 return __linearize(ctxt, addr, size, write, false, linear);
634}
635
636
3ca3ac4d
AK		 637static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
638 struct segmented_address addr,
639 void *data,
640 unsigned size)
641{
9fa088f4
AK		 642 int rc;
643 ulong linear;
644
83b8795a 645 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 646 if (rc != X86EMUL_CONTINUE)
647 return rc;
0f65dd70 648 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 649}
650
62266869
AK		 651static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
652 struct x86_emulate_ops *ops,
2fb53ad8 653 unsigned long eip, u8 *dest)
62266869
AK		 654{
655 struct fetch_cache *fc = &ctxt->decode.fetch;
656 int rc;
2fb53ad8 657 int size, cur_size;
62266869 658
2fb53ad8 659 if (eip == fc->end) {
3d9b938e
NE		 660 unsigned long linear;
661 struct segmented_address addr = { .seg=VCPU_SREG_CS, .ea=eip};
2fb53ad8
AK		 662 cur_size = fc->end - fc->start;
663 size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip));
3d9b938e
NE		 664 rc = __linearize(ctxt, addr, size, false, true, &linear);
665 if (rc != X86EMUL_CONTINUE)
666 return rc;
0f65dd70
AK		 667 rc = ops->fetch(ctxt, linear, fc->data + cur_size,
668 size, &ctxt->exception);
3e2815e9 669 if (rc != X86EMUL_CONTINUE)
62266869 670 return rc;
2fb53ad8 671 fc->end += size;
62266869 672 }
2fb53ad8 673 *dest = fc->data[eip - fc->start];
3e2815e9 674 return X86EMUL_CONTINUE;
62266869
AK		 675}
676
677static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
678 struct x86_emulate_ops *ops,
679 unsigned long eip, void *dest, unsigned size)
680{
3e2815e9 681 int rc;
62266869 682
eb3c79e6 683 /* x86 instructions are limited to 15 bytes. */
063db061 684 if (eip + size - ctxt->eip > 15)
eb3c79e6 685 return X86EMUL_UNHANDLEABLE;
62266869
AK		 686 while (size--) {
687 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
3e2815e9 688 if (rc != X86EMUL_CONTINUE)
62266869
AK		 689 return rc;
690 }
3e2815e9 691 return X86EMUL_CONTINUE;
62266869
AK		 692}
693
1e3c5cb0
RR		 694/*
695 * Given the 'reg' portion of a ModRM byte, and a register block, return a
696 * pointer into the block that addresses the relevant register.
697 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
698 */
699static void *decode_register(u8 modrm_reg, unsigned long *regs,
700 int highbyte_regs)
6aa8b732
AK		 701{
702 void *p;
703
704 p = &regs[modrm_reg];
705 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
706 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
707 return p;
708}
709
710static int read_descriptor(struct x86_emulate_ctxt *ctxt,
711 struct x86_emulate_ops *ops,
90de84f5 712 struct segmented_address addr,
6aa8b732
AK		 713 u16 *size, unsigned long *address, int op_bytes)
714{
715 int rc;
716
717 if (op_bytes == 2)
718 op_bytes = 3;
719 *address = 0;
3ca3ac4d 720 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 721 if (rc != X86EMUL_CONTINUE)
6aa8b732 722 return rc;
30b31ab6 723 addr.ea += 2;
3ca3ac4d 724 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 725 return rc;
726}
727
bbe9abbd
NK		 728static int test_cc(unsigned int condition, unsigned int flags)
729{
730 int rc = 0;
731
732 switch ((condition & 15) >> 1) {
733 case 0: /* o */
734 rc |= (flags & EFLG_OF);
735 break;
736 case 1: /* b/c/nae */
737 rc |= (flags & EFLG_CF);
738 break;
739 case 2: /* z/e */
740 rc |= (flags & EFLG_ZF);
741 break;
742 case 3: /* be/na */
743 rc |= (flags & (EFLG_CF|EFLG_ZF));
744 break;
745 case 4: /* s */
746 rc |= (flags & EFLG_SF);
747 break;
748 case 5: /* p/pe */
749 rc |= (flags & EFLG_PF);
750 break;
751 case 7: /* le/ng */
752 rc |= (flags & EFLG_ZF);
753 /* fall through */
754 case 6: /* l/nge */
755 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
756 break;
757 }
758
759 /* Odd condition identifiers (lsb == 1) have inverted sense. */
760 return (!!rc ^ (condition & 1));
761}
762
91ff3cb4
AK		 763static void fetch_register_operand(struct operand *op)
764{
765 switch (op->bytes) {
766 case 1:
767 op->val = *(u8 *)op->addr.reg;
768 break;
769 case 2:
770 op->val = *(u16 *)op->addr.reg;
771 break;
772 case 4:
773 op->val = *(u32 *)op->addr.reg;
774 break;
775 case 8:
776 op->val = *(u64 *)op->addr.reg;
777 break;
778 }
779}
780
1253791d
AK		 781static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
782{
783 ctxt->ops->get_fpu(ctxt);
784 switch (reg) {
785 case 0: asm("movdqu %%xmm0, %0" : "=m"(*data)); break;
786 case 1: asm("movdqu %%xmm1, %0" : "=m"(*data)); break;
787 case 2: asm("movdqu %%xmm2, %0" : "=m"(*data)); break;
788 case 3: asm("movdqu %%xmm3, %0" : "=m"(*data)); break;
789 case 4: asm("movdqu %%xmm4, %0" : "=m"(*data)); break;
790 case 5: asm("movdqu %%xmm5, %0" : "=m"(*data)); break;
791 case 6: asm("movdqu %%xmm6, %0" : "=m"(*data)); break;
792 case 7: asm("movdqu %%xmm7, %0" : "=m"(*data)); break;
793#ifdef CONFIG_X86_64
794 case 8: asm("movdqu %%xmm8, %0" : "=m"(*data)); break;
795 case 9: asm("movdqu %%xmm9, %0" : "=m"(*data)); break;
796 case 10: asm("movdqu %%xmm10, %0" : "=m"(*data)); break;
797 case 11: asm("movdqu %%xmm11, %0" : "=m"(*data)); break;
798 case 12: asm("movdqu %%xmm12, %0" : "=m"(*data)); break;
799 case 13: asm("movdqu %%xmm13, %0" : "=m"(*data)); break;
800 case 14: asm("movdqu %%xmm14, %0" : "=m"(*data)); break;
801 case 15: asm("movdqu %%xmm15, %0" : "=m"(*data)); break;
802#endif
803 default: BUG();
804 }
805 ctxt->ops->put_fpu(ctxt);
806}
807
808static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
809 int reg)
810{
811 ctxt->ops->get_fpu(ctxt);
812 switch (reg) {
813 case 0: asm("movdqu %0, %%xmm0" : : "m"(*data)); break;
814 case 1: asm("movdqu %0, %%xmm1" : : "m"(*data)); break;
815 case 2: asm("movdqu %0, %%xmm2" : : "m"(*data)); break;
816 case 3: asm("movdqu %0, %%xmm3" : : "m"(*data)); break;
817 case 4: asm("movdqu %0, %%xmm4" : : "m"(*data)); break;
818 case 5: asm("movdqu %0, %%xmm5" : : "m"(*data)); break;
819 case 6: asm("movdqu %0, %%xmm6" : : "m"(*data)); break;
820 case 7: asm("movdqu %0, %%xmm7" : : "m"(*data)); break;
821#ifdef CONFIG_X86_64
822 case 8: asm("movdqu %0, %%xmm8" : : "m"(*data)); break;
823 case 9: asm("movdqu %0, %%xmm9" : : "m"(*data)); break;
824 case 10: asm("movdqu %0, %%xmm10" : : "m"(*data)); break;
825 case 11: asm("movdqu %0, %%xmm11" : : "m"(*data)); break;
826 case 12: asm("movdqu %0, %%xmm12" : : "m"(*data)); break;
827 case 13: asm("movdqu %0, %%xmm13" : : "m"(*data)); break;
828 case 14: asm("movdqu %0, %%xmm14" : : "m"(*data)); break;
829 case 15: asm("movdqu %0, %%xmm15" : : "m"(*data)); break;
830#endif
831 default: BUG();
832 }
833 ctxt->ops->put_fpu(ctxt);
834}
835
836static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
837 struct operand *op,
3c118e24 838 struct decode_cache *c,
3c118e24
AK		 839 int inhibit_bytereg)
840{
33615aa9 841 unsigned reg = c->modrm_reg;
9f1ef3f8 842 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 843
844 if (!(c->d & ModRM))
845 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
1253791d
AK		 846
847 if (c->d & Sse) {
848 op->type = OP_XMM;
849 op->bytes = 16;
850 op->addr.xmm = reg;
851 read_sse_reg(ctxt, &op->vec_val, reg);
852 return;
853 }
854
3c118e24
AK		 855 op->type = OP_REG;
856 if ((c->d & ByteOp) && !inhibit_bytereg) {
1a6440ae 857 op->addr.reg = decode_register(reg, c->regs, highbyte_regs);
3c118e24
AK		 858 op->bytes = 1;
859 } else {
1a6440ae 860 op->addr.reg = decode_register(reg, c->regs, 0);
3c118e24 861 op->bytes = c->op_bytes;
3c118e24 862 }
91ff3cb4 863 fetch_register_operand(op);
3c118e24
AK		 864 op->orig_val = op->val;
865}
866
1c73ef66 867static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7
AK		 868 struct x86_emulate_ops *ops,
869 struct operand *op)
1c73ef66
AK		 870{
871 struct decode_cache *c = &ctxt->decode;
872 u8 sib;
f5b4edcd 873 int index_reg = 0, base_reg = 0, scale;
3e2815e9 874 int rc = X86EMUL_CONTINUE;
2dbd0dd7 875 ulong modrm_ea = 0;
1c73ef66
AK		 876
877 if (c->rex_prefix) {
878 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
879 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
880 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
881 }
882
883 c->modrm = insn_fetch(u8, 1, c->eip);
884 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
885 c->modrm_reg |= (c->modrm & 0x38) >> 3;
886 c->modrm_rm |= (c->modrm & 0x07);
09ee57cd 887 c->modrm_seg = VCPU_SREG_DS;
1c73ef66
AK		 888
889 if (c->modrm_mod == 3) {
2dbd0dd7
AK		 890 op->type = OP_REG;
891 op->bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
892 op->addr.reg = decode_register(c->modrm_rm,
107d6d2e 893 c->regs, c->d & ByteOp);
1253791d
AK		 894 if (c->d & Sse) {
895 op->type = OP_XMM;
896 op->bytes = 16;
897 op->addr.xmm = c->modrm_rm;
898 read_sse_reg(ctxt, &op->vec_val, c->modrm_rm);
899 return rc;
900 }
2dbd0dd7 901 fetch_register_operand(op);
1c73ef66
AK		 902 return rc;
903 }
904
2dbd0dd7
AK		 905 op->type = OP_MEM;
906
1c73ef66
AK		 907 if (c->ad_bytes == 2) {
908 unsigned bx = c->regs[VCPU_REGS_RBX];
909 unsigned bp = c->regs[VCPU_REGS_RBP];
910 unsigned si = c->regs[VCPU_REGS_RSI];
911 unsigned di = c->regs[VCPU_REGS_RDI];
912
913 /* 16-bit ModR/M decode. */
914 switch (c->modrm_mod) {
915 case 0:
916 if (c->modrm_rm == 6)
2dbd0dd7 917 modrm_ea += insn_fetch(u16, 2, c->eip);
1c73ef66
AK		 918 break;
919 case 1:
2dbd0dd7 920 modrm_ea += insn_fetch(s8, 1, c->eip);
1c73ef66
AK		 921 break;
922 case 2:
2dbd0dd7 923 modrm_ea += insn_fetch(u16, 2, c->eip);
1c73ef66
AK		 924 break;
925 }
926 switch (c->modrm_rm) {
927 case 0:
2dbd0dd7 928 modrm_ea += bx + si;
1c73ef66
AK		 929 break;
930 case 1:
2dbd0dd7 931 modrm_ea += bx + di;
1c73ef66
AK		 932 break;
933 case 2:
2dbd0dd7 934 modrm_ea += bp + si;
1c73ef66
AK		 935 break;
936 case 3:
2dbd0dd7 937 modrm_ea += bp + di;
1c73ef66
AK		 938 break;
939 case 4:
2dbd0dd7 940 modrm_ea += si;
1c73ef66
AK		 941 break;
942 case 5:
2dbd0dd7 943 modrm_ea += di;
1c73ef66
AK		 944 break;
945 case 6:
946 if (c->modrm_mod != 0)
2dbd0dd7 947 modrm_ea += bp;
1c73ef66
AK		 948 break;
949 case 7:
2dbd0dd7 950 modrm_ea += bx;
1c73ef66
AK		 951 break;
952 }
953 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
954 (c->modrm_rm == 6 && c->modrm_mod != 0))
09ee57cd 955 c->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 956 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 957 } else {
958 /* 32/64-bit ModR/M decode. */
84411d85 959 if ((c->modrm_rm & 7) == 4) {
1c73ef66
AK		 960 sib = insn_fetch(u8, 1, c->eip);
961 index_reg |= (sib >> 3) & 7;
962 base_reg |= sib & 7;
963 scale = sib >> 6;
964
dc71d0f1 965 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
2dbd0dd7 966 modrm_ea += insn_fetch(s32, 4, c->eip);
dc71d0f1 967 else
2dbd0dd7 968 modrm_ea += c->regs[base_reg];
dc71d0f1 969 if (index_reg != 4)
2dbd0dd7 970 modrm_ea += c->regs[index_reg] << scale;
84411d85
AK		 971 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
972 if (ctxt->mode == X86EMUL_MODE_PROT64)
f5b4edcd 973 c->rip_relative = 1;
84411d85 974 } else
2dbd0dd7 975 modrm_ea += c->regs[c->modrm_rm];
1c73ef66
AK		 976 switch (c->modrm_mod) {
977 case 0:
978 if (c->modrm_rm == 5)
2dbd0dd7 979 modrm_ea += insn_fetch(s32, 4, c->eip);
1c73ef66
AK		 980 break;
981 case 1:
2dbd0dd7 982 modrm_ea += insn_fetch(s8, 1, c->eip);
1c73ef66
AK		 983 break;
984 case 2:
2dbd0dd7 985 modrm_ea += insn_fetch(s32, 4, c->eip);
1c73ef66
AK		 986 break;
987 }
988 }
90de84f5 989 op->addr.mem.ea = modrm_ea;
1c73ef66
AK		 990done:
991 return rc;
992}
993
994static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7
AK		 995 struct x86_emulate_ops *ops,
996 struct operand *op)
1c73ef66
AK		 997{
998 struct decode_cache *c = &ctxt->decode;
3e2815e9 999 int rc = X86EMUL_CONTINUE;
1c73ef66 1000
2dbd0dd7 1001 op->type = OP_MEM;
1c73ef66
AK		 1002 switch (c->ad_bytes) {
1003 case 2:
90de84f5 1004 op->addr.mem.ea = insn_fetch(u16, 2, c->eip);
1c73ef66
AK		 1005 break;
1006 case 4:
90de84f5 1007 op->addr.mem.ea = insn_fetch(u32, 4, c->eip);
1c73ef66
AK		 1008 break;
1009 case 8:
90de84f5 1010 op->addr.mem.ea = insn_fetch(u64, 8, c->eip);
1c73ef66
AK		 1011 break;
1012 }
1013done:
1014 return rc;
1015}
1016
35c843c4
WY		 1017static void fetch_bit_operand(struct decode_cache *c)
1018{
7129eeca 1019 long sv = 0, mask;
35c843c4 1020
3885f18f 1021 if (c->dst.type == OP_MEM && c->src.type == OP_REG) {
35c843c4
WY		 1022 mask = ~(c->dst.bytes * 8 - 1);
1023
1024 if (c->src.bytes == 2)
1025 sv = (s16)c->src.val & (s16)mask;
1026 else if (c->src.bytes == 4)
1027 sv = (s32)c->src.val & (s32)mask;
1028
90de84f5 1029 c->dst.addr.mem.ea += (sv >> 3);
35c843c4 1030 }
ba7ff2b7
WY		 1031
1032 /* only subword offset */
1033 c->src.val &= (c->dst.bytes << 3) - 1;
35c843c4
WY		 1034}
1035
dde7e6d1
AK		 1036static int read_emulated(struct x86_emulate_ctxt *ctxt,
1037 struct x86_emulate_ops *ops,
1038 unsigned long addr, void *dest, unsigned size)
6aa8b732 1039{
dde7e6d1
AK		 1040 int rc;
1041 struct read_cache *mc = &ctxt->decode.mem_read;
6aa8b732 1042
dde7e6d1
AK		 1043 while (size) {
1044 int n = min(size, 8u);
1045 size -= n;
1046 if (mc->pos < mc->end)
1047 goto read_cached;
5cd21917 1048
0f65dd70
AK		 1049 rc = ops->read_emulated(ctxt, addr, mc->data + mc->end, n,
1050 &ctxt->exception);
dde7e6d1
AK		 1051 if (rc != X86EMUL_CONTINUE)
1052 return rc;
1053 mc->end += n;
6aa8b732 1054
dde7e6d1
AK		 1055 read_cached:
1056 memcpy(dest, mc->data + mc->pos, n);
1057 mc->pos += n;
1058 dest += n;
1059 addr += n;
6aa8b732 1060 }
dde7e6d1
AK		 1061 return X86EMUL_CONTINUE;
1062}
6aa8b732 1063
3ca3ac4d
AK		 1064static int segmented_read(struct x86_emulate_ctxt *ctxt,
1065 struct segmented_address addr,
1066 void *data,
1067 unsigned size)
1068{
9fa088f4
AK		 1069 int rc;
1070 ulong linear;
1071
83b8795a 1072 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1073 if (rc != X86EMUL_CONTINUE)
1074 return rc;
1075 return read_emulated(ctxt, ctxt->ops, linear, data, size);
3ca3ac4d
AK		 1076}
1077
1078static int segmented_write(struct x86_emulate_ctxt *ctxt,
1079 struct segmented_address addr,
1080 const void *data,
1081 unsigned size)
1082{
9fa088f4
AK		 1083 int rc;
1084 ulong linear;
1085
83b8795a 1086 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1087 if (rc != X86EMUL_CONTINUE)
1088 return rc;
0f65dd70
AK		 1089 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1090 &ctxt->exception);
3ca3ac4d
AK		 1091}
1092
1093static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1094 struct segmented_address addr,
1095 const void *orig_data, const void *data,
1096 unsigned size)
1097{
9fa088f4
AK		 1098 int rc;
1099 ulong linear;
1100
83b8795a 1101 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1102 if (rc != X86EMUL_CONTINUE)
1103 return rc;
0f65dd70
AK		 1104 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1105 size, &ctxt->exception);
3ca3ac4d
AK		 1106}
1107
dde7e6d1
AK		 1108static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
1109 struct x86_emulate_ops *ops,
1110 unsigned int size, unsigned short port,
1111 void *dest)
1112{
1113 struct read_cache *rc = &ctxt->decode.io_read;
b4c6abfe 1114
dde7e6d1
AK		 1115 if (rc->pos == rc->end) { /* refill pio read ahead */
1116 struct decode_cache *c = &ctxt->decode;
1117 unsigned int in_page, n;
1118 unsigned int count = c->rep_prefix ?
1119 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1;
1120 in_page = (ctxt->eflags & EFLG_DF) ?
1121 offset_in_page(c->regs[VCPU_REGS_RDI]) :
1122 PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]);
1123 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1124 count);
1125 if (n == 0)
1126 n = 1;
1127 rc->pos = rc->end = 0;
ca1d4a9e 1128 if (!ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1129 return 0;
1130 rc->end = n * size;
6aa8b732
AK		 1131 }
1132
dde7e6d1
AK		 1133 memcpy(dest, rc->data + rc->pos, size);
1134 rc->pos += size;
1135 return 1;
1136}
6aa8b732 1137
dde7e6d1
AK		 1138static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
1139 struct x86_emulate_ops *ops,
1140 u16 selector, struct desc_ptr *dt)
1141{
1142 if (selector & 1 << 2) {
1143 struct desc_struct desc;
1144 memset (dt, 0, sizeof *dt);
4bff1e86
AK		 1145 if (!ops->get_cached_descriptor(ctxt, &desc, NULL,
1146 VCPU_SREG_LDTR))
dde7e6d1 1147 return;
e09d082c 1148
dde7e6d1
AK		 1149 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1150 dt->address = get_desc_base(&desc);
1151 } else
4bff1e86 1152 ops->get_gdt(ctxt, dt);
dde7e6d1 1153}
120df890 1154
dde7e6d1
AK		 1155/* allowed just for 8 bytes segments */
1156static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1157 struct x86_emulate_ops *ops,
1158 u16 selector, struct desc_struct *desc)
1159{
1160 struct desc_ptr dt;
1161 u16 index = selector >> 3;
1162 int ret;
dde7e6d1 1163 ulong addr;
120df890 1164
dde7e6d1 1165 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
120df890 1166
35d3d4a1
AK		 1167 if (dt.size < index * 8 + 7)
1168 return emulate_gp(ctxt, selector & 0xfffc);
dde7e6d1 1169 addr = dt.address + index * 8;
0f65dd70 1170 ret = ops->read_std(ctxt, addr, desc, sizeof *desc, &ctxt->exception);
e09d082c 1171
dde7e6d1
AK		 1172 return ret;
1173}
ef65c889 1174
dde7e6d1
AK		 1175/* allowed just for 8 bytes segments */
1176static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1177 struct x86_emulate_ops *ops,
1178 u16 selector, struct desc_struct *desc)
1179{
1180 struct desc_ptr dt;
1181 u16 index = selector >> 3;
dde7e6d1
AK		 1182 ulong addr;
1183 int ret;
6aa8b732 1184
dde7e6d1 1185 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
6e3d5dfb 1186
35d3d4a1
AK		 1187 if (dt.size < index * 8 + 7)
1188 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1189
dde7e6d1 1190 addr = dt.address + index * 8;
0f65dd70 1191 ret = ops->write_std(ctxt, addr, desc, sizeof *desc, &ctxt->exception);
c7e75a3d 1192
dde7e6d1
AK		 1193 return ret;
1194}
c7e75a3d 1195
5601d05b 1196/* Does not support long mode */
dde7e6d1
AK		 1197static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1198 struct x86_emulate_ops *ops,
1199 u16 selector, int seg)
1200{
1201 struct desc_struct seg_desc;
1202 u8 dpl, rpl, cpl;
1203 unsigned err_vec = GP_VECTOR;
1204 u32 err_code = 0;
1205 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1206 int ret;
69f55cb1 1207
dde7e6d1 1208 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1209
dde7e6d1
AK		 1210 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1211 || ctxt->mode == X86EMUL_MODE_REAL) {
1212 /* set real mode segment descriptor */
1213 set_desc_base(&seg_desc, selector << 4);
1214 set_desc_limit(&seg_desc, 0xffff);
1215 seg_desc.type = 3;
1216 seg_desc.p = 1;
1217 seg_desc.s = 1;
1218 goto load;
1219 }
1220
1221 /* NULL selector is not valid for TR, CS and SS */
1222 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
1223 && null_selector)
1224 goto exception;
1225
1226 /* TR should be in GDT only */
1227 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1228 goto exception;
1229
1230 if (null_selector) /* for NULL selector skip all following checks */
1231 goto load;
1232
1233 ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc);
1234 if (ret != X86EMUL_CONTINUE)
1235 return ret;
1236
1237 err_code = selector & 0xfffc;
1238 err_vec = GP_VECTOR;
1239
1240 /* can't load system descriptor into segment selecor */
1241 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1242 goto exception;
1243
1244 if (!seg_desc.p) {
1245 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1246 goto exception;
1247 }
1248
1249 rpl = selector & 3;
1250 dpl = seg_desc.dpl;
717746e3 1251 cpl = ops->cpl(ctxt);
dde7e6d1
AK		 1252
1253 switch (seg) {
1254 case VCPU_SREG_SS:
1255 /*
1256 * segment is not a writable data segment or segment
1257 * selector's RPL != CPL or segment selector's RPL != CPL
1258 */
1259 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1260 goto exception;
6aa8b732 1261 break;
dde7e6d1
AK		 1262 case VCPU_SREG_CS:
1263 if (!(seg_desc.type & 8))
1264 goto exception;
1265
1266 if (seg_desc.type & 4) {
1267 /* conforming */
1268 if (dpl > cpl)
1269 goto exception;
1270 } else {
1271 /* nonconforming */
1272 if (rpl > cpl || dpl != cpl)
1273 goto exception;
1274 }
1275 /* CS(RPL) <- CPL */
1276 selector = (selector & 0xfffc) | cpl;
6aa8b732 1277 break;
dde7e6d1
AK		 1278 case VCPU_SREG_TR:
1279 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1280 goto exception;
1281 break;
1282 case VCPU_SREG_LDTR:
1283 if (seg_desc.s || seg_desc.type != 2)
1284 goto exception;
1285 break;
1286 default: /* DS, ES, FS, or GS */
4e62417b 1287 /*
dde7e6d1
AK		 1288 * segment is not a data or readable code segment or
1289 * ((segment is a data or nonconforming code segment)
1290 * and (both RPL and CPL > DPL))
4e62417b 1291 */
dde7e6d1
AK		 1292 if ((seg_desc.type & 0xa) == 0x8 ||
1293 (((seg_desc.type & 0xc) != 0xc) &&
1294 (rpl > dpl && cpl > dpl)))
1295 goto exception;
6aa8b732 1296 break;
dde7e6d1
AK		 1297 }
1298
1299 if (seg_desc.s) {
1300 /* mark segment as accessed */
1301 seg_desc.type |= 1;
1302 ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc);
1303 if (ret != X86EMUL_CONTINUE)
1304 return ret;
1305 }
1306load:
4bff1e86
AK		 1307 ops->set_segment_selector(ctxt, selector, seg);
1308 ops->set_cached_descriptor(ctxt, &seg_desc, 0, seg);
dde7e6d1
AK		 1309 return X86EMUL_CONTINUE;
1310exception:
1311 emulate_exception(ctxt, err_vec, err_code, true);
1312 return X86EMUL_PROPAGATE_FAULT;
1313}
1314
31be40b3
WY		 1315static void write_register_operand(struct operand *op)
1316{
1317 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1318 switch (op->bytes) {
1319 case 1:
1320 *(u8 *)op->addr.reg = (u8)op->val;
1321 break;
1322 case 2:
1323 *(u16 *)op->addr.reg = (u16)op->val;
1324 break;
1325 case 4:
1326 *op->addr.reg = (u32)op->val;
1327 break; /* 64b: zero-extend */
1328 case 8:
1329 *op->addr.reg = op->val;
1330 break;
1331 }
1332}
1333
dde7e6d1
AK		 1334static inline int writeback(struct x86_emulate_ctxt *ctxt,
1335 struct x86_emulate_ops *ops)
1336{
1337 int rc;
1338 struct decode_cache *c = &ctxt->decode;
dde7e6d1
AK		 1339
1340 switch (c->dst.type) {
1341 case OP_REG:
31be40b3 1342 write_register_operand(&c->dst);
6aa8b732 1343 break;
dde7e6d1
AK		 1344 case OP_MEM:
1345 if (c->lock_prefix)
3ca3ac4d
AK		 1346 rc = segmented_cmpxchg(ctxt,
1347 c->dst.addr.mem,
1348 &c->dst.orig_val,
1349 &c->dst.val,
1350 c->dst.bytes);
341de7e3 1351 else
3ca3ac4d
AK		 1352 rc = segmented_write(ctxt,
1353 c->dst.addr.mem,
1354 &c->dst.val,
1355 c->dst.bytes);
dde7e6d1
AK		 1356 if (rc != X86EMUL_CONTINUE)
1357 return rc;
a682e354 1358 break;
1253791d
AK		 1359 case OP_XMM:
1360 write_sse_reg(ctxt, &c->dst.vec_val, c->dst.addr.xmm);
1361 break;
dde7e6d1
AK		 1362 case OP_NONE:
1363 /* no writeback */
414e6277 1364 break;
dde7e6d1 1365 default:
414e6277 1366 break;
6aa8b732 1367 }
dde7e6d1
AK		 1368 return X86EMUL_CONTINUE;
1369}
6aa8b732 1370
4487b3b4 1371static int em_push(struct x86_emulate_ctxt *ctxt)
dde7e6d1
AK		 1372{
1373 struct decode_cache *c = &ctxt->decode;
4179bb02 1374 struct segmented_address addr;
0dc8d10f 1375
dde7e6d1 1376 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
4179bb02
TY		 1377 addr.ea = register_address(c, c->regs[VCPU_REGS_RSP]);
1378 addr.seg = VCPU_SREG_SS;
1379
1380 /* Disable writeback. */
1381 c->dst.type = OP_NONE;
1382 return segmented_write(ctxt, addr, &c->src.val, c->op_bytes);
dde7e6d1 1383}
69f55cb1 1384
dde7e6d1
AK		 1385static int emulate_pop(struct x86_emulate_ctxt *ctxt,
1386 struct x86_emulate_ops *ops,
1387 void *dest, int len)
1388{
1389 struct decode_cache *c = &ctxt->decode;
1390 int rc;
90de84f5 1391 struct segmented_address addr;
8b4caf66 1392
90de84f5
AK		 1393 addr.ea = register_address(c, c->regs[VCPU_REGS_RSP]);
1394 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1395 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1396 if (rc != X86EMUL_CONTINUE)
1397 return rc;
1398
1399 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
1400 return rc;
8b4caf66
LV		 1401}
1402
dde7e6d1
AK		 1403static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1404 struct x86_emulate_ops *ops,
1405 void *dest, int len)
9de41573
GN		 1406{
1407 int rc;
dde7e6d1
AK		 1408 unsigned long val, change_mask;
1409 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
717746e3 1410 int cpl = ops->cpl(ctxt);
9de41573 1411
dde7e6d1
AK		 1412 rc = emulate_pop(ctxt, ops, &val, len);
1413 if (rc != X86EMUL_CONTINUE)
1414 return rc;
9de41573 1415
dde7e6d1
AK		 1416 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1417 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1418
dde7e6d1
AK		 1419 switch(ctxt->mode) {
1420 case X86EMUL_MODE_PROT64:
1421 case X86EMUL_MODE_PROT32:
1422 case X86EMUL_MODE_PROT16:
1423 if (cpl == 0)
1424 change_mask |= EFLG_IOPL;
1425 if (cpl <= iopl)
1426 change_mask |= EFLG_IF;
1427 break;
1428 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1429 if (iopl < 3)
1430 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1431 change_mask |= EFLG_IF;
1432 break;
1433 default: /* real mode */
1434 change_mask |= (EFLG_IOPL | EFLG_IF);
1435 break;
9de41573 1436 }
dde7e6d1
AK		 1437
1438 *(unsigned long *)dest =
1439 (ctxt->eflags & ~change_mask) | (val & change_mask);
1440
1441 return rc;
9de41573
GN		 1442}
1443
4179bb02
TY		 1444static int emulate_push_sreg(struct x86_emulate_ctxt *ctxt,
1445 struct x86_emulate_ops *ops, int seg)
7b262e90 1446{
dde7e6d1 1447 struct decode_cache *c = &ctxt->decode;
7b262e90 1448
4bff1e86 1449 c->src.val = ops->get_segment_selector(ctxt, seg);
7b262e90 1450
4487b3b4 1451 return em_push(ctxt);
7b262e90
GN		 1452}
1453
dde7e6d1
AK		 1454static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
1455 struct x86_emulate_ops *ops, int seg)
38ba30ba 1456{
dde7e6d1
AK		 1457 struct decode_cache *c = &ctxt->decode;
1458 unsigned long selector;
1459 int rc;
38ba30ba 1460
dde7e6d1
AK		 1461 rc = emulate_pop(ctxt, ops, &selector, c->op_bytes);
1462 if (rc != X86EMUL_CONTINUE)
1463 return rc;
1464
1465 rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg);
1466 return rc;
38ba30ba
GN		 1467}
1468
4487b3b4 1469static int emulate_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1470{
dde7e6d1
AK		 1471 struct decode_cache *c = &ctxt->decode;
1472 unsigned long old_esp = c->regs[VCPU_REGS_RSP];
1473 int rc = X86EMUL_CONTINUE;
1474 int reg = VCPU_REGS_RAX;
38ba30ba 1475
dde7e6d1
AK		 1476 while (reg <= VCPU_REGS_RDI) {
1477 (reg == VCPU_REGS_RSP) ?
1478 (c->src.val = old_esp) : (c->src.val = c->regs[reg]);
38ba30ba 1479
4487b3b4 1480 rc = em_push(ctxt);
dde7e6d1
AK		 1481 if (rc != X86EMUL_CONTINUE)
1482 return rc;
38ba30ba 1483
dde7e6d1 1484 ++reg;
38ba30ba 1485 }
38ba30ba 1486
dde7e6d1 1487 return rc;
38ba30ba
GN		 1488}
1489
dde7e6d1
AK		 1490static int emulate_popa(struct x86_emulate_ctxt *ctxt,
1491 struct x86_emulate_ops *ops)
38ba30ba 1492{
dde7e6d1
AK		 1493 struct decode_cache *c = &ctxt->decode;
1494 int rc = X86EMUL_CONTINUE;
1495 int reg = VCPU_REGS_RDI;
38ba30ba 1496
dde7e6d1
AK		 1497 while (reg >= VCPU_REGS_RAX) {
1498 if (reg == VCPU_REGS_RSP) {
1499 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1500 c->op_bytes);
1501 --reg;
1502 }
38ba30ba 1503
dde7e6d1
AK		 1504 rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes);
1505 if (rc != X86EMUL_CONTINUE)
1506 break;
1507 --reg;
38ba30ba 1508 }
dde7e6d1 1509 return rc;
38ba30ba
GN		 1510}
1511
6e154e56
MG		 1512int emulate_int_real(struct x86_emulate_ctxt *ctxt,
1513 struct x86_emulate_ops *ops, int irq)
1514{
1515 struct decode_cache *c = &ctxt->decode;
5c56e1cf 1516 int rc;
6e154e56
MG		 1517 struct desc_ptr dt;
1518 gva_t cs_addr;
1519 gva_t eip_addr;
1520 u16 cs, eip;
6e154e56
MG		 1521
1522 /* TODO: Add limit checks */
1523 c->src.val = ctxt->eflags;
4487b3b4 1524 rc = em_push(ctxt);
5c56e1cf
AK		 1525 if (rc != X86EMUL_CONTINUE)
1526 return rc;
6e154e56
MG		 1527
1528 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1529
4bff1e86 1530 c->src.val = ops->get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1531 rc = em_push(ctxt);
5c56e1cf
AK		 1532 if (rc != X86EMUL_CONTINUE)
1533 return rc;
6e154e56
MG		 1534
1535 c->src.val = c->eip;
4487b3b4 1536 rc = em_push(ctxt);
5c56e1cf
AK		 1537 if (rc != X86EMUL_CONTINUE)
1538 return rc;
1539
4bff1e86 1540 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1541
1542 eip_addr = dt.address + (irq << 2);
1543 cs_addr = dt.address + (irq << 2) + 2;
1544
0f65dd70 1545 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1546 if (rc != X86EMUL_CONTINUE)
1547 return rc;
1548
0f65dd70 1549 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1550 if (rc != X86EMUL_CONTINUE)
1551 return rc;
1552
1553 rc = load_segment_descriptor(ctxt, ops, cs, VCPU_SREG_CS);
1554 if (rc != X86EMUL_CONTINUE)
1555 return rc;
1556
1557 c->eip = eip;
1558
1559 return rc;
1560}
1561
1562static int emulate_int(struct x86_emulate_ctxt *ctxt,
1563 struct x86_emulate_ops *ops, int irq)
1564{
1565 switch(ctxt->mode) {
1566 case X86EMUL_MODE_REAL:
1567 return emulate_int_real(ctxt, ops, irq);
1568 case X86EMUL_MODE_VM86:
1569 case X86EMUL_MODE_PROT16:
1570 case X86EMUL_MODE_PROT32:
1571 case X86EMUL_MODE_PROT64:
1572 default:
1573 /* Protected mode interrupts unimplemented yet */
1574 return X86EMUL_UNHANDLEABLE;
1575 }
1576}
1577
dde7e6d1
AK		 1578static int emulate_iret_real(struct x86_emulate_ctxt *ctxt,
1579 struct x86_emulate_ops *ops)
38ba30ba 1580{
dde7e6d1
AK		 1581 struct decode_cache *c = &ctxt->decode;
1582 int rc = X86EMUL_CONTINUE;
1583 unsigned long temp_eip = 0;
1584 unsigned long temp_eflags = 0;
1585 unsigned long cs = 0;
1586 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1587 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1588 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1589 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1590
dde7e6d1 1591 /* TODO: Add stack limit check */
38ba30ba 1592
dde7e6d1 1593 rc = emulate_pop(ctxt, ops, &temp_eip, c->op_bytes);
38ba30ba 1594
dde7e6d1
AK		 1595 if (rc != X86EMUL_CONTINUE)
1596 return rc;
38ba30ba 1597
35d3d4a1
AK		 1598 if (temp_eip & ~0xffff)
1599 return emulate_gp(ctxt, 0);
38ba30ba 1600
dde7e6d1 1601 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
38ba30ba 1602
dde7e6d1
AK		 1603 if (rc != X86EMUL_CONTINUE)
1604 return rc;
38ba30ba 1605
dde7e6d1 1606 rc = emulate_pop(ctxt, ops, &temp_eflags, c->op_bytes);
38ba30ba 1607
dde7e6d1
AK		 1608 if (rc != X86EMUL_CONTINUE)
1609 return rc;
38ba30ba 1610
dde7e6d1 1611 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
38ba30ba 1612
dde7e6d1
AK		 1613 if (rc != X86EMUL_CONTINUE)
1614 return rc;
38ba30ba 1615
dde7e6d1 1616 c->eip = temp_eip;
38ba30ba 1617
38ba30ba 1618
dde7e6d1
AK		 1619 if (c->op_bytes == 4)
1620 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
1621 else if (c->op_bytes == 2) {
1622 ctxt->eflags &= ~0xffff;
1623 ctxt->eflags |= temp_eflags;
38ba30ba 1624 }
dde7e6d1
AK		 1625
1626 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1627 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1628
1629 return rc;
38ba30ba
GN		 1630}
1631
dde7e6d1
AK		 1632static inline int emulate_iret(struct x86_emulate_ctxt *ctxt,
1633 struct x86_emulate_ops* ops)
c37eda13 1634{
dde7e6d1
AK		 1635 switch(ctxt->mode) {
1636 case X86EMUL_MODE_REAL:
1637 return emulate_iret_real(ctxt, ops);
1638 case X86EMUL_MODE_VM86:
1639 case X86EMUL_MODE_PROT16:
1640 case X86EMUL_MODE_PROT32:
1641 case X86EMUL_MODE_PROT64:
c37eda13 1642 default:
dde7e6d1
AK		 1643 /* iret from protected mode unimplemented yet */
1644 return X86EMUL_UNHANDLEABLE;
c37eda13 1645 }
c37eda13
WY		 1646}
1647
dde7e6d1 1648static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
79168fd1 1649 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1650{
1651 struct decode_cache *c = &ctxt->decode;
1652
dde7e6d1 1653 return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
8cdbd2c9
LV		 1654}
1655
dde7e6d1 1656static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1657{
05f086f8 1658 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1659 switch (c->modrm_reg) {
1660 case 0: /* rol */
05f086f8 1661 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1662 break;
1663 case 1: /* ror */
05f086f8 1664 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1665 break;
1666 case 2: /* rcl */
05f086f8 1667 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1668 break;
1669 case 3: /* rcr */
05f086f8 1670 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1671 break;
1672 case 4: /* sal/shl */
1673 case 6: /* sal/shl */
05f086f8 1674 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1675 break;
1676 case 5: /* shr */
05f086f8 1677 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1678 break;
1679 case 7: /* sar */
05f086f8 1680 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1681 break;
1682 }
1683}
1684
1685static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 1686 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1687{
1688 struct decode_cache *c = &ctxt->decode;
3f9f53b0
MG		 1689 unsigned long *rax = &c->regs[VCPU_REGS_RAX];
1690 unsigned long *rdx = &c->regs[VCPU_REGS_RDX];
34d1f490 1691 u8 de = 0;
8cdbd2c9
LV		 1692
1693 switch (c->modrm_reg) {
1694 case 0 ... 1: /* test */
05f086f8 1695 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1696 break;
1697 case 2: /* not */
1698 c->dst.val = ~c->dst.val;
1699 break;
1700 case 3: /* neg */
05f086f8 1701 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9 1702 break;
3f9f53b0
MG		 1703 case 4: /* mul */
1704 emulate_1op_rax_rdx("mul", c->src, *rax, *rdx, ctxt->eflags);
1705 break;
1706 case 5: /* imul */
1707 emulate_1op_rax_rdx("imul", c->src, *rax, *rdx, ctxt->eflags);
1708 break;
1709 case 6: /* div */
34d1f490
AK		 1710 emulate_1op_rax_rdx_ex("div", c->src, *rax, *rdx,
1711 ctxt->eflags, de);
3f9f53b0
MG		 1712 break;
1713 case 7: /* idiv */
34d1f490
AK		 1714 emulate_1op_rax_rdx_ex("idiv", c->src, *rax, *rdx,
1715 ctxt->eflags, de);
3f9f53b0 1716 break;
8cdbd2c9 1717 default:
8c5eee30 1718 return X86EMUL_UNHANDLEABLE;
8cdbd2c9 1719 }
34d1f490
AK		 1720 if (de)
1721 return emulate_de(ctxt);
8c5eee30 1722 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1723}
1724
4487b3b4 1725static int emulate_grp45(struct x86_emulate_ctxt *ctxt)
8cdbd2c9
LV		 1726{
1727 struct decode_cache *c = &ctxt->decode;
4179bb02 1728 int rc = X86EMUL_CONTINUE;
8cdbd2c9
LV		 1729
1730 switch (c->modrm_reg) {
1731 case 0: /* inc */
05f086f8 1732 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1733 break;
1734 case 1: /* dec */
05f086f8 1735 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9 1736 break;
d19292e4
MG		 1737 case 2: /* call near abs */ {
1738 long int old_eip;
1739 old_eip = c->eip;
1740 c->eip = c->src.val;
1741 c->src.val = old_eip;
4487b3b4 1742 rc = em_push(ctxt);
d19292e4
MG		 1743 break;
1744 }
8cdbd2c9 1745 case 4: /* jmp abs */
fd60754e 1746 c->eip = c->src.val;
8cdbd2c9
LV		 1747 break;
1748 case 6: /* push */
4487b3b4 1749 rc = em_push(ctxt);
8cdbd2c9 1750 break;
8cdbd2c9 1751 }
4179bb02 1752 return rc;
8cdbd2c9
LV		 1753}
1754
1755static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
69f55cb1 1756 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1757{
1758 struct decode_cache *c = &ctxt->decode;
16518d5a 1759 u64 old = c->dst.orig_val64;
8cdbd2c9
LV		 1760
1761 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1762 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
8cdbd2c9
LV		 1763 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1764 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1765 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 1766 } else {
16518d5a
AK		 1767 c->dst.val64 = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1768 (u32) c->regs[VCPU_REGS_RBX];
8cdbd2c9 1769
05f086f8 1770 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 1771 }
1b30eaa8 1772 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1773}
1774
a77ab5ea
AK		 1775static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1776 struct x86_emulate_ops *ops)
1777{
1778 struct decode_cache *c = &ctxt->decode;
1779 int rc;
1780 unsigned long cs;
1781
1782 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1b30eaa8 1783 if (rc != X86EMUL_CONTINUE)
a77ab5ea
AK		 1784 return rc;
1785 if (c->op_bytes == 4)
1786 c->eip = (u32)c->eip;
1787 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1b30eaa8 1788 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1789 return rc;
2e873022 1790 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 1791 return rc;
1792}
1793
09b5f4d3
WY		 1794static int emulate_load_segment(struct x86_emulate_ctxt *ctxt,
1795 struct x86_emulate_ops *ops, int seg)
1796{
1797 struct decode_cache *c = &ctxt->decode;
1798 unsigned short sel;
1799 int rc;
1800
1801 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
1802
1803 rc = load_segment_descriptor(ctxt, ops, sel, seg);
1804 if (rc != X86EMUL_CONTINUE)
1805 return rc;
1806
1807 c->dst.val = c->src.val;
1808 return rc;
1809}
1810
e66bb2cc
AP		 1811static inline void
1812setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
79168fd1
GN		 1813 struct x86_emulate_ops *ops, struct desc_struct *cs,
1814 struct desc_struct *ss)
e66bb2cc 1815{
79168fd1 1816 memset(cs, 0, sizeof(struct desc_struct));
4bff1e86 1817 ops->get_cached_descriptor(ctxt, cs, NULL, VCPU_SREG_CS);
79168fd1 1818 memset(ss, 0, sizeof(struct desc_struct));
e66bb2cc
AP		 1819
1820 cs->l = 0; /* will be adjusted later */
79168fd1 1821 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 1822 cs->g = 1; /* 4kb granularity */
79168fd1 1823 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1824 cs->type = 0x0b; /* Read, Execute, Accessed */
1825 cs->s = 1;
1826 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 1827 cs->p = 1;
1828 cs->d = 1;
e66bb2cc 1829
79168fd1
GN		 1830 set_desc_base(ss, 0); /* flat segment */
1831 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1832 ss->g = 1; /* 4kb granularity */
1833 ss->s = 1;
1834 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 1835 ss->d = 1; /* 32bit stack segment */
e66bb2cc 1836 ss->dpl = 0;
79168fd1 1837 ss->p = 1;
e66bb2cc
AP		 1838}
1839
1840static int
3fb1b5db 1841emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
e66bb2cc
AP		 1842{
1843 struct decode_cache *c = &ctxt->decode;
79168fd1 1844 struct desc_struct cs, ss;
e66bb2cc 1845 u64 msr_data;
79168fd1 1846 u16 cs_sel, ss_sel;
c2ad2bb3 1847 u64 efer = 0;
e66bb2cc
AP		 1848
1849 /* syscall is not available in real mode */
2e901c4c 1850 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 1851 ctxt->mode == X86EMUL_MODE_VM86)
1852 return emulate_ud(ctxt);
e66bb2cc 1853
c2ad2bb3 1854 ops->get_msr(ctxt, MSR_EFER, &efer);
79168fd1 1855 setup_syscalls_segments(ctxt, ops, &cs, &ss);
e66bb2cc 1856
717746e3 1857 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 1858 msr_data >>= 32;
79168fd1
GN		 1859 cs_sel = (u16)(msr_data & 0xfffc);
1860 ss_sel = (u16)(msr_data + 8);
e66bb2cc 1861
c2ad2bb3 1862 if (efer & EFER_LMA) {
79168fd1 1863 cs.d = 0;
e66bb2cc
AP		 1864 cs.l = 1;
1865 }
4bff1e86
AK		 1866 ops->set_cached_descriptor(ctxt, &cs, 0, VCPU_SREG_CS);
1867 ops->set_segment_selector(ctxt, cs_sel, VCPU_SREG_CS);
1868 ops->set_cached_descriptor(ctxt, &ss, 0, VCPU_SREG_SS);
1869 ops->set_segment_selector(ctxt, ss_sel, VCPU_SREG_SS);
e66bb2cc
AP		 1870
1871 c->regs[VCPU_REGS_RCX] = c->eip;
c2ad2bb3 1872 if (efer & EFER_LMA) {
e66bb2cc
AP		 1873#ifdef CONFIG_X86_64
1874 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
1875
717746e3 1876 ops->get_msr(ctxt,
3fb1b5db
GN		 1877 ctxt->mode == X86EMUL_MODE_PROT64 ?
1878 MSR_LSTAR : MSR_CSTAR, &msr_data);
e66bb2cc
AP		 1879 c->eip = msr_data;
1880
717746e3 1881 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 1882 ctxt->eflags &= ~(msr_data | EFLG_RF);
1883#endif
1884 } else {
1885 /* legacy mode */
717746e3 1886 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc
AP		 1887 c->eip = (u32)msr_data;
1888
1889 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1890 }
1891
e54cfa97 1892 return X86EMUL_CONTINUE;
e66bb2cc
AP		 1893}
1894
8c604352 1895static int
3fb1b5db 1896emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8c604352
AP		 1897{
1898 struct decode_cache *c = &ctxt->decode;
79168fd1 1899 struct desc_struct cs, ss;
8c604352 1900 u64 msr_data;
79168fd1 1901 u16 cs_sel, ss_sel;
c2ad2bb3 1902 u64 efer = 0;
8c604352 1903
c2ad2bb3 1904 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 1905 /* inject #GP if in real mode */
35d3d4a1
AK		 1906 if (ctxt->mode == X86EMUL_MODE_REAL)
1907 return emulate_gp(ctxt, 0);
8c604352
AP		 1908
1909 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1910 * Therefore, we inject an #UD.
1911 */
35d3d4a1
AK		 1912 if (ctxt->mode == X86EMUL_MODE_PROT64)
1913 return emulate_ud(ctxt);
8c604352 1914
79168fd1 1915 setup_syscalls_segments(ctxt, ops, &cs, &ss);
8c604352 1916
717746e3 1917 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 1918 switch (ctxt->mode) {
1919 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 1920 if ((msr_data & 0xfffc) == 0x0)
1921 return emulate_gp(ctxt, 0);
8c604352
AP		 1922 break;
1923 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 1924 if (msr_data == 0x0)
1925 return emulate_gp(ctxt, 0);
8c604352
AP		 1926 break;
1927 }
1928
1929 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 1930 cs_sel = (u16)msr_data;
1931 cs_sel &= ~SELECTOR_RPL_MASK;
1932 ss_sel = cs_sel + 8;
1933 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 1934 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 1935 cs.d = 0;
8c604352
AP		 1936 cs.l = 1;
1937 }
1938
4bff1e86
AK		 1939 ops->set_cached_descriptor(ctxt, &cs, 0, VCPU_SREG_CS);
1940 ops->set_segment_selector(ctxt, cs_sel, VCPU_SREG_CS);
1941 ops->set_cached_descriptor(ctxt, &ss, 0, VCPU_SREG_SS);
1942 ops->set_segment_selector(ctxt, ss_sel, VCPU_SREG_SS);
8c604352 1943
717746e3 1944 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
8c604352
AP		 1945 c->eip = msr_data;
1946
717746e3 1947 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
8c604352
AP		 1948 c->regs[VCPU_REGS_RSP] = msr_data;
1949
e54cfa97 1950 return X86EMUL_CONTINUE;
8c604352
AP		 1951}
1952
4668f050 1953static int
3fb1b5db 1954emulate_sysexit(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
4668f050
AP		 1955{
1956 struct decode_cache *c = &ctxt->decode;
79168fd1 1957 struct desc_struct cs, ss;
4668f050
AP		 1958 u64 msr_data;
1959 int usermode;
79168fd1 1960 u16 cs_sel, ss_sel;
4668f050 1961
a0044755
GN		 1962 /* inject #GP if in real mode or Virtual 8086 mode */
1963 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 1964 ctxt->mode == X86EMUL_MODE_VM86)
1965 return emulate_gp(ctxt, 0);
4668f050 1966
79168fd1 1967 setup_syscalls_segments(ctxt, ops, &cs, &ss);
4668f050
AP		 1968
1969 if ((c->rex_prefix & 0x8) != 0x0)
1970 usermode = X86EMUL_MODE_PROT64;
1971 else
1972 usermode = X86EMUL_MODE_PROT32;
1973
1974 cs.dpl = 3;
1975 ss.dpl = 3;
717746e3 1976 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 1977 switch (usermode) {
1978 case X86EMUL_MODE_PROT32:
79168fd1 1979 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 1980 if ((msr_data & 0xfffc) == 0x0)
1981 return emulate_gp(ctxt, 0);
79168fd1 1982 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 1983 break;
1984 case X86EMUL_MODE_PROT64:
79168fd1 1985 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 1986 if (msr_data == 0x0)
1987 return emulate_gp(ctxt, 0);
79168fd1
GN		 1988 ss_sel = cs_sel + 8;
1989 cs.d = 0;
4668f050
AP		 1990 cs.l = 1;
1991 break;
1992 }
79168fd1
GN		 1993 cs_sel |= SELECTOR_RPL_MASK;
1994 ss_sel |= SELECTOR_RPL_MASK;
4668f050 1995
4bff1e86
AK		 1996 ops->set_cached_descriptor(ctxt, &cs, 0, VCPU_SREG_CS);
1997 ops->set_segment_selector(ctxt, cs_sel, VCPU_SREG_CS);
1998 ops->set_cached_descriptor(ctxt, &ss, 0, VCPU_SREG_SS);
1999 ops->set_segment_selector(ctxt, ss_sel, VCPU_SREG_SS);
4668f050 2000
bdb475a3
GN		 2001 c->eip = c->regs[VCPU_REGS_RDX];
2002 c->regs[VCPU_REGS_RSP] = c->regs[VCPU_REGS_RCX];
4668f050 2003
e54cfa97 2004 return X86EMUL_CONTINUE;
4668f050
AP		 2005}
2006
9c537244
GN		 2007static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt,
2008 struct x86_emulate_ops *ops)
f850e2e6
GN		 2009{
2010 int iopl;
2011 if (ctxt->mode == X86EMUL_MODE_REAL)
2012 return false;
2013 if (ctxt->mode == X86EMUL_MODE_VM86)
2014 return true;
2015 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
717746e3 2016 return ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2017}
2018
2019static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
2020 struct x86_emulate_ops *ops,
2021 u16 port, u16 len)
2022{
79168fd1 2023 struct desc_struct tr_seg;
5601d05b 2024 u32 base3;
f850e2e6 2025 int r;
399a40c9 2026 u16 io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2027 unsigned mask = (1 << len) - 1;
5601d05b 2028 unsigned long base;
f850e2e6 2029
4bff1e86 2030 ops->get_cached_descriptor(ctxt, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2031 if (!tr_seg.p)
f850e2e6 2032 return false;
79168fd1 2033 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2034 return false;
5601d05b
GN		 2035 base = get_desc_base(&tr_seg);
2036#ifdef CONFIG_X86_64
2037 base |= ((u64)base3) << 32;
2038#endif
0f65dd70 2039 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2040 if (r != X86EMUL_CONTINUE)
2041 return false;
79168fd1 2042 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2043 return false;
0f65dd70 2044 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2045 if (r != X86EMUL_CONTINUE)
2046 return false;
2047 if ((perm >> bit_idx) & mask)
2048 return false;
2049 return true;
2050}
2051
2052static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
2053 struct x86_emulate_ops *ops,
2054 u16 port, u16 len)
2055{
4fc40f07
GN		 2056 if (ctxt->perm_ok)
2057 return true;
2058
9c537244 2059 if (emulator_bad_iopl(ctxt, ops))
f850e2e6
GN		 2060 if (!emulator_io_port_access_allowed(ctxt, ops, port, len))
2061 return false;
4fc40f07
GN		 2062
2063 ctxt->perm_ok = true;
2064
f850e2e6
GN		 2065 return true;
2066}
2067
38ba30ba
GN		 2068static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
2069 struct x86_emulate_ops *ops,
2070 struct tss_segment_16 *tss)
2071{
2072 struct decode_cache *c = &ctxt->decode;
2073
2074 tss->ip = c->eip;
2075 tss->flag = ctxt->eflags;
2076 tss->ax = c->regs[VCPU_REGS_RAX];
2077 tss->cx = c->regs[VCPU_REGS_RCX];
2078 tss->dx = c->regs[VCPU_REGS_RDX];
2079 tss->bx = c->regs[VCPU_REGS_RBX];
2080 tss->sp = c->regs[VCPU_REGS_RSP];
2081 tss->bp = c->regs[VCPU_REGS_RBP];
2082 tss->si = c->regs[VCPU_REGS_RSI];
2083 tss->di = c->regs[VCPU_REGS_RDI];
2084
4bff1e86
AK		 2085 tss->es = ops->get_segment_selector(ctxt, VCPU_SREG_ES);
2086 tss->cs = ops->get_segment_selector(ctxt, VCPU_SREG_CS);
2087 tss->ss = ops->get_segment_selector(ctxt, VCPU_SREG_SS);
2088 tss->ds = ops->get_segment_selector(ctxt, VCPU_SREG_DS);
2089 tss->ldt = ops->get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2090}
2091
2092static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
2093 struct x86_emulate_ops *ops,
2094 struct tss_segment_16 *tss)
2095{
2096 struct decode_cache *c = &ctxt->decode;
2097 int ret;
2098
2099 c->eip = tss->ip;
2100 ctxt->eflags = tss->flag | 2;
2101 c->regs[VCPU_REGS_RAX] = tss->ax;
2102 c->regs[VCPU_REGS_RCX] = tss->cx;
2103 c->regs[VCPU_REGS_RDX] = tss->dx;
2104 c->regs[VCPU_REGS_RBX] = tss->bx;
2105 c->regs[VCPU_REGS_RSP] = tss->sp;
2106 c->regs[VCPU_REGS_RBP] = tss->bp;
2107 c->regs[VCPU_REGS_RSI] = tss->si;
2108 c->regs[VCPU_REGS_RDI] = tss->di;
2109
2110 /*
2111 * SDM says that segment selectors are loaded before segment
2112 * descriptors
2113 */
4bff1e86
AK		 2114 ops->set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2115 ops->set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2116 ops->set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2117 ops->set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2118 ops->set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2119
2120 /*
2121 * Now load segment descriptors. If fault happenes at this stage
2122 * it is handled in a context of new task
2123 */
2124 ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR);
2125 if (ret != X86EMUL_CONTINUE)
2126 return ret;
2127 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2128 if (ret != X86EMUL_CONTINUE)
2129 return ret;
2130 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2131 if (ret != X86EMUL_CONTINUE)
2132 return ret;
2133 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2134 if (ret != X86EMUL_CONTINUE)
2135 return ret;
2136 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2137 if (ret != X86EMUL_CONTINUE)
2138 return ret;
2139
2140 return X86EMUL_CONTINUE;
2141}
2142
2143static int task_switch_16(struct x86_emulate_ctxt *ctxt,
2144 struct x86_emulate_ops *ops,
2145 u16 tss_selector, u16 old_tss_sel,
2146 ulong old_tss_base, struct desc_struct *new_desc)
2147{
2148 struct tss_segment_16 tss_seg;
2149 int ret;
bcc55cba 2150 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2151
0f65dd70 2152 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2153 &ctxt->exception);
db297e3d 2154 if (ret != X86EMUL_CONTINUE)
38ba30ba 2155 /* FIXME: need to provide precise fault address */
38ba30ba 2156 return ret;
38ba30ba
GN		 2157
2158 save_state_to_tss16(ctxt, ops, &tss_seg);
2159
0f65dd70 2160 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2161 &ctxt->exception);
db297e3d 2162 if (ret != X86EMUL_CONTINUE)
38ba30ba 2163 /* FIXME: need to provide precise fault address */
38ba30ba 2164 return ret;
38ba30ba 2165
0f65dd70 2166 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2167 &ctxt->exception);
db297e3d 2168 if (ret != X86EMUL_CONTINUE)
38ba30ba 2169 /* FIXME: need to provide precise fault address */
38ba30ba 2170 return ret;
38ba30ba
GN		 2171
2172 if (old_tss_sel != 0xffff) {
2173 tss_seg.prev_task_link = old_tss_sel;
2174
0f65dd70 2175 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2176 &tss_seg.prev_task_link,
2177 sizeof tss_seg.prev_task_link,
0f65dd70 2178 &ctxt->exception);
db297e3d 2179 if (ret != X86EMUL_CONTINUE)
38ba30ba 2180 /* FIXME: need to provide precise fault address */
38ba30ba 2181 return ret;
38ba30ba
GN		 2182 }
2183
2184 return load_state_from_tss16(ctxt, ops, &tss_seg);
2185}
2186
2187static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
2188 struct x86_emulate_ops *ops,
2189 struct tss_segment_32 *tss)
2190{
2191 struct decode_cache *c = &ctxt->decode;
2192
717746e3 2193 tss->cr3 = ops->get_cr(ctxt, 3);
38ba30ba
GN		 2194 tss->eip = c->eip;
2195 tss->eflags = ctxt->eflags;
2196 tss->eax = c->regs[VCPU_REGS_RAX];
2197 tss->ecx = c->regs[VCPU_REGS_RCX];
2198 tss->edx = c->regs[VCPU_REGS_RDX];
2199 tss->ebx = c->regs[VCPU_REGS_RBX];
2200 tss->esp = c->regs[VCPU_REGS_RSP];
2201 tss->ebp = c->regs[VCPU_REGS_RBP];
2202 tss->esi = c->regs[VCPU_REGS_RSI];
2203 tss->edi = c->regs[VCPU_REGS_RDI];
2204
4bff1e86
AK		 2205 tss->es = ops->get_segment_selector(ctxt, VCPU_SREG_ES);
2206 tss->cs = ops->get_segment_selector(ctxt, VCPU_SREG_CS);
2207 tss->ss = ops->get_segment_selector(ctxt, VCPU_SREG_SS);
2208 tss->ds = ops->get_segment_selector(ctxt, VCPU_SREG_DS);
2209 tss->fs = ops->get_segment_selector(ctxt, VCPU_SREG_FS);
2210 tss->gs = ops->get_segment_selector(ctxt, VCPU_SREG_GS);
2211 tss->ldt_selector = ops->get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2212}
2213
2214static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
2215 struct x86_emulate_ops *ops,
2216 struct tss_segment_32 *tss)
2217{
2218 struct decode_cache *c = &ctxt->decode;
2219 int ret;
2220
717746e3 2221 if (ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2222 return emulate_gp(ctxt, 0);
38ba30ba
GN		 2223 c->eip = tss->eip;
2224 ctxt->eflags = tss->eflags | 2;
2225 c->regs[VCPU_REGS_RAX] = tss->eax;
2226 c->regs[VCPU_REGS_RCX] = tss->ecx;
2227 c->regs[VCPU_REGS_RDX] = tss->edx;
2228 c->regs[VCPU_REGS_RBX] = tss->ebx;
2229 c->regs[VCPU_REGS_RSP] = tss->esp;
2230 c->regs[VCPU_REGS_RBP] = tss->ebp;
2231 c->regs[VCPU_REGS_RSI] = tss->esi;
2232 c->regs[VCPU_REGS_RDI] = tss->edi;
2233
2234 /*
2235 * SDM says that segment selectors are loaded before segment
2236 * descriptors
2237 */
4bff1e86
AK		 2238 ops->set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2239 ops->set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2240 ops->set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2241 ops->set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2242 ops->set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2243 ops->set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2244 ops->set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba
GN		 2245
2246 /*
2247 * Now load segment descriptors. If fault happenes at this stage
2248 * it is handled in a context of new task
2249 */
2250 ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR);
2251 if (ret != X86EMUL_CONTINUE)
2252 return ret;
2253 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2254 if (ret != X86EMUL_CONTINUE)
2255 return ret;
2256 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2257 if (ret != X86EMUL_CONTINUE)
2258 return ret;
2259 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2260 if (ret != X86EMUL_CONTINUE)
2261 return ret;
2262 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2263 if (ret != X86EMUL_CONTINUE)
2264 return ret;
2265 ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS);
2266 if (ret != X86EMUL_CONTINUE)
2267 return ret;
2268 ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS);
2269 if (ret != X86EMUL_CONTINUE)
2270 return ret;
2271
2272 return X86EMUL_CONTINUE;
2273}
2274
2275static int task_switch_32(struct x86_emulate_ctxt *ctxt,
2276 struct x86_emulate_ops *ops,
2277 u16 tss_selector, u16 old_tss_sel,
2278 ulong old_tss_base, struct desc_struct *new_desc)
2279{
2280 struct tss_segment_32 tss_seg;
2281 int ret;
bcc55cba 2282 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2283
0f65dd70 2284 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2285 &ctxt->exception);
db297e3d 2286 if (ret != X86EMUL_CONTINUE)
38ba30ba 2287 /* FIXME: need to provide precise fault address */
38ba30ba 2288 return ret;
38ba30ba
GN		 2289
2290 save_state_to_tss32(ctxt, ops, &tss_seg);
2291
0f65dd70 2292 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2293 &ctxt->exception);
db297e3d 2294 if (ret != X86EMUL_CONTINUE)
38ba30ba 2295 /* FIXME: need to provide precise fault address */
38ba30ba 2296 return ret;
38ba30ba 2297
0f65dd70 2298 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2299 &ctxt->exception);
db297e3d 2300 if (ret != X86EMUL_CONTINUE)
38ba30ba 2301 /* FIXME: need to provide precise fault address */
38ba30ba 2302 return ret;
38ba30ba
GN		 2303
2304 if (old_tss_sel != 0xffff) {
2305 tss_seg.prev_task_link = old_tss_sel;
2306
0f65dd70 2307 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2308 &tss_seg.prev_task_link,
2309 sizeof tss_seg.prev_task_link,
0f65dd70 2310 &ctxt->exception);
db297e3d 2311 if (ret != X86EMUL_CONTINUE)
38ba30ba 2312 /* FIXME: need to provide precise fault address */
38ba30ba 2313 return ret;
38ba30ba
GN		 2314 }
2315
2316 return load_state_from_tss32(ctxt, ops, &tss_seg);
2317}
2318
2319static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2320 struct x86_emulate_ops *ops,
2321 u16 tss_selector, int reason,
2322 bool has_error_code, u32 error_code)
38ba30ba
GN		 2323{
2324 struct desc_struct curr_tss_desc, next_tss_desc;
2325 int ret;
4bff1e86 2326 u16 old_tss_sel = ops->get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2327 ulong old_tss_base =
4bff1e86 2328 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2329 u32 desc_limit;
38ba30ba
GN		 2330
2331 /* FIXME: old_tss_base == ~0 ? */
2332
2333 ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc);
2334 if (ret != X86EMUL_CONTINUE)
2335 return ret;
2336 ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc);
2337 if (ret != X86EMUL_CONTINUE)
2338 return ret;
2339
2340 /* FIXME: check that next_tss_desc is tss */
2341
2342 if (reason != TASK_SWITCH_IRET) {
2343 if ((tss_selector & 3) > next_tss_desc.dpl ||
717746e3 2344 ops->cpl(ctxt) > next_tss_desc.dpl)
35d3d4a1 2345 return emulate_gp(ctxt, 0);
38ba30ba
GN		 2346 }
2347
ceffb459
GN		 2348 desc_limit = desc_limit_scaled(&next_tss_desc);
2349 if (!next_tss_desc.p ||
2350 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2351 desc_limit < 0x2b)) {
54b8486f 2352 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2353 return X86EMUL_PROPAGATE_FAULT;
2354 }
2355
2356 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2357 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2358 write_segment_descriptor(ctxt, ops, old_tss_sel,
2359 &curr_tss_desc);
2360 }
2361
2362 if (reason == TASK_SWITCH_IRET)
2363 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2364
2365 /* set back link to prev task only if NT bit is set in eflags
2366 note that old_tss_sel is not used afetr this point */
2367 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2368 old_tss_sel = 0xffff;
2369
2370 if (next_tss_desc.type & 8)
2371 ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel,
2372 old_tss_base, &next_tss_desc);
2373 else
2374 ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel,
2375 old_tss_base, &next_tss_desc);
0760d448
JK		 2376 if (ret != X86EMUL_CONTINUE)
2377 return ret;
38ba30ba
GN		 2378
2379 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2380 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2381
2382 if (reason != TASK_SWITCH_IRET) {
2383 next_tss_desc.type |= (1 << 1); /* set busy flag */
2384 write_segment_descriptor(ctxt, ops, tss_selector,
2385 &next_tss_desc);
2386 }
2387
717746e3 2388 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
4bff1e86
AK		 2389 ops->set_cached_descriptor(ctxt, &next_tss_desc, 0, VCPU_SREG_TR);
2390 ops->set_segment_selector(ctxt, tss_selector, VCPU_SREG_TR);
38ba30ba 2391
e269fb21
JK		 2392 if (has_error_code) {
2393 struct decode_cache *c = &ctxt->decode;
2394
2395 c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2396 c->lock_prefix = 0;
2397 c->src.val = (unsigned long) error_code;
4487b3b4 2398 ret = em_push(ctxt);
e269fb21
JK		 2399 }
2400
38ba30ba
GN		 2401 return ret;
2402}
2403
2404int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2405 u16 tss_selector, int reason,
2406 bool has_error_code, u32 error_code)
38ba30ba 2407{
9aabc88f 2408 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2409 struct decode_cache *c = &ctxt->decode;
2410 int rc;
2411
38ba30ba 2412 c->eip = ctxt->eip;
e269fb21 2413 c->dst.type = OP_NONE;
38ba30ba 2414
e269fb21
JK		 2415 rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason,
2416 has_error_code, error_code);
38ba30ba 2417
4179bb02
TY		 2418 if (rc == X86EMUL_CONTINUE)
2419 ctxt->eip = c->eip;
38ba30ba 2420
a0c0ab2f 2421 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2422}
2423
90de84f5 2424static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned seg,
d9271123 2425 int reg, struct operand *op)
a682e354
GN		 2426{
2427 struct decode_cache *c = &ctxt->decode;
2428 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2429
d9271123 2430 register_address_increment(c, &c->regs[reg], df * op->bytes);
90de84f5
AK		 2431 op->addr.mem.ea = register_address(c, c->regs[reg]);
2432 op->addr.mem.seg = seg;
a682e354
GN		 2433}
2434
7af04fc0
AK		 2435static int em_das(struct x86_emulate_ctxt *ctxt)
2436{
2437 struct decode_cache *c = &ctxt->decode;
2438 u8 al, old_al;
2439 bool af, cf, old_cf;
2440
2441 cf = ctxt->eflags & X86_EFLAGS_CF;
2442 al = c->dst.val;
2443
2444 old_al = al;
2445 old_cf = cf;
2446 cf = false;
2447 af = ctxt->eflags & X86_EFLAGS_AF;
2448 if ((al & 0x0f) > 9 || af) {
2449 al -= 6;
2450 cf = old_cf | (al >= 250);
2451 af = true;
2452 } else {
2453 af = false;
2454 }
2455 if (old_al > 0x99 || old_cf) {
2456 al -= 0x60;
2457 cf = true;
2458 }
2459
2460 c->dst.val = al;
2461 /* Set PF, ZF, SF */
2462 c->src.type = OP_IMM;
2463 c->src.val = 0;
2464 c->src.bytes = 1;
2465 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
2466 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2467 if (cf)
2468 ctxt->eflags |= X86_EFLAGS_CF;
2469 if (af)
2470 ctxt->eflags |= X86_EFLAGS_AF;
2471 return X86EMUL_CONTINUE;
2472}
2473
0ef753b8
AK		 2474static int em_call_far(struct x86_emulate_ctxt *ctxt)
2475{
2476 struct decode_cache *c = &ctxt->decode;
2477 u16 sel, old_cs;
2478 ulong old_eip;
2479 int rc;
2480
4bff1e86 2481 old_cs = ctxt->ops->get_segment_selector(ctxt, VCPU_SREG_CS);
0ef753b8
AK		 2482 old_eip = c->eip;
2483
2484 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
2485 if (load_segment_descriptor(ctxt, ctxt->ops, sel, VCPU_SREG_CS))
2486 return X86EMUL_CONTINUE;
2487
2488 c->eip = 0;
2489 memcpy(&c->eip, c->src.valptr, c->op_bytes);
2490
2491 c->src.val = old_cs;
4487b3b4 2492 rc = em_push(ctxt);
0ef753b8
AK		 2493 if (rc != X86EMUL_CONTINUE)
2494 return rc;
2495
2496 c->src.val = old_eip;
4487b3b4 2497 return em_push(ctxt);
0ef753b8
AK		 2498}
2499
40ece7c7
AK		 2500static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2501{
2502 struct decode_cache *c = &ctxt->decode;
2503 int rc;
2504
2505 c->dst.type = OP_REG;
2506 c->dst.addr.reg = &c->eip;
2507 c->dst.bytes = c->op_bytes;
2508 rc = emulate_pop(ctxt, ctxt->ops, &c->dst.val, c->op_bytes);
2509 if (rc != X86EMUL_CONTINUE)
2510 return rc;
2511 register_address_increment(c, &c->regs[VCPU_REGS_RSP], c->src.val);
2512 return X86EMUL_CONTINUE;
2513}
2514
5c82aa29 2515static int em_imul(struct x86_emulate_ctxt *ctxt)
f3a1b9f4
AK		 2516{
2517 struct decode_cache *c = &ctxt->decode;
2518
f3a1b9f4
AK		 2519 emulate_2op_SrcV_nobyte("imul", c->src, c->dst, ctxt->eflags);
2520 return X86EMUL_CONTINUE;
2521}
2522
5c82aa29
AK		 2523static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2524{
2525 struct decode_cache *c = &ctxt->decode;
2526
2527 c->dst.val = c->src2.val;
2528 return em_imul(ctxt);
2529}
2530
61429142
AK		 2531static int em_cwd(struct x86_emulate_ctxt *ctxt)
2532{
2533 struct decode_cache *c = &ctxt->decode;
2534
2535 c->dst.type = OP_REG;
2536 c->dst.bytes = c->src.bytes;
2537 c->dst.addr.reg = &c->regs[VCPU_REGS_RDX];
2538 c->dst.val = ~((c->src.val >> (c->src.bytes * 8 - 1)) - 1);
2539
2540 return X86EMUL_CONTINUE;
2541}
2542
48bb5d3c
AK		 2543static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2544{
48bb5d3c
AK		 2545 struct decode_cache *c = &ctxt->decode;
2546 u64 tsc = 0;
2547
717746e3 2548 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
48bb5d3c
AK		 2549 c->regs[VCPU_REGS_RAX] = (u32)tsc;
2550 c->regs[VCPU_REGS_RDX] = tsc >> 32;
2551 return X86EMUL_CONTINUE;
2552}
2553
b9eac5f4
AK		 2554static int em_mov(struct x86_emulate_ctxt *ctxt)
2555{
2556 struct decode_cache *c = &ctxt->decode;
2557 c->dst.val = c->src.val;
2558 return X86EMUL_CONTINUE;
2559}
2560
aa97bb48
AK		 2561static int em_movdqu(struct x86_emulate_ctxt *ctxt)
2562{
2563 struct decode_cache *c = &ctxt->decode;
2564 memcpy(&c->dst.vec_val, &c->src.vec_val, c->op_bytes);
2565 return X86EMUL_CONTINUE;
2566}
2567
38503911
AK		 2568static int em_invlpg(struct x86_emulate_ctxt *ctxt)
2569{
2570 struct decode_cache *c = &ctxt->decode;
9fa088f4
AK		 2571 int rc;
2572 ulong linear;
2573
83b8795a 2574 rc = linearize(ctxt, c->src.addr.mem, 1, false, &linear);
9fa088f4 2575 if (rc == X86EMUL_CONTINUE)
3cb16fe7 2576 ctxt->ops->invlpg(ctxt, linear);
38503911
AK		 2577 /* Disable writeback. */
2578 c->dst.type = OP_NONE;
2579 return X86EMUL_CONTINUE;
2580}
2581
2d04a05b
AK		 2582static int em_clts(struct x86_emulate_ctxt *ctxt)
2583{
2584 ulong cr0;
2585
2586 cr0 = ctxt->ops->get_cr(ctxt, 0);
2587 cr0 &= ~X86_CR0_TS;
2588 ctxt->ops->set_cr(ctxt, 0, cr0);
2589 return X86EMUL_CONTINUE;
2590}
2591
26d05cc7
AK		 2592static int em_vmcall(struct x86_emulate_ctxt *ctxt)
2593{
2594 struct decode_cache *c = &ctxt->decode;
2595 int rc;
2596
2597 if (c->modrm_mod != 3 || c->modrm_rm != 1)
2598 return X86EMUL_UNHANDLEABLE;
2599
2600 rc = ctxt->ops->fix_hypercall(ctxt);
2601 if (rc != X86EMUL_CONTINUE)
2602 return rc;
2603
2604 /* Let the processor re-execute the fixed hypercall */
2605 c->eip = ctxt->eip;
2606 /* Disable writeback. */
2607 c->dst.type = OP_NONE;
2608 return X86EMUL_CONTINUE;
2609}
2610
2611static int em_lgdt(struct x86_emulate_ctxt *ctxt)
2612{
2613 struct decode_cache *c = &ctxt->decode;
2614 struct desc_ptr desc_ptr;
2615 int rc;
2616
2617 rc = read_descriptor(ctxt, ctxt->ops, c->src.addr.mem,
2618 &desc_ptr.size, &desc_ptr.address,
2619 c->op_bytes);
2620 if (rc != X86EMUL_CONTINUE)
2621 return rc;
2622 ctxt->ops->set_gdt(ctxt, &desc_ptr);
2623 /* Disable writeback. */
2624 c->dst.type = OP_NONE;
2625 return X86EMUL_CONTINUE;
2626}
2627
2628static int em_svm(struct x86_emulate_ctxt *ctxt)
2629{
2630 struct decode_cache *c = &ctxt->decode;
2631 int rc;
2632
2633 switch (c->modrm_rm) {
2634 case 1:
2635 rc = ctxt->ops->fix_hypercall(ctxt);
2636 break;
2637 default:
2638 return X86EMUL_UNHANDLEABLE;
2639 }
2640 /* Disable writeback. */
2641 c->dst.type = OP_NONE;
2642 return rc;
2643}
2644
2645static int em_lidt(struct x86_emulate_ctxt *ctxt)
2646{
2647 struct decode_cache *c = &ctxt->decode;
2648 struct desc_ptr desc_ptr;
2649 int rc;
2650
2651 rc = read_descriptor(ctxt, ctxt->ops, c->src.addr.mem,
2652 &desc_ptr.size,
2653 &desc_ptr.address,
2654 c->op_bytes);
2655 if (rc != X86EMUL_CONTINUE)
2656 return rc;
2657 ctxt->ops->set_idt(ctxt, &desc_ptr);
2658 /* Disable writeback. */
2659 c->dst.type = OP_NONE;
2660 return X86EMUL_CONTINUE;
2661}
2662
2663static int em_smsw(struct x86_emulate_ctxt *ctxt)
2664{
2665 struct decode_cache *c = &ctxt->decode;
2666
2667 c->dst.bytes = 2;
2668 c->dst.val = ctxt->ops->get_cr(ctxt, 0);
2669 return X86EMUL_CONTINUE;
2670}
2671
2672static int em_lmsw(struct x86_emulate_ctxt *ctxt)
2673{
2674 struct decode_cache *c = &ctxt->decode;
2675 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
2676 | (c->src.val & 0x0f));
2677 c->dst.type = OP_NONE;
2678 return X86EMUL_CONTINUE;
2679}
2680
cfec82cb
JR		 2681static bool valid_cr(int nr)
2682{
2683 switch (nr) {
2684 case 0:
2685 case 2 ... 4:
2686 case 8:
2687 return true;
2688 default:
2689 return false;
2690 }
2691}
2692
2693static int check_cr_read(struct x86_emulate_ctxt *ctxt)
2694{
2695 struct decode_cache *c = &ctxt->decode;
2696
2697 if (!valid_cr(c->modrm_reg))
2698 return emulate_ud(ctxt);
2699
2700 return X86EMUL_CONTINUE;
2701}
2702
2703static int check_cr_write(struct x86_emulate_ctxt *ctxt)
2704{
2705 struct decode_cache *c = &ctxt->decode;
2706 u64 new_val = c->src.val64;
2707 int cr = c->modrm_reg;
c2ad2bb3 2708 u64 efer = 0;
cfec82cb
JR		 2709
2710 static u64 cr_reserved_bits[] = {
2711 0xffffffff00000000ULL,
2712 0, 0, 0, /* CR3 checked later */
2713 CR4_RESERVED_BITS,
2714 0, 0, 0,
2715 CR8_RESERVED_BITS,
2716 };
2717
2718 if (!valid_cr(cr))
2719 return emulate_ud(ctxt);
2720
2721 if (new_val & cr_reserved_bits[cr])
2722 return emulate_gp(ctxt, 0);
2723
2724 switch (cr) {
2725 case 0: {
c2ad2bb3 2726 u64 cr4;
cfec82cb
JR		 2727 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
2728 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
2729 return emulate_gp(ctxt, 0);
2730
717746e3
AK		 2731 cr4 = ctxt->ops->get_cr(ctxt, 4);
2732 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 2733
2734 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
2735 !(cr4 & X86_CR4_PAE))
2736 return emulate_gp(ctxt, 0);
2737
2738 break;
2739 }
2740 case 3: {
2741 u64 rsvd = 0;
2742
c2ad2bb3
AK		 2743 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
2744 if (efer & EFER_LMA)
cfec82cb 2745 rsvd = CR3_L_MODE_RESERVED_BITS;
fd72c419 2746 else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE)
cfec82cb 2747 rsvd = CR3_PAE_RESERVED_BITS;
fd72c419 2748 else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG)
cfec82cb
JR		 2749 rsvd = CR3_NONPAE_RESERVED_BITS;
2750
2751 if (new_val & rsvd)
2752 return emulate_gp(ctxt, 0);
2753
2754 break;
2755 }
2756 case 4: {
c2ad2bb3 2757 u64 cr4;
cfec82cb 2758
717746e3
AK		 2759 cr4 = ctxt->ops->get_cr(ctxt, 4);
2760 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 2761
2762 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
2763 return emulate_gp(ctxt, 0);
2764
2765 break;
2766 }
2767 }
2768
2769 return X86EMUL_CONTINUE;
2770}
2771
3b88e41a
JR		 2772static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
2773{
2774 unsigned long dr7;
2775
717746e3 2776 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 2777
2778 /* Check if DR7.Global_Enable is set */
2779 return dr7 & (1 << 13);
2780}
2781
2782static int check_dr_read(struct x86_emulate_ctxt *ctxt)
2783{
2784 struct decode_cache *c = &ctxt->decode;
2785 int dr = c->modrm_reg;
2786 u64 cr4;
2787
2788 if (dr > 7)
2789 return emulate_ud(ctxt);
2790
717746e3 2791 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 2792 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
2793 return emulate_ud(ctxt);
2794
2795 if (check_dr7_gd(ctxt))
2796 return emulate_db(ctxt);
2797
2798 return X86EMUL_CONTINUE;
2799}
2800
2801static int check_dr_write(struct x86_emulate_ctxt *ctxt)
2802{
2803 struct decode_cache *c = &ctxt->decode;
2804 u64 new_val = c->src.val64;
2805 int dr = c->modrm_reg;
2806
2807 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
2808 return emulate_gp(ctxt, 0);
2809
2810 return check_dr_read(ctxt);
2811}
2812
01de8b09
JR		 2813static int check_svme(struct x86_emulate_ctxt *ctxt)
2814{
2815 u64 efer;
2816
717746e3 2817 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 2818
2819 if (!(efer & EFER_SVME))
2820 return emulate_ud(ctxt);
2821
2822 return X86EMUL_CONTINUE;
2823}
2824
2825static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
2826{
fe870ab9 2827 u64 rax = ctxt->decode.regs[VCPU_REGS_RAX];
01de8b09
JR		 2828
2829 /* Valid physical address? */
d4224449 2830 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 2831 return emulate_gp(ctxt, 0);
2832
2833 return check_svme(ctxt);
2834}
2835
d7eb8203
JR		 2836static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
2837{
717746e3 2838 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 2839
717746e3 2840 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 2841 return emulate_ud(ctxt);
2842
2843 return X86EMUL_CONTINUE;
2844}
2845
8061252e
JR		 2846static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
2847{
717746e3 2848 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
fe870ab9 2849 u64 rcx = ctxt->decode.regs[VCPU_REGS_RCX];
8061252e 2850
717746e3 2851 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
8061252e
JR		 2852 (rcx > 3))
2853 return emulate_gp(ctxt, 0);
2854
2855 return X86EMUL_CONTINUE;
2856}
2857
f6511935
JR		 2858static int check_perm_in(struct x86_emulate_ctxt *ctxt)
2859{
2860 struct decode_cache *c = &ctxt->decode;
2861
2862 c->dst.bytes = min(c->dst.bytes, 4u);
2863 if (!emulator_io_permited(ctxt, ctxt->ops, c->src.val, c->dst.bytes))
2864 return emulate_gp(ctxt, 0);
2865
2866 return X86EMUL_CONTINUE;
2867}
2868
2869static int check_perm_out(struct x86_emulate_ctxt *ctxt)
2870{
2871 struct decode_cache *c = &ctxt->decode;
2872
2873 c->src.bytes = min(c->src.bytes, 4u);
2874 if (!emulator_io_permited(ctxt, ctxt->ops, c->dst.val, c->src.bytes))
2875 return emulate_gp(ctxt, 0);
2876
2877 return X86EMUL_CONTINUE;
2878}
2879
73fba5f4 2880#define D(_y) { .flags = (_y) }
c4f035c6 2881#define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
d09beabd
JR		 2882#define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
2883 .check_perm = (_p) }
73fba5f4 2884#define N D(0)
01de8b09 2885#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
73fba5f4
AK		 2886#define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) }
2887#define GD(_f, _g) { .flags = ((_f) | Group | GroupDual), .u.gdual = (_g) }
2888#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
c4f035c6
AK		 2889#define II(_f, _e, _i) \
2890 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd
JR		 2891#define IIP(_f, _e, _i, _p) \
2892 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
2893 .check_perm = (_p) }
aa97bb48 2894#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 2895
8d8f4e9f 2896#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 2897#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f
AK		 2898#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
2899
6230f7fc
AK		 2900#define D6ALU(_f) D2bv((_f) | DstMem | SrcReg | ModRM), \
2901 D2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock), \
2902 D2bv(((_f) & ~Lock) | DstAcc | SrcImm)
2903
d7eb8203
JR		 2904static struct opcode group7_rm1[] = {
2905 DI(SrcNone | ModRM | Priv, monitor),
2906 DI(SrcNone | ModRM | Priv, mwait),
2907 N, N, N, N, N, N,
2908};
2909
01de8b09
JR		 2910static struct opcode group7_rm3[] = {
2911 DIP(SrcNone | ModRM | Prot | Priv, vmrun, check_svme_pa),
bfeed29d 2912 DI(SrcNone | ModRM | Prot | VendorSpecific, vmmcall),
01de8b09
JR		 2913 DIP(SrcNone | ModRM | Prot | Priv, vmload, check_svme_pa),
2914 DIP(SrcNone | ModRM | Prot | Priv, vmsave, check_svme_pa),
2915 DIP(SrcNone | ModRM | Prot | Priv, stgi, check_svme),
2916 DIP(SrcNone | ModRM | Prot | Priv, clgi, check_svme),
2917 DIP(SrcNone | ModRM | Prot | Priv, skinit, check_svme),
2918 DIP(SrcNone | ModRM | Prot | Priv, invlpga, check_svme),
2919};
6230f7fc 2920
d7eb8203
JR		 2921static struct opcode group7_rm7[] = {
2922 N,
2923 DIP(SrcNone | ModRM, rdtscp, check_rdtsc),
2924 N, N, N, N, N, N,
2925};
73fba5f4
AK		 2926static struct opcode group1[] = {
2927 X7(D(Lock)), N
2928};
2929
2930static struct opcode group1A[] = {
2931 D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N,
2932};
2933
2934static struct opcode group3[] = {
2935 D(DstMem | SrcImm | ModRM), D(DstMem | SrcImm | ModRM),
2936 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
3f9f53b0 2937 X4(D(SrcMem | ModRM)),
73fba5f4
AK		 2938};
2939
2940static struct opcode group4[] = {
2941 D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock),
2942 N, N, N, N, N, N,
2943};
2944
2945static struct opcode group5[] = {
2946 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
0ef753b8
AK		 2947 D(SrcMem | ModRM | Stack),
2948 I(SrcMemFAddr | ModRM | ImplicitOps | Stack, em_call_far),
73fba5f4
AK		 2949 D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps),
2950 D(SrcMem | ModRM | Stack), N,
2951};
2952
dee6bb70
JR		 2953static struct opcode group6[] = {
2954 DI(ModRM | Prot, sldt),
2955 DI(ModRM | Prot, str),
2956 DI(ModRM | Prot | Priv, lldt),
2957 DI(ModRM | Prot | Priv, ltr),
2958 N, N, N, N,
2959};
2960
73fba5f4 2961static struct group_dual group7 = { {
dee6bb70
JR		 2962 DI(ModRM | Mov | DstMem | Priv, sgdt),
2963 DI(ModRM | Mov | DstMem | Priv, sidt),
2964 DI(ModRM | SrcMem | Priv, lgdt), DI(ModRM | SrcMem | Priv, lidt),
3c6e276f
AK		 2965 DI(SrcNone | ModRM | DstMem | Mov, smsw), N,
2966 DI(SrcMem16 | ModRM | Mov | Priv, lmsw),
2967 DI(SrcMem | ModRM | ByteOp | Priv | NoAccess, invlpg),
73fba5f4 2968}, {
d7eb8203 2969 D(SrcNone | ModRM | Priv | VendorSpecific), EXT(0, group7_rm1),
01de8b09 2970 N, EXT(0, group7_rm3),
3c6e276f 2971 DI(SrcNone | ModRM | DstMem | Mov, smsw), N,
d7eb8203 2972 DI(SrcMem16 | ModRM | Mov | Priv, lmsw), EXT(0, group7_rm7),
73fba5f4
AK		 2973} };
2974
2975static struct opcode group8[] = {
2976 N, N, N, N,
2977 D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock),
2978 D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock),
2979};
2980
2981static struct group_dual group9 = { {
2982 N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N,
2983}, {
2984 N, N, N, N, N, N, N, N,
2985} };
2986
a4d4a7c1
AK		 2987static struct opcode group11[] = {
2988 I(DstMem | SrcImm | ModRM | Mov, em_mov), X7(D(Undefined)),
2989};
2990
aa97bb48
AK		 2991static struct gprefix pfx_0f_6f_0f_7f = {
2992 N, N, N, I(Sse, em_movdqu),
2993};
2994
73fba5f4
AK		 2995static struct opcode opcode_table[256] = {
2996 /* 0x00 - 0x07 */
6230f7fc 2997 D6ALU(Lock),
73fba5f4
AK		 2998 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2999 /* 0x08 - 0x0F */
6230f7fc 3000 D6ALU(Lock),
73fba5f4
AK		 3001 D(ImplicitOps | Stack | No64), N,
3002 /* 0x10 - 0x17 */
6230f7fc 3003 D6ALU(Lock),
73fba5f4
AK		 3004 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
3005 /* 0x18 - 0x1F */
6230f7fc 3006 D6ALU(Lock),
73fba5f4
AK		 3007 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
3008 /* 0x20 - 0x27 */
6230f7fc 3009 D6ALU(Lock), N, N,
73fba5f4 3010 /* 0x28 - 0x2F */
6230f7fc 3011 D6ALU(Lock), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3012 /* 0x30 - 0x37 */
6230f7fc 3013 D6ALU(Lock), N, N,
73fba5f4 3014 /* 0x38 - 0x3F */
6230f7fc 3015 D6ALU(0), N, N,
73fba5f4
AK		 3016 /* 0x40 - 0x4F */
3017 X16(D(DstReg)),
3018 /* 0x50 - 0x57 */
63540382 3019 X8(I(SrcReg | Stack, em_push)),
73fba5f4
AK		 3020 /* 0x58 - 0x5F */
3021 X8(D(DstReg | Stack)),
3022 /* 0x60 - 0x67 */
3023 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
3024 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3025 N, N, N, N,
3026 /* 0x68 - 0x6F */
d46164db
AK		 3027 I(SrcImm | Mov | Stack, em_push),
3028 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3029 I(SrcImmByte | Mov | Stack, em_push),
3030 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
f6511935
JR		 3031 D2bvIP(DstDI | Mov | String, ins, check_perm_in), /* insb, insw/insd */
3032 D2bvIP(SrcSI | ImplicitOps | String, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4
AK		 3033 /* 0x70 - 0x7F */
3034 X16(D(SrcImmByte)),
3035 /* 0x80 - 0x87 */
3036 G(ByteOp | DstMem | SrcImm | ModRM | Group, group1),
3037 G(DstMem | SrcImm | ModRM | Group, group1),
3038 G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1),
3039 G(DstMem | SrcImmByte | ModRM | Group, group1),
76e8e68d 3040 D2bv(DstMem | SrcReg | ModRM), D2bv(DstMem | SrcReg | ModRM | Lock),
73fba5f4 3041 /* 0x88 - 0x8F */
b9eac5f4
AK		 3042 I2bv(DstMem | SrcReg | ModRM | Mov, em_mov),
3043 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
342fc630 3044 D(DstMem | SrcNone | ModRM | Mov), D(ModRM | SrcMem | NoAccess | DstReg),
73fba5f4
AK		 3045 D(ImplicitOps | SrcMem16 | ModRM), G(0, group1A),
3046 /* 0x90 - 0x97 */
bf608f88 3047 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3048 /* 0x98 - 0x9F */
61429142 3049 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3050 I(SrcImmFAddr | No64, em_call_far), N,
3c6e276f 3051 DI(ImplicitOps | Stack, pushf), DI(ImplicitOps | Stack, popf), N, N,
73fba5f4 3052 /* 0xA0 - 0xA7 */
b9eac5f4
AK		 3053 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
3054 I2bv(DstMem | SrcAcc | Mov | MemAbs, em_mov),
3055 I2bv(SrcSI | DstDI | Mov | String, em_mov),
3056 D2bv(SrcSI | DstDI | String),
73fba5f4 3057 /* 0xA8 - 0xAF */
50748613 3058 D2bv(DstAcc | SrcImm),
b9eac5f4
AK		 3059 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3060 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
48fe67b5 3061 D2bv(SrcAcc | DstDI | String),
73fba5f4 3062 /* 0xB0 - 0xB7 */
b9eac5f4 3063 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3064 /* 0xB8 - 0xBF */
b9eac5f4 3065 X8(I(DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3066 /* 0xC0 - 0xC7 */
d2c6c7ad 3067 D2bv(DstMem | SrcImmByte | ModRM),
40ece7c7
AK		 3068 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
3069 D(ImplicitOps | Stack),
09b5f4d3 3070 D(DstReg | SrcMemFAddr | ModRM | No64), D(DstReg | SrcMemFAddr | ModRM | No64),
a4d4a7c1 3071 G(ByteOp, group11), G(0, group11),
73fba5f4
AK		 3072 /* 0xC8 - 0xCF */
3073 N, N, N, D(ImplicitOps | Stack),
3c6e276f
AK		 3074 D(ImplicitOps), DI(SrcImmByte, intn),
3075 D(ImplicitOps | No64), DI(ImplicitOps, iret),
73fba5f4 3076 /* 0xD0 - 0xD7 */
d2c6c7ad 3077 D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM),
73fba5f4
AK		 3078 N, N, N, N,
3079 /* 0xD8 - 0xDF */
3080 N, N, N, N, N, N, N, N,
3081 /* 0xE0 - 0xE7 */
e4abac67 3082 X4(D(SrcImmByte)),
f6511935
JR		 3083 D2bvIP(SrcImmUByte | DstAcc, in, check_perm_in),
3084 D2bvIP(SrcAcc | DstImmUByte, out, check_perm_out),
73fba5f4
AK		 3085 /* 0xE8 - 0xEF */
3086 D(SrcImm | Stack), D(SrcImm | ImplicitOps),
3087 D(SrcImmFAddr | No64), D(SrcImmByte | ImplicitOps),
f6511935
JR		 3088 D2bvIP(SrcNone | DstAcc, in, check_perm_in),
3089 D2bvIP(SrcAcc | ImplicitOps, out, check_perm_out),
73fba5f4 3090 /* 0xF0 - 0xF7 */
bf608f88 3091 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 3092 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3093 G(ByteOp, group3), G(0, group3),
73fba5f4 3094 /* 0xF8 - 0xFF */
8744aa9a 3095 D(ImplicitOps), D(ImplicitOps), D(ImplicitOps), D(ImplicitOps),
73fba5f4
AK		 3096 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3097};
3098
3099static struct opcode twobyte_table[256] = {
3100 /* 0x00 - 0x0F */
dee6bb70 3101 G(0, group6), GD(0, &group7), N, N,
cfec82cb 3102 N, D(ImplicitOps | VendorSpecific), DI(ImplicitOps | Priv, clts), N,
3c6e276f 3103 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK		 3104 N, D(ImplicitOps | ModRM), N, N,
3105 /* 0x10 - 0x1F */
3106 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
3107 /* 0x20 - 0x2F */
cfec82cb 3108 DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
3b88e41a 3109 DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
cfec82cb 3110 DIP(ModRM | SrcMem | Priv | Op3264, cr_write, check_cr_write),
3b88e41a 3111 DIP(ModRM | SrcMem | Priv | Op3264, dr_write, check_dr_write),
73fba5f4
AK		 3112 N, N, N, N,
3113 N, N, N, N, N, N, N, N,
3114 /* 0x30 - 0x3F */
8061252e
JR		 3115 DI(ImplicitOps | Priv, wrmsr),
3116 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
3117 DI(ImplicitOps | Priv, rdmsr),
3118 DIP(ImplicitOps | Priv, rdpmc, check_rdpmc),
d867162c
AK		 3119 D(ImplicitOps | VendorSpecific), D(ImplicitOps | Priv | VendorSpecific),
3120 N, N,
73fba5f4
AK		 3121 N, N, N, N, N, N, N, N,
3122 /* 0x40 - 0x4F */
3123 X16(D(DstReg | SrcMem | ModRM | Mov)),
3124 /* 0x50 - 0x5F */
3125 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3126 /* 0x60 - 0x6F */
aa97bb48
AK		 3127 N, N, N, N,
3128 N, N, N, N,
3129 N, N, N, N,
3130 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 3131 /* 0x70 - 0x7F */
aa97bb48
AK		 3132 N, N, N, N,
3133 N, N, N, N,
3134 N, N, N, N,
3135 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK		 3136 /* 0x80 - 0x8F */
3137 X16(D(SrcImm)),
3138 /* 0x90 - 0x9F */
ee45b58e 3139 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4
AK		 3140 /* 0xA0 - 0xA7 */
3141 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
8061252e 3142 DI(ImplicitOps, cpuid), D(DstMem | SrcReg | ModRM | BitOp),
73fba5f4
AK		 3143 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3144 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
3145 /* 0xA8 - 0xAF */
3146 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
8061252e 3147 DI(ImplicitOps, rsm), D(DstMem | SrcReg | ModRM | BitOp | Lock),
73fba5f4
AK		 3148 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3149 D(DstMem | SrcReg | Src2CL | ModRM),
5c82aa29 3150 D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 3151 /* 0xB0 - 0xB7 */
739ae406 3152 D2bv(DstMem | SrcReg | ModRM | Lock),
09b5f4d3
WY		 3153 D(DstReg | SrcMemFAddr | ModRM), D(DstMem | SrcReg | ModRM | BitOp | Lock),
3154 D(DstReg | SrcMemFAddr | ModRM), D(DstReg | SrcMemFAddr | ModRM),
3155 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 3156 /* 0xB8 - 0xBF */
3157 N, N,
ba7ff2b7 3158 G(BitOp, group8), D(DstMem | SrcReg | ModRM | BitOp | Lock),
d9574a25
WY		 3159 D(DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
3160 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4 3161 /* 0xC0 - 0xCF */
739ae406 3162 D2bv(DstMem | SrcReg | ModRM | Lock),
92f738a5 3163 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4
AK		 3164 N, N, N, GD(0, &group9),
3165 N, N, N, N, N, N, N, N,
3166 /* 0xD0 - 0xDF */
3167 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3168 /* 0xE0 - 0xEF */
3169 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3170 /* 0xF0 - 0xFF */
3171 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
3172};
3173
3174#undef D
3175#undef N
3176#undef G
3177#undef GD
3178#undef I
aa97bb48 3179#undef GP
01de8b09 3180#undef EXT
73fba5f4 3181
8d8f4e9f 3182#undef D2bv
f6511935 3183#undef D2bvIP
8d8f4e9f 3184#undef I2bv
6230f7fc 3185#undef D6ALU
8d8f4e9f 3186
39f21ee5
AK		 3187static unsigned imm_size(struct decode_cache *c)
3188{
3189 unsigned size;
3190
3191 size = (c->d & ByteOp) ? 1 : c->op_bytes;
3192 if (size == 8)
3193 size = 4;
3194 return size;
3195}
3196
3197static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
3198 unsigned size, bool sign_extension)
3199{
3200 struct decode_cache *c = &ctxt->decode;
3201 struct x86_emulate_ops *ops = ctxt->ops;
3202 int rc = X86EMUL_CONTINUE;
3203
3204 op->type = OP_IMM;
3205 op->bytes = size;
90de84f5 3206 op->addr.mem.ea = c->eip;
39f21ee5
AK		 3207 /* NB. Immediates are sign-extended as necessary. */
3208 switch (op->bytes) {
3209 case 1:
3210 op->val = insn_fetch(s8, 1, c->eip);
3211 break;
3212 case 2:
3213 op->val = insn_fetch(s16, 2, c->eip);
3214 break;
3215 case 4:
3216 op->val = insn_fetch(s32, 4, c->eip);
3217 break;
3218 }
3219 if (!sign_extension) {
3220 switch (op->bytes) {
3221 case 1:
3222 op->val &= 0xff;
3223 break;
3224 case 2:
3225 op->val &= 0xffff;
3226 break;
3227 case 4:
3228 op->val &= 0xffffffff;
3229 break;
3230 }
3231 }
3232done:
3233 return rc;
3234}
3235
dde7e6d1 3236int
dc25e89e 3237x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1
AK		 3238{
3239 struct x86_emulate_ops *ops = ctxt->ops;
3240 struct decode_cache *c = &ctxt->decode;
3241 int rc = X86EMUL_CONTINUE;
3242 int mode = ctxt->mode;
0d7cdee8
AK		 3243 int def_op_bytes, def_ad_bytes, dual, goffset, simd_prefix;
3244 bool op_prefix = false;
dde7e6d1 3245 struct opcode opcode, *g_mod012, *g_mod3;
2dbd0dd7 3246 struct operand memop = { .type = OP_NONE };
dde7e6d1 3247
dde7e6d1 3248 c->eip = ctxt->eip;
dc25e89e
AP		 3249 c->fetch.start = c->eip;
3250 c->fetch.end = c->fetch.start + insn_len;
3251 if (insn_len > 0)
3252 memcpy(c->fetch.data, insn, insn_len);
dde7e6d1
AK		 3253
3254 switch (mode) {
3255 case X86EMUL_MODE_REAL:
3256 case X86EMUL_MODE_VM86:
3257 case X86EMUL_MODE_PROT16:
3258 def_op_bytes = def_ad_bytes = 2;
3259 break;
3260 case X86EMUL_MODE_PROT32:
3261 def_op_bytes = def_ad_bytes = 4;
3262 break;
3263#ifdef CONFIG_X86_64
3264 case X86EMUL_MODE_PROT64:
3265 def_op_bytes = 4;
3266 def_ad_bytes = 8;
3267 break;
3268#endif
3269 default:
3270 return -1;
3271 }
3272
3273 c->op_bytes = def_op_bytes;
3274 c->ad_bytes = def_ad_bytes;
3275
3276 /* Legacy prefixes. */
3277 for (;;) {
3278 switch (c->b = insn_fetch(u8, 1, c->eip)) {
3279 case 0x66: /* operand-size override */
0d7cdee8 3280 op_prefix = true;
dde7e6d1
AK		 3281 /* switch between 2/4 bytes */
3282 c->op_bytes = def_op_bytes ^ 6;
3283 break;
3284 case 0x67: /* address-size override */
3285 if (mode == X86EMUL_MODE_PROT64)
3286 /* switch between 4/8 bytes */
3287 c->ad_bytes = def_ad_bytes ^ 12;
3288 else
3289 /* switch between 2/4 bytes */
3290 c->ad_bytes = def_ad_bytes ^ 6;
3291 break;
3292 case 0x26: /* ES override */
3293 case 0x2e: /* CS override */
3294 case 0x36: /* SS override */
3295 case 0x3e: /* DS override */
3296 set_seg_override(c, (c->b >> 3) & 3);
3297 break;
3298 case 0x64: /* FS override */
3299 case 0x65: /* GS override */
3300 set_seg_override(c, c->b & 7);
3301 break;
3302 case 0x40 ... 0x4f: /* REX */
3303 if (mode != X86EMUL_MODE_PROT64)
3304 goto done_prefixes;
3305 c->rex_prefix = c->b;
3306 continue;
3307 case 0xf0: /* LOCK */
3308 c->lock_prefix = 1;
3309 break;
3310 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 3311 case 0xf3: /* REP/REPE/REPZ */
1d6b114f 3312 c->rep_prefix = c->b;
dde7e6d1
AK		 3313 break;
3314 default:
3315 goto done_prefixes;
3316 }
3317
3318 /* Any legacy prefix after a REX prefix nullifies its effect. */
3319
3320 c->rex_prefix = 0;
3321 }
3322
3323done_prefixes:
3324
3325 /* REX prefix. */
1e87e3ef
AK		 3326 if (c->rex_prefix & 8)
3327 c->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 3328
3329 /* Opcode byte(s). */
3330 opcode = opcode_table[c->b];
d3ad6243
WY		 3331 /* Two-byte opcode? */
3332 if (c->b == 0x0f) {
3333 c->twobyte = 1;
3334 c->b = insn_fetch(u8, 1, c->eip);
3335 opcode = twobyte_table[c->b];
dde7e6d1
AK		 3336 }
3337 c->d = opcode.flags;
3338
3339 if (c->d & Group) {
3340 dual = c->d & GroupDual;
3341 c->modrm = insn_fetch(u8, 1, c->eip);
3342 --c->eip;
3343
3344 if (c->d & GroupDual) {
3345 g_mod012 = opcode.u.gdual->mod012;
3346 g_mod3 = opcode.u.gdual->mod3;
3347 } else
3348 g_mod012 = g_mod3 = opcode.u.group;
3349
3350 c->d &= ~(Group | GroupDual);
3351
3352 goffset = (c->modrm >> 3) & 7;
3353
3354 if ((c->modrm >> 6) == 3)
3355 opcode = g_mod3[goffset];
3356 else
3357 opcode = g_mod012[goffset];
01de8b09
JR		 3358
3359 if (opcode.flags & RMExt) {
3360 goffset = c->modrm & 7;
3361 opcode = opcode.u.group[goffset];
3362 }
3363
dde7e6d1
AK		 3364 c->d |= opcode.flags;
3365 }
3366
0d7cdee8
AK		 3367 if (c->d & Prefix) {
3368 if (c->rep_prefix && op_prefix)
3369 return X86EMUL_UNHANDLEABLE;
3370 simd_prefix = op_prefix ? 0x66 : c->rep_prefix;
3371 switch (simd_prefix) {
3372 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
3373 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
3374 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
3375 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
3376 }
3377 c->d |= opcode.flags;
3378 }
3379
dde7e6d1 3380 c->execute = opcode.u.execute;
d09beabd 3381 c->check_perm = opcode.check_perm;
c4f035c6 3382 c->intercept = opcode.intercept;
dde7e6d1
AK		 3383
3384 /* Unrecognised? */
d53db5ef 3385 if (c->d == 0 || (c->d & Undefined))
dde7e6d1 3386 return -1;
dde7e6d1 3387
d867162c
AK		 3388 if (!(c->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
3389 return -1;
3390
dde7e6d1
AK		 3391 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
3392 c->op_bytes = 8;
3393
7f9b4b75
AK		 3394 if (c->d & Op3264) {
3395 if (mode == X86EMUL_MODE_PROT64)
3396 c->op_bytes = 8;
3397 else
3398 c->op_bytes = 4;
3399 }
3400
1253791d
AK		 3401 if (c->d & Sse)
3402 c->op_bytes = 16;
3403
dde7e6d1 3404 /* ModRM and SIB bytes. */
09ee57cd 3405 if (c->d & ModRM) {
2dbd0dd7 3406 rc = decode_modrm(ctxt, ops, &memop);
09ee57cd
AK		 3407 if (!c->has_seg_override)
3408 set_seg_override(c, c->modrm_seg);
3409 } else if (c->d & MemAbs)
2dbd0dd7 3410 rc = decode_abs(ctxt, ops, &memop);
dde7e6d1
AK		 3411 if (rc != X86EMUL_CONTINUE)
3412 goto done;
3413
3414 if (!c->has_seg_override)
3415 set_seg_override(c, VCPU_SREG_DS);
3416
90de84f5 3417 memop.addr.mem.seg = seg_override(ctxt, ops, c);
dde7e6d1 3418
2dbd0dd7 3419 if (memop.type == OP_MEM && c->ad_bytes != 8)
90de84f5 3420 memop.addr.mem.ea = (u32)memop.addr.mem.ea;
dde7e6d1 3421
2dbd0dd7 3422 if (memop.type == OP_MEM && c->rip_relative)
90de84f5 3423 memop.addr.mem.ea += c->eip;
dde7e6d1
AK		 3424
3425 /*
3426 * Decode and fetch the source operand: register, memory
3427 * or immediate.
3428 */
3429 switch (c->d & SrcMask) {
3430 case SrcNone:
3431 break;
3432 case SrcReg:
1253791d 3433 decode_register_operand(ctxt, &c->src, c, 0);
dde7e6d1
AK		 3434 break;
3435 case SrcMem16:
2dbd0dd7 3436 memop.bytes = 2;
dde7e6d1
AK		 3437 goto srcmem_common;
3438 case SrcMem32:
2dbd0dd7 3439 memop.bytes = 4;
dde7e6d1
AK		 3440 goto srcmem_common;
3441 case SrcMem:
2dbd0dd7 3442 memop.bytes = (c->d & ByteOp) ? 1 :
dde7e6d1 3443 c->op_bytes;
dde7e6d1 3444 srcmem_common:
2dbd0dd7 3445 c->src = memop;
dde7e6d1 3446 break;
b250e605 3447 case SrcImmU16:
39f21ee5
AK		 3448 rc = decode_imm(ctxt, &c->src, 2, false);
3449 break;
dde7e6d1 3450 case SrcImm:
39f21ee5
AK		 3451 rc = decode_imm(ctxt, &c->src, imm_size(c), true);
3452 break;
dde7e6d1 3453 case SrcImmU:
39f21ee5 3454 rc = decode_imm(ctxt, &c->src, imm_size(c), false);
dde7e6d1
AK		 3455 break;
3456 case SrcImmByte:
39f21ee5
AK		 3457 rc = decode_imm(ctxt, &c->src, 1, true);
3458 break;
dde7e6d1 3459 case SrcImmUByte:
39f21ee5 3460 rc = decode_imm(ctxt, &c->src, 1, false);
dde7e6d1
AK		 3461 break;
3462 case SrcAcc:
3463 c->src.type = OP_REG;
3464 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1a6440ae 3465 c->src.addr.reg = &c->regs[VCPU_REGS_RAX];
91ff3cb4 3466 fetch_register_operand(&c->src);
dde7e6d1
AK		 3467 break;
3468 case SrcOne:
3469 c->src.bytes = 1;
3470 c->src.val = 1;
3471 break;
3472 case SrcSI:
3473 c->src.type = OP_MEM;
3474 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
90de84f5
AK		 3475 c->src.addr.mem.ea =
3476 register_address(c, c->regs[VCPU_REGS_RSI]);
3477 c->src.addr.mem.seg = seg_override(ctxt, ops, c),
dde7e6d1
AK		 3478 c->src.val = 0;
3479 break;
3480 case SrcImmFAddr:
3481 c->src.type = OP_IMM;
90de84f5 3482 c->src.addr.mem.ea = c->eip;
dde7e6d1
AK		 3483 c->src.bytes = c->op_bytes + 2;
3484 insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip);
3485 break;
3486 case SrcMemFAddr:
2dbd0dd7
AK		 3487 memop.bytes = c->op_bytes + 2;
3488 goto srcmem_common;
dde7e6d1
AK		 3489 break;
3490 }
3491
39f21ee5
AK		 3492 if (rc != X86EMUL_CONTINUE)
3493 goto done;
3494
dde7e6d1
AK		 3495 /*
3496 * Decode and fetch the second source operand: register, memory
3497 * or immediate.
3498 */
3499 switch (c->d & Src2Mask) {
3500 case Src2None:
3501 break;
3502 case Src2CL:
3503 c->src2.bytes = 1;
3504 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
3505 break;
3506 case Src2ImmByte:
39f21ee5 3507 rc = decode_imm(ctxt, &c->src2, 1, true);
dde7e6d1
AK		 3508 break;
3509 case Src2One:
3510 c->src2.bytes = 1;
3511 c->src2.val = 1;
3512 break;
7db41eb7
AK		 3513 case Src2Imm:
3514 rc = decode_imm(ctxt, &c->src2, imm_size(c), true);
3515 break;
dde7e6d1
AK		 3516 }
3517
39f21ee5
AK		 3518 if (rc != X86EMUL_CONTINUE)
3519 goto done;
3520
dde7e6d1
AK		 3521 /* Decode and fetch the destination operand: register or memory. */
3522 switch (c->d & DstMask) {
dde7e6d1 3523 case DstReg:
1253791d 3524 decode_register_operand(ctxt, &c->dst, c,
dde7e6d1
AK		 3525 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
3526 break;
943858e2
WY		 3527 case DstImmUByte:
3528 c->dst.type = OP_IMM;
90de84f5 3529 c->dst.addr.mem.ea = c->eip;
943858e2
WY		 3530 c->dst.bytes = 1;
3531 c->dst.val = insn_fetch(u8, 1, c->eip);
3532 break;
dde7e6d1
AK		 3533 case DstMem:
3534 case DstMem64:
2dbd0dd7 3535 c->dst = memop;
dde7e6d1
AK		 3536 if ((c->d & DstMask) == DstMem64)
3537 c->dst.bytes = 8;
3538 else
3539 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
35c843c4
WY		 3540 if (c->d & BitOp)
3541 fetch_bit_operand(c);
2dbd0dd7 3542 c->dst.orig_val = c->dst.val;
dde7e6d1
AK		 3543 break;
3544 case DstAcc:
3545 c->dst.type = OP_REG;
3546 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1a6440ae 3547 c->dst.addr.reg = &c->regs[VCPU_REGS_RAX];
91ff3cb4 3548 fetch_register_operand(&c->dst);
dde7e6d1
AK		 3549 c->dst.orig_val = c->dst.val;
3550 break;
3551 case DstDI:
3552 c->dst.type = OP_MEM;
3553 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
90de84f5
AK		 3554 c->dst.addr.mem.ea =
3555 register_address(c, c->regs[VCPU_REGS_RDI]);
3556 c->dst.addr.mem.seg = VCPU_SREG_ES;
dde7e6d1
AK		 3557 c->dst.val = 0;
3558 break;
36089fed
WY		 3559 case ImplicitOps:
3560 /* Special instructions do their own operand decoding. */
3561 default:
3562 c->dst.type = OP_NONE; /* Disable writeback. */
3563 return 0;
dde7e6d1
AK		 3564 }
3565
3566done:
a0c0ab2f 3567 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 3568}
3569
3e2f65d5
GN		 3570static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
3571{
3572 struct decode_cache *c = &ctxt->decode;
3573
3574 /* The second termination condition only applies for REPE
3575 * and REPNE. Test if the repeat string operation prefix is
3576 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
3577 * corresponding termination condition according to:
3578 * - if REPE/REPZ and ZF = 0 then done
3579 * - if REPNE/REPNZ and ZF = 1 then done
3580 */
3581 if (((c->b == 0xa6) || (c->b == 0xa7) ||
3582 (c->b == 0xae) || (c->b == 0xaf))
3583 && (((c->rep_prefix == REPE_PREFIX) &&
3584 ((ctxt->eflags & EFLG_ZF) == 0))
3585 || ((c->rep_prefix == REPNE_PREFIX) &&
3586 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
3587 return true;
3588
3589 return false;
3590}
3591
8b4caf66 3592int
9aabc88f 3593x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 3594{
9aabc88f 3595 struct x86_emulate_ops *ops = ctxt->ops;
8b4caf66 3596 u64 msr_data;
8b4caf66 3597 struct decode_cache *c = &ctxt->decode;
1b30eaa8 3598 int rc = X86EMUL_CONTINUE;
5cd21917 3599 int saved_dst_type = c->dst.type;
6e154e56 3600 int irq; /* Used for int 3, int, and into */
8b4caf66 3601
9de41573 3602 ctxt->decode.mem_read.pos = 0;
310b5d30 3603
1161624f 3604 if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
35d3d4a1 3605 rc = emulate_ud(ctxt);
1161624f
GN		 3606 goto done;
3607 }
3608
d380a5e4 3609 /* LOCK prefix is allowed only with some instructions */
a41ffb75 3610 if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) {
35d3d4a1 3611 rc = emulate_ud(ctxt);
d380a5e4
GN		 3612 goto done;
3613 }
3614
081bca0e 3615 if ((c->d & SrcMask) == SrcMemFAddr && c->src.type != OP_MEM) {
35d3d4a1 3616 rc = emulate_ud(ctxt);
081bca0e
AK		 3617 goto done;
3618 }
3619
1253791d 3620 if ((c->d & Sse)
717746e3
AK		 3621 && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)
3622 || !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
1253791d
AK		 3623 rc = emulate_ud(ctxt);
3624 goto done;
3625 }
3626
717746e3 3627 if ((c->d & Sse) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
1253791d
AK		 3628 rc = emulate_nm(ctxt);
3629 goto done;
3630 }
3631
c4f035c6 3632 if (unlikely(ctxt->guest_mode) && c->intercept) {
8a76d7f2
JR		 3633 rc = emulator_check_intercept(ctxt, c->intercept,
3634 X86_ICPT_PRE_EXCEPT);
c4f035c6
AK		 3635 if (rc != X86EMUL_CONTINUE)
3636 goto done;
3637 }
3638
e92805ac 3639 /* Privileged instruction can be executed only in CPL=0 */
717746e3 3640 if ((c->d & Priv) && ops->cpl(ctxt)) {
35d3d4a1 3641 rc = emulate_gp(ctxt, 0);
e92805ac
GN		 3642 goto done;
3643 }
3644
8ea7d6ae
JR		 3645 /* Instruction can only be executed in protected mode */
3646 if ((c->d & Prot) && !(ctxt->mode & X86EMUL_MODE_PROT)) {
3647 rc = emulate_ud(ctxt);
3648 goto done;
3649 }
3650
d09beabd
JR		 3651 /* Do instruction specific permission checks */
3652 if (c->check_perm) {
3653 rc = c->check_perm(ctxt);
3654 if (rc != X86EMUL_CONTINUE)
3655 goto done;
3656 }
3657
c4f035c6 3658 if (unlikely(ctxt->guest_mode) && c->intercept) {
8a76d7f2
JR		 3659 rc = emulator_check_intercept(ctxt, c->intercept,
3660 X86_ICPT_POST_EXCEPT);
c4f035c6
AK		 3661 if (rc != X86EMUL_CONTINUE)
3662 goto done;
3663 }
3664
b9fa9d6b
AK		 3665 if (c->rep_prefix && (c->d & String)) {
3666 /* All REP prefixes have the same first termination condition */
c73e197b 3667 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) {
95c55886 3668 ctxt->eip = c->eip;
b9fa9d6b
AK		 3669 goto done;
3670 }
b9fa9d6b
AK		 3671 }
3672
c483c02a 3673 if ((c->src.type == OP_MEM) && !(c->d & NoAccess)) {
3ca3ac4d
AK		 3674 rc = segmented_read(ctxt, c->src.addr.mem,
3675 c->src.valptr, c->src.bytes);
b60d513c 3676 if (rc != X86EMUL_CONTINUE)
8b4caf66 3677 goto done;
16518d5a 3678 c->src.orig_val64 = c->src.val64;
8b4caf66
LV		 3679 }
3680
e35b7b9c 3681 if (c->src2.type == OP_MEM) {
3ca3ac4d
AK		 3682 rc = segmented_read(ctxt, c->src2.addr.mem,
3683 &c->src2.val, c->src2.bytes);
e35b7b9c
GN		 3684 if (rc != X86EMUL_CONTINUE)
3685 goto done;
3686 }
3687
8b4caf66
LV		 3688 if ((c->d & DstMask) == ImplicitOps)
3689 goto special_insn;
3690
3691
69f55cb1
GN		 3692 if ((c->dst.type == OP_MEM) && !(c->d & Mov)) {
3693 /* optimisation - avoid slow emulated read if Mov */
3ca3ac4d 3694 rc = segmented_read(ctxt, c->dst.addr.mem,
9de41573 3695 &c->dst.val, c->dst.bytes);
69f55cb1
GN		 3696 if (rc != X86EMUL_CONTINUE)
3697 goto done;
038e51de 3698 }
e4e03ded 3699 c->dst.orig_val = c->dst.val;
038e51de 3700
018a98db
AK		 3701special_insn:
3702
c4f035c6 3703 if (unlikely(ctxt->guest_mode) && c->intercept) {
8a76d7f2
JR		 3704 rc = emulator_check_intercept(ctxt, c->intercept,
3705 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 3706 if (rc != X86EMUL_CONTINUE)
3707 goto done;
3708 }
3709
ef65c889
AK		 3710 if (c->execute) {
3711 rc = c->execute(ctxt);
3712 if (rc != X86EMUL_CONTINUE)
3713 goto done;
3714 goto writeback;
3715 }
3716
e4e03ded 3717 if (c->twobyte)
6aa8b732
AK		 3718 goto twobyte_insn;
3719
e4e03ded 3720 switch (c->b) {
6aa8b732
AK		 3721 case 0x00 ... 0x05:
3722 add: /* add */
05f086f8 3723 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
6aa8b732 3724 break;
0934ac9d 3725 case 0x06: /* push es */
4179bb02 3726 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_ES);
0934ac9d
MG		 3727 break;
3728 case 0x07: /* pop es */
0934ac9d 3729 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
0934ac9d 3730 break;
6aa8b732
AK		 3731 case 0x08 ... 0x0d:
3732 or: /* or */
05f086f8 3733 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
6aa8b732 3734 break;
0934ac9d 3735 case 0x0e: /* push cs */
4179bb02 3736 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_CS);
0934ac9d 3737 break;
6aa8b732
AK		 3738 case 0x10 ... 0x15:
3739 adc: /* adc */
05f086f8 3740 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
6aa8b732 3741 break;
0934ac9d 3742 case 0x16: /* push ss */
4179bb02 3743 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_SS);
0934ac9d
MG		 3744 break;
3745 case 0x17: /* pop ss */
0934ac9d 3746 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
0934ac9d 3747 break;
6aa8b732
AK		 3748 case 0x18 ... 0x1d:
3749 sbb: /* sbb */
05f086f8 3750 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
6aa8b732 3751 break;
0934ac9d 3752 case 0x1e: /* push ds */
4179bb02 3753 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_DS);
0934ac9d
MG		 3754 break;
3755 case 0x1f: /* pop ds */
0934ac9d 3756 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
0934ac9d 3757 break;
aa3a816b 3758 case 0x20 ... 0x25:
6aa8b732 3759 and: /* and */
05f086f8 3760 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 3761 break;
3762 case 0x28 ... 0x2d:
3763 sub: /* sub */
05f086f8 3764 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 3765 break;
3766 case 0x30 ... 0x35:
3767 xor: /* xor */
05f086f8 3768 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 3769 break;
3770 case 0x38 ... 0x3d:
3771 cmp: /* cmp */
575e7c14 3772 c->dst.type = OP_NONE; /* Disable writeback. */
05f086f8 3773 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
6aa8b732 3774 break;
33615aa9
AK		 3775 case 0x40 ... 0x47: /* inc r16/r32 */
3776 emulate_1op("inc", c->dst, ctxt->eflags);
3777 break;
3778 case 0x48 ... 0x4f: /* dec r16/r32 */
3779 emulate_1op("dec", c->dst, ctxt->eflags);
3780 break;
33615aa9
AK		 3781 case 0x58 ... 0x5f: /* pop reg */
3782 pop_instruction:
350f69dc 3783 rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes);
33615aa9 3784 break;
abcf14b5 3785 case 0x60: /* pusha */
4487b3b4 3786 rc = emulate_pusha(ctxt);
abcf14b5
MG		 3787 break;
3788 case 0x61: /* popa */
3789 rc = emulate_popa(ctxt, ops);
abcf14b5 3790 break;
6aa8b732 3791 case 0x63: /* movsxd */
8b4caf66 3792 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 3793 goto cannot_emulate;
e4e03ded 3794 c->dst.val = (s32) c->src.val;
6aa8b732 3795 break;
018a98db
AK		 3796 case 0x6c: /* insb */
3797 case 0x6d: /* insw/insd */
a13a63fa
WY		 3798 c->src.val = c->regs[VCPU_REGS_RDX];
3799 goto do_io_in;
018a98db
AK		 3800 case 0x6e: /* outsb */
3801 case 0x6f: /* outsw/outsd */
a13a63fa
WY		 3802 c->dst.val = c->regs[VCPU_REGS_RDX];
3803 goto do_io_out;
7972995b 3804 break;
b2833e3c 3805 case 0x70 ... 0x7f: /* jcc (short) */
018a98db 3806 if (test_cc(c->b, ctxt->eflags))
b2833e3c 3807 jmp_rel(c, c->src.val);
018a98db 3808 break;
6aa8b732 3809 case 0x80 ... 0x83: /* Grp1 */
e4e03ded 3810 switch (c->modrm_reg) {
6aa8b732
AK		 3811 case 0:
3812 goto add;
3813 case 1:
3814 goto or;
3815 case 2:
3816 goto adc;
3817 case 3:
3818 goto sbb;
3819 case 4:
3820 goto and;
3821 case 5:
3822 goto sub;
3823 case 6:
3824 goto xor;
3825 case 7:
3826 goto cmp;
3827 }
3828 break;
3829 case 0x84 ... 0x85:
dfb507c4 3830 test:
05f086f8 3831 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 3832 break;
3833 case 0x86 ... 0x87: /* xchg */
b13354f8 3834 xchg:
6aa8b732 3835 /* Write back the register source. */
31be40b3
WY		 3836 c->src.val = c->dst.val;
3837 write_register_operand(&c->src);
6aa8b732
AK		 3838 /*
3839 * Write back the memory destination with implicit LOCK
3840 * prefix.
3841 */
31be40b3 3842 c->dst.val = c->src.orig_val;
e4e03ded 3843 c->lock_prefix = 1;
6aa8b732 3844 break;
79168fd1
GN		 3845 case 0x8c: /* mov r/m, sreg */
3846 if (c->modrm_reg > VCPU_SREG_GS) {
35d3d4a1 3847 rc = emulate_ud(ctxt);
5e3ae6c5 3848 goto done;
38d5bc6d 3849 }
4bff1e86 3850 c->dst.val = ops->get_segment_selector(ctxt, c->modrm_reg);
38d5bc6d 3851 break;
7e0b54b1 3852 case 0x8d: /* lea r16/r32, m */
90de84f5 3853 c->dst.val = c->src.addr.mem.ea;
7e0b54b1 3854 break;
4257198a
GT		 3855 case 0x8e: { /* mov seg, r/m16 */
3856 uint16_t sel;
4257198a
GT		 3857
3858 sel = c->src.val;
8b9f4414 3859
c697518a
GN		 3860 if (c->modrm_reg == VCPU_SREG_CS ||
3861 c->modrm_reg > VCPU_SREG_GS) {
35d3d4a1 3862 rc = emulate_ud(ctxt);
8b9f4414
GN		 3863 goto done;
3864 }
3865
310b5d30 3866 if (c->modrm_reg == VCPU_SREG_SS)
95cb2295 3867 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
310b5d30 3868
2e873022 3869 rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg);
4257198a
GT		 3870
3871 c->dst.type = OP_NONE; /* Disable writeback. */
3872 break;
3873 }
6aa8b732 3874 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9 3875 rc = emulate_grp1a(ctxt, ops);
6aa8b732 3876 break;
3d9e77df
AK		 3877 case 0x90 ... 0x97: /* nop / xchg reg, rax */
3878 if (c->dst.addr.reg == &c->regs[VCPU_REGS_RAX])
34698d8c 3879 break;
b13354f8 3880 goto xchg;
e8b6fa70
WY		 3881 case 0x98: /* cbw/cwde/cdqe */
3882 switch (c->op_bytes) {
3883 case 2: c->dst.val = (s8)c->dst.val; break;
3884 case 4: c->dst.val = (s16)c->dst.val; break;
3885 case 8: c->dst.val = (s32)c->dst.val; break;
3886 }
3887 break;
fd2a7608 3888 case 0x9c: /* pushf */
05f086f8 3889 c->src.val = (unsigned long) ctxt->eflags;
4487b3b4 3890 rc = em_push(ctxt);
8cdbd2c9 3891 break;
535eabcf 3892 case 0x9d: /* popf */
2b48cc75 3893 c->dst.type = OP_REG;
1a6440ae 3894 c->dst.addr.reg = &ctxt->eflags;
2b48cc75 3895 c->dst.bytes = c->op_bytes;
d4c6a154 3896 rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes);
d4c6a154 3897 break;
6aa8b732 3898 case 0xa6 ... 0xa7: /* cmps */
a682e354 3899 goto cmp;
dfb507c4
MG		 3900 case 0xa8 ... 0xa9: /* test ax, imm */
3901 goto test;
6aa8b732 3902 case 0xae ... 0xaf: /* scas */
f6b33fc5 3903 goto cmp;
018a98db
AK		 3904 case 0xc0 ... 0xc1:
3905 emulate_grp2(ctxt);
3906 break;
111de5d6 3907 case 0xc3: /* ret */
cf5de4f8 3908 c->dst.type = OP_REG;
1a6440ae 3909 c->dst.addr.reg = &c->eip;
cf5de4f8 3910 c->dst.bytes = c->op_bytes;
111de5d6 3911 goto pop_instruction;
09b5f4d3
WY		 3912 case 0xc4: /* les */
3913 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_ES);
09b5f4d3
WY		 3914 break;
3915 case 0xc5: /* lds */
3916 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_DS);
09b5f4d3 3917 break;
a77ab5ea
AK		 3918 case 0xcb: /* ret far */
3919 rc = emulate_ret_far(ctxt, ops);
62bd430e 3920 break;
6e154e56
MG		 3921 case 0xcc: /* int3 */
3922 irq = 3;
3923 goto do_interrupt;
3924 case 0xcd: /* int n */
3925 irq = c->src.val;
3926 do_interrupt:
3927 rc = emulate_int(ctxt, ops, irq);
6e154e56
MG		 3928 break;
3929 case 0xce: /* into */
3930 if (ctxt->eflags & EFLG_OF) {
3931 irq = 4;
3932 goto do_interrupt;
3933 }
3934 break;
62bd430e
MG		 3935 case 0xcf: /* iret */
3936 rc = emulate_iret(ctxt, ops);
a77ab5ea 3937 break;
018a98db 3938 case 0xd0 ... 0xd1: /* Grp2 */
018a98db
AK		 3939 emulate_grp2(ctxt);
3940 break;
3941 case 0xd2 ... 0xd3: /* Grp2 */
3942 c->src.val = c->regs[VCPU_REGS_RCX];
3943 emulate_grp2(ctxt);
3944 break;
f2f31845
WY		 3945 case 0xe0 ... 0xe2: /* loop/loopz/loopnz */
3946 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
3947 if (address_mask(c, c->regs[VCPU_REGS_RCX]) != 0 &&
3948 (c->b == 0xe2 || test_cc(c->b ^ 0x5, ctxt->eflags)))
3949 jmp_rel(c, c->src.val);
3950 break;
e4abac67
WY		 3951 case 0xe3: /* jcxz/jecxz/jrcxz */
3952 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0)
3953 jmp_rel(c, c->src.val);
3954 break;
a6a3034c
MG		 3955 case 0xe4: /* inb */
3956 case 0xe5: /* in */
cf8f70bf 3957 goto do_io_in;
a6a3034c
MG		 3958 case 0xe6: /* outb */
3959 case 0xe7: /* out */
cf8f70bf 3960 goto do_io_out;
1a52e051 3961 case 0xe8: /* call (near) */ {
d53c4777 3962 long int rel = c->src.val;
e4e03ded 3963 c->src.val = (unsigned long) c->eip;
7a957275 3964 jmp_rel(c, rel);
4487b3b4 3965 rc = em_push(ctxt);
8cdbd2c9 3966 break;
1a52e051
NK		 3967 }
3968 case 0xe9: /* jmp rel */
954cd36f 3969 goto jmp;
414e6277
GN		 3970 case 0xea: { /* jmp far */
3971 unsigned short sel;
ea79849d 3972 jump_far:
414e6277
GN		 3973 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
3974
3975 if (load_segment_descriptor(ctxt, ops, sel, VCPU_SREG_CS))
c697518a 3976 goto done;
954cd36f 3977
414e6277
GN		 3978 c->eip = 0;
3979 memcpy(&c->eip, c->src.valptr, c->op_bytes);
954cd36f 3980 break;
414e6277 3981 }
954cd36f
GT		 3982 case 0xeb:
3983 jmp: /* jmp rel short */
7a957275 3984 jmp_rel(c, c->src.val);
a01af5ec 3985 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 3986 break;
a6a3034c
MG		 3987 case 0xec: /* in al,dx */
3988 case 0xed: /* in (e/r)ax,dx */
cf8f70bf
GN		 3989 c->src.val = c->regs[VCPU_REGS_RDX];
3990 do_io_in:
7b262e90
GN		 3991 if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val,
3992 &c->dst.val))
cf8f70bf
GN		 3993 goto done; /* IO is needed */
3994 break;
ce7a0ad3
WY		 3995 case 0xee: /* out dx,al */
3996 case 0xef: /* out dx,(e/r)ax */
41167be5 3997 c->dst.val = c->regs[VCPU_REGS_RDX];
cf8f70bf 3998 do_io_out:
ca1d4a9e
AK		 3999 ops->pio_out_emulated(ctxt, c->src.bytes, c->dst.val,
4000 &c->src.val, 1);
cf8f70bf 4001 c->dst.type = OP_NONE; /* Disable writeback. */
e93f36bc 4002 break;
111de5d6 4003 case 0xf4: /* hlt */
6c3287f7 4004 ctxt->ops->halt(ctxt);
19fdfa0d 4005 break;
111de5d6
AK		 4006 case 0xf5: /* cmc */
4007 /* complement carry flag from eflags reg */
4008 ctxt->eflags ^= EFLG_CF;
111de5d6 4009 break;
018a98db 4010 case 0xf6 ... 0xf7: /* Grp3 */
34d1f490 4011 rc = emulate_grp3(ctxt, ops);
018a98db 4012 break;
111de5d6
AK		 4013 case 0xf8: /* clc */
4014 ctxt->eflags &= ~EFLG_CF;
111de5d6 4015 break;
8744aa9a
MG		 4016 case 0xf9: /* stc */
4017 ctxt->eflags |= EFLG_CF;
4018 break;
111de5d6 4019 case 0xfa: /* cli */
07cbc6c1 4020 if (emulator_bad_iopl(ctxt, ops)) {
35d3d4a1 4021 rc = emulate_gp(ctxt, 0);
07cbc6c1 4022 goto done;
36089fed 4023 } else
f850e2e6 4024 ctxt->eflags &= ~X86_EFLAGS_IF;
111de5d6
AK		 4025 break;
4026 case 0xfb: /* sti */
07cbc6c1 4027 if (emulator_bad_iopl(ctxt, ops)) {
35d3d4a1 4028 rc = emulate_gp(ctxt, 0);
07cbc6c1
WY		 4029 goto done;
4030 } else {
95cb2295 4031 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
f850e2e6 4032 ctxt->eflags |= X86_EFLAGS_IF;
f850e2e6 4033 }
111de5d6 4034 break;
fb4616f4
MG		 4035 case 0xfc: /* cld */
4036 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 4037 break;
4038 case 0xfd: /* std */
4039 ctxt->eflags |= EFLG_DF;
fb4616f4 4040 break;
ea79849d
GN		 4041 case 0xfe: /* Grp4 */
4042 grp45:
4487b3b4 4043 rc = emulate_grp45(ctxt);
018a98db 4044 break;
ea79849d
GN		 4045 case 0xff: /* Grp5 */
4046 if (c->modrm_reg == 5)
4047 goto jump_far;
4048 goto grp45;
91269b8f
AK		 4049 default:
4050 goto cannot_emulate;
6aa8b732 4051 }
018a98db 4052
7d9ddaed
AK		 4053 if (rc != X86EMUL_CONTINUE)
4054 goto done;
4055
018a98db
AK		 4056writeback:
4057 rc = writeback(ctxt, ops);
1b30eaa8 4058 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 4059 goto done;
4060
5cd21917
GN		 4061 /*
4062 * restore dst type in case the decoding will be reused
4063 * (happens for string instruction )
4064 */
4065 c->dst.type = saved_dst_type;
4066
a682e354 4067 if ((c->d & SrcMask) == SrcSI)
90de84f5 4068 string_addr_inc(ctxt, seg_override(ctxt, ops, c),
79168fd1 4069 VCPU_REGS_RSI, &c->src);
a682e354
GN		 4070
4071 if ((c->d & DstMask) == DstDI)
90de84f5 4072 string_addr_inc(ctxt, VCPU_SREG_ES, VCPU_REGS_RDI,
79168fd1 4073 &c->dst);
d9271123 4074
5cd21917 4075 if (c->rep_prefix && (c->d & String)) {
6e2fb2ca 4076 struct read_cache *r = &ctxt->decode.io_read;
d9271123 4077 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
3e2f65d5 4078
d2ddd1c4
GN		 4079 if (!string_insn_completed(ctxt)) {
4080 /*
4081 * Re-enter guest when pio read ahead buffer is empty
4082 * or, if it is not used, after each 1024 iteration.
4083 */
4084 if ((r->end != 0 || c->regs[VCPU_REGS_RCX] & 0x3ff) &&
4085 (r->end == 0 || r->end != r->pos)) {
4086 /*
4087 * Reset read cache. Usually happens before
4088 * decode, but since instruction is restarted
4089 * we have to do it here.
4090 */
4091 ctxt->decode.mem_read.end = 0;
4092 return EMULATION_RESTART;
4093 }
4094 goto done; /* skip rip writeback */
0fa6ccbd 4095 }
5cd21917 4096 }
d2ddd1c4
GN		 4097
4098 ctxt->eip = c->eip;
018a98db
AK		 4099
4100done:
da9cb575
AK		 4101 if (rc == X86EMUL_PROPAGATE_FAULT)
4102 ctxt->have_exception = true;
775fde86
JR		 4103 if (rc == X86EMUL_INTERCEPTED)
4104 return EMULATION_INTERCEPTED;
4105
d2ddd1c4 4106 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 4107
4108twobyte_insn:
e4e03ded 4109 switch (c->b) {
6aa8b732 4110 case 0x01: /* lgdt, lidt, lmsw */
e4e03ded 4111 switch (c->modrm_reg) {
aca7f966 4112 case 0: /* vmcall */
26d05cc7 4113 rc = em_vmcall(ctxt);
aca7f966 4114 break;
6aa8b732 4115 case 2: /* lgdt */
26d05cc7 4116 rc = em_lgdt(ctxt);
6aa8b732 4117 break;
aca7f966 4118 case 3: /* lidt/vmmcall */
26d05cc7
AK		 4119 if (c->modrm_mod == 3)
4120 return em_svm(ctxt);
4121 else
4122 return em_lidt(ctxt);
6aa8b732
AK		 4123 break;
4124 case 4: /* smsw */
26d05cc7 4125 rc = em_smsw(ctxt);
6aa8b732
AK		 4126 break;
4127 case 6: /* lmsw */
26d05cc7 4128 rc = em_lmsw(ctxt);
6aa8b732
AK		 4129 break;
4130 case 7: /* invlpg*/
38503911 4131 rc = em_invlpg(ctxt);
6aa8b732
AK		 4132 break;
4133 default:
4134 goto cannot_emulate;
4135 }
4136 break;
e99f0507 4137 case 0x05: /* syscall */
3fb1b5db 4138 rc = emulate_syscall(ctxt, ops);
e99f0507 4139 break;
018a98db 4140 case 0x06:
2d04a05b 4141 rc = em_clts(ctxt);
018a98db 4142 break;
018a98db 4143 case 0x09: /* wbinvd */
cfb22375 4144 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 4145 break;
4146 case 0x08: /* invd */
018a98db
AK		 4147 case 0x0d: /* GrpP (prefetch) */
4148 case 0x18: /* Grp16 (prefetch/nop) */
018a98db
AK		 4149 break;
4150 case 0x20: /* mov cr, reg */
717746e3 4151 c->dst.val = ops->get_cr(ctxt, c->modrm_reg);
018a98db 4152 break;
6aa8b732 4153 case 0x21: /* mov from dr to reg */
717746e3 4154 ops->get_dr(ctxt, c->modrm_reg, &c->dst.val);
6aa8b732 4155 break;
018a98db 4156 case 0x22: /* mov reg, cr */
717746e3 4157 if (ops->set_cr(ctxt, c->modrm_reg, c->src.val)) {
54b8486f 4158 emulate_gp(ctxt, 0);
da9cb575 4159 rc = X86EMUL_PROPAGATE_FAULT;
0f12244f
GN		 4160 goto done;
4161 }
018a98db
AK		 4162 c->dst.type = OP_NONE;
4163 break;
6aa8b732 4164 case 0x23: /* mov from reg to dr */
717746e3 4165 if (ops->set_dr(ctxt, c->modrm_reg, c->src.val &
338dbc97 4166 ((ctxt->mode == X86EMUL_MODE_PROT64) ?
717746e3 4167 ~0ULL : ~0U)) < 0) {
338dbc97 4168 /* #UD condition is already handled by the code above */
54b8486f 4169 emulate_gp(ctxt, 0);
da9cb575 4170 rc = X86EMUL_PROPAGATE_FAULT;
338dbc97
GN		 4171 goto done;
4172 }
4173
a01af5ec 4174 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 4175 break;
018a98db
AK		 4176 case 0x30:
4177 /* wrmsr */
4178 msr_data = (u32)c->regs[VCPU_REGS_RAX]
4179 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
717746e3 4180 if (ops->set_msr(ctxt, c->regs[VCPU_REGS_RCX], msr_data)) {
54b8486f 4181 emulate_gp(ctxt, 0);
da9cb575 4182 rc = X86EMUL_PROPAGATE_FAULT;
fd525365 4183 goto done;
018a98db
AK		 4184 }
4185 rc = X86EMUL_CONTINUE;
018a98db
AK		 4186 break;
4187 case 0x32:
4188 /* rdmsr */
717746e3 4189 if (ops->get_msr(ctxt, c->regs[VCPU_REGS_RCX], &msr_data)) {
54b8486f 4190 emulate_gp(ctxt, 0);
da9cb575 4191 rc = X86EMUL_PROPAGATE_FAULT;
fd525365 4192 goto done;
018a98db
AK		 4193 } else {
4194 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
4195 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
4196 }
4197 rc = X86EMUL_CONTINUE;
018a98db 4198 break;
e99f0507 4199 case 0x34: /* sysenter */
3fb1b5db 4200 rc = emulate_sysenter(ctxt, ops);
e99f0507
AP		 4201 break;
4202 case 0x35: /* sysexit */
3fb1b5db 4203 rc = emulate_sysexit(ctxt, ops);
e99f0507 4204 break;
6aa8b732 4205 case 0x40 ... 0x4f: /* cmov */
e4e03ded 4206 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 4207 if (!test_cc(c->b, ctxt->eflags))
4208 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 4209 break;
b2833e3c 4210 case 0x80 ... 0x8f: /* jnz rel, etc*/
018a98db 4211 if (test_cc(c->b, ctxt->eflags))
b2833e3c 4212 jmp_rel(c, c->src.val);
018a98db 4213 break;
ee45b58e
WY		 4214 case 0x90 ... 0x9f: /* setcc r/m8 */
4215 c->dst.val = test_cc(c->b, ctxt->eflags);
4216 break;
0934ac9d 4217 case 0xa0: /* push fs */
4179bb02 4218 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_FS);
0934ac9d
MG		 4219 break;
4220 case 0xa1: /* pop fs */
4221 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
0934ac9d 4222 break;
7de75248
NK		 4223 case 0xa3:
4224 bt: /* bt */
e4f8e039 4225 c->dst.type = OP_NONE;
e4e03ded
LV		 4226 /* only subword offset */
4227 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 4228 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248 4229 break;
9bf8ea42
GT		 4230 case 0xa4: /* shld imm8, r, r/m */
4231 case 0xa5: /* shld cl, r, r/m */
4232 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
4233 break;
0934ac9d 4234 case 0xa8: /* push gs */
4179bb02 4235 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_GS);
0934ac9d
MG		 4236 break;
4237 case 0xa9: /* pop gs */
4238 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
0934ac9d 4239 break;
7de75248
NK		 4240 case 0xab:
4241 bts: /* bts */
05f086f8 4242 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 4243 break;
9bf8ea42
GT		 4244 case 0xac: /* shrd imm8, r, r/m */
4245 case 0xad: /* shrd cl, r, r/m */
4246 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
4247 break;
2a7c5b8b
GC		 4248 case 0xae: /* clflush */
4249 break;
6aa8b732
AK		 4250 case 0xb0 ... 0xb1: /* cmpxchg */
4251 /*
4252 * Save real source value, then compare EAX against
4253 * destination.
4254 */
e4e03ded
LV		 4255 c->src.orig_val = c->src.val;
4256 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 4257 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
4258 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 4259 /* Success: write back to memory. */
e4e03ded 4260 c->dst.val = c->src.orig_val;
6aa8b732
AK		 4261 } else {
4262 /* Failure: write the value we saw to EAX. */
e4e03ded 4263 c->dst.type = OP_REG;
1a6440ae 4264 c->dst.addr.reg = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 4265 }
4266 break;
09b5f4d3
WY		 4267 case 0xb2: /* lss */
4268 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_SS);
09b5f4d3 4269 break;
6aa8b732
AK		 4270 case 0xb3:
4271 btr: /* btr */
05f086f8 4272 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 4273 break;
09b5f4d3
WY		 4274 case 0xb4: /* lfs */
4275 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_FS);
09b5f4d3
WY		 4276 break;
4277 case 0xb5: /* lgs */
4278 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_GS);
09b5f4d3 4279 break;
6aa8b732 4280 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 4281 c->dst.bytes = c->op_bytes;
4282 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
4283 : (u16) c->src.val;
6aa8b732 4284 break;
6aa8b732 4285 case 0xba: /* Grp8 */
e4e03ded 4286 switch (c->modrm_reg & 3) {
6aa8b732
AK		 4287 case 0:
4288 goto bt;
4289 case 1:
4290 goto bts;
4291 case 2:
4292 goto btr;
4293 case 3:
4294 goto btc;
4295 }
4296 break;
7de75248
NK		 4297 case 0xbb:
4298 btc: /* btc */
05f086f8 4299 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 4300 break;
d9574a25
WY		 4301 case 0xbc: { /* bsf */
4302 u8 zf;
4303 __asm__ ("bsf %2, %0; setz %1"
4304 : "=r"(c->dst.val), "=q"(zf)
4305 : "r"(c->src.val));
4306 ctxt->eflags &= ~X86_EFLAGS_ZF;
4307 if (zf) {
4308 ctxt->eflags |= X86_EFLAGS_ZF;
4309 c->dst.type = OP_NONE; /* Disable writeback. */
4310 }
4311 break;
4312 }
4313 case 0xbd: { /* bsr */
4314 u8 zf;
4315 __asm__ ("bsr %2, %0; setz %1"
4316 : "=r"(c->dst.val), "=q"(zf)
4317 : "r"(c->src.val));
4318 ctxt->eflags &= ~X86_EFLAGS_ZF;
4319 if (zf) {
4320 ctxt->eflags |= X86_EFLAGS_ZF;
4321 c->dst.type = OP_NONE; /* Disable writeback. */
4322 }
4323 break;
4324 }
6aa8b732 4325 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 4326 c->dst.bytes = c->op_bytes;
4327 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
4328 (s16) c->src.val;
6aa8b732 4329 break;
92f738a5
WY		 4330 case 0xc0 ... 0xc1: /* xadd */
4331 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
4332 /* Write back the register source. */
4333 c->src.val = c->dst.orig_val;
4334 write_register_operand(&c->src);
4335 break;
a012e65a 4336 case 0xc3: /* movnti */
e4e03ded
LV		 4337 c->dst.bytes = c->op_bytes;
4338 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
4339 (u64) c->src.val;
a012e65a 4340 break;
6aa8b732 4341 case 0xc7: /* Grp9 (cmpxchg8b) */
69f55cb1 4342 rc = emulate_grp9(ctxt, ops);
8cdbd2c9 4343 break;
91269b8f
AK		 4344 default:
4345 goto cannot_emulate;
6aa8b732 4346 }
7d9ddaed
AK		 4347
4348 if (rc != X86EMUL_CONTINUE)
4349 goto done;
4350
6aa8b732
AK		 4351 goto writeback;
4352
4353cannot_emulate:
a0c0ab2f 4354 return EMULATION_FAILED;
6aa8b732 4355}
Linux 6.x block layer and io_uring tree(s)