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KVM: PPC: book3s: fix build error caused by gfn_to_hva_memslot()
[linux-2.6-block.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
6aa8b732 27
3eeb3288 28#include "x86.h"
38ba30ba 29#include "tss.h"
e99f0507 30
a9945549
AK		 31/*
32 * Operand types
33 */
b1ea50b2
AK		 34#define OpNone 0ull
35#define OpImplicit 1ull /* No generic decode */
36#define OpReg 2ull /* Register */
37#define OpMem 3ull /* Memory */
38#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
39#define OpDI 5ull /* ES:DI/EDI/RDI */
40#define OpMem64 6ull /* Memory, 64-bit */
41#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
42#define OpDX 8ull /* DX register */
4dd6a57d
AK		 43#define OpCL 9ull /* CL register (for shifts) */
44#define OpImmByte 10ull /* 8-bit sign extended immediate */
45#define OpOne 11ull /* Implied 1 */
46#define OpImm 12ull /* Sign extended immediate */
0fe59128
AK		 47#define OpMem16 13ull /* Memory operand (16-bit). */
48#define OpMem32 14ull /* Memory operand (32-bit). */
49#define OpImmU 15ull /* Immediate operand, zero extended */
50#define OpSI 16ull /* SI/ESI/RSI */
51#define OpImmFAddr 17ull /* Immediate far address */
52#define OpMemFAddr 18ull /* Far address in memory */
53#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 54#define OpES 20ull /* ES */
55#define OpCS 21ull /* CS */
56#define OpSS 22ull /* SS */
57#define OpDS 23ull /* DS */
58#define OpFS 24ull /* FS */
59#define OpGS 25ull /* GS */
28867cee 60#define OpMem8 26ull /* 8-bit zero extended memory operand */
0fe59128
AK		 61
62#define OpBits 5 /* Width of operand field */
b1ea50b2 63#define OpMask ((1ull << OpBits) - 1)
a9945549 64
6aa8b732
AK		 65/*
66 * Opcode effective-address decode tables.
67 * Note that we only emulate instructions that have at least one memory
68 * operand (excluding implicit stack references). We assume that stack
69 * references and instruction fetches will never occur in special memory
70 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
71 * not be handled.
72 */
73
74/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 75#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 76/* Destination operand type. */
a9945549
AK		 77#define DstShift 1
78#define ImplicitOps (OpImplicit << DstShift)
79#define DstReg (OpReg << DstShift)
80#define DstMem (OpMem << DstShift)
81#define DstAcc (OpAcc << DstShift)
82#define DstDI (OpDI << DstShift)
83#define DstMem64 (OpMem64 << DstShift)
84#define DstImmUByte (OpImmUByte << DstShift)
85#define DstDX (OpDX << DstShift)
86#define DstMask (OpMask << DstShift)
6aa8b732 87/* Source operand type. */
0fe59128
AK		 88#define SrcShift 6
89#define SrcNone (OpNone << SrcShift)
90#define SrcReg (OpReg << SrcShift)
91#define SrcMem (OpMem << SrcShift)
92#define SrcMem16 (OpMem16 << SrcShift)
93#define SrcMem32 (OpMem32 << SrcShift)
94#define SrcImm (OpImm << SrcShift)
95#define SrcImmByte (OpImmByte << SrcShift)
96#define SrcOne (OpOne << SrcShift)
97#define SrcImmUByte (OpImmUByte << SrcShift)
98#define SrcImmU (OpImmU << SrcShift)
99#define SrcSI (OpSI << SrcShift)
100#define SrcImmFAddr (OpImmFAddr << SrcShift)
101#define SrcMemFAddr (OpMemFAddr << SrcShift)
102#define SrcAcc (OpAcc << SrcShift)
103#define SrcImmU16 (OpImmU16 << SrcShift)
104#define SrcDX (OpDX << SrcShift)
28867cee 105#define SrcMem8 (OpMem8 << SrcShift)
0fe59128 106#define SrcMask (OpMask << SrcShift)
221192bd
MT		 107#define BitOp (1<<11)
108#define MemAbs (1<<12) /* Memory operand is absolute displacement */
109#define String (1<<13) /* String instruction (rep capable) */
110#define Stack (1<<14) /* Stack instruction (push/pop) */
111#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
112#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
113#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
114#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
115#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
116#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 117/* Generic ModRM decode. */
118#define ModRM (1<<19)
119/* Destination is only written; never read. */
120#define Mov (1<<20)
d8769fed 121/* Misc flags */
8ea7d6ae 122#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
d867162c 123#define VendorSpecific (1<<22) /* Vendor specific instruction */
5a506b12 124#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 125#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 126#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 127#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 128#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 129#define No64 (1<<28)
d5ae7ce8 130#define PageTable (1 << 29) /* instruction used to write page table */
0dc8d10f 131/* Source 2 operand type */
d5ae7ce8 132#define Src2Shift (30)
4dd6a57d
AK		 133#define Src2None (OpNone << Src2Shift)
134#define Src2CL (OpCL << Src2Shift)
135#define Src2ImmByte (OpImmByte << Src2Shift)
136#define Src2One (OpOne << Src2Shift)
137#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 138#define Src2ES (OpES << Src2Shift)
139#define Src2CS (OpCS << Src2Shift)
140#define Src2SS (OpSS << Src2Shift)
141#define Src2DS (OpDS << Src2Shift)
142#define Src2FS (OpFS << Src2Shift)
143#define Src2GS (OpGS << Src2Shift)
4dd6a57d 144#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 145#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
1c11b376
AK		 146#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
147#define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
148#define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
6aa8b732 149
d0e53325
AK		 150#define X2(x...) x, x
151#define X3(x...) X2(x), x
152#define X4(x...) X2(x), X2(x)
153#define X5(x...) X4(x), x
154#define X6(x...) X4(x), X2(x)
155#define X7(x...) X4(x), X3(x)
156#define X8(x...) X4(x), X4(x)
157#define X16(x...) X8(x), X8(x)
83babbca 158
d65b1dee 159struct opcode {
b1ea50b2
AK		 160 u64 flags : 56;
161 u64 intercept : 8;
120df890 162 union {
ef65c889 163 int (*execute)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 164 struct opcode *group;
165 struct group_dual *gdual;
0d7cdee8 166 struct gprefix *gprefix;
120df890 167 } u;
d09beabd 168 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 169};
170
171struct group_dual {
172 struct opcode mod012[8];
173 struct opcode mod3[8];
d65b1dee
AK		 174};
175
0d7cdee8
AK		 176struct gprefix {
177 struct opcode pfx_no;
178 struct opcode pfx_66;
179 struct opcode pfx_f2;
180 struct opcode pfx_f3;
181};
182
6aa8b732 183/* EFLAGS bit definitions. */
d4c6a154
GN		 184#define EFLG_ID (1<<21)
185#define EFLG_VIP (1<<20)
186#define EFLG_VIF (1<<19)
187#define EFLG_AC (1<<18)
b1d86143
AP		 188#define EFLG_VM (1<<17)
189#define EFLG_RF (1<<16)
d4c6a154
GN		 190#define EFLG_IOPL (3<<12)
191#define EFLG_NT (1<<14)
6aa8b732
AK		 192#define EFLG_OF (1<<11)
193#define EFLG_DF (1<<10)
b1d86143 194#define EFLG_IF (1<<9)
d4c6a154 195#define EFLG_TF (1<<8)
6aa8b732
AK		 196#define EFLG_SF (1<<7)
197#define EFLG_ZF (1<<6)
198#define EFLG_AF (1<<4)
199#define EFLG_PF (1<<2)
200#define EFLG_CF (1<<0)
201
62bd430e
MG		 202#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
203#define EFLG_RESERVED_ONE_MASK 2
204
6aa8b732
AK		 205/*
206 * Instruction emulation:
207 * Most instructions are emulated directly via a fragment of inline assembly
208 * code. This allows us to save/restore EFLAGS and thus very easily pick up
209 * any modified flags.
210 */
211
05b3e0c2 212#if defined(CONFIG_X86_64)
6aa8b732
AK		 213#define _LO32 "k" /* force 32-bit operand */
214#define _STK "%%rsp" /* stack pointer */
215#elif defined(__i386__)
216#define _LO32 "" /* force 32-bit operand */
217#define _STK "%%esp" /* stack pointer */
218#endif
219
220/*
221 * These EFLAGS bits are restored from saved value during emulation, and
222 * any changes are written back to the saved value after emulation.
223 */
224#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
225
226/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 227#define _PRE_EFLAGS(_sav, _msk, _tmp) \
228 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
229 "movl %"_sav",%"_LO32 _tmp"; " \
230 "push %"_tmp"; " \
231 "push %"_tmp"; " \
232 "movl %"_msk",%"_LO32 _tmp"; " \
233 "andl %"_LO32 _tmp",("_STK"); " \
234 "pushf; " \
235 "notl %"_LO32 _tmp"; " \
236 "andl %"_LO32 _tmp",("_STK"); " \
237 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
238 "pop %"_tmp"; " \
239 "orl %"_LO32 _tmp",("_STK"); " \
240 "popf; " \
241 "pop %"_sav"; "
6aa8b732
AK		 242
243/* After executing instruction: write-back necessary bits in EFLAGS. */
244#define _POST_EFLAGS(_sav, _msk, _tmp) \
245 /* _sav |= EFLAGS & _msk; */ \
246 "pushf; " \
247 "pop %"_tmp"; " \
248 "andl %"_msk",%"_LO32 _tmp"; " \
249 "orl %"_LO32 _tmp",%"_sav"; "
250
dda96d8f
AK		 251#ifdef CONFIG_X86_64
252#define ON64(x) x
253#else
254#define ON64(x)
255#endif
256
a31b9cea 257#define ____emulate_2op(ctxt, _op, _x, _y, _suffix, _dsttype) \
6b7ad61f
AK		 258 do { \
259 __asm__ __volatile__ ( \
260 _PRE_EFLAGS("0", "4", "2") \
261 _op _suffix " %"_x"3,%1; " \
262 _POST_EFLAGS("0", "4", "2") \
a31b9cea
AK		 263 : "=m" ((ctxt)->eflags), \
264 "+q" (*(_dsttype*)&(ctxt)->dst.val), \
6b7ad61f 265 "=&r" (_tmp) \
a31b9cea 266 : _y ((ctxt)->src.val), "i" (EFLAGS_MASK)); \
f3fd92fb 267 } while (0)
6b7ad61f
AK		 268
269
6aa8b732 270/* Raw emulation: instruction has two explicit operands. */
a31b9cea 271#define __emulate_2op_nobyte(ctxt,_op,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 272 do { \
273 unsigned long _tmp; \
274 \
a31b9cea 275 switch ((ctxt)->dst.bytes) { \
6b7ad61f 276 case 2: \
a31b9cea 277 ____emulate_2op(ctxt,_op,_wx,_wy,"w",u16); \
6b7ad61f
AK		 278 break; \
279 case 4: \
a31b9cea 280 ____emulate_2op(ctxt,_op,_lx,_ly,"l",u32); \
6b7ad61f
AK		 281 break; \
282 case 8: \
a31b9cea 283 ON64(____emulate_2op(ctxt,_op,_qx,_qy,"q",u64)); \
6b7ad61f
AK		 284 break; \
285 } \
6aa8b732
AK		 286 } while (0)
287
a31b9cea 288#define __emulate_2op(ctxt,_op,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
6aa8b732 289 do { \
6b7ad61f 290 unsigned long _tmp; \
a31b9cea 291 switch ((ctxt)->dst.bytes) { \
6aa8b732 292 case 1: \
a31b9cea 293 ____emulate_2op(ctxt,_op,_bx,_by,"b",u8); \
6aa8b732
AK		 294 break; \
295 default: \
a31b9cea 296 __emulate_2op_nobyte(ctxt, _op, \
6aa8b732
AK		 297 _wx, _wy, _lx, _ly, _qx, _qy); \
298 break; \
299 } \
300 } while (0)
301
302/* Source operand is byte-sized and may be restricted to just %cl. */
a31b9cea
AK		 303#define emulate_2op_SrcB(ctxt, _op) \
304 __emulate_2op(ctxt, _op, "b", "c", "b", "c", "b", "c", "b", "c")
6aa8b732
AK		 305
306/* Source operand is byte, word, long or quad sized. */
a31b9cea
AK		 307#define emulate_2op_SrcV(ctxt, _op) \
308 __emulate_2op(ctxt, _op, "b", "q", "w", "r", _LO32, "r", "", "r")
6aa8b732
AK		 309
310/* Source operand is word, long or quad sized. */
a31b9cea
AK		 311#define emulate_2op_SrcV_nobyte(ctxt, _op) \
312 __emulate_2op_nobyte(ctxt, _op, "w", "r", _LO32, "r", "", "r")
6aa8b732 313
d175226a 314/* Instruction has three operands and one operand is stored in ECX register */
29053a60 315#define __emulate_2op_cl(ctxt, _op, _suffix, _type) \
7295261c
AK		 316 do { \
317 unsigned long _tmp; \
761441b9
AK		 318 _type _clv = (ctxt)->src2.val; \
319 _type _srcv = (ctxt)->src.val; \
320 _type _dstv = (ctxt)->dst.val; \
7295261c
AK		 321 \
322 __asm__ __volatile__ ( \
323 _PRE_EFLAGS("0", "5", "2") \
324 _op _suffix " %4,%1 \n" \
325 _POST_EFLAGS("0", "5", "2") \
761441b9 326 : "=m" ((ctxt)->eflags), "+r" (_dstv), "=&r" (_tmp) \
7295261c
AK		 327 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
328 ); \
329 \
761441b9
AK		 330 (ctxt)->src2.val = (unsigned long) _clv; \
331 (ctxt)->src2.val = (unsigned long) _srcv; \
332 (ctxt)->dst.val = (unsigned long) _dstv; \
d175226a
GT		 333 } while (0)
334
761441b9 335#define emulate_2op_cl(ctxt, _op) \
7295261c 336 do { \
761441b9 337 switch ((ctxt)->dst.bytes) { \
7295261c 338 case 2: \
29053a60 339 __emulate_2op_cl(ctxt, _op, "w", u16); \
7295261c
AK		 340 break; \
341 case 4: \
29053a60 342 __emulate_2op_cl(ctxt, _op, "l", u32); \
7295261c
AK		 343 break; \
344 case 8: \
29053a60 345 ON64(__emulate_2op_cl(ctxt, _op, "q", ulong)); \
7295261c
AK		 346 break; \
347 } \
d175226a
GT		 348 } while (0)
349
d1eef45d 350#define __emulate_1op(ctxt, _op, _suffix) \
6aa8b732
AK		 351 do { \
352 unsigned long _tmp; \
353 \
dda96d8f
AK		 354 __asm__ __volatile__ ( \
355 _PRE_EFLAGS("0", "3", "2") \
356 _op _suffix " %1; " \
357 _POST_EFLAGS("0", "3", "2") \
d1eef45d 358 : "=m" ((ctxt)->eflags), "+m" ((ctxt)->dst.val), \
dda96d8f
AK		 359 "=&r" (_tmp) \
360 : "i" (EFLAGS_MASK)); \
361 } while (0)
362
363/* Instruction has only one explicit operand (no source operand). */
d1eef45d 364#define emulate_1op(ctxt, _op) \
dda96d8f 365 do { \
d1eef45d
AK		 366 switch ((ctxt)->dst.bytes) { \
367 case 1: __emulate_1op(ctxt, _op, "b"); break; \
368 case 2: __emulate_1op(ctxt, _op, "w"); break; \
369 case 4: __emulate_1op(ctxt, _op, "l"); break; \
370 case 8: ON64(__emulate_1op(ctxt, _op, "q")); break; \
6aa8b732
AK		 371 } \
372 } while (0)
373
e8f2b1d6 374#define __emulate_1op_rax_rdx(ctxt, _op, _suffix, _ex) \
f6b3597b
AK		 375 do { \
376 unsigned long _tmp; \
e8f2b1d6
AK		 377 ulong *rax = &(ctxt)->regs[VCPU_REGS_RAX]; \
378 ulong *rdx = &(ctxt)->regs[VCPU_REGS_RDX]; \
f6b3597b
AK		 379 \
380 __asm__ __volatile__ ( \
381 _PRE_EFLAGS("0", "5", "1") \
382 "1: \n\t" \
383 _op _suffix " %6; " \
384 "2: \n\t" \
385 _POST_EFLAGS("0", "5", "1") \
386 ".pushsection .fixup,\"ax\" \n\t" \
387 "3: movb $1, %4 \n\t" \
388 "jmp 2b \n\t" \
389 ".popsection \n\t" \
390 _ASM_EXTABLE(1b, 3b) \
e8f2b1d6
AK		 391 : "=m" ((ctxt)->eflags), "=&r" (_tmp), \
392 "+a" (*rax), "+d" (*rdx), "+qm"(_ex) \
393 : "i" (EFLAGS_MASK), "m" ((ctxt)->src.val), \
394 "a" (*rax), "d" (*rdx)); \
f6b3597b
AK		 395 } while (0)
396
3f9f53b0 397/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
e8f2b1d6 398#define emulate_1op_rax_rdx(ctxt, _op, _ex) \
7295261c 399 do { \
e8f2b1d6 400 switch((ctxt)->src.bytes) { \
7295261c 401 case 1: \
e8f2b1d6 402 __emulate_1op_rax_rdx(ctxt, _op, "b", _ex); \
7295261c
AK		 403 break; \
404 case 2: \
e8f2b1d6 405 __emulate_1op_rax_rdx(ctxt, _op, "w", _ex); \
7295261c
AK		 406 break; \
407 case 4: \
e8f2b1d6 408 __emulate_1op_rax_rdx(ctxt, _op, "l", _ex); \
f6b3597b
AK		 409 break; \
410 case 8: ON64( \
e8f2b1d6 411 __emulate_1op_rax_rdx(ctxt, _op, "q", _ex)); \
f6b3597b
AK		 412 break; \
413 } \
414 } while (0)
415
8a76d7f2
JR		 416static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
417 enum x86_intercept intercept,
418 enum x86_intercept_stage stage)
419{
420 struct x86_instruction_info info = {
421 .intercept = intercept,
9dac77fa
AK		 422 .rep_prefix = ctxt->rep_prefix,
423 .modrm_mod = ctxt->modrm_mod,
424 .modrm_reg = ctxt->modrm_reg,
425 .modrm_rm = ctxt->modrm_rm,
426 .src_val = ctxt->src.val64,
427 .src_bytes = ctxt->src.bytes,
428 .dst_bytes = ctxt->dst.bytes,
429 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 430 .next_rip = ctxt->eip,
431 };
432
2953538e 433 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 434}
435
f47cfa31
AK		 436static void assign_masked(ulong *dest, ulong src, ulong mask)
437{
438 *dest = (*dest & ~mask) | (src & mask);
439}
440
9dac77fa 441static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 442{
9dac77fa 443 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 444}
445
f47cfa31
AK		 446static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
447{
448 u16 sel;
449 struct desc_struct ss;
450
451 if (ctxt->mode == X86EMUL_MODE_PROT64)
452 return ~0UL;
453 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
454 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
455}
456
612e89f0
AK		 457static int stack_size(struct x86_emulate_ctxt *ctxt)
458{
459 return (__fls(stack_mask(ctxt)) + 1) >> 3;
460}
461
6aa8b732 462/* Access/update address held in a register, based on addressing mode. */
e4706772 463static inline unsigned long
9dac77fa 464address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 465{
9dac77fa 466 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 467 return reg;
468 else
9dac77fa 469 return reg & ad_mask(ctxt);
e4706772
HH		 470}
471
472static inline unsigned long
9dac77fa 473register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 474{
9dac77fa 475 return address_mask(ctxt, reg);
e4706772
HH		 476}
477
5ad105e5
AK		 478static void masked_increment(ulong *reg, ulong mask, int inc)
479{
480 assign_masked(reg, *reg + inc, mask);
481}
482
7a957275 483static inline void
9dac77fa 484register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
7a957275 485{
5ad105e5
AK		 486 ulong mask;
487
9dac77fa 488 if (ctxt->ad_bytes == sizeof(unsigned long))
5ad105e5 489 mask = ~0UL;
7a957275 490 else
5ad105e5
AK		 491 mask = ad_mask(ctxt);
492 masked_increment(reg, mask, inc);
493}
494
495static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
496{
497 masked_increment(&ctxt->regs[VCPU_REGS_RSP], stack_mask(ctxt), inc);
7a957275 498}
6aa8b732 499
9dac77fa 500static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
7a957275 501{
9dac77fa 502 register_address_increment(ctxt, &ctxt->_eip, rel);
7a957275 503}
098c937b 504
56697687
AK		 505static u32 desc_limit_scaled(struct desc_struct *desc)
506{
507 u32 limit = get_desc_limit(desc);
508
509 return desc->g ? (limit << 12) | 0xfff : limit;
510}
511
9dac77fa 512static void set_seg_override(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df 513{
9dac77fa
AK		 514 ctxt->has_seg_override = true;
515 ctxt->seg_override = seg;
7a5b56df
AK		 516}
517
7b105ca2 518static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 519{
520 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
521 return 0;
522
7b105ca2 523 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 524}
525
9dac77fa 526static unsigned seg_override(struct x86_emulate_ctxt *ctxt)
7a5b56df 527{
9dac77fa 528 if (!ctxt->has_seg_override)
7a5b56df
AK		 529 return 0;
530
9dac77fa 531 return ctxt->seg_override;
7a5b56df
AK		 532}
533
35d3d4a1
AK		 534static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
535 u32 error, bool valid)
54b8486f 536{
da9cb575
AK		 537 ctxt->exception.vector = vec;
538 ctxt->exception.error_code = error;
539 ctxt->exception.error_code_valid = valid;
35d3d4a1 540 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 541}
542
3b88e41a
JR		 543static int emulate_db(struct x86_emulate_ctxt *ctxt)
544{
545 return emulate_exception(ctxt, DB_VECTOR, 0, false);
546}
547
35d3d4a1 548static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 549{
35d3d4a1 550 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 551}
552
618ff15d
AK		 553static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
554{
555 return emulate_exception(ctxt, SS_VECTOR, err, true);
556}
557
35d3d4a1 558static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 559{
35d3d4a1 560 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 561}
562
35d3d4a1 563static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 564{
35d3d4a1 565 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 566}
567
34d1f490
AK		 568static int emulate_de(struct x86_emulate_ctxt *ctxt)
569{
35d3d4a1 570 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 571}
572
1253791d
AK		 573static int emulate_nm(struct x86_emulate_ctxt *ctxt)
574{
575 return emulate_exception(ctxt, NM_VECTOR, 0, false);
576}
577
1aa36616
AK		 578static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
579{
580 u16 selector;
581 struct desc_struct desc;
582
583 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
584 return selector;
585}
586
587static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
588 unsigned seg)
589{
590 u16 dummy;
591 u32 base3;
592 struct desc_struct desc;
593
594 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
595 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
596}
597
1c11b376
AK		 598/*
599 * x86 defines three classes of vector instructions: explicitly
600 * aligned, explicitly unaligned, and the rest, which change behaviour
601 * depending on whether they're AVX encoded or not.
602 *
603 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
604 * subject to the same check.
605 */
606static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
607{
608 if (likely(size < 16))
609 return false;
610
611 if (ctxt->d & Aligned)
612 return true;
613 else if (ctxt->d & Unaligned)
614 return false;
615 else if (ctxt->d & Avx)
616 return false;
617 else
618 return true;
619}
620
3d9b938e 621static int __linearize(struct x86_emulate_ctxt *ctxt,
52fd8b44 622 struct segmented_address addr,
3d9b938e 623 unsigned size, bool write, bool fetch,
52fd8b44
AK		 624 ulong *linear)
625{
618ff15d
AK		 626 struct desc_struct desc;
627 bool usable;
52fd8b44 628 ulong la;
618ff15d 629 u32 lim;
1aa36616 630 u16 sel;
618ff15d 631 unsigned cpl, rpl;
52fd8b44 632
7b105ca2 633 la = seg_base(ctxt, addr.seg) + addr.ea;
618ff15d
AK		 634 switch (ctxt->mode) {
635 case X86EMUL_MODE_REAL:
636 break;
637 case X86EMUL_MODE_PROT64:
638 if (((signed long)la << 16) >> 16 != la)
639 return emulate_gp(ctxt, 0);
640 break;
641 default:
1aa36616
AK		 642 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
643 addr.seg);
618ff15d
AK		 644 if (!usable)
645 goto bad;
646 /* code segment or read-only data segment */
647 if (((desc.type & 8) || !(desc.type & 2)) && write)
648 goto bad;
649 /* unreadable code segment */
3d9b938e 650 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 651 goto bad;
652 lim = desc_limit_scaled(&desc);
653 if ((desc.type & 8) || !(desc.type & 4)) {
654 /* expand-up segment */
655 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
656 goto bad;
657 } else {
fc058680 658 /* expand-down segment */
618ff15d
AK		 659 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
660 goto bad;
661 lim = desc.d ? 0xffffffff : 0xffff;
662 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
663 goto bad;
664 }
717746e3 665 cpl = ctxt->ops->cpl(ctxt);
1aa36616 666 rpl = sel & 3;
618ff15d
AK		 667 cpl = max(cpl, rpl);
668 if (!(desc.type & 8)) {
669 /* data segment */
670 if (cpl > desc.dpl)
671 goto bad;
672 } else if ((desc.type & 8) && !(desc.type & 4)) {
673 /* nonconforming code segment */
674 if (cpl != desc.dpl)
675 goto bad;
676 } else if ((desc.type & 8) && (desc.type & 4)) {
677 /* conforming code segment */
678 if (cpl < desc.dpl)
679 goto bad;
680 }
681 break;
682 }
9dac77fa 683 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
52fd8b44 684 la &= (u32)-1;
1c11b376
AK		 685 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
686 return emulate_gp(ctxt, 0);
52fd8b44
AK		 687 *linear = la;
688 return X86EMUL_CONTINUE;
618ff15d
AK		 689bad:
690 if (addr.seg == VCPU_SREG_SS)
691 return emulate_ss(ctxt, addr.seg);
692 else
693 return emulate_gp(ctxt, addr.seg);
52fd8b44
AK		 694}
695
3d9b938e
NE		 696static int linearize(struct x86_emulate_ctxt *ctxt,
697 struct segmented_address addr,
698 unsigned size, bool write,
699 ulong *linear)
700{
701 return __linearize(ctxt, addr, size, write, false, linear);
702}
703
704
3ca3ac4d
AK		 705static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
706 struct segmented_address addr,
707 void *data,
708 unsigned size)
709{
9fa088f4
AK		 710 int rc;
711 ulong linear;
712
83b8795a 713 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 714 if (rc != X86EMUL_CONTINUE)
715 return rc;
0f65dd70 716 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 717}
718
807941b1
TY		 719/*
720 * Fetch the next byte of the instruction being emulated which is pointed to
721 * by ctxt->_eip, then increment ctxt->_eip.
722 *
723 * Also prefetch the remaining bytes of the instruction without crossing page
724 * boundary if they are not in fetch_cache yet.
725 */
726static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest)
62266869 727{
9dac77fa 728 struct fetch_cache *fc = &ctxt->fetch;
62266869 729 int rc;
2fb53ad8 730 int size, cur_size;
62266869 731
807941b1 732 if (ctxt->_eip == fc->end) {
3d9b938e 733 unsigned long linear;
807941b1
TY		 734 struct segmented_address addr = { .seg = VCPU_SREG_CS,
735 .ea = ctxt->_eip };
2fb53ad8 736 cur_size = fc->end - fc->start;
807941b1
TY		 737 size = min(15UL - cur_size,
738 PAGE_SIZE - offset_in_page(ctxt->_eip));
3d9b938e 739 rc = __linearize(ctxt, addr, size, false, true, &linear);
7d88bb48 740 if (unlikely(rc != X86EMUL_CONTINUE))
3d9b938e 741 return rc;
ef5d75cc
TY		 742 rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size,
743 size, &ctxt->exception);
7d88bb48 744 if (unlikely(rc != X86EMUL_CONTINUE))
62266869 745 return rc;
2fb53ad8 746 fc->end += size;
62266869 747 }
807941b1
TY		 748 *dest = fc->data[ctxt->_eip - fc->start];
749 ctxt->_eip++;
3e2815e9 750 return X86EMUL_CONTINUE;
62266869
AK		 751}
752
753static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
807941b1 754 void *dest, unsigned size)
62266869 755{
3e2815e9 756 int rc;
62266869 757
eb3c79e6 758 /* x86 instructions are limited to 15 bytes. */
7d88bb48 759 if (unlikely(ctxt->_eip + size - ctxt->eip > 15))
eb3c79e6 760 return X86EMUL_UNHANDLEABLE;
62266869 761 while (size--) {
807941b1 762 rc = do_insn_fetch_byte(ctxt, dest++);
3e2815e9 763 if (rc != X86EMUL_CONTINUE)
62266869
AK		 764 return rc;
765 }
3e2815e9 766 return X86EMUL_CONTINUE;
62266869
AK		 767}
768
67cbc90d 769/* Fetch next part of the instruction being emulated. */
e85a1085 770#define insn_fetch(_type, _ctxt) \
67cbc90d 771({ unsigned long _x; \
e85a1085 772 rc = do_insn_fetch(_ctxt, &_x, sizeof(_type)); \
67cbc90d
TY		 773 if (rc != X86EMUL_CONTINUE) \
774 goto done; \
67cbc90d
TY		 775 (_type)_x; \
776})
777
807941b1
TY		 778#define insn_fetch_arr(_arr, _size, _ctxt) \
779({ rc = do_insn_fetch(_ctxt, _arr, (_size)); \
67cbc90d
TY		 780 if (rc != X86EMUL_CONTINUE) \
781 goto done; \
67cbc90d
TY		 782})
783
1e3c5cb0
RR		 784/*
785 * Given the 'reg' portion of a ModRM byte, and a register block, return a
786 * pointer into the block that addresses the relevant register.
787 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
788 */
789static void *decode_register(u8 modrm_reg, unsigned long *regs,
790 int highbyte_regs)
6aa8b732
AK		 791{
792 void *p;
793
794 p = &regs[modrm_reg];
795 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
796 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
797 return p;
798}
799
800static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 801 struct segmented_address addr,
6aa8b732
AK		 802 u16 *size, unsigned long *address, int op_bytes)
803{
804 int rc;
805
806 if (op_bytes == 2)
807 op_bytes = 3;
808 *address = 0;
3ca3ac4d 809 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 810 if (rc != X86EMUL_CONTINUE)
6aa8b732 811 return rc;
30b31ab6 812 addr.ea += 2;
3ca3ac4d 813 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 814 return rc;
815}
816
bbe9abbd
NK		 817static int test_cc(unsigned int condition, unsigned int flags)
818{
819 int rc = 0;
820
821 switch ((condition & 15) >> 1) {
822 case 0: /* o */
823 rc |= (flags & EFLG_OF);
824 break;
825 case 1: /* b/c/nae */
826 rc |= (flags & EFLG_CF);
827 break;
828 case 2: /* z/e */
829 rc |= (flags & EFLG_ZF);
830 break;
831 case 3: /* be/na */
832 rc |= (flags & (EFLG_CF|EFLG_ZF));
833 break;
834 case 4: /* s */
835 rc |= (flags & EFLG_SF);
836 break;
837 case 5: /* p/pe */
838 rc |= (flags & EFLG_PF);
839 break;
840 case 7: /* le/ng */
841 rc |= (flags & EFLG_ZF);
842 /* fall through */
843 case 6: /* l/nge */
844 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
845 break;
846 }
847
848 /* Odd condition identifiers (lsb == 1) have inverted sense. */
849 return (!!rc ^ (condition & 1));
850}
851
91ff3cb4
AK		 852static void fetch_register_operand(struct operand *op)
853{
854 switch (op->bytes) {
855 case 1:
856 op->val = *(u8 *)op->addr.reg;
857 break;
858 case 2:
859 op->val = *(u16 *)op->addr.reg;
860 break;
861 case 4:
862 op->val = *(u32 *)op->addr.reg;
863 break;
864 case 8:
865 op->val = *(u64 *)op->addr.reg;
866 break;
867 }
868}
869
1253791d
AK		 870static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
871{
872 ctxt->ops->get_fpu(ctxt);
873 switch (reg) {
874 case 0: asm("movdqu %%xmm0, %0" : "=m"(*data)); break;
875 case 1: asm("movdqu %%xmm1, %0" : "=m"(*data)); break;
876 case 2: asm("movdqu %%xmm2, %0" : "=m"(*data)); break;
877 case 3: asm("movdqu %%xmm3, %0" : "=m"(*data)); break;
878 case 4: asm("movdqu %%xmm4, %0" : "=m"(*data)); break;
879 case 5: asm("movdqu %%xmm5, %0" : "=m"(*data)); break;
880 case 6: asm("movdqu %%xmm6, %0" : "=m"(*data)); break;
881 case 7: asm("movdqu %%xmm7, %0" : "=m"(*data)); break;
882#ifdef CONFIG_X86_64
883 case 8: asm("movdqu %%xmm8, %0" : "=m"(*data)); break;
884 case 9: asm("movdqu %%xmm9, %0" : "=m"(*data)); break;
885 case 10: asm("movdqu %%xmm10, %0" : "=m"(*data)); break;
886 case 11: asm("movdqu %%xmm11, %0" : "=m"(*data)); break;
887 case 12: asm("movdqu %%xmm12, %0" : "=m"(*data)); break;
888 case 13: asm("movdqu %%xmm13, %0" : "=m"(*data)); break;
889 case 14: asm("movdqu %%xmm14, %0" : "=m"(*data)); break;
890 case 15: asm("movdqu %%xmm15, %0" : "=m"(*data)); break;
891#endif
892 default: BUG();
893 }
894 ctxt->ops->put_fpu(ctxt);
895}
896
897static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
898 int reg)
899{
900 ctxt->ops->get_fpu(ctxt);
901 switch (reg) {
902 case 0: asm("movdqu %0, %%xmm0" : : "m"(*data)); break;
903 case 1: asm("movdqu %0, %%xmm1" : : "m"(*data)); break;
904 case 2: asm("movdqu %0, %%xmm2" : : "m"(*data)); break;
905 case 3: asm("movdqu %0, %%xmm3" : : "m"(*data)); break;
906 case 4: asm("movdqu %0, %%xmm4" : : "m"(*data)); break;
907 case 5: asm("movdqu %0, %%xmm5" : : "m"(*data)); break;
908 case 6: asm("movdqu %0, %%xmm6" : : "m"(*data)); break;
909 case 7: asm("movdqu %0, %%xmm7" : : "m"(*data)); break;
910#ifdef CONFIG_X86_64
911 case 8: asm("movdqu %0, %%xmm8" : : "m"(*data)); break;
912 case 9: asm("movdqu %0, %%xmm9" : : "m"(*data)); break;
913 case 10: asm("movdqu %0, %%xmm10" : : "m"(*data)); break;
914 case 11: asm("movdqu %0, %%xmm11" : : "m"(*data)); break;
915 case 12: asm("movdqu %0, %%xmm12" : : "m"(*data)); break;
916 case 13: asm("movdqu %0, %%xmm13" : : "m"(*data)); break;
917 case 14: asm("movdqu %0, %%xmm14" : : "m"(*data)); break;
918 case 15: asm("movdqu %0, %%xmm15" : : "m"(*data)); break;
919#endif
920 default: BUG();
921 }
922 ctxt->ops->put_fpu(ctxt);
923}
924
cbe2c9d3
AK		 925static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
926{
927 ctxt->ops->get_fpu(ctxt);
928 switch (reg) {
929 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
930 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
931 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
932 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
933 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
934 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
935 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
936 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
937 default: BUG();
938 }
939 ctxt->ops->put_fpu(ctxt);
940}
941
942static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
943{
944 ctxt->ops->get_fpu(ctxt);
945 switch (reg) {
946 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
947 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
948 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
949 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
950 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
951 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
952 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
953 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
954 default: BUG();
955 }
956 ctxt->ops->put_fpu(ctxt);
957}
958
1253791d 959static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 960 struct operand *op)
3c118e24 961{
9dac77fa
AK		 962 unsigned reg = ctxt->modrm_reg;
963 int highbyte_regs = ctxt->rex_prefix == 0;
33615aa9 964
9dac77fa
AK		 965 if (!(ctxt->d & ModRM))
966 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 967
9dac77fa 968 if (ctxt->d & Sse) {
1253791d
AK		 969 op->type = OP_XMM;
970 op->bytes = 16;
971 op->addr.xmm = reg;
972 read_sse_reg(ctxt, &op->vec_val, reg);
973 return;
974 }
cbe2c9d3
AK		 975 if (ctxt->d & Mmx) {
976 reg &= 7;
977 op->type = OP_MM;
978 op->bytes = 8;
979 op->addr.mm = reg;
980 return;
981 }
1253791d 982
3c118e24 983 op->type = OP_REG;
2adb5ad9 984 if (ctxt->d & ByteOp) {
9dac77fa 985 op->addr.reg = decode_register(reg, ctxt->regs, highbyte_regs);
3c118e24
AK		 986 op->bytes = 1;
987 } else {
9dac77fa
AK		 988 op->addr.reg = decode_register(reg, ctxt->regs, 0);
989 op->bytes = ctxt->op_bytes;
3c118e24 990 }
91ff3cb4 991 fetch_register_operand(op);
3c118e24
AK		 992 op->orig_val = op->val;
993}
994
a6e3407b
AK		 995static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
996{
997 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
998 ctxt->modrm_seg = VCPU_SREG_SS;
999}
1000
1c73ef66 1001static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1002 struct operand *op)
1c73ef66 1003{
1c73ef66 1004 u8 sib;
f5b4edcd 1005 int index_reg = 0, base_reg = 0, scale;
3e2815e9 1006 int rc = X86EMUL_CONTINUE;
2dbd0dd7 1007 ulong modrm_ea = 0;
1c73ef66 1008
9dac77fa
AK		 1009 if (ctxt->rex_prefix) {
1010 ctxt->modrm_reg = (ctxt->rex_prefix & 4) << 1; /* REX.R */
1011 index_reg = (ctxt->rex_prefix & 2) << 2; /* REX.X */
1012 ctxt->modrm_rm = base_reg = (ctxt->rex_prefix & 1) << 3; /* REG.B */
1c73ef66
AK		 1013 }
1014
9dac77fa
AK		 1015 ctxt->modrm_mod |= (ctxt->modrm & 0xc0) >> 6;
1016 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
1017 ctxt->modrm_rm |= (ctxt->modrm & 0x07);
1018 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 1019
9dac77fa 1020 if (ctxt->modrm_mod == 3) {
2dbd0dd7 1021 op->type = OP_REG;
9dac77fa
AK		 1022 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1023 op->addr.reg = decode_register(ctxt->modrm_rm,
1024 ctxt->regs, ctxt->d & ByteOp);
1025 if (ctxt->d & Sse) {
1253791d
AK		 1026 op->type = OP_XMM;
1027 op->bytes = 16;
9dac77fa
AK		 1028 op->addr.xmm = ctxt->modrm_rm;
1029 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 1030 return rc;
1031 }
cbe2c9d3
AK		 1032 if (ctxt->d & Mmx) {
1033 op->type = OP_MM;
1034 op->bytes = 8;
1035 op->addr.xmm = ctxt->modrm_rm & 7;
1036 return rc;
1037 }
2dbd0dd7 1038 fetch_register_operand(op);
1c73ef66
AK		 1039 return rc;
1040 }
1041
2dbd0dd7
AK		 1042 op->type = OP_MEM;
1043
9dac77fa
AK		 1044 if (ctxt->ad_bytes == 2) {
1045 unsigned bx = ctxt->regs[VCPU_REGS_RBX];
1046 unsigned bp = ctxt->regs[VCPU_REGS_RBP];
1047 unsigned si = ctxt->regs[VCPU_REGS_RSI];
1048 unsigned di = ctxt->regs[VCPU_REGS_RDI];
1c73ef66
AK		 1049
1050 /* 16-bit ModR/M decode. */
9dac77fa 1051 switch (ctxt->modrm_mod) {
1c73ef66 1052 case 0:
9dac77fa 1053 if (ctxt->modrm_rm == 6)
e85a1085 1054 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1055 break;
1056 case 1:
e85a1085 1057 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1058 break;
1059 case 2:
e85a1085 1060 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1061 break;
1062 }
9dac77fa 1063 switch (ctxt->modrm_rm) {
1c73ef66 1064 case 0:
2dbd0dd7 1065 modrm_ea += bx + si;
1c73ef66
AK		 1066 break;
1067 case 1:
2dbd0dd7 1068 modrm_ea += bx + di;
1c73ef66
AK		 1069 break;
1070 case 2:
2dbd0dd7 1071 modrm_ea += bp + si;
1c73ef66
AK		 1072 break;
1073 case 3:
2dbd0dd7 1074 modrm_ea += bp + di;
1c73ef66
AK		 1075 break;
1076 case 4:
2dbd0dd7 1077 modrm_ea += si;
1c73ef66
AK		 1078 break;
1079 case 5:
2dbd0dd7 1080 modrm_ea += di;
1c73ef66
AK		 1081 break;
1082 case 6:
9dac77fa 1083 if (ctxt->modrm_mod != 0)
2dbd0dd7 1084 modrm_ea += bp;
1c73ef66
AK		 1085 break;
1086 case 7:
2dbd0dd7 1087 modrm_ea += bx;
1c73ef66
AK		 1088 break;
1089 }
9dac77fa
AK		 1090 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1091 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1092 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1093 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1094 } else {
1095 /* 32/64-bit ModR/M decode. */
9dac77fa 1096 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1097 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1098 index_reg |= (sib >> 3) & 7;
1099 base_reg |= sib & 7;
1100 scale = sib >> 6;
1101
9dac77fa 1102 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1103 modrm_ea += insn_fetch(s32, ctxt);
a6e3407b 1104 else {
9dac77fa 1105 modrm_ea += ctxt->regs[base_reg];
a6e3407b
AK		 1106 adjust_modrm_seg(ctxt, base_reg);
1107 }
dc71d0f1 1108 if (index_reg != 4)
9dac77fa
AK		 1109 modrm_ea += ctxt->regs[index_reg] << scale;
1110 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
84411d85 1111 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1112 ctxt->rip_relative = 1;
a6e3407b
AK		 1113 } else {
1114 base_reg = ctxt->modrm_rm;
1115 modrm_ea += ctxt->regs[base_reg];
1116 adjust_modrm_seg(ctxt, base_reg);
1117 }
9dac77fa 1118 switch (ctxt->modrm_mod) {
1c73ef66 1119 case 0:
9dac77fa 1120 if (ctxt->modrm_rm == 5)
e85a1085 1121 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1122 break;
1123 case 1:
e85a1085 1124 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1125 break;
1126 case 2:
e85a1085 1127 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1128 break;
1129 }
1130 }
90de84f5 1131 op->addr.mem.ea = modrm_ea;
1c73ef66
AK		 1132done:
1133 return rc;
1134}
1135
1136static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1137 struct operand *op)
1c73ef66 1138{
3e2815e9 1139 int rc = X86EMUL_CONTINUE;
1c73ef66 1140
2dbd0dd7 1141 op->type = OP_MEM;
9dac77fa 1142 switch (ctxt->ad_bytes) {
1c73ef66 1143 case 2:
e85a1085 1144 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1145 break;
1146 case 4:
e85a1085 1147 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1148 break;
1149 case 8:
e85a1085 1150 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1151 break;
1152 }
1153done:
1154 return rc;
1155}
1156
9dac77fa 1157static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1158{
7129eeca 1159 long sv = 0, mask;
35c843c4 1160
9dac77fa
AK		 1161 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
1162 mask = ~(ctxt->dst.bytes * 8 - 1);
35c843c4 1163
9dac77fa
AK		 1164 if (ctxt->src.bytes == 2)
1165 sv = (s16)ctxt->src.val & (s16)mask;
1166 else if (ctxt->src.bytes == 4)
1167 sv = (s32)ctxt->src.val & (s32)mask;
35c843c4 1168
9dac77fa 1169 ctxt->dst.addr.mem.ea += (sv >> 3);
35c843c4 1170 }
ba7ff2b7
WY		 1171
1172 /* only subword offset */
9dac77fa 1173 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1174}
1175
dde7e6d1 1176static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1177 unsigned long addr, void *dest, unsigned size)
6aa8b732 1178{
dde7e6d1 1179 int rc;
9dac77fa 1180 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1181
f23b070e
XG		 1182 if (mc->pos < mc->end)
1183 goto read_cached;
6aa8b732 1184
f23b070e
XG		 1185 WARN_ON((mc->end + size) >= sizeof(mc->data));
1186
1187 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1188 &ctxt->exception);
1189 if (rc != X86EMUL_CONTINUE)
1190 return rc;
1191
1192 mc->end += size;
1193
1194read_cached:
1195 memcpy(dest, mc->data + mc->pos, size);
1196 mc->pos += size;
dde7e6d1
AK		 1197 return X86EMUL_CONTINUE;
1198}
6aa8b732 1199
3ca3ac4d
AK		 1200static int segmented_read(struct x86_emulate_ctxt *ctxt,
1201 struct segmented_address addr,
1202 void *data,
1203 unsigned size)
1204{
9fa088f4
AK		 1205 int rc;
1206 ulong linear;
1207
83b8795a 1208 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1209 if (rc != X86EMUL_CONTINUE)
1210 return rc;
7b105ca2 1211 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1212}
1213
1214static int segmented_write(struct x86_emulate_ctxt *ctxt,
1215 struct segmented_address addr,
1216 const void *data,
1217 unsigned size)
1218{
9fa088f4
AK		 1219 int rc;
1220 ulong linear;
1221
83b8795a 1222 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1223 if (rc != X86EMUL_CONTINUE)
1224 return rc;
0f65dd70
AK		 1225 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1226 &ctxt->exception);
3ca3ac4d
AK		 1227}
1228
1229static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1230 struct segmented_address addr,
1231 const void *orig_data, const void *data,
1232 unsigned size)
1233{
9fa088f4
AK		 1234 int rc;
1235 ulong linear;
1236
83b8795a 1237 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1238 if (rc != X86EMUL_CONTINUE)
1239 return rc;
0f65dd70
AK		 1240 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1241 size, &ctxt->exception);
3ca3ac4d
AK		 1242}
1243
dde7e6d1 1244static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1245 unsigned int size, unsigned short port,
1246 void *dest)
1247{
9dac77fa 1248 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1249
dde7e6d1 1250 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1251 unsigned int in_page, n;
9dac77fa
AK		 1252 unsigned int count = ctxt->rep_prefix ?
1253 address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) : 1;
dde7e6d1 1254 in_page = (ctxt->eflags & EFLG_DF) ?
9dac77fa
AK		 1255 offset_in_page(ctxt->regs[VCPU_REGS_RDI]) :
1256 PAGE_SIZE - offset_in_page(ctxt->regs[VCPU_REGS_RDI]);
dde7e6d1
AK		 1257 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1258 count);
1259 if (n == 0)
1260 n = 1;
1261 rc->pos = rc->end = 0;
7b105ca2 1262 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1263 return 0;
1264 rc->end = n * size;
6aa8b732
AK		 1265 }
1266
dde7e6d1
AK		 1267 memcpy(dest, rc->data + rc->pos, size);
1268 rc->pos += size;
1269 return 1;
1270}
6aa8b732 1271
7f3d35fd
KW		 1272static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1273 u16 index, struct desc_struct *desc)
1274{
1275 struct desc_ptr dt;
1276 ulong addr;
1277
1278 ctxt->ops->get_idt(ctxt, &dt);
1279
1280 if (dt.size < index * 8 + 7)
1281 return emulate_gp(ctxt, index << 3 | 0x2);
1282
1283 addr = dt.address + index * 8;
1284 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1285 &ctxt->exception);
1286}
1287
dde7e6d1 1288static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1289 u16 selector, struct desc_ptr *dt)
1290{
7b105ca2
TY		 1291 struct x86_emulate_ops *ops = ctxt->ops;
1292
dde7e6d1
AK		 1293 if (selector & 1 << 2) {
1294 struct desc_struct desc;
1aa36616
AK		 1295 u16 sel;
1296
dde7e6d1 1297 memset (dt, 0, sizeof *dt);
1aa36616 1298 if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR))
dde7e6d1 1299 return;
e09d082c 1300
dde7e6d1
AK		 1301 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1302 dt->address = get_desc_base(&desc);
1303 } else
4bff1e86 1304 ops->get_gdt(ctxt, dt);
dde7e6d1 1305}
120df890 1306
dde7e6d1
AK		 1307/* allowed just for 8 bytes segments */
1308static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
e919464b
AK		 1309 u16 selector, struct desc_struct *desc,
1310 ulong *desc_addr_p)
dde7e6d1
AK		 1311{
1312 struct desc_ptr dt;
1313 u16 index = selector >> 3;
dde7e6d1 1314 ulong addr;
120df890 1315
7b105ca2 1316 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1317
35d3d4a1
AK		 1318 if (dt.size < index * 8 + 7)
1319 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1320
e919464b 1321 *desc_addr_p = addr = dt.address + index * 8;
7b105ca2
TY		 1322 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1323 &ctxt->exception);
dde7e6d1 1324}
ef65c889 1325
dde7e6d1
AK		 1326/* allowed just for 8 bytes segments */
1327static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1328 u16 selector, struct desc_struct *desc)
1329{
1330 struct desc_ptr dt;
1331 u16 index = selector >> 3;
dde7e6d1 1332 ulong addr;
6aa8b732 1333
7b105ca2 1334 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1335
35d3d4a1
AK		 1336 if (dt.size < index * 8 + 7)
1337 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1338
dde7e6d1 1339 addr = dt.address + index * 8;
7b105ca2
TY		 1340 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1341 &ctxt->exception);
dde7e6d1 1342}
c7e75a3d 1343
5601d05b 1344/* Does not support long mode */
dde7e6d1 1345static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1346 u16 selector, int seg)
1347{
869be99c 1348 struct desc_struct seg_desc, old_desc;
dde7e6d1
AK		 1349 u8 dpl, rpl, cpl;
1350 unsigned err_vec = GP_VECTOR;
1351 u32 err_code = 0;
1352 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
e919464b 1353 ulong desc_addr;
dde7e6d1 1354 int ret;
69f55cb1 1355
dde7e6d1 1356 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1357
dde7e6d1
AK		 1358 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1359 || ctxt->mode == X86EMUL_MODE_REAL) {
1360 /* set real mode segment descriptor */
1361 set_desc_base(&seg_desc, selector << 4);
1362 set_desc_limit(&seg_desc, 0xffff);
1363 seg_desc.type = 3;
1364 seg_desc.p = 1;
1365 seg_desc.s = 1;
66b0ab8f
KW		 1366 if (ctxt->mode == X86EMUL_MODE_VM86)
1367 seg_desc.dpl = 3;
dde7e6d1
AK		 1368 goto load;
1369 }
1370
79d5b4c3
AK		 1371 rpl = selector & 3;
1372 cpl = ctxt->ops->cpl(ctxt);
1373
1374 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1375 if ((seg == VCPU_SREG_CS
1376 || (seg == VCPU_SREG_SS
1377 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1378 || seg == VCPU_SREG_TR)
dde7e6d1
AK		 1379 && null_selector)
1380 goto exception;
1381
1382 /* TR should be in GDT only */
1383 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1384 goto exception;
1385
1386 if (null_selector) /* for NULL selector skip all following checks */
1387 goto load;
1388
e919464b 1389 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
dde7e6d1
AK		 1390 if (ret != X86EMUL_CONTINUE)
1391 return ret;
1392
1393 err_code = selector & 0xfffc;
1394 err_vec = GP_VECTOR;
1395
fc058680 1396 /* can't load system descriptor into segment selector */
dde7e6d1
AK		 1397 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1398 goto exception;
1399
1400 if (!seg_desc.p) {
1401 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1402 goto exception;
1403 }
1404
dde7e6d1 1405 dpl = seg_desc.dpl;
dde7e6d1
AK		 1406
1407 switch (seg) {
1408 case VCPU_SREG_SS:
1409 /*
1410 * segment is not a writable data segment or segment
1411 * selector's RPL != CPL or segment selector's RPL != CPL
1412 */
1413 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1414 goto exception;
6aa8b732 1415 break;
dde7e6d1
AK		 1416 case VCPU_SREG_CS:
1417 if (!(seg_desc.type & 8))
1418 goto exception;
1419
1420 if (seg_desc.type & 4) {
1421 /* conforming */
1422 if (dpl > cpl)
1423 goto exception;
1424 } else {
1425 /* nonconforming */
1426 if (rpl > cpl || dpl != cpl)
1427 goto exception;
1428 }
1429 /* CS(RPL) <- CPL */
1430 selector = (selector & 0xfffc) | cpl;
6aa8b732 1431 break;
dde7e6d1
AK		 1432 case VCPU_SREG_TR:
1433 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1434 goto exception;
869be99c
AK		 1435 old_desc = seg_desc;
1436 seg_desc.type |= 2; /* busy */
1437 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1438 sizeof(seg_desc), &ctxt->exception);
1439 if (ret != X86EMUL_CONTINUE)
1440 return ret;
dde7e6d1
AK		 1441 break;
1442 case VCPU_SREG_LDTR:
1443 if (seg_desc.s || seg_desc.type != 2)
1444 goto exception;
1445 break;
1446 default: /* DS, ES, FS, or GS */
4e62417b 1447 /*
dde7e6d1
AK		 1448 * segment is not a data or readable code segment or
1449 * ((segment is a data or nonconforming code segment)
1450 * and (both RPL and CPL > DPL))
4e62417b 1451 */
dde7e6d1
AK		 1452 if ((seg_desc.type & 0xa) == 0x8 ||
1453 (((seg_desc.type & 0xc) != 0xc) &&
1454 (rpl > dpl && cpl > dpl)))
1455 goto exception;
6aa8b732 1456 break;
dde7e6d1
AK		 1457 }
1458
1459 if (seg_desc.s) {
1460 /* mark segment as accessed */
1461 seg_desc.type |= 1;
7b105ca2 1462 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1463 if (ret != X86EMUL_CONTINUE)
1464 return ret;
1465 }
1466load:
7b105ca2 1467 ctxt->ops->set_segment(ctxt, selector, &seg_desc, 0, seg);
dde7e6d1
AK		 1468 return X86EMUL_CONTINUE;
1469exception:
1470 emulate_exception(ctxt, err_vec, err_code, true);
1471 return X86EMUL_PROPAGATE_FAULT;
1472}
1473
31be40b3
WY		 1474static void write_register_operand(struct operand *op)
1475{
1476 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1477 switch (op->bytes) {
1478 case 1:
1479 *(u8 *)op->addr.reg = (u8)op->val;
1480 break;
1481 case 2:
1482 *(u16 *)op->addr.reg = (u16)op->val;
1483 break;
1484 case 4:
1485 *op->addr.reg = (u32)op->val;
1486 break; /* 64b: zero-extend */
1487 case 8:
1488 *op->addr.reg = op->val;
1489 break;
1490 }
1491}
1492
adddcecf 1493static int writeback(struct x86_emulate_ctxt *ctxt)
dde7e6d1
AK		 1494{
1495 int rc;
dde7e6d1 1496
9dac77fa 1497 switch (ctxt->dst.type) {
dde7e6d1 1498 case OP_REG:
9dac77fa 1499 write_register_operand(&ctxt->dst);
6aa8b732 1500 break;
dde7e6d1 1501 case OP_MEM:
9dac77fa 1502 if (ctxt->lock_prefix)
3ca3ac4d 1503 rc = segmented_cmpxchg(ctxt,
9dac77fa
AK		 1504 ctxt->dst.addr.mem,
1505 &ctxt->dst.orig_val,
1506 &ctxt->dst.val,
1507 ctxt->dst.bytes);
341de7e3 1508 else
3ca3ac4d 1509 rc = segmented_write(ctxt,
9dac77fa
AK		 1510 ctxt->dst.addr.mem,
1511 &ctxt->dst.val,
1512 ctxt->dst.bytes);
dde7e6d1
AK		 1513 if (rc != X86EMUL_CONTINUE)
1514 return rc;
a682e354 1515 break;
1253791d 1516 case OP_XMM:
9dac77fa 1517 write_sse_reg(ctxt, &ctxt->dst.vec_val, ctxt->dst.addr.xmm);
1253791d 1518 break;
cbe2c9d3
AK		 1519 case OP_MM:
1520 write_mmx_reg(ctxt, &ctxt->dst.mm_val, ctxt->dst.addr.mm);
1521 break;
dde7e6d1
AK		 1522 case OP_NONE:
1523 /* no writeback */
414e6277 1524 break;
dde7e6d1 1525 default:
414e6277 1526 break;
6aa8b732 1527 }
dde7e6d1
AK		 1528 return X86EMUL_CONTINUE;
1529}
6aa8b732 1530
51ddff50 1531static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
dde7e6d1 1532{
4179bb02 1533 struct segmented_address addr;
0dc8d10f 1534
5ad105e5
AK		 1535 rsp_increment(ctxt, -bytes);
1536 addr.ea = ctxt->regs[VCPU_REGS_RSP] & stack_mask(ctxt);
4179bb02
TY		 1537 addr.seg = VCPU_SREG_SS;
1538
51ddff50
AK		 1539 return segmented_write(ctxt, addr, data, bytes);
1540}
1541
1542static int em_push(struct x86_emulate_ctxt *ctxt)
1543{
4179bb02 1544 /* Disable writeback. */
9dac77fa 1545 ctxt->dst.type = OP_NONE;
51ddff50 1546 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1547}
69f55cb1 1548
dde7e6d1 1549static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1550 void *dest, int len)
1551{
dde7e6d1 1552 int rc;
90de84f5 1553 struct segmented_address addr;
8b4caf66 1554
5ad105e5 1555 addr.ea = ctxt->regs[VCPU_REGS_RSP] & stack_mask(ctxt);
90de84f5 1556 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1557 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1558 if (rc != X86EMUL_CONTINUE)
1559 return rc;
1560
5ad105e5 1561 rsp_increment(ctxt, len);
dde7e6d1 1562 return rc;
8b4caf66
LV		 1563}
1564
c54fe504
TY		 1565static int em_pop(struct x86_emulate_ctxt *ctxt)
1566{
9dac77fa 1567 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1568}
1569
dde7e6d1 1570static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1571 void *dest, int len)
9de41573
GN		 1572{
1573 int rc;
dde7e6d1
AK		 1574 unsigned long val, change_mask;
1575 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1576 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1577
3b9be3bf 1578 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1579 if (rc != X86EMUL_CONTINUE)
1580 return rc;
9de41573 1581
dde7e6d1
AK		 1582 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1583 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1584
dde7e6d1
AK		 1585 switch(ctxt->mode) {
1586 case X86EMUL_MODE_PROT64:
1587 case X86EMUL_MODE_PROT32:
1588 case X86EMUL_MODE_PROT16:
1589 if (cpl == 0)
1590 change_mask |= EFLG_IOPL;
1591 if (cpl <= iopl)
1592 change_mask |= EFLG_IF;
1593 break;
1594 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1595 if (iopl < 3)
1596 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1597 change_mask |= EFLG_IF;
1598 break;
1599 default: /* real mode */
1600 change_mask |= (EFLG_IOPL | EFLG_IF);
1601 break;
9de41573 1602 }
dde7e6d1
AK		 1603
1604 *(unsigned long *)dest =
1605 (ctxt->eflags & ~change_mask) | (val & change_mask);
1606
1607 return rc;
9de41573
GN		 1608}
1609
62aaa2f0
TY		 1610static int em_popf(struct x86_emulate_ctxt *ctxt)
1611{
9dac77fa
AK		 1612 ctxt->dst.type = OP_REG;
1613 ctxt->dst.addr.reg = &ctxt->eflags;
1614 ctxt->dst.bytes = ctxt->op_bytes;
1615 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1616}
1617
612e89f0
AK		 1618static int em_enter(struct x86_emulate_ctxt *ctxt)
1619{
1620 int rc;
1621 unsigned frame_size = ctxt->src.val;
1622 unsigned nesting_level = ctxt->src2.val & 31;
1623
1624 if (nesting_level)
1625 return X86EMUL_UNHANDLEABLE;
1626
1627 rc = push(ctxt, &ctxt->regs[VCPU_REGS_RBP], stack_size(ctxt));
1628 if (rc != X86EMUL_CONTINUE)
1629 return rc;
1630 assign_masked(&ctxt->regs[VCPU_REGS_RBP], ctxt->regs[VCPU_REGS_RSP],
1631 stack_mask(ctxt));
1632 assign_masked(&ctxt->regs[VCPU_REGS_RSP],
1633 ctxt->regs[VCPU_REGS_RSP] - frame_size,
1634 stack_mask(ctxt));
1635 return X86EMUL_CONTINUE;
1636}
1637
f47cfa31
AK		 1638static int em_leave(struct x86_emulate_ctxt *ctxt)
1639{
1640 assign_masked(&ctxt->regs[VCPU_REGS_RSP], ctxt->regs[VCPU_REGS_RBP],
1641 stack_mask(ctxt));
1642 return emulate_pop(ctxt, &ctxt->regs[VCPU_REGS_RBP], ctxt->op_bytes);
1643}
1644
1cd196ea 1645static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1646{
1cd196ea
AK		 1647 int seg = ctxt->src2.val;
1648
9dac77fa 1649 ctxt->src.val = get_segment_selector(ctxt, seg);
7b262e90 1650
4487b3b4 1651 return em_push(ctxt);
7b262e90
GN		 1652}
1653
1cd196ea 1654static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1655{
1cd196ea 1656 int seg = ctxt->src2.val;
dde7e6d1
AK		 1657 unsigned long selector;
1658 int rc;
38ba30ba 1659
9dac77fa 1660 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
dde7e6d1
AK		 1661 if (rc != X86EMUL_CONTINUE)
1662 return rc;
1663
7b105ca2 1664 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1665 return rc;
38ba30ba
GN		 1666}
1667
b96a7fad 1668static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1669{
9dac77fa 1670 unsigned long old_esp = ctxt->regs[VCPU_REGS_RSP];
dde7e6d1
AK		 1671 int rc = X86EMUL_CONTINUE;
1672 int reg = VCPU_REGS_RAX;
38ba30ba 1673
dde7e6d1
AK		 1674 while (reg <= VCPU_REGS_RDI) {
1675 (reg == VCPU_REGS_RSP) ?
9dac77fa 1676 (ctxt->src.val = old_esp) : (ctxt->src.val = ctxt->regs[reg]);
38ba30ba 1677
4487b3b4 1678 rc = em_push(ctxt);
dde7e6d1
AK		 1679 if (rc != X86EMUL_CONTINUE)
1680 return rc;
38ba30ba 1681
dde7e6d1 1682 ++reg;
38ba30ba 1683 }
38ba30ba 1684
dde7e6d1 1685 return rc;
38ba30ba
GN		 1686}
1687
62aaa2f0
TY		 1688static int em_pushf(struct x86_emulate_ctxt *ctxt)
1689{
9dac77fa 1690 ctxt->src.val = (unsigned long)ctxt->eflags;
62aaa2f0
TY		 1691 return em_push(ctxt);
1692}
1693
b96a7fad 1694static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1695{
dde7e6d1
AK		 1696 int rc = X86EMUL_CONTINUE;
1697 int reg = VCPU_REGS_RDI;
38ba30ba 1698
dde7e6d1
AK		 1699 while (reg >= VCPU_REGS_RAX) {
1700 if (reg == VCPU_REGS_RSP) {
5ad105e5 1701 rsp_increment(ctxt, ctxt->op_bytes);
dde7e6d1
AK		 1702 --reg;
1703 }
38ba30ba 1704
9dac77fa 1705 rc = emulate_pop(ctxt, &ctxt->regs[reg], ctxt->op_bytes);
dde7e6d1
AK		 1706 if (rc != X86EMUL_CONTINUE)
1707 break;
1708 --reg;
38ba30ba 1709 }
dde7e6d1 1710 return rc;
38ba30ba
GN		 1711}
1712
7b105ca2 1713int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1714{
7b105ca2 1715 struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1716 int rc;
6e154e56
MG		 1717 struct desc_ptr dt;
1718 gva_t cs_addr;
1719 gva_t eip_addr;
1720 u16 cs, eip;
6e154e56
MG		 1721
1722 /* TODO: Add limit checks */
9dac77fa 1723 ctxt->src.val = ctxt->eflags;
4487b3b4 1724 rc = em_push(ctxt);
5c56e1cf
AK		 1725 if (rc != X86EMUL_CONTINUE)
1726 return rc;
6e154e56
MG		 1727
1728 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1729
9dac77fa 1730 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1731 rc = em_push(ctxt);
5c56e1cf
AK		 1732 if (rc != X86EMUL_CONTINUE)
1733 return rc;
6e154e56 1734
9dac77fa 1735 ctxt->src.val = ctxt->_eip;
4487b3b4 1736 rc = em_push(ctxt);
5c56e1cf
AK		 1737 if (rc != X86EMUL_CONTINUE)
1738 return rc;
1739
4bff1e86 1740 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1741
1742 eip_addr = dt.address + (irq << 2);
1743 cs_addr = dt.address + (irq << 2) + 2;
1744
0f65dd70 1745 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1746 if (rc != X86EMUL_CONTINUE)
1747 return rc;
1748
0f65dd70 1749 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1750 if (rc != X86EMUL_CONTINUE)
1751 return rc;
1752
7b105ca2 1753 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1754 if (rc != X86EMUL_CONTINUE)
1755 return rc;
1756
9dac77fa 1757 ctxt->_eip = eip;
6e154e56
MG		 1758
1759 return rc;
1760}
1761
7b105ca2 1762static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 1763{
1764 switch(ctxt->mode) {
1765 case X86EMUL_MODE_REAL:
7b105ca2 1766 return emulate_int_real(ctxt, irq);
6e154e56
MG		 1767 case X86EMUL_MODE_VM86:
1768 case X86EMUL_MODE_PROT16:
1769 case X86EMUL_MODE_PROT32:
1770 case X86EMUL_MODE_PROT64:
1771 default:
1772 /* Protected mode interrupts unimplemented yet */
1773 return X86EMUL_UNHANDLEABLE;
1774 }
1775}
1776
7b105ca2 1777static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 1778{
dde7e6d1
AK		 1779 int rc = X86EMUL_CONTINUE;
1780 unsigned long temp_eip = 0;
1781 unsigned long temp_eflags = 0;
1782 unsigned long cs = 0;
1783 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1784 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1785 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1786 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1787
dde7e6d1 1788 /* TODO: Add stack limit check */
38ba30ba 1789
9dac77fa 1790 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 1791
dde7e6d1
AK		 1792 if (rc != X86EMUL_CONTINUE)
1793 return rc;
38ba30ba 1794
35d3d4a1
AK		 1795 if (temp_eip & ~0xffff)
1796 return emulate_gp(ctxt, 0);
38ba30ba 1797
9dac77fa 1798 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 1799
dde7e6d1
AK		 1800 if (rc != X86EMUL_CONTINUE)
1801 return rc;
38ba30ba 1802
9dac77fa 1803 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 1804
dde7e6d1
AK		 1805 if (rc != X86EMUL_CONTINUE)
1806 return rc;
38ba30ba 1807
7b105ca2 1808 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 1809
dde7e6d1
AK		 1810 if (rc != X86EMUL_CONTINUE)
1811 return rc;
38ba30ba 1812
9dac77fa 1813 ctxt->_eip = temp_eip;
38ba30ba 1814
38ba30ba 1815
9dac77fa 1816 if (ctxt->op_bytes == 4)
dde7e6d1 1817 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 1818 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 1819 ctxt->eflags &= ~0xffff;
1820 ctxt->eflags |= temp_eflags;
38ba30ba 1821 }
dde7e6d1
AK		 1822
1823 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1824 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1825
1826 return rc;
38ba30ba
GN		 1827}
1828
e01991e7 1829static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 1830{
dde7e6d1
AK		 1831 switch(ctxt->mode) {
1832 case X86EMUL_MODE_REAL:
7b105ca2 1833 return emulate_iret_real(ctxt);
dde7e6d1
AK		 1834 case X86EMUL_MODE_VM86:
1835 case X86EMUL_MODE_PROT16:
1836 case X86EMUL_MODE_PROT32:
1837 case X86EMUL_MODE_PROT64:
c37eda13 1838 default:
dde7e6d1
AK		 1839 /* iret from protected mode unimplemented yet */
1840 return X86EMUL_UNHANDLEABLE;
c37eda13 1841 }
c37eda13
WY		 1842}
1843
d2f62766
TY		 1844static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
1845{
d2f62766
TY		 1846 int rc;
1847 unsigned short sel;
1848
9dac77fa 1849 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 1850
7b105ca2 1851 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS);
d2f62766
TY		 1852 if (rc != X86EMUL_CONTINUE)
1853 return rc;
1854
9dac77fa
AK		 1855 ctxt->_eip = 0;
1856 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
d2f62766
TY		 1857 return X86EMUL_CONTINUE;
1858}
1859
51187683 1860static int em_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1861{
9dac77fa 1862 switch (ctxt->modrm_reg) {
8cdbd2c9 1863 case 0: /* rol */
a31b9cea 1864 emulate_2op_SrcB(ctxt, "rol");
8cdbd2c9
LV		 1865 break;
1866 case 1: /* ror */
a31b9cea 1867 emulate_2op_SrcB(ctxt, "ror");
8cdbd2c9
LV		 1868 break;
1869 case 2: /* rcl */
a31b9cea 1870 emulate_2op_SrcB(ctxt, "rcl");
8cdbd2c9
LV		 1871 break;
1872 case 3: /* rcr */
a31b9cea 1873 emulate_2op_SrcB(ctxt, "rcr");
8cdbd2c9
LV		 1874 break;
1875 case 4: /* sal/shl */
1876 case 6: /* sal/shl */
a31b9cea 1877 emulate_2op_SrcB(ctxt, "sal");
8cdbd2c9
LV		 1878 break;
1879 case 5: /* shr */
a31b9cea 1880 emulate_2op_SrcB(ctxt, "shr");
8cdbd2c9
LV		 1881 break;
1882 case 7: /* sar */
a31b9cea 1883 emulate_2op_SrcB(ctxt, "sar");
8cdbd2c9
LV		 1884 break;
1885 }
51187683 1886 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1887}
1888
3329ece1
AK		 1889static int em_not(struct x86_emulate_ctxt *ctxt)
1890{
1891 ctxt->dst.val = ~ctxt->dst.val;
1892 return X86EMUL_CONTINUE;
1893}
1894
1895static int em_neg(struct x86_emulate_ctxt *ctxt)
1896{
1897 emulate_1op(ctxt, "neg");
1898 return X86EMUL_CONTINUE;
1899}
1900
1901static int em_mul_ex(struct x86_emulate_ctxt *ctxt)
1902{
1903 u8 ex = 0;
1904
1905 emulate_1op_rax_rdx(ctxt, "mul", ex);
1906 return X86EMUL_CONTINUE;
1907}
1908
1909static int em_imul_ex(struct x86_emulate_ctxt *ctxt)
1910{
1911 u8 ex = 0;
1912
1913 emulate_1op_rax_rdx(ctxt, "imul", ex);
1914 return X86EMUL_CONTINUE;
1915}
1916
1917static int em_div_ex(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1918{
34d1f490 1919 u8 de = 0;
8cdbd2c9 1920
3329ece1
AK		 1921 emulate_1op_rax_rdx(ctxt, "div", de);
1922 if (de)
1923 return emulate_de(ctxt);
1924 return X86EMUL_CONTINUE;
1925}
1926
1927static int em_idiv_ex(struct x86_emulate_ctxt *ctxt)
1928{
1929 u8 de = 0;
1930
1931 emulate_1op_rax_rdx(ctxt, "idiv", de);
34d1f490
AK		 1932 if (de)
1933 return emulate_de(ctxt);
8c5eee30 1934 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1935}
1936
51187683 1937static int em_grp45(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1938{
4179bb02 1939 int rc = X86EMUL_CONTINUE;
8cdbd2c9 1940
9dac77fa 1941 switch (ctxt->modrm_reg) {
8cdbd2c9 1942 case 0: /* inc */
d1eef45d 1943 emulate_1op(ctxt, "inc");
8cdbd2c9
LV		 1944 break;
1945 case 1: /* dec */
d1eef45d 1946 emulate_1op(ctxt, "dec");
8cdbd2c9 1947 break;
d19292e4
MG		 1948 case 2: /* call near abs */ {
1949 long int old_eip;
9dac77fa
AK		 1950 old_eip = ctxt->_eip;
1951 ctxt->_eip = ctxt->src.val;
1952 ctxt->src.val = old_eip;
4487b3b4 1953 rc = em_push(ctxt);
d19292e4
MG		 1954 break;
1955 }
8cdbd2c9 1956 case 4: /* jmp abs */
9dac77fa 1957 ctxt->_eip = ctxt->src.val;
8cdbd2c9 1958 break;
d2f62766
TY		 1959 case 5: /* jmp far */
1960 rc = em_jmp_far(ctxt);
1961 break;
8cdbd2c9 1962 case 6: /* push */
4487b3b4 1963 rc = em_push(ctxt);
8cdbd2c9 1964 break;
8cdbd2c9 1965 }
4179bb02 1966 return rc;
8cdbd2c9
LV		 1967}
1968
e0dac408 1969static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1970{
9dac77fa 1971 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 1972
9dac77fa
AK		 1973 if (((u32) (old >> 0) != (u32) ctxt->regs[VCPU_REGS_RAX]) ||
1974 ((u32) (old >> 32) != (u32) ctxt->regs[VCPU_REGS_RDX])) {
1975 ctxt->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1976 ctxt->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1977 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 1978 } else {
9dac77fa
AK		 1979 ctxt->dst.val64 = ((u64)ctxt->regs[VCPU_REGS_RCX] << 32) |
1980 (u32) ctxt->regs[VCPU_REGS_RBX];
8cdbd2c9 1981
05f086f8 1982 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 1983 }
1b30eaa8 1984 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1985}
1986
ebda02c2
TY		 1987static int em_ret(struct x86_emulate_ctxt *ctxt)
1988{
9dac77fa
AK		 1989 ctxt->dst.type = OP_REG;
1990 ctxt->dst.addr.reg = &ctxt->_eip;
1991 ctxt->dst.bytes = ctxt->op_bytes;
ebda02c2
TY		 1992 return em_pop(ctxt);
1993}
1994
e01991e7 1995static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 1996{
a77ab5ea
AK		 1997 int rc;
1998 unsigned long cs;
1999
9dac77fa 2000 rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes);
1b30eaa8 2001 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2002 return rc;
9dac77fa
AK		 2003 if (ctxt->op_bytes == 4)
2004 ctxt->_eip = (u32)ctxt->_eip;
2005 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 2006 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2007 return rc;
7b105ca2 2008 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 2009 return rc;
2010}
2011
e940b5c2
TY		 2012static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2013{
2014 /* Save real source value, then compare EAX against destination. */
2015 ctxt->src.orig_val = ctxt->src.val;
2016 ctxt->src.val = ctxt->regs[VCPU_REGS_RAX];
2017 emulate_2op_SrcV(ctxt, "cmp");
2018
2019 if (ctxt->eflags & EFLG_ZF) {
2020 /* Success: write back to memory. */
2021 ctxt->dst.val = ctxt->src.orig_val;
2022 } else {
2023 /* Failure: write the value we saw to EAX. */
2024 ctxt->dst.type = OP_REG;
2025 ctxt->dst.addr.reg = (unsigned long *)&ctxt->regs[VCPU_REGS_RAX];
2026 }
2027 return X86EMUL_CONTINUE;
2028}
2029
d4b4325f 2030static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 2031{
d4b4325f 2032 int seg = ctxt->src2.val;
09b5f4d3
WY		 2033 unsigned short sel;
2034 int rc;
2035
9dac77fa 2036 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 2037
7b105ca2 2038 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 2039 if (rc != X86EMUL_CONTINUE)
2040 return rc;
2041
9dac77fa 2042 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 2043 return rc;
2044}
2045
7b105ca2 2046static void
e66bb2cc 2047setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 2048 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 2049{
e66bb2cc 2050 cs->l = 0; /* will be adjusted later */
79168fd1 2051 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 2052 cs->g = 1; /* 4kb granularity */
79168fd1 2053 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2054 cs->type = 0x0b; /* Read, Execute, Accessed */
2055 cs->s = 1;
2056 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 2057 cs->p = 1;
2058 cs->d = 1;
99245b50 2059 cs->avl = 0;
e66bb2cc 2060
79168fd1
GN		 2061 set_desc_base(ss, 0); /* flat segment */
2062 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2063 ss->g = 1; /* 4kb granularity */
2064 ss->s = 1;
2065 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2066 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2067 ss->dpl = 0;
79168fd1 2068 ss->p = 1;
99245b50
GN		 2069 ss->l = 0;
2070 ss->avl = 0;
e66bb2cc
AP		 2071}
2072
1a18a69b
AK		 2073static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2074{
2075 u32 eax, ebx, ecx, edx;
2076
2077 eax = ecx = 0;
0017f93a
AK		 2078 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2079 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1a18a69b
AK		 2080 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2081 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2082}
2083
c2226fc9
SB		 2084static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2085{
2086 struct x86_emulate_ops *ops = ctxt->ops;
2087 u32 eax, ebx, ecx, edx;
2088
2089 /*
2090 * syscall should always be enabled in longmode - so only become
2091 * vendor specific (cpuid) if other modes are active...
2092 */
2093 if (ctxt->mode == X86EMUL_MODE_PROT64)
2094 return true;
2095
2096 eax = 0x00000000;
2097 ecx = 0x00000000;
0017f93a
AK		 2098 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2099 /*
2100 * Intel ("GenuineIntel")
2101 * remark: Intel CPUs only support "syscall" in 64bit
2102 * longmode. Also an 64bit guest with a
2103 * 32bit compat-app running will #UD !! While this
2104 * behaviour can be fixed (by emulating) into AMD
2105 * response - CPUs of AMD can't behave like Intel.
2106 */
2107 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2108 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2109 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2110 return false;
2111
2112 /* AMD ("AuthenticAMD") */
2113 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2114 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2115 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2116 return true;
2117
2118 /* AMD ("AMDisbetter!") */
2119 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2120 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2121 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2122 return true;
c2226fc9
SB		 2123
2124 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2125 return false;
2126}
2127
e01991e7 2128static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2129{
7b105ca2 2130 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2131 struct desc_struct cs, ss;
e66bb2cc 2132 u64 msr_data;
79168fd1 2133 u16 cs_sel, ss_sel;
c2ad2bb3 2134 u64 efer = 0;
e66bb2cc
AP		 2135
2136 /* syscall is not available in real mode */
2e901c4c 2137 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2138 ctxt->mode == X86EMUL_MODE_VM86)
2139 return emulate_ud(ctxt);
e66bb2cc 2140
c2226fc9
SB		 2141 if (!(em_syscall_is_enabled(ctxt)))
2142 return emulate_ud(ctxt);
2143
c2ad2bb3 2144 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2145 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2146
c2226fc9
SB		 2147 if (!(efer & EFER_SCE))
2148 return emulate_ud(ctxt);
2149
717746e3 2150 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2151 msr_data >>= 32;
79168fd1
GN		 2152 cs_sel = (u16)(msr_data & 0xfffc);
2153 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2154
c2ad2bb3 2155 if (efer & EFER_LMA) {
79168fd1 2156 cs.d = 0;
e66bb2cc
AP		 2157 cs.l = 1;
2158 }
1aa36616
AK		 2159 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2160 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2161
9dac77fa 2162 ctxt->regs[VCPU_REGS_RCX] = ctxt->_eip;
c2ad2bb3 2163 if (efer & EFER_LMA) {
e66bb2cc 2164#ifdef CONFIG_X86_64
9dac77fa 2165 ctxt->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
e66bb2cc 2166
717746e3 2167 ops->get_msr(ctxt,
3fb1b5db
GN		 2168 ctxt->mode == X86EMUL_MODE_PROT64 ?
2169 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2170 ctxt->_eip = msr_data;
e66bb2cc 2171
717746e3 2172 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 2173 ctxt->eflags &= ~(msr_data | EFLG_RF);
2174#endif
2175 } else {
2176 /* legacy mode */
717746e3 2177 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2178 ctxt->_eip = (u32)msr_data;
e66bb2cc
AP		 2179
2180 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
2181 }
2182
e54cfa97 2183 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2184}
2185
e01991e7 2186static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2187{
7b105ca2 2188 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2189 struct desc_struct cs, ss;
8c604352 2190 u64 msr_data;
79168fd1 2191 u16 cs_sel, ss_sel;
c2ad2bb3 2192 u64 efer = 0;
8c604352 2193
7b105ca2 2194 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2195 /* inject #GP if in real mode */
35d3d4a1
AK		 2196 if (ctxt->mode == X86EMUL_MODE_REAL)
2197 return emulate_gp(ctxt, 0);
8c604352 2198
1a18a69b
AK		 2199 /*
2200 * Not recognized on AMD in compat mode (but is recognized in legacy
2201 * mode).
2202 */
2203 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
2204 && !vendor_intel(ctxt))
2205 return emulate_ud(ctxt);
2206
8c604352
AP		 2207 /* XXX sysenter/sysexit have not been tested in 64bit mode.
2208 * Therefore, we inject an #UD.
2209 */
35d3d4a1
AK		 2210 if (ctxt->mode == X86EMUL_MODE_PROT64)
2211 return emulate_ud(ctxt);
8c604352 2212
7b105ca2 2213 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2214
717746e3 2215 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2216 switch (ctxt->mode) {
2217 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 2218 if ((msr_data & 0xfffc) == 0x0)
2219 return emulate_gp(ctxt, 0);
8c604352
AP		 2220 break;
2221 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 2222 if (msr_data == 0x0)
2223 return emulate_gp(ctxt, 0);
8c604352
AP		 2224 break;
2225 }
2226
2227 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 2228 cs_sel = (u16)msr_data;
2229 cs_sel &= ~SELECTOR_RPL_MASK;
2230 ss_sel = cs_sel + 8;
2231 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 2232 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 2233 cs.d = 0;
8c604352
AP		 2234 cs.l = 1;
2235 }
2236
1aa36616
AK		 2237 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2238 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2239
717746e3 2240 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 2241 ctxt->_eip = msr_data;
8c604352 2242
717746e3 2243 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
9dac77fa 2244 ctxt->regs[VCPU_REGS_RSP] = msr_data;
8c604352 2245
e54cfa97 2246 return X86EMUL_CONTINUE;
8c604352
AP		 2247}
2248
e01991e7 2249static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2250{
7b105ca2 2251 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2252 struct desc_struct cs, ss;
4668f050
AP		 2253 u64 msr_data;
2254 int usermode;
1249b96e 2255 u16 cs_sel = 0, ss_sel = 0;
4668f050 2256
a0044755
GN		 2257 /* inject #GP if in real mode or Virtual 8086 mode */
2258 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2259 ctxt->mode == X86EMUL_MODE_VM86)
2260 return emulate_gp(ctxt, 0);
4668f050 2261
7b105ca2 2262 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2263
9dac77fa 2264 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2265 usermode = X86EMUL_MODE_PROT64;
2266 else
2267 usermode = X86EMUL_MODE_PROT32;
2268
2269 cs.dpl = 3;
2270 ss.dpl = 3;
717746e3 2271 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2272 switch (usermode) {
2273 case X86EMUL_MODE_PROT32:
79168fd1 2274 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2275 if ((msr_data & 0xfffc) == 0x0)
2276 return emulate_gp(ctxt, 0);
79168fd1 2277 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2278 break;
2279 case X86EMUL_MODE_PROT64:
79168fd1 2280 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2281 if (msr_data == 0x0)
2282 return emulate_gp(ctxt, 0);
79168fd1
GN		 2283 ss_sel = cs_sel + 8;
2284 cs.d = 0;
4668f050
AP		 2285 cs.l = 1;
2286 break;
2287 }
79168fd1
GN		 2288 cs_sel |= SELECTOR_RPL_MASK;
2289 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2290
1aa36616
AK		 2291 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2292 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2293
9dac77fa
AK		 2294 ctxt->_eip = ctxt->regs[VCPU_REGS_RDX];
2295 ctxt->regs[VCPU_REGS_RSP] = ctxt->regs[VCPU_REGS_RCX];
4668f050 2296
e54cfa97 2297 return X86EMUL_CONTINUE;
4668f050
AP		 2298}
2299
7b105ca2 2300static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2301{
2302 int iopl;
2303 if (ctxt->mode == X86EMUL_MODE_REAL)
2304 return false;
2305 if (ctxt->mode == X86EMUL_MODE_VM86)
2306 return true;
2307 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2308 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2309}
2310
2311static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2312 u16 port, u16 len)
2313{
7b105ca2 2314 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2315 struct desc_struct tr_seg;
5601d05b 2316 u32 base3;
f850e2e6 2317 int r;
1aa36616 2318 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2319 unsigned mask = (1 << len) - 1;
5601d05b 2320 unsigned long base;
f850e2e6 2321
1aa36616 2322 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2323 if (!tr_seg.p)
f850e2e6 2324 return false;
79168fd1 2325 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2326 return false;
5601d05b
GN		 2327 base = get_desc_base(&tr_seg);
2328#ifdef CONFIG_X86_64
2329 base |= ((u64)base3) << 32;
2330#endif
0f65dd70 2331 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2332 if (r != X86EMUL_CONTINUE)
2333 return false;
79168fd1 2334 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2335 return false;
0f65dd70 2336 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2337 if (r != X86EMUL_CONTINUE)
2338 return false;
2339 if ((perm >> bit_idx) & mask)
2340 return false;
2341 return true;
2342}
2343
2344static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2345 u16 port, u16 len)
2346{
4fc40f07
GN		 2347 if (ctxt->perm_ok)
2348 return true;
2349
7b105ca2
TY		 2350 if (emulator_bad_iopl(ctxt))
2351 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2352 return false;
4fc40f07
GN		 2353
2354 ctxt->perm_ok = true;
2355
f850e2e6
GN		 2356 return true;
2357}
2358
38ba30ba 2359static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2360 struct tss_segment_16 *tss)
2361{
9dac77fa 2362 tss->ip = ctxt->_eip;
38ba30ba 2363 tss->flag = ctxt->eflags;
9dac77fa
AK		 2364 tss->ax = ctxt->regs[VCPU_REGS_RAX];
2365 tss->cx = ctxt->regs[VCPU_REGS_RCX];
2366 tss->dx = ctxt->regs[VCPU_REGS_RDX];
2367 tss->bx = ctxt->regs[VCPU_REGS_RBX];
2368 tss->sp = ctxt->regs[VCPU_REGS_RSP];
2369 tss->bp = ctxt->regs[VCPU_REGS_RBP];
2370 tss->si = ctxt->regs[VCPU_REGS_RSI];
2371 tss->di = ctxt->regs[VCPU_REGS_RDI];
38ba30ba 2372
1aa36616
AK		 2373 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2374 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2375 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2376 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2377 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2378}
2379
2380static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2381 struct tss_segment_16 *tss)
2382{
38ba30ba
GN		 2383 int ret;
2384
9dac77fa 2385 ctxt->_eip = tss->ip;
38ba30ba 2386 ctxt->eflags = tss->flag | 2;
9dac77fa
AK		 2387 ctxt->regs[VCPU_REGS_RAX] = tss->ax;
2388 ctxt->regs[VCPU_REGS_RCX] = tss->cx;
2389 ctxt->regs[VCPU_REGS_RDX] = tss->dx;
2390 ctxt->regs[VCPU_REGS_RBX] = tss->bx;
2391 ctxt->regs[VCPU_REGS_RSP] = tss->sp;
2392 ctxt->regs[VCPU_REGS_RBP] = tss->bp;
2393 ctxt->regs[VCPU_REGS_RSI] = tss->si;
2394 ctxt->regs[VCPU_REGS_RDI] = tss->di;
38ba30ba
GN		 2395
2396 /*
2397 * SDM says that segment selectors are loaded before segment
2398 * descriptors
2399 */
1aa36616
AK		 2400 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2401 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2402 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2403 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2404 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2405
2406 /*
fc058680 2407 * Now load segment descriptors. If fault happens at this stage
38ba30ba
GN		 2408 * it is handled in a context of new task
2409 */
7b105ca2 2410 ret = load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR);
38ba30ba
GN		 2411 if (ret != X86EMUL_CONTINUE)
2412 return ret;
7b105ca2 2413 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2414 if (ret != X86EMUL_CONTINUE)
2415 return ret;
7b105ca2 2416 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2417 if (ret != X86EMUL_CONTINUE)
2418 return ret;
7b105ca2 2419 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2420 if (ret != X86EMUL_CONTINUE)
2421 return ret;
7b105ca2 2422 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2423 if (ret != X86EMUL_CONTINUE)
2424 return ret;
2425
2426 return X86EMUL_CONTINUE;
2427}
2428
2429static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2430 u16 tss_selector, u16 old_tss_sel,
2431 ulong old_tss_base, struct desc_struct *new_desc)
2432{
7b105ca2 2433 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2434 struct tss_segment_16 tss_seg;
2435 int ret;
bcc55cba 2436 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2437
0f65dd70 2438 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2439 &ctxt->exception);
db297e3d 2440 if (ret != X86EMUL_CONTINUE)
38ba30ba 2441 /* FIXME: need to provide precise fault address */
38ba30ba 2442 return ret;
38ba30ba 2443
7b105ca2 2444 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2445
0f65dd70 2446 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2447 &ctxt->exception);
db297e3d 2448 if (ret != X86EMUL_CONTINUE)
38ba30ba 2449 /* FIXME: need to provide precise fault address */
38ba30ba 2450 return ret;
38ba30ba 2451
0f65dd70 2452 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2453 &ctxt->exception);
db297e3d 2454 if (ret != X86EMUL_CONTINUE)
38ba30ba 2455 /* FIXME: need to provide precise fault address */
38ba30ba 2456 return ret;
38ba30ba
GN		 2457
2458 if (old_tss_sel != 0xffff) {
2459 tss_seg.prev_task_link = old_tss_sel;
2460
0f65dd70 2461 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2462 &tss_seg.prev_task_link,
2463 sizeof tss_seg.prev_task_link,
0f65dd70 2464 &ctxt->exception);
db297e3d 2465 if (ret != X86EMUL_CONTINUE)
38ba30ba 2466 /* FIXME: need to provide precise fault address */
38ba30ba 2467 return ret;
38ba30ba
GN		 2468 }
2469
7b105ca2 2470 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2471}
2472
2473static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2474 struct tss_segment_32 *tss)
2475{
7b105ca2 2476 tss->cr3 = ctxt->ops->get_cr(ctxt, 3);
9dac77fa 2477 tss->eip = ctxt->_eip;
38ba30ba 2478 tss->eflags = ctxt->eflags;
9dac77fa
AK		 2479 tss->eax = ctxt->regs[VCPU_REGS_RAX];
2480 tss->ecx = ctxt->regs[VCPU_REGS_RCX];
2481 tss->edx = ctxt->regs[VCPU_REGS_RDX];
2482 tss->ebx = ctxt->regs[VCPU_REGS_RBX];
2483 tss->esp = ctxt->regs[VCPU_REGS_RSP];
2484 tss->ebp = ctxt->regs[VCPU_REGS_RBP];
2485 tss->esi = ctxt->regs[VCPU_REGS_RSI];
2486 tss->edi = ctxt->regs[VCPU_REGS_RDI];
38ba30ba 2487
1aa36616
AK		 2488 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2489 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2490 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2491 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2492 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2493 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
2494 tss->ldt_selector = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2495}
2496
2497static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2498 struct tss_segment_32 *tss)
2499{
38ba30ba
GN		 2500 int ret;
2501
7b105ca2 2502 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2503 return emulate_gp(ctxt, 0);
9dac77fa 2504 ctxt->_eip = tss->eip;
38ba30ba 2505 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 2506
2507 /* General purpose registers */
9dac77fa
AK		 2508 ctxt->regs[VCPU_REGS_RAX] = tss->eax;
2509 ctxt->regs[VCPU_REGS_RCX] = tss->ecx;
2510 ctxt->regs[VCPU_REGS_RDX] = tss->edx;
2511 ctxt->regs[VCPU_REGS_RBX] = tss->ebx;
2512 ctxt->regs[VCPU_REGS_RSP] = tss->esp;
2513 ctxt->regs[VCPU_REGS_RBP] = tss->ebp;
2514 ctxt->regs[VCPU_REGS_RSI] = tss->esi;
2515 ctxt->regs[VCPU_REGS_RDI] = tss->edi;
38ba30ba
GN		 2516
2517 /*
2518 * SDM says that segment selectors are loaded before segment
2519 * descriptors
2520 */
1aa36616
AK		 2521 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2522 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2523 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2524 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2525 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2526 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2527 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 2528
4cee4798
KW		 2529 /*
2530 * If we're switching between Protected Mode and VM86, we need to make
2531 * sure to update the mode before loading the segment descriptors so
2532 * that the selectors are interpreted correctly.
2533 *
2534 * Need to get rflags to the vcpu struct immediately because it
2535 * influences the CPL which is checked at least when loading the segment
2536 * descriptors and when pushing an error code to the new kernel stack.
2537 *
2538 * TODO Introduce a separate ctxt->ops->set_cpl callback
2539 */
2540 if (ctxt->eflags & X86_EFLAGS_VM)
2541 ctxt->mode = X86EMUL_MODE_VM86;
2542 else
2543 ctxt->mode = X86EMUL_MODE_PROT32;
2544
2545 ctxt->ops->set_rflags(ctxt, ctxt->eflags);
2546
38ba30ba
GN		 2547 /*
2548 * Now load segment descriptors. If fault happenes at this stage
2549 * it is handled in a context of new task
2550 */
7b105ca2 2551 ret = load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
38ba30ba
GN		 2552 if (ret != X86EMUL_CONTINUE)
2553 return ret;
7b105ca2 2554 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2555 if (ret != X86EMUL_CONTINUE)
2556 return ret;
7b105ca2 2557 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2558 if (ret != X86EMUL_CONTINUE)
2559 return ret;
7b105ca2 2560 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2561 if (ret != X86EMUL_CONTINUE)
2562 return ret;
7b105ca2 2563 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2564 if (ret != X86EMUL_CONTINUE)
2565 return ret;
7b105ca2 2566 ret = load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS);
38ba30ba
GN		 2567 if (ret != X86EMUL_CONTINUE)
2568 return ret;
7b105ca2 2569 ret = load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba
GN		 2570 if (ret != X86EMUL_CONTINUE)
2571 return ret;
2572
2573 return X86EMUL_CONTINUE;
2574}
2575
2576static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2577 u16 tss_selector, u16 old_tss_sel,
2578 ulong old_tss_base, struct desc_struct *new_desc)
2579{
7b105ca2 2580 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2581 struct tss_segment_32 tss_seg;
2582 int ret;
bcc55cba 2583 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2584
0f65dd70 2585 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2586 &ctxt->exception);
db297e3d 2587 if (ret != X86EMUL_CONTINUE)
38ba30ba 2588 /* FIXME: need to provide precise fault address */
38ba30ba 2589 return ret;
38ba30ba 2590
7b105ca2 2591 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2592
0f65dd70 2593 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2594 &ctxt->exception);
db297e3d 2595 if (ret != X86EMUL_CONTINUE)
38ba30ba 2596 /* FIXME: need to provide precise fault address */
38ba30ba 2597 return ret;
38ba30ba 2598
0f65dd70 2599 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2600 &ctxt->exception);
db297e3d 2601 if (ret != X86EMUL_CONTINUE)
38ba30ba 2602 /* FIXME: need to provide precise fault address */
38ba30ba 2603 return ret;
38ba30ba
GN		 2604
2605 if (old_tss_sel != 0xffff) {
2606 tss_seg.prev_task_link = old_tss_sel;
2607
0f65dd70 2608 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2609 &tss_seg.prev_task_link,
2610 sizeof tss_seg.prev_task_link,
0f65dd70 2611 &ctxt->exception);
db297e3d 2612 if (ret != X86EMUL_CONTINUE)
38ba30ba 2613 /* FIXME: need to provide precise fault address */
38ba30ba 2614 return ret;
38ba30ba
GN		 2615 }
2616
7b105ca2 2617 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2618}
2619
2620static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2621 u16 tss_selector, int idt_index, int reason,
e269fb21 2622 bool has_error_code, u32 error_code)
38ba30ba 2623{
7b105ca2 2624 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2625 struct desc_struct curr_tss_desc, next_tss_desc;
2626 int ret;
1aa36616 2627 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2628 ulong old_tss_base =
4bff1e86 2629 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2630 u32 desc_limit;
e919464b 2631 ulong desc_addr;
38ba30ba
GN		 2632
2633 /* FIXME: old_tss_base == ~0 ? */
2634
e919464b 2635 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
38ba30ba
GN		 2636 if (ret != X86EMUL_CONTINUE)
2637 return ret;
e919464b 2638 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
38ba30ba
GN		 2639 if (ret != X86EMUL_CONTINUE)
2640 return ret;
2641
2642 /* FIXME: check that next_tss_desc is tss */
2643
7f3d35fd
KW		 2644 /*
2645 * Check privileges. The three cases are task switch caused by...
2646 *
2647 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2648 * 2. Exception/IRQ/iret: No check is performed
fc058680 2649 * 3. jmp/call to TSS: Check against DPL of the TSS
7f3d35fd
KW		 2650 */
2651 if (reason == TASK_SWITCH_GATE) {
2652 if (idt_index != -1) {
2653 /* Software interrupts */
2654 struct desc_struct task_gate_desc;
2655 int dpl;
2656
2657 ret = read_interrupt_descriptor(ctxt, idt_index,
2658 &task_gate_desc);
2659 if (ret != X86EMUL_CONTINUE)
2660 return ret;
2661
2662 dpl = task_gate_desc.dpl;
2663 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2664 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2665 }
2666 } else if (reason != TASK_SWITCH_IRET) {
2667 int dpl = next_tss_desc.dpl;
2668 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2669 return emulate_gp(ctxt, tss_selector);
38ba30ba
GN		 2670 }
2671
7f3d35fd 2672
ceffb459
GN		 2673 desc_limit = desc_limit_scaled(&next_tss_desc);
2674 if (!next_tss_desc.p ||
2675 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2676 desc_limit < 0x2b)) {
54b8486f 2677 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2678 return X86EMUL_PROPAGATE_FAULT;
2679 }
2680
2681 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2682 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2683 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2684 }
2685
2686 if (reason == TASK_SWITCH_IRET)
2687 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2688
2689 /* set back link to prev task only if NT bit is set in eflags
fc058680 2690 note that old_tss_sel is not used after this point */
38ba30ba
GN		 2691 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2692 old_tss_sel = 0xffff;
2693
2694 if (next_tss_desc.type & 8)
7b105ca2 2695 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2696 old_tss_base, &next_tss_desc);
2697 else
7b105ca2 2698 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2699 old_tss_base, &next_tss_desc);
0760d448
JK		 2700 if (ret != X86EMUL_CONTINUE)
2701 return ret;
38ba30ba
GN		 2702
2703 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2704 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2705
2706 if (reason != TASK_SWITCH_IRET) {
2707 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2708 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2709 }
2710
717746e3 2711 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2712 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2713
e269fb21 2714 if (has_error_code) {
9dac77fa
AK		 2715 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2716 ctxt->lock_prefix = 0;
2717 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2718 ret = em_push(ctxt);
e269fb21
JK		 2719 }
2720
38ba30ba
GN		 2721 return ret;
2722}
2723
2724int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2725 u16 tss_selector, int idt_index, int reason,
e269fb21 2726 bool has_error_code, u32 error_code)
38ba30ba 2727{
38ba30ba
GN		 2728 int rc;
2729
9dac77fa
AK		 2730 ctxt->_eip = ctxt->eip;
2731 ctxt->dst.type = OP_NONE;
38ba30ba 2732
7f3d35fd 2733 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 2734 has_error_code, error_code);
38ba30ba 2735
4179bb02 2736 if (rc == X86EMUL_CONTINUE)
9dac77fa 2737 ctxt->eip = ctxt->_eip;
38ba30ba 2738
a0c0ab2f 2739 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2740}
2741
90de84f5 2742static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned seg,
d9271123 2743 int reg, struct operand *op)
a682e354 2744{
a682e354
GN		 2745 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2746
9dac77fa
AK		 2747 register_address_increment(ctxt, &ctxt->regs[reg], df * op->bytes);
2748 op->addr.mem.ea = register_address(ctxt, ctxt->regs[reg]);
90de84f5 2749 op->addr.mem.seg = seg;
a682e354
GN		 2750}
2751
7af04fc0
AK		 2752static int em_das(struct x86_emulate_ctxt *ctxt)
2753{
7af04fc0
AK		 2754 u8 al, old_al;
2755 bool af, cf, old_cf;
2756
2757 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2758 al = ctxt->dst.val;
7af04fc0
AK		 2759
2760 old_al = al;
2761 old_cf = cf;
2762 cf = false;
2763 af = ctxt->eflags & X86_EFLAGS_AF;
2764 if ((al & 0x0f) > 9 || af) {
2765 al -= 6;
2766 cf = old_cf | (al >= 250);
2767 af = true;
2768 } else {
2769 af = false;
2770 }
2771 if (old_al > 0x99 || old_cf) {
2772 al -= 0x60;
2773 cf = true;
2774 }
2775
9dac77fa 2776 ctxt->dst.val = al;
7af04fc0 2777 /* Set PF, ZF, SF */
9dac77fa
AK		 2778 ctxt->src.type = OP_IMM;
2779 ctxt->src.val = 0;
2780 ctxt->src.bytes = 1;
a31b9cea 2781 emulate_2op_SrcV(ctxt, "or");
7af04fc0
AK		 2782 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2783 if (cf)
2784 ctxt->eflags |= X86_EFLAGS_CF;
2785 if (af)
2786 ctxt->eflags |= X86_EFLAGS_AF;
2787 return X86EMUL_CONTINUE;
2788}
2789
d4ddafcd
TY		 2790static int em_call(struct x86_emulate_ctxt *ctxt)
2791{
2792 long rel = ctxt->src.val;
2793
2794 ctxt->src.val = (unsigned long)ctxt->_eip;
2795 jmp_rel(ctxt, rel);
2796 return em_push(ctxt);
2797}
2798
0ef753b8
AK		 2799static int em_call_far(struct x86_emulate_ctxt *ctxt)
2800{
0ef753b8
AK		 2801 u16 sel, old_cs;
2802 ulong old_eip;
2803 int rc;
2804
1aa36616 2805 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
9dac77fa 2806 old_eip = ctxt->_eip;
0ef753b8 2807
9dac77fa 2808 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
7b105ca2 2809 if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS))
0ef753b8
AK		 2810 return X86EMUL_CONTINUE;
2811
9dac77fa
AK		 2812 ctxt->_eip = 0;
2813 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
0ef753b8 2814
9dac77fa 2815 ctxt->src.val = old_cs;
4487b3b4 2816 rc = em_push(ctxt);
0ef753b8
AK		 2817 if (rc != X86EMUL_CONTINUE)
2818 return rc;
2819
9dac77fa 2820 ctxt->src.val = old_eip;
4487b3b4 2821 return em_push(ctxt);
0ef753b8
AK		 2822}
2823
40ece7c7
AK		 2824static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2825{
40ece7c7
AK		 2826 int rc;
2827
9dac77fa
AK		 2828 ctxt->dst.type = OP_REG;
2829 ctxt->dst.addr.reg = &ctxt->_eip;
2830 ctxt->dst.bytes = ctxt->op_bytes;
2831 rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
40ece7c7
AK		 2832 if (rc != X86EMUL_CONTINUE)
2833 return rc;
5ad105e5 2834 rsp_increment(ctxt, ctxt->src.val);
40ece7c7
AK		 2835 return X86EMUL_CONTINUE;
2836}
2837
d67fc27a
TY		 2838static int em_add(struct x86_emulate_ctxt *ctxt)
2839{
a31b9cea 2840 emulate_2op_SrcV(ctxt, "add");
d67fc27a
TY		 2841 return X86EMUL_CONTINUE;
2842}
2843
2844static int em_or(struct x86_emulate_ctxt *ctxt)
2845{
a31b9cea 2846 emulate_2op_SrcV(ctxt, "or");
d67fc27a
TY		 2847 return X86EMUL_CONTINUE;
2848}
2849
2850static int em_adc(struct x86_emulate_ctxt *ctxt)
2851{
a31b9cea 2852 emulate_2op_SrcV(ctxt, "adc");
d67fc27a
TY		 2853 return X86EMUL_CONTINUE;
2854}
2855
2856static int em_sbb(struct x86_emulate_ctxt *ctxt)
2857{
a31b9cea 2858 emulate_2op_SrcV(ctxt, "sbb");
d67fc27a
TY		 2859 return X86EMUL_CONTINUE;
2860}
2861
2862static int em_and(struct x86_emulate_ctxt *ctxt)
2863{
a31b9cea 2864 emulate_2op_SrcV(ctxt, "and");
d67fc27a
TY		 2865 return X86EMUL_CONTINUE;
2866}
2867
2868static int em_sub(struct x86_emulate_ctxt *ctxt)
2869{
a31b9cea 2870 emulate_2op_SrcV(ctxt, "sub");
d67fc27a
TY		 2871 return X86EMUL_CONTINUE;
2872}
2873
2874static int em_xor(struct x86_emulate_ctxt *ctxt)
2875{
a31b9cea 2876 emulate_2op_SrcV(ctxt, "xor");
d67fc27a
TY		 2877 return X86EMUL_CONTINUE;
2878}
2879
2880static int em_cmp(struct x86_emulate_ctxt *ctxt)
2881{
a31b9cea 2882 emulate_2op_SrcV(ctxt, "cmp");
d67fc27a 2883 /* Disable writeback. */
9dac77fa 2884 ctxt->dst.type = OP_NONE;
d67fc27a
TY		 2885 return X86EMUL_CONTINUE;
2886}
2887
9f21ca59
TY		 2888static int em_test(struct x86_emulate_ctxt *ctxt)
2889{
a31b9cea 2890 emulate_2op_SrcV(ctxt, "test");
caa8a168
AK		 2891 /* Disable writeback. */
2892 ctxt->dst.type = OP_NONE;
9f21ca59
TY		 2893 return X86EMUL_CONTINUE;
2894}
2895
e4f973ae
TY		 2896static int em_xchg(struct x86_emulate_ctxt *ctxt)
2897{
e4f973ae 2898 /* Write back the register source. */
9dac77fa
AK		 2899 ctxt->src.val = ctxt->dst.val;
2900 write_register_operand(&ctxt->src);
e4f973ae
TY		 2901
2902 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 2903 ctxt->dst.val = ctxt->src.orig_val;
2904 ctxt->lock_prefix = 1;
e4f973ae
TY		 2905 return X86EMUL_CONTINUE;
2906}
2907
5c82aa29 2908static int em_imul(struct x86_emulate_ctxt *ctxt)
f3a1b9f4 2909{
a31b9cea 2910 emulate_2op_SrcV_nobyte(ctxt, "imul");
f3a1b9f4
AK		 2911 return X86EMUL_CONTINUE;
2912}
2913
5c82aa29
AK		 2914static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2915{
9dac77fa 2916 ctxt->dst.val = ctxt->src2.val;
5c82aa29
AK		 2917 return em_imul(ctxt);
2918}
2919
61429142
AK		 2920static int em_cwd(struct x86_emulate_ctxt *ctxt)
2921{
9dac77fa
AK		 2922 ctxt->dst.type = OP_REG;
2923 ctxt->dst.bytes = ctxt->src.bytes;
2924 ctxt->dst.addr.reg = &ctxt->regs[VCPU_REGS_RDX];
2925 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 2926
2927 return X86EMUL_CONTINUE;
2928}
2929
48bb5d3c
AK		 2930static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2931{
48bb5d3c
AK		 2932 u64 tsc = 0;
2933
717746e3 2934 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
9dac77fa
AK		 2935 ctxt->regs[VCPU_REGS_RAX] = (u32)tsc;
2936 ctxt->regs[VCPU_REGS_RDX] = tsc >> 32;
48bb5d3c
AK		 2937 return X86EMUL_CONTINUE;
2938}
2939
222d21aa
AK		 2940static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
2941{
2942 u64 pmc;
2943
2944 if (ctxt->ops->read_pmc(ctxt, ctxt->regs[VCPU_REGS_RCX], &pmc))
2945 return emulate_gp(ctxt, 0);
2946 ctxt->regs[VCPU_REGS_RAX] = (u32)pmc;
2947 ctxt->regs[VCPU_REGS_RDX] = pmc >> 32;
2948 return X86EMUL_CONTINUE;
2949}
2950
b9eac5f4
AK		 2951static int em_mov(struct x86_emulate_ctxt *ctxt)
2952{
49597d81 2953 memcpy(ctxt->dst.valptr, ctxt->src.valptr, ctxt->op_bytes);
b9eac5f4
AK		 2954 return X86EMUL_CONTINUE;
2955}
2956
bc00f8d2
TY		 2957static int em_cr_write(struct x86_emulate_ctxt *ctxt)
2958{
2959 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
2960 return emulate_gp(ctxt, 0);
2961
2962 /* Disable writeback. */
2963 ctxt->dst.type = OP_NONE;
2964 return X86EMUL_CONTINUE;
2965}
2966
2967static int em_dr_write(struct x86_emulate_ctxt *ctxt)
2968{
2969 unsigned long val;
2970
2971 if (ctxt->mode == X86EMUL_MODE_PROT64)
2972 val = ctxt->src.val & ~0ULL;
2973 else
2974 val = ctxt->src.val & ~0U;
2975
2976 /* #UD condition is already handled. */
2977 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
2978 return emulate_gp(ctxt, 0);
2979
2980 /* Disable writeback. */
2981 ctxt->dst.type = OP_NONE;
2982 return X86EMUL_CONTINUE;
2983}
2984
e1e210b0
TY		 2985static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
2986{
2987 u64 msr_data;
2988
2989 msr_data = (u32)ctxt->regs[VCPU_REGS_RAX]
2990 | ((u64)ctxt->regs[VCPU_REGS_RDX] << 32);
2991 if (ctxt->ops->set_msr(ctxt, ctxt->regs[VCPU_REGS_RCX], msr_data))
2992 return emulate_gp(ctxt, 0);
2993
2994 return X86EMUL_CONTINUE;
2995}
2996
2997static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
2998{
2999 u64 msr_data;
3000
3001 if (ctxt->ops->get_msr(ctxt, ctxt->regs[VCPU_REGS_RCX], &msr_data))
3002 return emulate_gp(ctxt, 0);
3003
3004 ctxt->regs[VCPU_REGS_RAX] = (u32)msr_data;
3005 ctxt->regs[VCPU_REGS_RDX] = msr_data >> 32;
3006 return X86EMUL_CONTINUE;
3007}
3008
1bd5f469
TY		 3009static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3010{
9dac77fa 3011 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3012 return emulate_ud(ctxt);
3013
9dac77fa 3014 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
1bd5f469
TY		 3015 return X86EMUL_CONTINUE;
3016}
3017
3018static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3019{
9dac77fa 3020 u16 sel = ctxt->src.val;
1bd5f469 3021
9dac77fa 3022 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3023 return emulate_ud(ctxt);
3024
9dac77fa 3025 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 3026 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3027
3028 /* Disable writeback. */
9dac77fa
AK		 3029 ctxt->dst.type = OP_NONE;
3030 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 3031}
3032
a14e579f
AK		 3033static int em_lldt(struct x86_emulate_ctxt *ctxt)
3034{
3035 u16 sel = ctxt->src.val;
3036
3037 /* Disable writeback. */
3038 ctxt->dst.type = OP_NONE;
3039 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3040}
3041
80890006
AK		 3042static int em_ltr(struct x86_emulate_ctxt *ctxt)
3043{
3044 u16 sel = ctxt->src.val;
3045
3046 /* Disable writeback. */
3047 ctxt->dst.type = OP_NONE;
3048 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3049}
3050
38503911
AK		 3051static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3052{
9fa088f4
AK		 3053 int rc;
3054 ulong linear;
3055
9dac77fa 3056 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 3057 if (rc == X86EMUL_CONTINUE)
3cb16fe7 3058 ctxt->ops->invlpg(ctxt, linear);
38503911 3059 /* Disable writeback. */
9dac77fa 3060 ctxt->dst.type = OP_NONE;
38503911
AK		 3061 return X86EMUL_CONTINUE;
3062}
3063
2d04a05b
AK		 3064static int em_clts(struct x86_emulate_ctxt *ctxt)
3065{
3066 ulong cr0;
3067
3068 cr0 = ctxt->ops->get_cr(ctxt, 0);
3069 cr0 &= ~X86_CR0_TS;
3070 ctxt->ops->set_cr(ctxt, 0, cr0);
3071 return X86EMUL_CONTINUE;
3072}
3073
26d05cc7
AK		 3074static int em_vmcall(struct x86_emulate_ctxt *ctxt)
3075{
26d05cc7
AK		 3076 int rc;
3077
9dac77fa 3078 if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1)
26d05cc7
AK		 3079 return X86EMUL_UNHANDLEABLE;
3080
3081 rc = ctxt->ops->fix_hypercall(ctxt);
3082 if (rc != X86EMUL_CONTINUE)
3083 return rc;
3084
3085 /* Let the processor re-execute the fixed hypercall */
9dac77fa 3086 ctxt->_eip = ctxt->eip;
26d05cc7 3087 /* Disable writeback. */
9dac77fa 3088 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3089 return X86EMUL_CONTINUE;
3090}
3091
96051572
AK		 3092static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3093 void (*get)(struct x86_emulate_ctxt *ctxt,
3094 struct desc_ptr *ptr))
3095{
3096 struct desc_ptr desc_ptr;
3097
3098 if (ctxt->mode == X86EMUL_MODE_PROT64)
3099 ctxt->op_bytes = 8;
3100 get(ctxt, &desc_ptr);
3101 if (ctxt->op_bytes == 2) {
3102 ctxt->op_bytes = 4;
3103 desc_ptr.address &= 0x00ffffff;
3104 }
3105 /* Disable writeback. */
3106 ctxt->dst.type = OP_NONE;
3107 return segmented_write(ctxt, ctxt->dst.addr.mem,
3108 &desc_ptr, 2 + ctxt->op_bytes);
3109}
3110
3111static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3112{
3113 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3114}
3115
3116static int em_sidt(struct x86_emulate_ctxt *ctxt)
3117{
3118 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3119}
3120
26d05cc7
AK		 3121static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3122{
26d05cc7
AK		 3123 struct desc_ptr desc_ptr;
3124 int rc;
3125
510425ff
AK		 3126 if (ctxt->mode == X86EMUL_MODE_PROT64)
3127 ctxt->op_bytes = 8;
9dac77fa 3128 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3129 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3130 ctxt->op_bytes);
26d05cc7
AK		 3131 if (rc != X86EMUL_CONTINUE)
3132 return rc;
3133 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3134 /* Disable writeback. */
9dac77fa 3135 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3136 return X86EMUL_CONTINUE;
3137}
3138
5ef39c71 3139static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3140{
26d05cc7
AK		 3141 int rc;
3142
5ef39c71
AK		 3143 rc = ctxt->ops->fix_hypercall(ctxt);
3144
26d05cc7 3145 /* Disable writeback. */
9dac77fa 3146 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3147 return rc;
3148}
3149
3150static int em_lidt(struct x86_emulate_ctxt *ctxt)
3151{
26d05cc7
AK		 3152 struct desc_ptr desc_ptr;
3153 int rc;
3154
510425ff
AK		 3155 if (ctxt->mode == X86EMUL_MODE_PROT64)
3156 ctxt->op_bytes = 8;
9dac77fa 3157 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
509cf9fe 3158 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3159 ctxt->op_bytes);
26d05cc7
AK		 3160 if (rc != X86EMUL_CONTINUE)
3161 return rc;
3162 ctxt->ops->set_idt(ctxt, &desc_ptr);
3163 /* Disable writeback. */
9dac77fa 3164 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3165 return X86EMUL_CONTINUE;
3166}
3167
3168static int em_smsw(struct x86_emulate_ctxt *ctxt)
3169{
9dac77fa
AK		 3170 ctxt->dst.bytes = 2;
3171 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3172 return X86EMUL_CONTINUE;
3173}
3174
3175static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3176{
26d05cc7 3177 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3178 | (ctxt->src.val & 0x0f));
3179 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3180 return X86EMUL_CONTINUE;
3181}
3182
d06e03ad
TY		 3183static int em_loop(struct x86_emulate_ctxt *ctxt)
3184{
9dac77fa
AK		 3185 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RCX], -1);
3186 if ((address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) != 0) &&
3187 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
3188 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3189
3190 return X86EMUL_CONTINUE;
3191}
3192
3193static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3194{
9dac77fa
AK		 3195 if (address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) == 0)
3196 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3197
3198 return X86EMUL_CONTINUE;
3199}
3200
d7841a4b
TY		 3201static int em_in(struct x86_emulate_ctxt *ctxt)
3202{
3203 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3204 &ctxt->dst.val))
3205 return X86EMUL_IO_NEEDED;
3206
3207 return X86EMUL_CONTINUE;
3208}
3209
3210static int em_out(struct x86_emulate_ctxt *ctxt)
3211{
3212 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3213 &ctxt->src.val, 1);
3214 /* Disable writeback. */
3215 ctxt->dst.type = OP_NONE;
3216 return X86EMUL_CONTINUE;
3217}
3218
f411e6cd
TY		 3219static int em_cli(struct x86_emulate_ctxt *ctxt)
3220{
3221 if (emulator_bad_iopl(ctxt))
3222 return emulate_gp(ctxt, 0);
3223
3224 ctxt->eflags &= ~X86_EFLAGS_IF;
3225 return X86EMUL_CONTINUE;
3226}
3227
3228static int em_sti(struct x86_emulate_ctxt *ctxt)
3229{
3230 if (emulator_bad_iopl(ctxt))
3231 return emulate_gp(ctxt, 0);
3232
3233 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3234 ctxt->eflags |= X86_EFLAGS_IF;
3235 return X86EMUL_CONTINUE;
3236}
3237
ce7faab2
TY		 3238static int em_bt(struct x86_emulate_ctxt *ctxt)
3239{
3240 /* Disable writeback. */
3241 ctxt->dst.type = OP_NONE;
3242 /* only subword offset */
3243 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
3244
3245 emulate_2op_SrcV_nobyte(ctxt, "bt");
3246 return X86EMUL_CONTINUE;
3247}
3248
3249static int em_bts(struct x86_emulate_ctxt *ctxt)
3250{
3251 emulate_2op_SrcV_nobyte(ctxt, "bts");
3252 return X86EMUL_CONTINUE;
3253}
3254
3255static int em_btr(struct x86_emulate_ctxt *ctxt)
3256{
3257 emulate_2op_SrcV_nobyte(ctxt, "btr");
3258 return X86EMUL_CONTINUE;
3259}
3260
3261static int em_btc(struct x86_emulate_ctxt *ctxt)
3262{
3263 emulate_2op_SrcV_nobyte(ctxt, "btc");
3264 return X86EMUL_CONTINUE;
3265}
3266
ff227392
TY		 3267static int em_bsf(struct x86_emulate_ctxt *ctxt)
3268{
d54e4237 3269 emulate_2op_SrcV_nobyte(ctxt, "bsf");
ff227392
TY		 3270 return X86EMUL_CONTINUE;
3271}
3272
3273static int em_bsr(struct x86_emulate_ctxt *ctxt)
3274{
d54e4237 3275 emulate_2op_SrcV_nobyte(ctxt, "bsr");
ff227392
TY		 3276 return X86EMUL_CONTINUE;
3277}
3278
6d6eede4
AK		 3279static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3280{
3281 u32 eax, ebx, ecx, edx;
3282
3283 eax = ctxt->regs[VCPU_REGS_RAX];
3284 ecx = ctxt->regs[VCPU_REGS_RCX];
3285 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
3286 ctxt->regs[VCPU_REGS_RAX] = eax;
3287 ctxt->regs[VCPU_REGS_RBX] = ebx;
3288 ctxt->regs[VCPU_REGS_RCX] = ecx;
3289 ctxt->regs[VCPU_REGS_RDX] = edx;
3290 return X86EMUL_CONTINUE;
3291}
3292
2dd7caa0
AK		 3293static int em_lahf(struct x86_emulate_ctxt *ctxt)
3294{
3295 ctxt->regs[VCPU_REGS_RAX] &= ~0xff00UL;
3296 ctxt->regs[VCPU_REGS_RAX] |= (ctxt->eflags & 0xff) << 8;
3297 return X86EMUL_CONTINUE;
3298}
3299
9299836e
AK		 3300static int em_bswap(struct x86_emulate_ctxt *ctxt)
3301{
3302 switch (ctxt->op_bytes) {
3303#ifdef CONFIG_X86_64
3304 case 8:
3305 asm("bswap %0" : "+r"(ctxt->dst.val));
3306 break;
3307#endif
3308 default:
3309 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3310 break;
3311 }
3312 return X86EMUL_CONTINUE;
3313}
3314
cfec82cb
JR		 3315static bool valid_cr(int nr)
3316{
3317 switch (nr) {
3318 case 0:
3319 case 2 ... 4:
3320 case 8:
3321 return true;
3322 default:
3323 return false;
3324 }
3325}
3326
3327static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3328{
9dac77fa 3329 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 3330 return emulate_ud(ctxt);
3331
3332 return X86EMUL_CONTINUE;
3333}
3334
3335static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3336{
9dac77fa
AK		 3337 u64 new_val = ctxt->src.val64;
3338 int cr = ctxt->modrm_reg;
c2ad2bb3 3339 u64 efer = 0;
cfec82cb
JR		 3340
3341 static u64 cr_reserved_bits[] = {
3342 0xffffffff00000000ULL,
3343 0, 0, 0, /* CR3 checked later */
3344 CR4_RESERVED_BITS,
3345 0, 0, 0,
3346 CR8_RESERVED_BITS,
3347 };
3348
3349 if (!valid_cr(cr))
3350 return emulate_ud(ctxt);
3351
3352 if (new_val & cr_reserved_bits[cr])
3353 return emulate_gp(ctxt, 0);
3354
3355 switch (cr) {
3356 case 0: {
c2ad2bb3 3357 u64 cr4;
cfec82cb
JR		 3358 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3359 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3360 return emulate_gp(ctxt, 0);
3361
717746e3
AK		 3362 cr4 = ctxt->ops->get_cr(ctxt, 4);
3363 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3364
3365 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3366 !(cr4 & X86_CR4_PAE))
3367 return emulate_gp(ctxt, 0);
3368
3369 break;
3370 }
3371 case 3: {
3372 u64 rsvd = 0;
3373
c2ad2bb3
AK		 3374 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3375 if (efer & EFER_LMA)
cfec82cb 3376 rsvd = CR3_L_MODE_RESERVED_BITS;
fd72c419 3377 else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE)
cfec82cb 3378 rsvd = CR3_PAE_RESERVED_BITS;
fd72c419 3379 else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG)
cfec82cb
JR		 3380 rsvd = CR3_NONPAE_RESERVED_BITS;
3381
3382 if (new_val & rsvd)
3383 return emulate_gp(ctxt, 0);
3384
3385 break;
3386 }
3387 case 4: {
717746e3 3388 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3389
3390 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3391 return emulate_gp(ctxt, 0);
3392
3393 break;
3394 }
3395 }
3396
3397 return X86EMUL_CONTINUE;
3398}
3399
3b88e41a
JR		 3400static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3401{
3402 unsigned long dr7;
3403
717746e3 3404 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 3405
3406 /* Check if DR7.Global_Enable is set */
3407 return dr7 & (1 << 13);
3408}
3409
3410static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3411{
9dac77fa 3412 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3413 u64 cr4;
3414
3415 if (dr > 7)
3416 return emulate_ud(ctxt);
3417
717746e3 3418 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 3419 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3420 return emulate_ud(ctxt);
3421
3422 if (check_dr7_gd(ctxt))
3423 return emulate_db(ctxt);
3424
3425 return X86EMUL_CONTINUE;
3426}
3427
3428static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3429{
9dac77fa
AK		 3430 u64 new_val = ctxt->src.val64;
3431 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3432
3433 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3434 return emulate_gp(ctxt, 0);
3435
3436 return check_dr_read(ctxt);
3437}
3438
01de8b09
JR		 3439static int check_svme(struct x86_emulate_ctxt *ctxt)
3440{
3441 u64 efer;
3442
717746e3 3443 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 3444
3445 if (!(efer & EFER_SVME))
3446 return emulate_ud(ctxt);
3447
3448 return X86EMUL_CONTINUE;
3449}
3450
3451static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3452{
9dac77fa 3453 u64 rax = ctxt->regs[VCPU_REGS_RAX];
01de8b09
JR		 3454
3455 /* Valid physical address? */
d4224449 3456 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 3457 return emulate_gp(ctxt, 0);
3458
3459 return check_svme(ctxt);
3460}
3461
d7eb8203
JR		 3462static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3463{
717746e3 3464 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 3465
717746e3 3466 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 3467 return emulate_ud(ctxt);
3468
3469 return X86EMUL_CONTINUE;
3470}
3471
8061252e
JR		 3472static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3473{
717746e3 3474 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
9dac77fa 3475 u64 rcx = ctxt->regs[VCPU_REGS_RCX];
8061252e 3476
717746e3 3477 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
8061252e
JR		 3478 (rcx > 3))
3479 return emulate_gp(ctxt, 0);
3480
3481 return X86EMUL_CONTINUE;
3482}
3483
f6511935
JR		 3484static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3485{
9dac77fa
AK		 3486 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3487 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 3488 return emulate_gp(ctxt, 0);
3489
3490 return X86EMUL_CONTINUE;
3491}
3492
3493static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3494{
9dac77fa
AK		 3495 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3496 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 3497 return emulate_gp(ctxt, 0);
3498
3499 return X86EMUL_CONTINUE;
3500}
3501
73fba5f4 3502#define D(_y) { .flags = (_y) }
c4f035c6 3503#define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
d09beabd
JR		 3504#define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
3505 .check_perm = (_p) }
73fba5f4 3506#define N D(0)
01de8b09 3507#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 3508#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3509#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
73fba5f4 3510#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
c4f035c6
AK		 3511#define II(_f, _e, _i) \
3512 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd
JR		 3513#define IIP(_f, _e, _i, _p) \
3514 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
3515 .check_perm = (_p) }
aa97bb48 3516#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3517
8d8f4e9f 3518#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3519#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 3520#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
d7841a4b
TY		 3521#define I2bvIP(_f, _e, _i, _p) \
3522 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 3523
d67fc27a
TY		 3524#define I6ALU(_f, _e) I2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3525 I2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3526 I2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3527
d7eb8203 3528static struct opcode group7_rm1[] = {
1c2545be
TY		 3529 DI(SrcNone | Priv, monitor),
3530 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 3531 N, N, N, N, N, N,
3532};
3533
01de8b09 3534static struct opcode group7_rm3[] = {
1c2545be
TY		 3535 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
3536 II(SrcNone | Prot | VendorSpecific, em_vmmcall, vmmcall),
3537 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3538 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3539 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3540 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3541 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3542 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 3543};
6230f7fc 3544
d7eb8203
JR		 3545static struct opcode group7_rm7[] = {
3546 N,
1c2545be 3547 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 3548 N, N, N, N, N, N,
3549};
d67fc27a 3550
73fba5f4 3551static struct opcode group1[] = {
d67fc27a 3552 I(Lock, em_add),
d5ae7ce8 3553 I(Lock | PageTable, em_or),
d67fc27a
TY		 3554 I(Lock, em_adc),
3555 I(Lock, em_sbb),
d5ae7ce8 3556 I(Lock | PageTable, em_and),
d67fc27a
TY		 3557 I(Lock, em_sub),
3558 I(Lock, em_xor),
3559 I(0, em_cmp),
73fba5f4
AK		 3560};
3561
3562static struct opcode group1A[] = {
1c2545be 3563 I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 3564};
3565
3566static struct opcode group3[] = {
1c2545be
TY		 3567 I(DstMem | SrcImm, em_test),
3568 I(DstMem | SrcImm, em_test),
3569 I(DstMem | SrcNone | Lock, em_not),
3570 I(DstMem | SrcNone | Lock, em_neg),
3571 I(SrcMem, em_mul_ex),
3572 I(SrcMem, em_imul_ex),
3573 I(SrcMem, em_div_ex),
3574 I(SrcMem, em_idiv_ex),
73fba5f4
AK		 3575};
3576
3577static struct opcode group4[] = {
1c2545be
TY		 3578 I(ByteOp | DstMem | SrcNone | Lock, em_grp45),
3579 I(ByteOp | DstMem | SrcNone | Lock, em_grp45),
73fba5f4
AK		 3580 N, N, N, N, N, N,
3581};
3582
3583static struct opcode group5[] = {
1c2545be
TY		 3584 I(DstMem | SrcNone | Lock, em_grp45),
3585 I(DstMem | SrcNone | Lock, em_grp45),
3586 I(SrcMem | Stack, em_grp45),
3587 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far),
3588 I(SrcMem | Stack, em_grp45),
3589 I(SrcMemFAddr | ImplicitOps, em_grp45),
3590 I(SrcMem | Stack, em_grp45), N,
73fba5f4
AK		 3591};
3592
dee6bb70 3593static struct opcode group6[] = {
1c2545be
TY		 3594 DI(Prot, sldt),
3595 DI(Prot, str),
a14e579f 3596 II(Prot | Priv | SrcMem16, em_lldt, lldt),
80890006 3597 II(Prot | Priv | SrcMem16, em_ltr, ltr),
dee6bb70
JR		 3598 N, N, N, N,
3599};
3600
73fba5f4 3601static struct group_dual group7 = { {
96051572
AK		 3602 II(Mov | DstMem | Priv, em_sgdt, sgdt),
3603 II(Mov | DstMem | Priv, em_sidt, sidt),
1c2545be
TY		 3604 II(SrcMem | Priv, em_lgdt, lgdt),
3605 II(SrcMem | Priv, em_lidt, lidt),
3606 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3607 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3608 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3609}, {
1c2545be 3610 I(SrcNone | Priv | VendorSpecific, em_vmcall),
5ef39c71 3611 EXT(0, group7_rm1),
01de8b09 3612 N, EXT(0, group7_rm3),
1c2545be
TY		 3613 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3614 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3615 EXT(0, group7_rm7),
73fba5f4
AK		 3616} };
3617
3618static struct opcode group8[] = {
3619 N, N, N, N,
1c2545be
TY		 3620 I(DstMem | SrcImmByte, em_bt),
3621 I(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3622 I(DstMem | SrcImmByte | Lock, em_btr),
3623 I(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 3624};
3625
3626static struct group_dual group9 = { {
1c2545be 3627 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 3628}, {
3629 N, N, N, N, N, N, N, N,
3630} };
3631
a4d4a7c1 3632static struct opcode group11[] = {
1c2545be 3633 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 3634 X7(D(Undefined)),
a4d4a7c1
AK		 3635};
3636
aa97bb48 3637static struct gprefix pfx_0f_6f_0f_7f = {
e5971755 3638 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 3639};
3640
3e114eb4
AK		 3641static struct gprefix pfx_vmovntpx = {
3642 I(0, em_mov), N, N, N,
3643};
3644
73fba5f4
AK		 3645static struct opcode opcode_table[256] = {
3646 /* 0x00 - 0x07 */
d67fc27a 3647 I6ALU(Lock, em_add),
1cd196ea
AK		 3648 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3649 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 3650 /* 0x08 - 0x0F */
d5ae7ce8 3651 I6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 3652 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3653 N,
73fba5f4 3654 /* 0x10 - 0x17 */
d67fc27a 3655 I6ALU(Lock, em_adc),
1cd196ea
AK		 3656 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3657 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 3658 /* 0x18 - 0x1F */
d67fc27a 3659 I6ALU(Lock, em_sbb),
1cd196ea
AK		 3660 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3661 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 3662 /* 0x20 - 0x27 */
d5ae7ce8 3663 I6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 3664 /* 0x28 - 0x2F */
d67fc27a 3665 I6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3666 /* 0x30 - 0x37 */
d67fc27a 3667 I6ALU(Lock, em_xor), N, N,
73fba5f4 3668 /* 0x38 - 0x3F */
d67fc27a 3669 I6ALU(0, em_cmp), N, N,
73fba5f4
AK		 3670 /* 0x40 - 0x4F */
3671 X16(D(DstReg)),
3672 /* 0x50 - 0x57 */
63540382 3673 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3674 /* 0x58 - 0x5F */
c54fe504 3675 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3676 /* 0x60 - 0x67 */
b96a7fad
TY		 3677 I(ImplicitOps | Stack | No64, em_pusha),
3678 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3679 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3680 N, N, N, N,
3681 /* 0x68 - 0x6F */
d46164db
AK		 3682 I(SrcImm | Mov | Stack, em_push),
3683 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3684 I(SrcImmByte | Mov | Stack, em_push),
3685 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
2b5e97e1
TY		 3686 I2bvIP(DstDI | SrcDX | Mov | String, em_in, ins, check_perm_in), /* insb, insw/insd */
3687 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4
AK		 3688 /* 0x70 - 0x7F */
3689 X16(D(SrcImmByte)),
3690 /* 0x80 - 0x87 */
1c2545be
TY		 3691 G(ByteOp | DstMem | SrcImm, group1),
3692 G(DstMem | SrcImm, group1),
3693 G(ByteOp | DstMem | SrcImm | No64, group1),
3694 G(DstMem | SrcImmByte, group1),
9f21ca59 3695 I2bv(DstMem | SrcReg | ModRM, em_test),
d5ae7ce8 3696 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 3697 /* 0x88 - 0x8F */
d5ae7ce8 3698 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 3699 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 3700 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 3701 D(ModRM | SrcMem | NoAccess | DstReg),
3702 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3703 G(0, group1A),
73fba5f4 3704 /* 0x90 - 0x97 */
bf608f88 3705 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3706 /* 0x98 - 0x9F */
61429142 3707 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3708 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0 3709 II(ImplicitOps | Stack, em_pushf, pushf),
2dd7caa0 3710 II(ImplicitOps | Stack, em_popf, popf), N, I(ImplicitOps, em_lahf),
73fba5f4 3711 /* 0xA0 - 0xA7 */
b9eac5f4 3712 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 3713 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 3714 I2bv(SrcSI | DstDI | Mov | String, em_mov),
d67fc27a 3715 I2bv(SrcSI | DstDI | String, em_cmp),
73fba5f4 3716 /* 0xA8 - 0xAF */
9f21ca59 3717 I2bv(DstAcc | SrcImm, em_test),
b9eac5f4
AK		 3718 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3719 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
d67fc27a 3720 I2bv(SrcAcc | DstDI | String, em_cmp),
73fba5f4 3721 /* 0xB0 - 0xB7 */
b9eac5f4 3722 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3723 /* 0xB8 - 0xBF */
b9eac5f4 3724 X8(I(DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3725 /* 0xC0 - 0xC7 */
d2c6c7ad 3726 D2bv(DstMem | SrcImmByte | ModRM),
40ece7c7 3727 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
ebda02c2 3728 I(ImplicitOps | Stack, em_ret),
d4b4325f
AK		 3729 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
3730 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 3731 G(ByteOp, group11), G(0, group11),
73fba5f4 3732 /* 0xC8 - 0xCF */
612e89f0
AK		 3733 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
3734 N, I(ImplicitOps | Stack, em_ret_far),
3c6e276f 3735 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 3736 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 3737 /* 0xD0 - 0xD7 */
d2c6c7ad 3738 D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM),
73fba5f4
AK		 3739 N, N, N, N,
3740 /* 0xD8 - 0xDF */
3741 N, N, N, N, N, N, N, N,
3742 /* 0xE0 - 0xE7 */
d06e03ad
TY		 3743 X3(I(SrcImmByte, em_loop)),
3744 I(SrcImmByte, em_jcxz),
d7841a4b
TY		 3745 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
3746 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 3747 /* 0xE8 - 0xEF */
d4ddafcd 3748 I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps),
db5b0762 3749 I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
d7841a4b
TY		 3750 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
3751 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 3752 /* 0xF0 - 0xF7 */
bf608f88 3753 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 3754 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3755 G(ByteOp, group3), G(0, group3),
73fba5f4 3756 /* 0xF8 - 0xFF */
f411e6cd
TY		 3757 D(ImplicitOps), D(ImplicitOps),
3758 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 3759 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3760};
3761
3762static struct opcode twobyte_table[256] = {
3763 /* 0x00 - 0x0F */
dee6bb70 3764 G(0, group6), GD(0, &group7), N, N,
db5b0762
TY		 3765 N, I(ImplicitOps | VendorSpecific, em_syscall),
3766 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 3767 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK		 3768 N, D(ImplicitOps | ModRM), N, N,
3769 /* 0x10 - 0x1F */
3770 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
3771 /* 0x20 - 0x2F */
cfec82cb 3772 DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
3b88e41a 3773 DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
bc00f8d2
TY		 3774 IIP(ModRM | SrcMem | Priv | Op3264, em_cr_write, cr_write, check_cr_write),
3775 IIP(ModRM | SrcMem | Priv | Op3264, em_dr_write, dr_write, check_dr_write),
73fba5f4 3776 N, N, N, N,
3e114eb4
AK		 3777 N, N, N, GP(ModRM | DstMem | SrcReg | Sse | Mov | Aligned, &pfx_vmovntpx),
3778 N, N, N, N,
73fba5f4 3779 /* 0x30 - 0x3F */
e1e210b0 3780 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 3781 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 3782 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 3783 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
db5b0762
TY		 3784 I(ImplicitOps | VendorSpecific, em_sysenter),
3785 I(ImplicitOps | Priv | VendorSpecific, em_sysexit),
d867162c 3786 N, N,
73fba5f4
AK		 3787 N, N, N, N, N, N, N, N,
3788 /* 0x40 - 0x4F */
3789 X16(D(DstReg | SrcMem | ModRM | Mov)),
3790 /* 0x50 - 0x5F */
3791 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3792 /* 0x60 - 0x6F */
aa97bb48
AK		 3793 N, N, N, N,
3794 N, N, N, N,
3795 N, N, N, N,
3796 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 3797 /* 0x70 - 0x7F */
aa97bb48
AK		 3798 N, N, N, N,
3799 N, N, N, N,
3800 N, N, N, N,
3801 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK		 3802 /* 0x80 - 0x8F */
3803 X16(D(SrcImm)),
3804 /* 0x90 - 0x9F */
ee45b58e 3805 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 3806 /* 0xA0 - 0xA7 */
1cd196ea 3807 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
6d6eede4 3808 II(ImplicitOps, em_cpuid, cpuid), I(DstMem | SrcReg | ModRM | BitOp, em_bt),
73fba5f4
AK		 3809 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3810 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
3811 /* 0xA8 - 0xAF */
1cd196ea 3812 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
d5ae7ce8 3813 DI(ImplicitOps, rsm),
ce7faab2 3814 I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
73fba5f4
AK		 3815 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3816 D(DstMem | SrcReg | Src2CL | ModRM),
5c82aa29 3817 D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 3818 /* 0xB0 - 0xB7 */
e940b5c2 3819 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
d4b4325f 3820 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
ce7faab2 3821 I(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 3822 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
3823 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 3824 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 3825 /* 0xB8 - 0xBF */
3826 N, N,
ce7faab2
TY		 3827 G(BitOp, group8),
3828 I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
ff227392 3829 I(DstReg | SrcMem | ModRM, em_bsf), I(DstReg | SrcMem | ModRM, em_bsr),
2adb5ad9 3830 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
9299836e 3831 /* 0xC0 - 0xC7 */
739ae406 3832 D2bv(DstMem | SrcReg | ModRM | Lock),
92f738a5 3833 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4 3834 N, N, N, GD(0, &group9),
9299836e
AK		 3835 /* 0xC8 - 0xCF */
3836 X8(I(DstReg, em_bswap)),
73fba5f4
AK		 3837 /* 0xD0 - 0xDF */
3838 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3839 /* 0xE0 - 0xEF */
3840 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3841 /* 0xF0 - 0xFF */
3842 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
3843};
3844
3845#undef D
3846#undef N
3847#undef G
3848#undef GD
3849#undef I
aa97bb48 3850#undef GP
01de8b09 3851#undef EXT
73fba5f4 3852
8d8f4e9f 3853#undef D2bv
f6511935 3854#undef D2bvIP
8d8f4e9f 3855#undef I2bv
d7841a4b 3856#undef I2bvIP
d67fc27a 3857#undef I6ALU
8d8f4e9f 3858
9dac77fa 3859static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 3860{
3861 unsigned size;
3862
9dac77fa 3863 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 3864 if (size == 8)
3865 size = 4;
3866 return size;
3867}
3868
3869static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
3870 unsigned size, bool sign_extension)
3871{
39f21ee5
AK		 3872 int rc = X86EMUL_CONTINUE;
3873
3874 op->type = OP_IMM;
3875 op->bytes = size;
9dac77fa 3876 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 3877 /* NB. Immediates are sign-extended as necessary. */
3878 switch (op->bytes) {
3879 case 1:
e85a1085 3880 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 3881 break;
3882 case 2:
e85a1085 3883 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 3884 break;
3885 case 4:
e85a1085 3886 op->val = insn_fetch(s32, ctxt);
39f21ee5
AK		 3887 break;
3888 }
3889 if (!sign_extension) {
3890 switch (op->bytes) {
3891 case 1:
3892 op->val &= 0xff;
3893 break;
3894 case 2:
3895 op->val &= 0xffff;
3896 break;
3897 case 4:
3898 op->val &= 0xffffffff;
3899 break;
3900 }
3901 }
3902done:
3903 return rc;
3904}
3905
a9945549
AK		 3906static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
3907 unsigned d)
3908{
3909 int rc = X86EMUL_CONTINUE;
3910
3911 switch (d) {
3912 case OpReg:
2adb5ad9 3913 decode_register_operand(ctxt, op);
a9945549
AK		 3914 break;
3915 case OpImmUByte:
608aabe3 3916 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 3917 break;
3918 case OpMem:
41ddf978 3919 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 3920 mem_common:
3921 *op = ctxt->memop;
3922 ctxt->memopp = op;
3923 if ((ctxt->d & BitOp) && op == &ctxt->dst)
a9945549
AK		 3924 fetch_bit_operand(ctxt);
3925 op->orig_val = op->val;
3926 break;
41ddf978
AK		 3927 case OpMem64:
3928 ctxt->memop.bytes = 8;
3929 goto mem_common;
a9945549
AK		 3930 case OpAcc:
3931 op->type = OP_REG;
3932 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3933 op->addr.reg = &ctxt->regs[VCPU_REGS_RAX];
3934 fetch_register_operand(op);
3935 op->orig_val = op->val;
3936 break;
3937 case OpDI:
3938 op->type = OP_MEM;
3939 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3940 op->addr.mem.ea =
3941 register_address(ctxt, ctxt->regs[VCPU_REGS_RDI]);
3942 op->addr.mem.seg = VCPU_SREG_ES;
3943 op->val = 0;
3944 break;
3945 case OpDX:
3946 op->type = OP_REG;
3947 op->bytes = 2;
3948 op->addr.reg = &ctxt->regs[VCPU_REGS_RDX];
3949 fetch_register_operand(op);
3950 break;
4dd6a57d
AK		 3951 case OpCL:
3952 op->bytes = 1;
3953 op->val = ctxt->regs[VCPU_REGS_RCX] & 0xff;
3954 break;
3955 case OpImmByte:
3956 rc = decode_imm(ctxt, op, 1, true);
3957 break;
3958 case OpOne:
3959 op->bytes = 1;
3960 op->val = 1;
3961 break;
3962 case OpImm:
3963 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
3964 break;
28867cee
AK		 3965 case OpMem8:
3966 ctxt->memop.bytes = 1;
3967 goto mem_common;
0fe59128
AK		 3968 case OpMem16:
3969 ctxt->memop.bytes = 2;
3970 goto mem_common;
3971 case OpMem32:
3972 ctxt->memop.bytes = 4;
3973 goto mem_common;
3974 case OpImmU16:
3975 rc = decode_imm(ctxt, op, 2, false);
3976 break;
3977 case OpImmU:
3978 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
3979 break;
3980 case OpSI:
3981 op->type = OP_MEM;
3982 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3983 op->addr.mem.ea =
3984 register_address(ctxt, ctxt->regs[VCPU_REGS_RSI]);
3985 op->addr.mem.seg = seg_override(ctxt);
3986 op->val = 0;
3987 break;
3988 case OpImmFAddr:
3989 op->type = OP_IMM;
3990 op->addr.mem.ea = ctxt->_eip;
3991 op->bytes = ctxt->op_bytes + 2;
3992 insn_fetch_arr(op->valptr, op->bytes, ctxt);
3993 break;
3994 case OpMemFAddr:
3995 ctxt->memop.bytes = ctxt->op_bytes + 2;
3996 goto mem_common;
c191a7a0
AK		 3997 case OpES:
3998 op->val = VCPU_SREG_ES;
3999 break;
4000 case OpCS:
4001 op->val = VCPU_SREG_CS;
4002 break;
4003 case OpSS:
4004 op->val = VCPU_SREG_SS;
4005 break;
4006 case OpDS:
4007 op->val = VCPU_SREG_DS;
4008 break;
4009 case OpFS:
4010 op->val = VCPU_SREG_FS;
4011 break;
4012 case OpGS:
4013 op->val = VCPU_SREG_GS;
4014 break;
a9945549
AK		 4015 case OpImplicit:
4016 /* Special instructions do their own operand decoding. */
4017 default:
4018 op->type = OP_NONE; /* Disable writeback. */
4019 break;
4020 }
4021
4022done:
4023 return rc;
4024}
4025
ef5d75cc 4026int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 4027{
dde7e6d1
AK		 4028 int rc = X86EMUL_CONTINUE;
4029 int mode = ctxt->mode;
46561646 4030 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 4031 bool op_prefix = false;
46561646 4032 struct opcode opcode;
dde7e6d1 4033
f09ed83e
AK		 4034 ctxt->memop.type = OP_NONE;
4035 ctxt->memopp = NULL;
9dac77fa
AK		 4036 ctxt->_eip = ctxt->eip;
4037 ctxt->fetch.start = ctxt->_eip;
4038 ctxt->fetch.end = ctxt->fetch.start + insn_len;
dc25e89e 4039 if (insn_len > 0)
9dac77fa 4040 memcpy(ctxt->fetch.data, insn, insn_len);
dde7e6d1
AK		 4041
4042 switch (mode) {
4043 case X86EMUL_MODE_REAL:
4044 case X86EMUL_MODE_VM86:
4045 case X86EMUL_MODE_PROT16:
4046 def_op_bytes = def_ad_bytes = 2;
4047 break;
4048 case X86EMUL_MODE_PROT32:
4049 def_op_bytes = def_ad_bytes = 4;
4050 break;
4051#ifdef CONFIG_X86_64
4052 case X86EMUL_MODE_PROT64:
4053 def_op_bytes = 4;
4054 def_ad_bytes = 8;
4055 break;
4056#endif
4057 default:
1d2887e2 4058 return EMULATION_FAILED;
dde7e6d1
AK		 4059 }
4060
9dac77fa
AK		 4061 ctxt->op_bytes = def_op_bytes;
4062 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 4063
4064 /* Legacy prefixes. */
4065 for (;;) {
e85a1085 4066 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 4067 case 0x66: /* operand-size override */
0d7cdee8 4068 op_prefix = true;
dde7e6d1 4069 /* switch between 2/4 bytes */
9dac77fa 4070 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 4071 break;
4072 case 0x67: /* address-size override */
4073 if (mode == X86EMUL_MODE_PROT64)
4074 /* switch between 4/8 bytes */
9dac77fa 4075 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 4076 else
4077 /* switch between 2/4 bytes */
9dac77fa 4078 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 4079 break;
4080 case 0x26: /* ES override */
4081 case 0x2e: /* CS override */
4082 case 0x36: /* SS override */
4083 case 0x3e: /* DS override */
9dac77fa 4084 set_seg_override(ctxt, (ctxt->b >> 3) & 3);
dde7e6d1
AK		 4085 break;
4086 case 0x64: /* FS override */
4087 case 0x65: /* GS override */
9dac77fa 4088 set_seg_override(ctxt, ctxt->b & 7);
dde7e6d1
AK		 4089 break;
4090 case 0x40 ... 0x4f: /* REX */
4091 if (mode != X86EMUL_MODE_PROT64)
4092 goto done_prefixes;
9dac77fa 4093 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 4094 continue;
4095 case 0xf0: /* LOCK */
9dac77fa 4096 ctxt->lock_prefix = 1;
dde7e6d1
AK		 4097 break;
4098 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 4099 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 4100 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 4101 break;
4102 default:
4103 goto done_prefixes;
4104 }
4105
4106 /* Any legacy prefix after a REX prefix nullifies its effect. */
4107
9dac77fa 4108 ctxt->rex_prefix = 0;
dde7e6d1
AK		 4109 }
4110
4111done_prefixes:
4112
4113 /* REX prefix. */
9dac77fa
AK		 4114 if (ctxt->rex_prefix & 8)
4115 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 4116
4117 /* Opcode byte(s). */
9dac77fa 4118 opcode = opcode_table[ctxt->b];
d3ad6243 4119 /* Two-byte opcode? */
9dac77fa
AK		 4120 if (ctxt->b == 0x0f) {
4121 ctxt->twobyte = 1;
e85a1085 4122 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 4123 opcode = twobyte_table[ctxt->b];
dde7e6d1 4124 }
9dac77fa 4125 ctxt->d = opcode.flags;
dde7e6d1 4126
9f4260e7
TY		 4127 if (ctxt->d & ModRM)
4128 ctxt->modrm = insn_fetch(u8, ctxt);
4129
9dac77fa
AK		 4130 while (ctxt->d & GroupMask) {
4131 switch (ctxt->d & GroupMask) {
46561646 4132 case Group:
9dac77fa 4133 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 4134 opcode = opcode.u.group[goffset];
4135 break;
4136 case GroupDual:
9dac77fa
AK		 4137 goffset = (ctxt->modrm >> 3) & 7;
4138 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 4139 opcode = opcode.u.gdual->mod3[goffset];
4140 else
4141 opcode = opcode.u.gdual->mod012[goffset];
4142 break;
4143 case RMExt:
9dac77fa 4144 goffset = ctxt->modrm & 7;
01de8b09 4145 opcode = opcode.u.group[goffset];
46561646
AK		 4146 break;
4147 case Prefix:
9dac77fa 4148 if (ctxt->rep_prefix && op_prefix)
1d2887e2 4149 return EMULATION_FAILED;
9dac77fa 4150 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 4151 switch (simd_prefix) {
4152 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4153 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4154 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4155 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4156 }
4157 break;
4158 default:
1d2887e2 4159 return EMULATION_FAILED;
0d7cdee8 4160 }
46561646 4161
b1ea50b2 4162 ctxt->d &= ~(u64)GroupMask;
9dac77fa 4163 ctxt->d |= opcode.flags;
0d7cdee8
AK		 4164 }
4165
9dac77fa
AK		 4166 ctxt->execute = opcode.u.execute;
4167 ctxt->check_perm = opcode.check_perm;
4168 ctxt->intercept = opcode.intercept;
dde7e6d1
AK		 4169
4170 /* Unrecognised? */
9dac77fa 4171 if (ctxt->d == 0 || (ctxt->d & Undefined))
1d2887e2 4172 return EMULATION_FAILED;
dde7e6d1 4173
9dac77fa 4174 if (!(ctxt->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
1d2887e2 4175 return EMULATION_FAILED;
d867162c 4176
9dac77fa
AK		 4177 if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
4178 ctxt->op_bytes = 8;
dde7e6d1 4179
9dac77fa 4180 if (ctxt->d & Op3264) {
7f9b4b75 4181 if (mode == X86EMUL_MODE_PROT64)
9dac77fa 4182 ctxt->op_bytes = 8;
7f9b4b75 4183 else
9dac77fa 4184 ctxt->op_bytes = 4;
7f9b4b75
AK		 4185 }
4186
9dac77fa
AK		 4187 if (ctxt->d & Sse)
4188 ctxt->op_bytes = 16;
cbe2c9d3
AK		 4189 else if (ctxt->d & Mmx)
4190 ctxt->op_bytes = 8;
1253791d 4191
dde7e6d1 4192 /* ModRM and SIB bytes. */
9dac77fa 4193 if (ctxt->d & ModRM) {
f09ed83e 4194 rc = decode_modrm(ctxt, &ctxt->memop);
9dac77fa
AK		 4195 if (!ctxt->has_seg_override)
4196 set_seg_override(ctxt, ctxt->modrm_seg);
4197 } else if (ctxt->d & MemAbs)
f09ed83e 4198 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 4199 if (rc != X86EMUL_CONTINUE)
4200 goto done;
4201
9dac77fa
AK		 4202 if (!ctxt->has_seg_override)
4203 set_seg_override(ctxt, VCPU_SREG_DS);
dde7e6d1 4204
f09ed83e 4205 ctxt->memop.addr.mem.seg = seg_override(ctxt);
dde7e6d1 4206
f09ed83e
AK		 4207 if (ctxt->memop.type == OP_MEM && ctxt->ad_bytes != 8)
4208 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
dde7e6d1 4209
dde7e6d1
AK		 4210 /*
4211 * Decode and fetch the source operand: register, memory
4212 * or immediate.
4213 */
0fe59128 4214 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 4215 if (rc != X86EMUL_CONTINUE)
4216 goto done;
4217
dde7e6d1
AK		 4218 /*
4219 * Decode and fetch the second source operand: register, memory
4220 * or immediate.
4221 */
4dd6a57d 4222 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 4223 if (rc != X86EMUL_CONTINUE)
4224 goto done;
4225
dde7e6d1 4226 /* Decode and fetch the destination operand: register or memory. */
a9945549 4227 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1
AK		 4228
4229done:
f09ed83e
AK		 4230 if (ctxt->memopp && ctxt->memopp->type == OP_MEM && ctxt->rip_relative)
4231 ctxt->memopp->addr.mem.ea += ctxt->_eip;
cb16c348 4232
1d2887e2 4233 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 4234}
4235
1cb3f3ae
XG		 4236bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4237{
4238 return ctxt->d & PageTable;
4239}
4240
3e2f65d5
GN		 4241static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4242{
3e2f65d5
GN		 4243 /* The second termination condition only applies for REPE
4244 * and REPNE. Test if the repeat string operation prefix is
4245 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4246 * corresponding termination condition according to:
4247 * - if REPE/REPZ and ZF = 0 then done
4248 * - if REPNE/REPNZ and ZF = 1 then done
4249 */
9dac77fa
AK		 4250 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4251 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4252 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 4253 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 4254 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 4255 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
4256 return true;
4257
4258 return false;
4259}
4260
cbe2c9d3
AK		 4261static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4262{
4263 bool fault = false;
4264
4265 ctxt->ops->get_fpu(ctxt);
4266 asm volatile("1: fwait \n\t"
4267 "2: \n\t"
4268 ".pushsection .fixup,\"ax\" \n\t"
4269 "3: \n\t"
4270 "movb $1, %[fault] \n\t"
4271 "jmp 2b \n\t"
4272 ".popsection \n\t"
4273 _ASM_EXTABLE(1b, 3b)
38e8a2dd 4274 : [fault]"+qm"(fault));
cbe2c9d3
AK		 4275 ctxt->ops->put_fpu(ctxt);
4276
4277 if (unlikely(fault))
4278 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4279
4280 return X86EMUL_CONTINUE;
4281}
4282
4283static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4284 struct operand *op)
4285{
4286 if (op->type == OP_MM)
4287 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4288}
4289
7b105ca2 4290int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 4291{
9aabc88f 4292 struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 4293 int rc = X86EMUL_CONTINUE;
9dac77fa 4294 int saved_dst_type = ctxt->dst.type;
8b4caf66 4295
9dac77fa 4296 ctxt->mem_read.pos = 0;
310b5d30 4297
9dac77fa 4298 if (ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) {
35d3d4a1 4299 rc = emulate_ud(ctxt);
1161624f
GN		 4300 goto done;
4301 }
4302
d380a5e4 4303 /* LOCK prefix is allowed only with some instructions */
9dac77fa 4304 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 4305 rc = emulate_ud(ctxt);
d380a5e4
GN		 4306 goto done;
4307 }
4308
9dac77fa 4309 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 4310 rc = emulate_ud(ctxt);
081bca0e
AK		 4311 goto done;
4312 }
4313
cbe2c9d3
AK		 4314 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4315 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
1253791d
AK		 4316 rc = emulate_ud(ctxt);
4317 goto done;
4318 }
4319
cbe2c9d3 4320 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
1253791d
AK		 4321 rc = emulate_nm(ctxt);
4322 goto done;
4323 }
4324
cbe2c9d3
AK		 4325 if (ctxt->d & Mmx) {
4326 rc = flush_pending_x87_faults(ctxt);
4327 if (rc != X86EMUL_CONTINUE)
4328 goto done;
4329 /*
4330 * Now that we know the fpu is exception safe, we can fetch
4331 * operands from it.
4332 */
4333 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4334 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4335 if (!(ctxt->d & Mov))
4336 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4337 }
4338
9dac77fa
AK		 4339 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4340 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4341 X86_ICPT_PRE_EXCEPT);
c4f035c6
AK		 4342 if (rc != X86EMUL_CONTINUE)
4343 goto done;
4344 }
4345
e92805ac 4346 /* Privileged instruction can be executed only in CPL=0 */
9dac77fa 4347 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
35d3d4a1 4348 rc = emulate_gp(ctxt, 0);
e92805ac
GN		 4349 goto done;
4350 }
4351
8ea7d6ae 4352 /* Instruction can only be executed in protected mode */
9dac77fa 4353 if ((ctxt->d & Prot) && !(ctxt->mode & X86EMUL_MODE_PROT)) {
8ea7d6ae
JR		 4354 rc = emulate_ud(ctxt);
4355 goto done;
4356 }
4357
d09beabd 4358 /* Do instruction specific permission checks */
9dac77fa
AK		 4359 if (ctxt->check_perm) {
4360 rc = ctxt->check_perm(ctxt);
d09beabd
JR		 4361 if (rc != X86EMUL_CONTINUE)
4362 goto done;
4363 }
4364
9dac77fa
AK		 4365 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4366 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4367 X86_ICPT_POST_EXCEPT);
c4f035c6
AK		 4368 if (rc != X86EMUL_CONTINUE)
4369 goto done;
4370 }
4371
9dac77fa 4372 if (ctxt->rep_prefix && (ctxt->d & String)) {
b9fa9d6b 4373 /* All REP prefixes have the same first termination condition */
9dac77fa
AK		 4374 if (address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) == 0) {
4375 ctxt->eip = ctxt->_eip;
b9fa9d6b
AK		 4376 goto done;
4377 }
b9fa9d6b
AK		 4378 }
4379
9dac77fa
AK		 4380 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4381 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4382 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 4383 if (rc != X86EMUL_CONTINUE)
8b4caf66 4384 goto done;
9dac77fa 4385 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 4386 }
4387
9dac77fa
AK		 4388 if (ctxt->src2.type == OP_MEM) {
4389 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4390 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 4391 if (rc != X86EMUL_CONTINUE)
4392 goto done;
4393 }
4394
9dac77fa 4395 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 4396 goto special_insn;
4397
4398
9dac77fa 4399 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 4400 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 4401 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4402 &ctxt->dst.val, ctxt->dst.bytes);
69f55cb1
GN		 4403 if (rc != X86EMUL_CONTINUE)
4404 goto done;
038e51de 4405 }
9dac77fa 4406 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 4407
018a98db
AK		 4408special_insn:
4409
9dac77fa
AK		 4410 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4411 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4412 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 4413 if (rc != X86EMUL_CONTINUE)
4414 goto done;
4415 }
4416
9dac77fa
AK		 4417 if (ctxt->execute) {
4418 rc = ctxt->execute(ctxt);
ef65c889
AK		 4419 if (rc != X86EMUL_CONTINUE)
4420 goto done;
4421 goto writeback;
4422 }
4423
9dac77fa 4424 if (ctxt->twobyte)
6aa8b732
AK		 4425 goto twobyte_insn;
4426
9dac77fa 4427 switch (ctxt->b) {
33615aa9 4428 case 0x40 ... 0x47: /* inc r16/r32 */
d1eef45d 4429 emulate_1op(ctxt, "inc");
33615aa9
AK		 4430 break;
4431 case 0x48 ... 0x4f: /* dec r16/r32 */
d1eef45d 4432 emulate_1op(ctxt, "dec");
33615aa9 4433 break;
6aa8b732 4434 case 0x63: /* movsxd */
8b4caf66 4435 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 4436 goto cannot_emulate;
9dac77fa 4437 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 4438 break;
b2833e3c 4439 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa
AK		 4440 if (test_cc(ctxt->b, ctxt->eflags))
4441 jmp_rel(ctxt, ctxt->src.val);
018a98db 4442 break;
7e0b54b1 4443 case 0x8d: /* lea r16/r32, m */
9dac77fa 4444 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 4445 break;
3d9e77df 4446 case 0x90 ... 0x97: /* nop / xchg reg, rax */
9dac77fa 4447 if (ctxt->dst.addr.reg == &ctxt->regs[VCPU_REGS_RAX])
34698d8c 4448 break;
e4f973ae
TY		 4449 rc = em_xchg(ctxt);
4450 break;
e8b6fa70 4451 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 4452 switch (ctxt->op_bytes) {
4453 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
4454 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
4455 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 4456 }
4457 break;
018a98db 4458 case 0xc0 ... 0xc1:
51187683 4459 rc = em_grp2(ctxt);
018a98db 4460 break;
6e154e56 4461 case 0xcc: /* int3 */
5c5df76b
TY		 4462 rc = emulate_int(ctxt, 3);
4463 break;
6e154e56 4464 case 0xcd: /* int n */
9dac77fa 4465 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 4466 break;
4467 case 0xce: /* into */
5c5df76b
TY		 4468 if (ctxt->eflags & EFLG_OF)
4469 rc = emulate_int(ctxt, 4);
6e154e56 4470 break;
018a98db 4471 case 0xd0 ... 0xd1: /* Grp2 */
51187683 4472 rc = em_grp2(ctxt);
018a98db
AK		 4473 break;
4474 case 0xd2 ... 0xd3: /* Grp2 */
9dac77fa 4475 ctxt->src.val = ctxt->regs[VCPU_REGS_RCX];
51187683 4476 rc = em_grp2(ctxt);
018a98db 4477 break;
1a52e051 4478 case 0xe9: /* jmp rel */
db5b0762 4479 case 0xeb: /* jmp rel short */
9dac77fa
AK		 4480 jmp_rel(ctxt, ctxt->src.val);
4481 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4482 break;
111de5d6 4483 case 0xf4: /* hlt */
6c3287f7 4484 ctxt->ops->halt(ctxt);
19fdfa0d 4485 break;
111de5d6
AK		 4486 case 0xf5: /* cmc */
4487 /* complement carry flag from eflags reg */
4488 ctxt->eflags ^= EFLG_CF;
111de5d6
AK		 4489 break;
4490 case 0xf8: /* clc */
4491 ctxt->eflags &= ~EFLG_CF;
111de5d6 4492 break;
8744aa9a
MG		 4493 case 0xf9: /* stc */
4494 ctxt->eflags |= EFLG_CF;
4495 break;
fb4616f4
MG		 4496 case 0xfc: /* cld */
4497 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 4498 break;
4499 case 0xfd: /* std */
4500 ctxt->eflags |= EFLG_DF;
fb4616f4 4501 break;
91269b8f
AK		 4502 default:
4503 goto cannot_emulate;
6aa8b732 4504 }
018a98db 4505
7d9ddaed
AK		 4506 if (rc != X86EMUL_CONTINUE)
4507 goto done;
4508
018a98db 4509writeback:
adddcecf 4510 rc = writeback(ctxt);
1b30eaa8 4511 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 4512 goto done;
4513
5cd21917
GN		 4514 /*
4515 * restore dst type in case the decoding will be reused
4516 * (happens for string instruction )
4517 */
9dac77fa 4518 ctxt->dst.type = saved_dst_type;
5cd21917 4519
9dac77fa
AK		 4520 if ((ctxt->d & SrcMask) == SrcSI)
4521 string_addr_inc(ctxt, seg_override(ctxt),
4522 VCPU_REGS_RSI, &ctxt->src);
a682e354 4523
9dac77fa 4524 if ((ctxt->d & DstMask) == DstDI)
90de84f5 4525 string_addr_inc(ctxt, VCPU_SREG_ES, VCPU_REGS_RDI,
9dac77fa 4526 &ctxt->dst);
d9271123 4527
9dac77fa
AK		 4528 if (ctxt->rep_prefix && (ctxt->d & String)) {
4529 struct read_cache *r = &ctxt->io_read;
4530 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RCX], -1);
3e2f65d5 4531
d2ddd1c4
GN		 4532 if (!string_insn_completed(ctxt)) {
4533 /*
4534 * Re-enter guest when pio read ahead buffer is empty
4535 * or, if it is not used, after each 1024 iteration.
4536 */
9dac77fa 4537 if ((r->end != 0 || ctxt->regs[VCPU_REGS_RCX] & 0x3ff) &&
d2ddd1c4
GN		 4538 (r->end == 0 || r->end != r->pos)) {
4539 /*
4540 * Reset read cache. Usually happens before
4541 * decode, but since instruction is restarted
4542 * we have to do it here.
4543 */
9dac77fa 4544 ctxt->mem_read.end = 0;
d2ddd1c4
GN		 4545 return EMULATION_RESTART;
4546 }
4547 goto done; /* skip rip writeback */
0fa6ccbd 4548 }
5cd21917 4549 }
d2ddd1c4 4550
9dac77fa 4551 ctxt->eip = ctxt->_eip;
018a98db
AK		 4552
4553done:
da9cb575
AK		 4554 if (rc == X86EMUL_PROPAGATE_FAULT)
4555 ctxt->have_exception = true;
775fde86
JR		 4556 if (rc == X86EMUL_INTERCEPTED)
4557 return EMULATION_INTERCEPTED;
4558
d2ddd1c4 4559 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 4560
4561twobyte_insn:
9dac77fa 4562 switch (ctxt->b) {
018a98db 4563 case 0x09: /* wbinvd */
cfb22375 4564 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 4565 break;
4566 case 0x08: /* invd */
018a98db
AK		 4567 case 0x0d: /* GrpP (prefetch) */
4568 case 0x18: /* Grp16 (prefetch/nop) */
018a98db
AK		 4569 break;
4570 case 0x20: /* mov cr, reg */
9dac77fa 4571 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 4572 break;
6aa8b732 4573 case 0x21: /* mov from dr to reg */
9dac77fa 4574 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 4575 break;
6aa8b732 4576 case 0x40 ... 0x4f: /* cmov */
9dac77fa
AK		 4577 ctxt->dst.val = ctxt->dst.orig_val = ctxt->src.val;
4578 if (!test_cc(ctxt->b, ctxt->eflags))
4579 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 4580 break;
b2833e3c 4581 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa
AK		 4582 if (test_cc(ctxt->b, ctxt->eflags))
4583 jmp_rel(ctxt, ctxt->src.val);
018a98db 4584 break;
ee45b58e 4585 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 4586 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 4587 break;
9bf8ea42
GT		 4588 case 0xa4: /* shld imm8, r, r/m */
4589 case 0xa5: /* shld cl, r, r/m */
761441b9 4590 emulate_2op_cl(ctxt, "shld");
9bf8ea42 4591 break;
9bf8ea42
GT		 4592 case 0xac: /* shrd imm8, r, r/m */
4593 case 0xad: /* shrd cl, r, r/m */
761441b9 4594 emulate_2op_cl(ctxt, "shrd");
9bf8ea42 4595 break;
2a7c5b8b
GC		 4596 case 0xae: /* clflush */
4597 break;
6aa8b732 4598 case 0xb6 ... 0xb7: /* movzx */
9dac77fa 4599 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4600 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
9dac77fa 4601 : (u16) ctxt->src.val;
6aa8b732 4602 break;
6aa8b732 4603 case 0xbe ... 0xbf: /* movsx */
9dac77fa 4604 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4605 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
9dac77fa 4606 (s16) ctxt->src.val;
6aa8b732 4607 break;
92f738a5 4608 case 0xc0 ... 0xc1: /* xadd */
a31b9cea 4609 emulate_2op_SrcV(ctxt, "add");
92f738a5 4610 /* Write back the register source. */
9dac77fa
AK		 4611 ctxt->src.val = ctxt->dst.orig_val;
4612 write_register_operand(&ctxt->src);
92f738a5 4613 break;
a012e65a 4614 case 0xc3: /* movnti */
9dac77fa
AK		 4615 ctxt->dst.bytes = ctxt->op_bytes;
4616 ctxt->dst.val = (ctxt->op_bytes == 4) ? (u32) ctxt->src.val :
4617 (u64) ctxt->src.val;
a012e65a 4618 break;
91269b8f
AK		 4619 default:
4620 goto cannot_emulate;
6aa8b732 4621 }
7d9ddaed
AK		 4622
4623 if (rc != X86EMUL_CONTINUE)
4624 goto done;
4625
6aa8b732
AK		 4626 goto writeback;
4627
4628cannot_emulate:
a0c0ab2f 4629 return EMULATION_FAILED;
6aa8b732 4630}
Linux 6.x block layer and io_uring tree(s)