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KVM: emulator: Fix io permission checking for 64bit guest
[linux-block.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
6aa8b732 27
3eeb3288 28#include "x86.h"
38ba30ba 29#include "tss.h"
e99f0507 30
6aa8b732
AK		 31/*
32 * Opcode effective-address decode tables.
33 * Note that we only emulate instructions that have at least one memory
34 * operand (excluding implicit stack references). We assume that stack
35 * references and instruction fetches will never occur in special memory
36 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
37 * not be handled.
38 */
39
40/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 41#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 42/* Destination operand type. */
ab85b12b
AK		 43#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
44#define DstReg (2<<1) /* Register operand. */
45#define DstMem (3<<1) /* Memory operand. */
46#define DstAcc (4<<1) /* Destination Accumulator */
47#define DstDI (5<<1) /* Destination is in ES:(E)DI */
48#define DstMem64 (6<<1) /* 64bit memory operand */
943858e2 49#define DstImmUByte (7<<1) /* 8-bit unsigned immediate operand */
ab85b12b 50#define DstMask (7<<1)
6aa8b732 51/* Source operand type. */
9c9fddd0 52#define SrcNone (0<<4) /* No source operand. */
9c9fddd0
GT		 53#define SrcReg (1<<4) /* Register operand. */
54#define SrcMem (2<<4) /* Memory operand. */
55#define SrcMem16 (3<<4) /* Memory operand (16-bit). */
56#define SrcMem32 (4<<4) /* Memory operand (32-bit). */
57#define SrcImm (5<<4) /* Immediate operand. */
58#define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
bfcadf83 59#define SrcOne (7<<4) /* Implied '1' */
341de7e3 60#define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
c9eaf20f 61#define SrcImmU (9<<4) /* Immediate operand, unsigned */
a682e354 62#define SrcSI (0xa<<4) /* Source is in the DS:RSI */
414e6277
GN		 63#define SrcImmFAddr (0xb<<4) /* Source is immediate far address */
64#define SrcMemFAddr (0xc<<4) /* Source is far address in memory */
5d55f299 65#define SrcAcc (0xd<<4) /* Source Accumulator */
b250e605 66#define SrcImmU16 (0xe<<4) /* Immediate operand, unsigned, 16 bits */
341de7e3 67#define SrcMask (0xf<<4)
6aa8b732 68/* Generic ModRM decode. */
341de7e3 69#define ModRM (1<<8)
6aa8b732 70/* Destination is only written; never read. */
341de7e3
GN		 71#define Mov (1<<9)
72#define BitOp (1<<10)
73#define MemAbs (1<<11) /* Memory operand is absolute displacement */
9c9fddd0
GT		 74#define String (1<<12) /* String instruction (rep capable) */
75#define Stack (1<<13) /* Stack instruction (push/pop) */
e09d082c
AK		 76#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
77#define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
d8769fed 78/* Misc flags */
d867162c 79#define VendorSpecific (1<<22) /* Vendor specific instruction */
5a506b12 80#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 81#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 82#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 83#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 84#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 85#define No64 (1<<28)
0dc8d10f
GT		 86/* Source 2 operand type */
87#define Src2None (0<<29)
88#define Src2CL (1<<29)
89#define Src2ImmByte (2<<29)
90#define Src2One (3<<29)
7db41eb7 91#define Src2Imm (4<<29)
0dc8d10f 92#define Src2Mask (7<<29)
6aa8b732 93
d0e53325
AK		 94#define X2(x...) x, x
95#define X3(x...) X2(x), x
96#define X4(x...) X2(x), X2(x)
97#define X5(x...) X4(x), x
98#define X6(x...) X4(x), X2(x)
99#define X7(x...) X4(x), X3(x)
100#define X8(x...) X4(x), X4(x)
101#define X16(x...) X8(x), X8(x)
83babbca 102
d65b1dee
AK		 103struct opcode {
104 u32 flags;
120df890 105 union {
ef65c889 106 int (*execute)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 107 struct opcode *group;
108 struct group_dual *gdual;
109 } u;
110};
111
112struct group_dual {
113 struct opcode mod012[8];
114 struct opcode mod3[8];
d65b1dee
AK		 115};
116
6aa8b732 117/* EFLAGS bit definitions. */
d4c6a154
GN		 118#define EFLG_ID (1<<21)
119#define EFLG_VIP (1<<20)
120#define EFLG_VIF (1<<19)
121#define EFLG_AC (1<<18)
b1d86143
AP		 122#define EFLG_VM (1<<17)
123#define EFLG_RF (1<<16)
d4c6a154
GN		 124#define EFLG_IOPL (3<<12)
125#define EFLG_NT (1<<14)
6aa8b732
AK		 126#define EFLG_OF (1<<11)
127#define EFLG_DF (1<<10)
b1d86143 128#define EFLG_IF (1<<9)
d4c6a154 129#define EFLG_TF (1<<8)
6aa8b732
AK		 130#define EFLG_SF (1<<7)
131#define EFLG_ZF (1<<6)
132#define EFLG_AF (1<<4)
133#define EFLG_PF (1<<2)
134#define EFLG_CF (1<<0)
135
62bd430e
MG		 136#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
137#define EFLG_RESERVED_ONE_MASK 2
138
6aa8b732
AK		 139/*
140 * Instruction emulation:
141 * Most instructions are emulated directly via a fragment of inline assembly
142 * code. This allows us to save/restore EFLAGS and thus very easily pick up
143 * any modified flags.
144 */
145
05b3e0c2 146#if defined(CONFIG_X86_64)
6aa8b732
AK		 147#define _LO32 "k" /* force 32-bit operand */
148#define _STK "%%rsp" /* stack pointer */
149#elif defined(__i386__)
150#define _LO32 "" /* force 32-bit operand */
151#define _STK "%%esp" /* stack pointer */
152#endif
153
154/*
155 * These EFLAGS bits are restored from saved value during emulation, and
156 * any changes are written back to the saved value after emulation.
157 */
158#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
159
160/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 161#define _PRE_EFLAGS(_sav, _msk, _tmp) \
162 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
163 "movl %"_sav",%"_LO32 _tmp"; " \
164 "push %"_tmp"; " \
165 "push %"_tmp"; " \
166 "movl %"_msk",%"_LO32 _tmp"; " \
167 "andl %"_LO32 _tmp",("_STK"); " \
168 "pushf; " \
169 "notl %"_LO32 _tmp"; " \
170 "andl %"_LO32 _tmp",("_STK"); " \
171 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
172 "pop %"_tmp"; " \
173 "orl %"_LO32 _tmp",("_STK"); " \
174 "popf; " \
175 "pop %"_sav"; "
6aa8b732
AK		 176
177/* After executing instruction: write-back necessary bits in EFLAGS. */
178#define _POST_EFLAGS(_sav, _msk, _tmp) \
179 /* _sav |= EFLAGS & _msk; */ \
180 "pushf; " \
181 "pop %"_tmp"; " \
182 "andl %"_msk",%"_LO32 _tmp"; " \
183 "orl %"_LO32 _tmp",%"_sav"; "
184
dda96d8f
AK		 185#ifdef CONFIG_X86_64
186#define ON64(x) x
187#else
188#define ON64(x)
189#endif
190
b3b3d25a 191#define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix, _dsttype) \
6b7ad61f
AK		 192 do { \
193 __asm__ __volatile__ ( \
194 _PRE_EFLAGS("0", "4", "2") \
195 _op _suffix " %"_x"3,%1; " \
196 _POST_EFLAGS("0", "4", "2") \
fb2c2641 197 : "=m" (_eflags), "+q" (*(_dsttype*)&(_dst).val),\
6b7ad61f
AK		 198 "=&r" (_tmp) \
199 : _y ((_src).val), "i" (EFLAGS_MASK)); \
f3fd92fb 200 } while (0)
6b7ad61f
AK		 201
202
6aa8b732
AK		 203/* Raw emulation: instruction has two explicit operands. */
204#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 205 do { \
206 unsigned long _tmp; \
207 \
208 switch ((_dst).bytes) { \
209 case 2: \
b3b3d25a 210 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w",u16);\
6b7ad61f
AK		 211 break; \
212 case 4: \
b3b3d25a 213 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l",u32);\
6b7ad61f
AK		 214 break; \
215 case 8: \
b3b3d25a 216 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q",u64)); \
6b7ad61f
AK		 217 break; \
218 } \
6aa8b732
AK		 219 } while (0)
220
221#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
222 do { \
6b7ad61f 223 unsigned long _tmp; \
d77c26fc 224 switch ((_dst).bytes) { \
6aa8b732 225 case 1: \
b3b3d25a 226 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b",u8); \
6aa8b732
AK		 227 break; \
228 default: \
229 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
230 _wx, _wy, _lx, _ly, _qx, _qy); \
231 break; \
232 } \
233 } while (0)
234
235/* Source operand is byte-sized and may be restricted to just %cl. */
236#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
237 __emulate_2op(_op, _src, _dst, _eflags, \
238 "b", "c", "b", "c", "b", "c", "b", "c")
239
240/* Source operand is byte, word, long or quad sized. */
241#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
242 __emulate_2op(_op, _src, _dst, _eflags, \
243 "b", "q", "w", "r", _LO32, "r", "", "r")
244
245/* Source operand is word, long or quad sized. */
246#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
247 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
248 "w", "r", _LO32, "r", "", "r")
249
d175226a
GT		 250/* Instruction has three operands and one operand is stored in ECX register */
251#define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
252 do { \
253 unsigned long _tmp; \
254 _type _clv = (_cl).val; \
255 _type _srcv = (_src).val; \
256 _type _dstv = (_dst).val; \
257 \
258 __asm__ __volatile__ ( \
259 _PRE_EFLAGS("0", "5", "2") \
260 _op _suffix " %4,%1 \n" \
261 _POST_EFLAGS("0", "5", "2") \
262 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
263 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
264 ); \
265 \
266 (_cl).val = (unsigned long) _clv; \
267 (_src).val = (unsigned long) _srcv; \
268 (_dst).val = (unsigned long) _dstv; \
269 } while (0)
270
271#define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
272 do { \
273 switch ((_dst).bytes) { \
274 case 2: \
275 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
276 "w", unsigned short); \
277 break; \
278 case 4: \
279 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
280 "l", unsigned int); \
281 break; \
282 case 8: \
283 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
284 "q", unsigned long)); \
285 break; \
286 } \
287 } while (0)
288
dda96d8f 289#define __emulate_1op(_op, _dst, _eflags, _suffix) \
6aa8b732
AK		 290 do { \
291 unsigned long _tmp; \
292 \
dda96d8f
AK		 293 __asm__ __volatile__ ( \
294 _PRE_EFLAGS("0", "3", "2") \
295 _op _suffix " %1; " \
296 _POST_EFLAGS("0", "3", "2") \
297 : "=m" (_eflags), "+m" ((_dst).val), \
298 "=&r" (_tmp) \
299 : "i" (EFLAGS_MASK)); \
300 } while (0)
301
302/* Instruction has only one explicit operand (no source operand). */
303#define emulate_1op(_op, _dst, _eflags) \
304 do { \
d77c26fc 305 switch ((_dst).bytes) { \
dda96d8f
AK		 306 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
307 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
308 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
309 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
6aa8b732
AK		 310 } \
311 } while (0)
312
3f9f53b0
MG		 313#define __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, _suffix) \
314 do { \
315 unsigned long _tmp; \
316 \
317 __asm__ __volatile__ ( \
318 _PRE_EFLAGS("0", "4", "1") \
319 _op _suffix " %5; " \
320 _POST_EFLAGS("0", "4", "1") \
321 : "=m" (_eflags), "=&r" (_tmp), \
322 "+a" (_rax), "+d" (_rdx) \
323 : "i" (EFLAGS_MASK), "m" ((_src).val), \
324 "a" (_rax), "d" (_rdx)); \
325 } while (0)
326
f6b3597b
AK		 327#define __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _suffix, _ex) \
328 do { \
329 unsigned long _tmp; \
330 \
331 __asm__ __volatile__ ( \
332 _PRE_EFLAGS("0", "5", "1") \
333 "1: \n\t" \
334 _op _suffix " %6; " \
335 "2: \n\t" \
336 _POST_EFLAGS("0", "5", "1") \
337 ".pushsection .fixup,\"ax\" \n\t" \
338 "3: movb $1, %4 \n\t" \
339 "jmp 2b \n\t" \
340 ".popsection \n\t" \
341 _ASM_EXTABLE(1b, 3b) \
342 : "=m" (_eflags), "=&r" (_tmp), \
343 "+a" (_rax), "+d" (_rdx), "+qm"(_ex) \
344 : "i" (EFLAGS_MASK), "m" ((_src).val), \
345 "a" (_rax), "d" (_rdx)); \
346 } while (0)
347
3f9f53b0
MG		 348/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
349#define emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags) \
350 do { \
351 switch((_src).bytes) { \
352 case 1: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "b"); break; \
353 case 2: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "w"); break; \
354 case 4: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "l"); break; \
355 case 8: ON64(__emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "q")); break; \
356 } \
357 } while (0)
358
f6b3597b
AK		 359#define emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _ex) \
360 do { \
361 switch((_src).bytes) { \
362 case 1: \
363 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
364 _eflags, "b", _ex); \
365 break; \
366 case 2: \
367 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
368 _eflags, "w", _ex); \
369 break; \
370 case 4: \
371 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
372 _eflags, "l", _ex); \
373 break; \
374 case 8: ON64( \
375 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
376 _eflags, "q", _ex)); \
377 break; \
378 } \
379 } while (0)
380
6aa8b732
AK		 381/* Fetch next part of the instruction being emulated. */
382#define insn_fetch(_type, _size, _eip) \
383({ unsigned long _x; \
62266869 384 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
af5b4f7f 385 if (rc != X86EMUL_CONTINUE) \
6aa8b732
AK		 386 goto done; \
387 (_eip) += (_size); \
388 (_type)_x; \
389})
390
414e6277
GN		 391#define insn_fetch_arr(_arr, _size, _eip) \
392({ rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size)); \
393 if (rc != X86EMUL_CONTINUE) \
394 goto done; \
395 (_eip) += (_size); \
396})
397
ddcb2885
HH		 398static inline unsigned long ad_mask(struct decode_cache *c)
399{
400 return (1UL << (c->ad_bytes << 3)) - 1;
401}
402
6aa8b732 403/* Access/update address held in a register, based on addressing mode. */
e4706772
HH		 404static inline unsigned long
405address_mask(struct decode_cache *c, unsigned long reg)
406{
407 if (c->ad_bytes == sizeof(unsigned long))
408 return reg;
409 else
410 return reg & ad_mask(c);
411}
412
413static inline unsigned long
90de84f5 414register_address(struct decode_cache *c, unsigned long reg)
e4706772 415{
90de84f5 416 return address_mask(c, reg);
e4706772
HH		 417}
418
7a957275
HH		 419static inline void
420register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
421{
422 if (c->ad_bytes == sizeof(unsigned long))
423 *reg += inc;
424 else
425 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
426}
6aa8b732 427
7a957275
HH		 428static inline void jmp_rel(struct decode_cache *c, int rel)
429{
430 register_address_increment(c, &c->eip, rel);
431}
098c937b 432
7a5b56df
AK		 433static void set_seg_override(struct decode_cache *c, int seg)
434{
435 c->has_seg_override = true;
436 c->seg_override = seg;
437}
438
79168fd1
GN		 439static unsigned long seg_base(struct x86_emulate_ctxt *ctxt,
440 struct x86_emulate_ops *ops, int seg)
7a5b56df
AK		 441{
442 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
443 return 0;
444
79168fd1 445 return ops->get_cached_segment_base(seg, ctxt->vcpu);
7a5b56df
AK		 446}
447
90de84f5
AK		 448static unsigned seg_override(struct x86_emulate_ctxt *ctxt,
449 struct x86_emulate_ops *ops,
450 struct decode_cache *c)
7a5b56df
AK		 451{
452 if (!c->has_seg_override)
453 return 0;
454
90de84f5 455 return c->seg_override;
7a5b56df
AK		 456}
457
90de84f5
AK		 458static ulong linear(struct x86_emulate_ctxt *ctxt,
459 struct segmented_address addr)
7a5b56df 460{
90de84f5
AK		 461 struct decode_cache *c = &ctxt->decode;
462 ulong la;
7a5b56df 463
90de84f5
AK		 464 la = seg_base(ctxt, ctxt->ops, addr.seg) + addr.ea;
465 if (c->ad_bytes != 8)
466 la &= (u32)-1;
467 return la;
7a5b56df
AK		 468}
469
35d3d4a1
AK		 470static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
471 u32 error, bool valid)
54b8486f 472{
da9cb575
AK		 473 ctxt->exception.vector = vec;
474 ctxt->exception.error_code = error;
475 ctxt->exception.error_code_valid = valid;
35d3d4a1 476 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 477}
478
35d3d4a1 479static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 480{
35d3d4a1 481 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 482}
483
35d3d4a1 484static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 485{
35d3d4a1 486 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 487}
488
35d3d4a1 489static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 490{
35d3d4a1 491 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 492}
493
34d1f490
AK		 494static int emulate_de(struct x86_emulate_ctxt *ctxt)
495{
35d3d4a1 496 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 497}
498
62266869
AK		 499static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
500 struct x86_emulate_ops *ops,
2fb53ad8 501 unsigned long eip, u8 *dest)
62266869
AK		 502{
503 struct fetch_cache *fc = &ctxt->decode.fetch;
504 int rc;
2fb53ad8 505 int size, cur_size;
62266869 506
2fb53ad8
AK		 507 if (eip == fc->end) {
508 cur_size = fc->end - fc->start;
509 size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip));
510 rc = ops->fetch(ctxt->cs_base + eip, fc->data + cur_size,
bcc55cba 511 size, ctxt->vcpu, &ctxt->exception);
3e2815e9 512 if (rc != X86EMUL_CONTINUE)
62266869 513 return rc;
2fb53ad8 514 fc->end += size;
62266869 515 }
2fb53ad8 516 *dest = fc->data[eip - fc->start];
3e2815e9 517 return X86EMUL_CONTINUE;
62266869
AK		 518}
519
520static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
521 struct x86_emulate_ops *ops,
522 unsigned long eip, void *dest, unsigned size)
523{
3e2815e9 524 int rc;
62266869 525
eb3c79e6 526 /* x86 instructions are limited to 15 bytes. */
063db061 527 if (eip + size - ctxt->eip > 15)
eb3c79e6 528 return X86EMUL_UNHANDLEABLE;
62266869
AK		 529 while (size--) {
530 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
3e2815e9 531 if (rc != X86EMUL_CONTINUE)
62266869
AK		 532 return rc;
533 }
3e2815e9 534 return X86EMUL_CONTINUE;
62266869
AK		 535}
536
1e3c5cb0
RR		 537/*
538 * Given the 'reg' portion of a ModRM byte, and a register block, return a
539 * pointer into the block that addresses the relevant register.
540 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
541 */
542static void *decode_register(u8 modrm_reg, unsigned long *regs,
543 int highbyte_regs)
6aa8b732
AK		 544{
545 void *p;
546
547 p = &regs[modrm_reg];
548 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
549 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
550 return p;
551}
552
553static int read_descriptor(struct x86_emulate_ctxt *ctxt,
554 struct x86_emulate_ops *ops,
90de84f5 555 struct segmented_address addr,
6aa8b732
AK		 556 u16 *size, unsigned long *address, int op_bytes)
557{
558 int rc;
559
560 if (op_bytes == 2)
561 op_bytes = 3;
562 *address = 0;
90de84f5 563 rc = ops->read_std(linear(ctxt, addr), (unsigned long *)size, 2,
bcc55cba 564 ctxt->vcpu, &ctxt->exception);
1b30eaa8 565 if (rc != X86EMUL_CONTINUE)
6aa8b732 566 return rc;
30b31ab6
AK		 567 addr.ea += 2;
568 rc = ops->read_std(linear(ctxt, addr), address, op_bytes,
bcc55cba 569 ctxt->vcpu, &ctxt->exception);
6aa8b732
AK		 570 return rc;
571}
572
bbe9abbd
NK		 573static int test_cc(unsigned int condition, unsigned int flags)
574{
575 int rc = 0;
576
577 switch ((condition & 15) >> 1) {
578 case 0: /* o */
579 rc |= (flags & EFLG_OF);
580 break;
581 case 1: /* b/c/nae */
582 rc |= (flags & EFLG_CF);
583 break;
584 case 2: /* z/e */
585 rc |= (flags & EFLG_ZF);
586 break;
587 case 3: /* be/na */
588 rc |= (flags & (EFLG_CF|EFLG_ZF));
589 break;
590 case 4: /* s */
591 rc |= (flags & EFLG_SF);
592 break;
593 case 5: /* p/pe */
594 rc |= (flags & EFLG_PF);
595 break;
596 case 7: /* le/ng */
597 rc |= (flags & EFLG_ZF);
598 /* fall through */
599 case 6: /* l/nge */
600 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
601 break;
602 }
603
604 /* Odd condition identifiers (lsb == 1) have inverted sense. */
605 return (!!rc ^ (condition & 1));
606}
607
91ff3cb4
AK		 608static void fetch_register_operand(struct operand *op)
609{
610 switch (op->bytes) {
611 case 1:
612 op->val = *(u8 *)op->addr.reg;
613 break;
614 case 2:
615 op->val = *(u16 *)op->addr.reg;
616 break;
617 case 4:
618 op->val = *(u32 *)op->addr.reg;
619 break;
620 case 8:
621 op->val = *(u64 *)op->addr.reg;
622 break;
623 }
624}
625
3c118e24
AK		 626static void decode_register_operand(struct operand *op,
627 struct decode_cache *c,
3c118e24
AK		 628 int inhibit_bytereg)
629{
33615aa9 630 unsigned reg = c->modrm_reg;
9f1ef3f8 631 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 632
633 if (!(c->d & ModRM))
634 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
3c118e24
AK		 635 op->type = OP_REG;
636 if ((c->d & ByteOp) && !inhibit_bytereg) {
1a6440ae 637 op->addr.reg = decode_register(reg, c->regs, highbyte_regs);
3c118e24
AK		 638 op->bytes = 1;
639 } else {
1a6440ae 640 op->addr.reg = decode_register(reg, c->regs, 0);
3c118e24 641 op->bytes = c->op_bytes;
3c118e24 642 }
91ff3cb4 643 fetch_register_operand(op);
3c118e24
AK		 644 op->orig_val = op->val;
645}
646
1c73ef66 647static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7
AK		 648 struct x86_emulate_ops *ops,
649 struct operand *op)
1c73ef66
AK		 650{
651 struct decode_cache *c = &ctxt->decode;
652 u8 sib;
f5b4edcd 653 int index_reg = 0, base_reg = 0, scale;
3e2815e9 654 int rc = X86EMUL_CONTINUE;
2dbd0dd7 655 ulong modrm_ea = 0;
1c73ef66
AK		 656
657 if (c->rex_prefix) {
658 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
659 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
660 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
661 }
662
663 c->modrm = insn_fetch(u8, 1, c->eip);
664 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
665 c->modrm_reg |= (c->modrm & 0x38) >> 3;
666 c->modrm_rm |= (c->modrm & 0x07);
09ee57cd 667 c->modrm_seg = VCPU_SREG_DS;
1c73ef66
AK		 668
669 if (c->modrm_mod == 3) {
2dbd0dd7
AK		 670 op->type = OP_REG;
671 op->bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
672 op->addr.reg = decode_register(c->modrm_rm,
107d6d2e 673 c->regs, c->d & ByteOp);
2dbd0dd7 674 fetch_register_operand(op);
1c73ef66
AK		 675 return rc;
676 }
677
2dbd0dd7
AK		 678 op->type = OP_MEM;
679
1c73ef66
AK		 680 if (c->ad_bytes == 2) {
681 unsigned bx = c->regs[VCPU_REGS_RBX];
682 unsigned bp = c->regs[VCPU_REGS_RBP];
683 unsigned si = c->regs[VCPU_REGS_RSI];
684 unsigned di = c->regs[VCPU_REGS_RDI];
685
686 /* 16-bit ModR/M decode. */
687 switch (c->modrm_mod) {
688 case 0:
689 if (c->modrm_rm == 6)
2dbd0dd7 690 modrm_ea += insn_fetch(u16, 2, c->eip);
1c73ef66
AK		 691 break;
692 case 1:
2dbd0dd7 693 modrm_ea += insn_fetch(s8, 1, c->eip);
1c73ef66
AK		 694 break;
695 case 2:
2dbd0dd7 696 modrm_ea += insn_fetch(u16, 2, c->eip);
1c73ef66
AK		 697 break;
698 }
699 switch (c->modrm_rm) {
700 case 0:
2dbd0dd7 701 modrm_ea += bx + si;
1c73ef66
AK		 702 break;
703 case 1:
2dbd0dd7 704 modrm_ea += bx + di;
1c73ef66
AK		 705 break;
706 case 2:
2dbd0dd7 707 modrm_ea += bp + si;
1c73ef66
AK		 708 break;
709 case 3:
2dbd0dd7 710 modrm_ea += bp + di;
1c73ef66
AK		 711 break;
712 case 4:
2dbd0dd7 713 modrm_ea += si;
1c73ef66
AK		 714 break;
715 case 5:
2dbd0dd7 716 modrm_ea += di;
1c73ef66
AK		 717 break;
718 case 6:
719 if (c->modrm_mod != 0)
2dbd0dd7 720 modrm_ea += bp;
1c73ef66
AK		 721 break;
722 case 7:
2dbd0dd7 723 modrm_ea += bx;
1c73ef66
AK		 724 break;
725 }
726 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
727 (c->modrm_rm == 6 && c->modrm_mod != 0))
09ee57cd 728 c->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 729 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 730 } else {
731 /* 32/64-bit ModR/M decode. */
84411d85 732 if ((c->modrm_rm & 7) == 4) {
1c73ef66
AK		 733 sib = insn_fetch(u8, 1, c->eip);
734 index_reg |= (sib >> 3) & 7;
735 base_reg |= sib & 7;
736 scale = sib >> 6;
737
dc71d0f1 738 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
2dbd0dd7 739 modrm_ea += insn_fetch(s32, 4, c->eip);
dc71d0f1 740 else
2dbd0dd7 741 modrm_ea += c->regs[base_reg];
dc71d0f1 742 if (index_reg != 4)
2dbd0dd7 743 modrm_ea += c->regs[index_reg] << scale;
84411d85
AK		 744 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
745 if (ctxt->mode == X86EMUL_MODE_PROT64)
f5b4edcd 746 c->rip_relative = 1;
84411d85 747 } else
2dbd0dd7 748 modrm_ea += c->regs[c->modrm_rm];
1c73ef66
AK		 749 switch (c->modrm_mod) {
750 case 0:
751 if (c->modrm_rm == 5)
2dbd0dd7 752 modrm_ea += insn_fetch(s32, 4, c->eip);
1c73ef66
AK		 753 break;
754 case 1:
2dbd0dd7 755 modrm_ea += insn_fetch(s8, 1, c->eip);
1c73ef66
AK		 756 break;
757 case 2:
2dbd0dd7 758 modrm_ea += insn_fetch(s32, 4, c->eip);
1c73ef66
AK		 759 break;
760 }
761 }
90de84f5 762 op->addr.mem.ea = modrm_ea;
1c73ef66
AK		 763done:
764 return rc;
765}
766
767static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7
AK		 768 struct x86_emulate_ops *ops,
769 struct operand *op)
1c73ef66
AK		 770{
771 struct decode_cache *c = &ctxt->decode;
3e2815e9 772 int rc = X86EMUL_CONTINUE;
1c73ef66 773
2dbd0dd7 774 op->type = OP_MEM;
1c73ef66
AK		 775 switch (c->ad_bytes) {
776 case 2:
90de84f5 777 op->addr.mem.ea = insn_fetch(u16, 2, c->eip);
1c73ef66
AK		 778 break;
779 case 4:
90de84f5 780 op->addr.mem.ea = insn_fetch(u32, 4, c->eip);
1c73ef66
AK		 781 break;
782 case 8:
90de84f5 783 op->addr.mem.ea = insn_fetch(u64, 8, c->eip);
1c73ef66
AK		 784 break;
785 }
786done:
787 return rc;
788}
789
35c843c4
WY		 790static void fetch_bit_operand(struct decode_cache *c)
791{
7129eeca 792 long sv = 0, mask;
35c843c4 793
3885f18f 794 if (c->dst.type == OP_MEM && c->src.type == OP_REG) {
35c843c4
WY		 795 mask = ~(c->dst.bytes * 8 - 1);
796
797 if (c->src.bytes == 2)
798 sv = (s16)c->src.val & (s16)mask;
799 else if (c->src.bytes == 4)
800 sv = (s32)c->src.val & (s32)mask;
801
90de84f5 802 c->dst.addr.mem.ea += (sv >> 3);
35c843c4 803 }
ba7ff2b7
WY		 804
805 /* only subword offset */
806 c->src.val &= (c->dst.bytes << 3) - 1;
35c843c4
WY		 807}
808
dde7e6d1
AK		 809static int read_emulated(struct x86_emulate_ctxt *ctxt,
810 struct x86_emulate_ops *ops,
811 unsigned long addr, void *dest, unsigned size)
6aa8b732 812{
dde7e6d1
AK		 813 int rc;
814 struct read_cache *mc = &ctxt->decode.mem_read;
6aa8b732 815
dde7e6d1
AK		 816 while (size) {
817 int n = min(size, 8u);
818 size -= n;
819 if (mc->pos < mc->end)
820 goto read_cached;
5cd21917 821
bcc55cba
AK		 822 rc = ops->read_emulated(addr, mc->data + mc->end, n,
823 &ctxt->exception, ctxt->vcpu);
dde7e6d1
AK		 824 if (rc != X86EMUL_CONTINUE)
825 return rc;
826 mc->end += n;
6aa8b732 827
dde7e6d1
AK		 828 read_cached:
829 memcpy(dest, mc->data + mc->pos, n);
830 mc->pos += n;
831 dest += n;
832 addr += n;
6aa8b732 833 }
dde7e6d1
AK		 834 return X86EMUL_CONTINUE;
835}
6aa8b732 836
dde7e6d1
AK		 837static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
838 struct x86_emulate_ops *ops,
839 unsigned int size, unsigned short port,
840 void *dest)
841{
842 struct read_cache *rc = &ctxt->decode.io_read;
b4c6abfe 843
dde7e6d1
AK		 844 if (rc->pos == rc->end) { /* refill pio read ahead */
845 struct decode_cache *c = &ctxt->decode;
846 unsigned int in_page, n;
847 unsigned int count = c->rep_prefix ?
848 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1;
849 in_page = (ctxt->eflags & EFLG_DF) ?
850 offset_in_page(c->regs[VCPU_REGS_RDI]) :
851 PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]);
852 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
853 count);
854 if (n == 0)
855 n = 1;
856 rc->pos = rc->end = 0;
857 if (!ops->pio_in_emulated(size, port, rc->data, n, ctxt->vcpu))
858 return 0;
859 rc->end = n * size;
6aa8b732
AK		 860 }
861
dde7e6d1
AK		 862 memcpy(dest, rc->data + rc->pos, size);
863 rc->pos += size;
864 return 1;
865}
6aa8b732 866
dde7e6d1
AK		 867static u32 desc_limit_scaled(struct desc_struct *desc)
868{
869 u32 limit = get_desc_limit(desc);
6aa8b732 870
dde7e6d1
AK		 871 return desc->g ? (limit << 12) | 0xfff : limit;
872}
6aa8b732 873
dde7e6d1
AK		 874static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
875 struct x86_emulate_ops *ops,
876 u16 selector, struct desc_ptr *dt)
877{
878 if (selector & 1 << 2) {
879 struct desc_struct desc;
880 memset (dt, 0, sizeof *dt);
5601d05b
GN		 881 if (!ops->get_cached_descriptor(&desc, NULL, VCPU_SREG_LDTR,
882 ctxt->vcpu))
dde7e6d1 883 return;
e09d082c 884
dde7e6d1
AK		 885 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
886 dt->address = get_desc_base(&desc);
887 } else
888 ops->get_gdt(dt, ctxt->vcpu);
889}
120df890 890
dde7e6d1
AK		 891/* allowed just for 8 bytes segments */
892static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
893 struct x86_emulate_ops *ops,
894 u16 selector, struct desc_struct *desc)
895{
896 struct desc_ptr dt;
897 u16 index = selector >> 3;
898 int ret;
dde7e6d1 899 ulong addr;
120df890 900
dde7e6d1 901 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
120df890 902
35d3d4a1
AK		 903 if (dt.size < index * 8 + 7)
904 return emulate_gp(ctxt, selector & 0xfffc);
dde7e6d1 905 addr = dt.address + index * 8;
bcc55cba
AK		 906 ret = ops->read_std(addr, desc, sizeof *desc, ctxt->vcpu,
907 &ctxt->exception);
e09d082c 908
dde7e6d1
AK		 909 return ret;
910}
ef65c889 911
dde7e6d1
AK		 912/* allowed just for 8 bytes segments */
913static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
914 struct x86_emulate_ops *ops,
915 u16 selector, struct desc_struct *desc)
916{
917 struct desc_ptr dt;
918 u16 index = selector >> 3;
dde7e6d1
AK		 919 ulong addr;
920 int ret;
6aa8b732 921
dde7e6d1 922 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
6e3d5dfb 923
35d3d4a1
AK		 924 if (dt.size < index * 8 + 7)
925 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 926
dde7e6d1 927 addr = dt.address + index * 8;
bcc55cba
AK		 928 ret = ops->write_std(addr, desc, sizeof *desc, ctxt->vcpu,
929 &ctxt->exception);
c7e75a3d 930
dde7e6d1
AK		 931 return ret;
932}
c7e75a3d 933
5601d05b 934/* Does not support long mode */
dde7e6d1
AK		 935static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
936 struct x86_emulate_ops *ops,
937 u16 selector, int seg)
938{
939 struct desc_struct seg_desc;
940 u8 dpl, rpl, cpl;
941 unsigned err_vec = GP_VECTOR;
942 u32 err_code = 0;
943 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
944 int ret;
69f55cb1 945
dde7e6d1 946 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 947
dde7e6d1
AK		 948 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
949 || ctxt->mode == X86EMUL_MODE_REAL) {
950 /* set real mode segment descriptor */
951 set_desc_base(&seg_desc, selector << 4);
952 set_desc_limit(&seg_desc, 0xffff);
953 seg_desc.type = 3;
954 seg_desc.p = 1;
955 seg_desc.s = 1;
956 goto load;
957 }
958
959 /* NULL selector is not valid for TR, CS and SS */
960 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
961 && null_selector)
962 goto exception;
963
964 /* TR should be in GDT only */
965 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
966 goto exception;
967
968 if (null_selector) /* for NULL selector skip all following checks */
969 goto load;
970
971 ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc);
972 if (ret != X86EMUL_CONTINUE)
973 return ret;
974
975 err_code = selector & 0xfffc;
976 err_vec = GP_VECTOR;
977
978 /* can't load system descriptor into segment selecor */
979 if (seg <= VCPU_SREG_GS && !seg_desc.s)
980 goto exception;
981
982 if (!seg_desc.p) {
983 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
984 goto exception;
985 }
986
987 rpl = selector & 3;
988 dpl = seg_desc.dpl;
989 cpl = ops->cpl(ctxt->vcpu);
990
991 switch (seg) {
992 case VCPU_SREG_SS:
993 /*
994 * segment is not a writable data segment or segment
995 * selector's RPL != CPL or segment selector's RPL != CPL
996 */
997 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
998 goto exception;
6aa8b732 999 break;
dde7e6d1
AK		 1000 case VCPU_SREG_CS:
1001 if (!(seg_desc.type & 8))
1002 goto exception;
1003
1004 if (seg_desc.type & 4) {
1005 /* conforming */
1006 if (dpl > cpl)
1007 goto exception;
1008 } else {
1009 /* nonconforming */
1010 if (rpl > cpl || dpl != cpl)
1011 goto exception;
1012 }
1013 /* CS(RPL) <- CPL */
1014 selector = (selector & 0xfffc) | cpl;
6aa8b732 1015 break;
dde7e6d1
AK		 1016 case VCPU_SREG_TR:
1017 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1018 goto exception;
1019 break;
1020 case VCPU_SREG_LDTR:
1021 if (seg_desc.s || seg_desc.type != 2)
1022 goto exception;
1023 break;
1024 default: /* DS, ES, FS, or GS */
4e62417b 1025 /*
dde7e6d1
AK		 1026 * segment is not a data or readable code segment or
1027 * ((segment is a data or nonconforming code segment)
1028 * and (both RPL and CPL > DPL))
4e62417b 1029 */
dde7e6d1
AK		 1030 if ((seg_desc.type & 0xa) == 0x8 ||
1031 (((seg_desc.type & 0xc) != 0xc) &&
1032 (rpl > dpl && cpl > dpl)))
1033 goto exception;
6aa8b732 1034 break;
dde7e6d1
AK		 1035 }
1036
1037 if (seg_desc.s) {
1038 /* mark segment as accessed */
1039 seg_desc.type |= 1;
1040 ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc);
1041 if (ret != X86EMUL_CONTINUE)
1042 return ret;
1043 }
1044load:
1045 ops->set_segment_selector(selector, seg, ctxt->vcpu);
5601d05b 1046 ops->set_cached_descriptor(&seg_desc, 0, seg, ctxt->vcpu);
dde7e6d1
AK		 1047 return X86EMUL_CONTINUE;
1048exception:
1049 emulate_exception(ctxt, err_vec, err_code, true);
1050 return X86EMUL_PROPAGATE_FAULT;
1051}
1052
31be40b3
WY		 1053static void write_register_operand(struct operand *op)
1054{
1055 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1056 switch (op->bytes) {
1057 case 1:
1058 *(u8 *)op->addr.reg = (u8)op->val;
1059 break;
1060 case 2:
1061 *(u16 *)op->addr.reg = (u16)op->val;
1062 break;
1063 case 4:
1064 *op->addr.reg = (u32)op->val;
1065 break; /* 64b: zero-extend */
1066 case 8:
1067 *op->addr.reg = op->val;
1068 break;
1069 }
1070}
1071
dde7e6d1
AK		 1072static inline int writeback(struct x86_emulate_ctxt *ctxt,
1073 struct x86_emulate_ops *ops)
1074{
1075 int rc;
1076 struct decode_cache *c = &ctxt->decode;
dde7e6d1
AK		 1077
1078 switch (c->dst.type) {
1079 case OP_REG:
31be40b3 1080 write_register_operand(&c->dst);
6aa8b732 1081 break;
dde7e6d1
AK		 1082 case OP_MEM:
1083 if (c->lock_prefix)
1084 rc = ops->cmpxchg_emulated(
90de84f5 1085 linear(ctxt, c->dst.addr.mem),
dde7e6d1
AK		 1086 &c->dst.orig_val,
1087 &c->dst.val,
1088 c->dst.bytes,
bcc55cba 1089 &ctxt->exception,
dde7e6d1 1090 ctxt->vcpu);
341de7e3 1091 else
dde7e6d1 1092 rc = ops->write_emulated(
90de84f5 1093 linear(ctxt, c->dst.addr.mem),
dde7e6d1
AK		 1094 &c->dst.val,
1095 c->dst.bytes,
bcc55cba 1096 &ctxt->exception,
dde7e6d1 1097 ctxt->vcpu);
dde7e6d1
AK		 1098 if (rc != X86EMUL_CONTINUE)
1099 return rc;
a682e354 1100 break;
dde7e6d1
AK		 1101 case OP_NONE:
1102 /* no writeback */
414e6277 1103 break;
dde7e6d1 1104 default:
414e6277 1105 break;
6aa8b732 1106 }
dde7e6d1
AK		 1107 return X86EMUL_CONTINUE;
1108}
6aa8b732 1109
dde7e6d1
AK		 1110static inline void emulate_push(struct x86_emulate_ctxt *ctxt,
1111 struct x86_emulate_ops *ops)
1112{
1113 struct decode_cache *c = &ctxt->decode;
0dc8d10f 1114
dde7e6d1
AK		 1115 c->dst.type = OP_MEM;
1116 c->dst.bytes = c->op_bytes;
1117 c->dst.val = c->src.val;
1118 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
90de84f5
AK		 1119 c->dst.addr.mem.ea = register_address(c, c->regs[VCPU_REGS_RSP]);
1120 c->dst.addr.mem.seg = VCPU_SREG_SS;
dde7e6d1 1121}
69f55cb1 1122
dde7e6d1
AK		 1123static int emulate_pop(struct x86_emulate_ctxt *ctxt,
1124 struct x86_emulate_ops *ops,
1125 void *dest, int len)
1126{
1127 struct decode_cache *c = &ctxt->decode;
1128 int rc;
90de84f5 1129 struct segmented_address addr;
8b4caf66 1130
90de84f5
AK		 1131 addr.ea = register_address(c, c->regs[VCPU_REGS_RSP]);
1132 addr.seg = VCPU_SREG_SS;
1133 rc = read_emulated(ctxt, ops, linear(ctxt, addr), dest, len);
dde7e6d1
AK		 1134 if (rc != X86EMUL_CONTINUE)
1135 return rc;
1136
1137 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
1138 return rc;
8b4caf66
LV		 1139}
1140
dde7e6d1
AK		 1141static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1142 struct x86_emulate_ops *ops,
1143 void *dest, int len)
9de41573
GN		 1144{
1145 int rc;
dde7e6d1
AK		 1146 unsigned long val, change_mask;
1147 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1148 int cpl = ops->cpl(ctxt->vcpu);
9de41573 1149
dde7e6d1
AK		 1150 rc = emulate_pop(ctxt, ops, &val, len);
1151 if (rc != X86EMUL_CONTINUE)
1152 return rc;
9de41573 1153
dde7e6d1
AK		 1154 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1155 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1156
dde7e6d1
AK		 1157 switch(ctxt->mode) {
1158 case X86EMUL_MODE_PROT64:
1159 case X86EMUL_MODE_PROT32:
1160 case X86EMUL_MODE_PROT16:
1161 if (cpl == 0)
1162 change_mask |= EFLG_IOPL;
1163 if (cpl <= iopl)
1164 change_mask |= EFLG_IF;
1165 break;
1166 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1167 if (iopl < 3)
1168 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1169 change_mask |= EFLG_IF;
1170 break;
1171 default: /* real mode */
1172 change_mask |= (EFLG_IOPL | EFLG_IF);
1173 break;
9de41573 1174 }
dde7e6d1
AK		 1175
1176 *(unsigned long *)dest =
1177 (ctxt->eflags & ~change_mask) | (val & change_mask);
1178
1179 return rc;
9de41573
GN		 1180}
1181
dde7e6d1
AK		 1182static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt,
1183 struct x86_emulate_ops *ops, int seg)
7b262e90 1184{
dde7e6d1 1185 struct decode_cache *c = &ctxt->decode;
7b262e90 1186
dde7e6d1 1187 c->src.val = ops->get_segment_selector(seg, ctxt->vcpu);
7b262e90 1188
dde7e6d1 1189 emulate_push(ctxt, ops);
7b262e90
GN		 1190}
1191
dde7e6d1
AK		 1192static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
1193 struct x86_emulate_ops *ops, int seg)
38ba30ba 1194{
dde7e6d1
AK		 1195 struct decode_cache *c = &ctxt->decode;
1196 unsigned long selector;
1197 int rc;
38ba30ba 1198
dde7e6d1
AK		 1199 rc = emulate_pop(ctxt, ops, &selector, c->op_bytes);
1200 if (rc != X86EMUL_CONTINUE)
1201 return rc;
1202
1203 rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg);
1204 return rc;
38ba30ba
GN		 1205}
1206
dde7e6d1
AK		 1207static int emulate_pusha(struct x86_emulate_ctxt *ctxt,
1208 struct x86_emulate_ops *ops)
38ba30ba 1209{
dde7e6d1
AK		 1210 struct decode_cache *c = &ctxt->decode;
1211 unsigned long old_esp = c->regs[VCPU_REGS_RSP];
1212 int rc = X86EMUL_CONTINUE;
1213 int reg = VCPU_REGS_RAX;
38ba30ba 1214
dde7e6d1
AK		 1215 while (reg <= VCPU_REGS_RDI) {
1216 (reg == VCPU_REGS_RSP) ?
1217 (c->src.val = old_esp) : (c->src.val = c->regs[reg]);
38ba30ba 1218
dde7e6d1 1219 emulate_push(ctxt, ops);
38ba30ba 1220
dde7e6d1
AK		 1221 rc = writeback(ctxt, ops);
1222 if (rc != X86EMUL_CONTINUE)
1223 return rc;
38ba30ba 1224
dde7e6d1 1225 ++reg;
38ba30ba 1226 }
38ba30ba 1227
dde7e6d1
AK		 1228 /* Disable writeback. */
1229 c->dst.type = OP_NONE;
1230
1231 return rc;
38ba30ba
GN		 1232}
1233
dde7e6d1
AK		 1234static int emulate_popa(struct x86_emulate_ctxt *ctxt,
1235 struct x86_emulate_ops *ops)
38ba30ba 1236{
dde7e6d1
AK		 1237 struct decode_cache *c = &ctxt->decode;
1238 int rc = X86EMUL_CONTINUE;
1239 int reg = VCPU_REGS_RDI;
38ba30ba 1240
dde7e6d1
AK		 1241 while (reg >= VCPU_REGS_RAX) {
1242 if (reg == VCPU_REGS_RSP) {
1243 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1244 c->op_bytes);
1245 --reg;
1246 }
38ba30ba 1247
dde7e6d1
AK		 1248 rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes);
1249 if (rc != X86EMUL_CONTINUE)
1250 break;
1251 --reg;
38ba30ba 1252 }
dde7e6d1 1253 return rc;
38ba30ba
GN		 1254}
1255
6e154e56
MG		 1256int emulate_int_real(struct x86_emulate_ctxt *ctxt,
1257 struct x86_emulate_ops *ops, int irq)
1258{
1259 struct decode_cache *c = &ctxt->decode;
5c56e1cf 1260 int rc;
6e154e56
MG		 1261 struct desc_ptr dt;
1262 gva_t cs_addr;
1263 gva_t eip_addr;
1264 u16 cs, eip;
6e154e56
MG		 1265
1266 /* TODO: Add limit checks */
1267 c->src.val = ctxt->eflags;
1268 emulate_push(ctxt, ops);
5c56e1cf
AK		 1269 rc = writeback(ctxt, ops);
1270 if (rc != X86EMUL_CONTINUE)
1271 return rc;
6e154e56
MG		 1272
1273 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1274
1275 c->src.val = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
1276 emulate_push(ctxt, ops);
5c56e1cf
AK		 1277 rc = writeback(ctxt, ops);
1278 if (rc != X86EMUL_CONTINUE)
1279 return rc;
6e154e56
MG		 1280
1281 c->src.val = c->eip;
1282 emulate_push(ctxt, ops);
5c56e1cf
AK		 1283 rc = writeback(ctxt, ops);
1284 if (rc != X86EMUL_CONTINUE)
1285 return rc;
1286
1287 c->dst.type = OP_NONE;
6e154e56
MG		 1288
1289 ops->get_idt(&dt, ctxt->vcpu);
1290
1291 eip_addr = dt.address + (irq << 2);
1292 cs_addr = dt.address + (irq << 2) + 2;
1293
bcc55cba 1294 rc = ops->read_std(cs_addr, &cs, 2, ctxt->vcpu, &ctxt->exception);
6e154e56
MG		 1295 if (rc != X86EMUL_CONTINUE)
1296 return rc;
1297
bcc55cba 1298 rc = ops->read_std(eip_addr, &eip, 2, ctxt->vcpu, &ctxt->exception);
6e154e56
MG		 1299 if (rc != X86EMUL_CONTINUE)
1300 return rc;
1301
1302 rc = load_segment_descriptor(ctxt, ops, cs, VCPU_SREG_CS);
1303 if (rc != X86EMUL_CONTINUE)
1304 return rc;
1305
1306 c->eip = eip;
1307
1308 return rc;
1309}
1310
1311static int emulate_int(struct x86_emulate_ctxt *ctxt,
1312 struct x86_emulate_ops *ops, int irq)
1313{
1314 switch(ctxt->mode) {
1315 case X86EMUL_MODE_REAL:
1316 return emulate_int_real(ctxt, ops, irq);
1317 case X86EMUL_MODE_VM86:
1318 case X86EMUL_MODE_PROT16:
1319 case X86EMUL_MODE_PROT32:
1320 case X86EMUL_MODE_PROT64:
1321 default:
1322 /* Protected mode interrupts unimplemented yet */
1323 return X86EMUL_UNHANDLEABLE;
1324 }
1325}
1326
dde7e6d1
AK		 1327static int emulate_iret_real(struct x86_emulate_ctxt *ctxt,
1328 struct x86_emulate_ops *ops)
38ba30ba 1329{
dde7e6d1
AK		 1330 struct decode_cache *c = &ctxt->decode;
1331 int rc = X86EMUL_CONTINUE;
1332 unsigned long temp_eip = 0;
1333 unsigned long temp_eflags = 0;
1334 unsigned long cs = 0;
1335 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1336 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1337 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1338 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1339
dde7e6d1 1340 /* TODO: Add stack limit check */
38ba30ba 1341
dde7e6d1 1342 rc = emulate_pop(ctxt, ops, &temp_eip, c->op_bytes);
38ba30ba 1343
dde7e6d1
AK		 1344 if (rc != X86EMUL_CONTINUE)
1345 return rc;
38ba30ba 1346
35d3d4a1
AK		 1347 if (temp_eip & ~0xffff)
1348 return emulate_gp(ctxt, 0);
38ba30ba 1349
dde7e6d1 1350 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
38ba30ba 1351
dde7e6d1
AK		 1352 if (rc != X86EMUL_CONTINUE)
1353 return rc;
38ba30ba 1354
dde7e6d1 1355 rc = emulate_pop(ctxt, ops, &temp_eflags, c->op_bytes);
38ba30ba 1356
dde7e6d1
AK		 1357 if (rc != X86EMUL_CONTINUE)
1358 return rc;
38ba30ba 1359
dde7e6d1 1360 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
38ba30ba 1361
dde7e6d1
AK		 1362 if (rc != X86EMUL_CONTINUE)
1363 return rc;
38ba30ba 1364
dde7e6d1 1365 c->eip = temp_eip;
38ba30ba 1366
38ba30ba 1367
dde7e6d1
AK		 1368 if (c->op_bytes == 4)
1369 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
1370 else if (c->op_bytes == 2) {
1371 ctxt->eflags &= ~0xffff;
1372 ctxt->eflags |= temp_eflags;
38ba30ba 1373 }
dde7e6d1
AK		 1374
1375 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1376 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1377
1378 return rc;
38ba30ba
GN		 1379}
1380
dde7e6d1
AK		 1381static inline int emulate_iret(struct x86_emulate_ctxt *ctxt,
1382 struct x86_emulate_ops* ops)
c37eda13 1383{
dde7e6d1
AK		 1384 switch(ctxt->mode) {
1385 case X86EMUL_MODE_REAL:
1386 return emulate_iret_real(ctxt, ops);
1387 case X86EMUL_MODE_VM86:
1388 case X86EMUL_MODE_PROT16:
1389 case X86EMUL_MODE_PROT32:
1390 case X86EMUL_MODE_PROT64:
c37eda13 1391 default:
dde7e6d1
AK		 1392 /* iret from protected mode unimplemented yet */
1393 return X86EMUL_UNHANDLEABLE;
c37eda13 1394 }
c37eda13
WY		 1395}
1396
dde7e6d1 1397static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
79168fd1 1398 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1399{
1400 struct decode_cache *c = &ctxt->decode;
1401
dde7e6d1 1402 return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
8cdbd2c9
LV		 1403}
1404
dde7e6d1 1405static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1406{
05f086f8 1407 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1408 switch (c->modrm_reg) {
1409 case 0: /* rol */
05f086f8 1410 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1411 break;
1412 case 1: /* ror */
05f086f8 1413 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1414 break;
1415 case 2: /* rcl */
05f086f8 1416 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1417 break;
1418 case 3: /* rcr */
05f086f8 1419 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1420 break;
1421 case 4: /* sal/shl */
1422 case 6: /* sal/shl */
05f086f8 1423 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1424 break;
1425 case 5: /* shr */
05f086f8 1426 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1427 break;
1428 case 7: /* sar */
05f086f8 1429 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1430 break;
1431 }
1432}
1433
1434static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 1435 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1436{
1437 struct decode_cache *c = &ctxt->decode;
3f9f53b0
MG		 1438 unsigned long *rax = &c->regs[VCPU_REGS_RAX];
1439 unsigned long *rdx = &c->regs[VCPU_REGS_RDX];
34d1f490 1440 u8 de = 0;
8cdbd2c9
LV		 1441
1442 switch (c->modrm_reg) {
1443 case 0 ... 1: /* test */
05f086f8 1444 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1445 break;
1446 case 2: /* not */
1447 c->dst.val = ~c->dst.val;
1448 break;
1449 case 3: /* neg */
05f086f8 1450 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9 1451 break;
3f9f53b0
MG		 1452 case 4: /* mul */
1453 emulate_1op_rax_rdx("mul", c->src, *rax, *rdx, ctxt->eflags);
1454 break;
1455 case 5: /* imul */
1456 emulate_1op_rax_rdx("imul", c->src, *rax, *rdx, ctxt->eflags);
1457 break;
1458 case 6: /* div */
34d1f490
AK		 1459 emulate_1op_rax_rdx_ex("div", c->src, *rax, *rdx,
1460 ctxt->eflags, de);
3f9f53b0
MG		 1461 break;
1462 case 7: /* idiv */
34d1f490
AK		 1463 emulate_1op_rax_rdx_ex("idiv", c->src, *rax, *rdx,
1464 ctxt->eflags, de);
3f9f53b0 1465 break;
8cdbd2c9 1466 default:
8c5eee30 1467 return X86EMUL_UNHANDLEABLE;
8cdbd2c9 1468 }
34d1f490
AK		 1469 if (de)
1470 return emulate_de(ctxt);
8c5eee30 1471 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1472}
1473
1474static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
a01af5ec 1475 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1476{
1477 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1478
1479 switch (c->modrm_reg) {
1480 case 0: /* inc */
05f086f8 1481 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1482 break;
1483 case 1: /* dec */
05f086f8 1484 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9 1485 break;
d19292e4
MG		 1486 case 2: /* call near abs */ {
1487 long int old_eip;
1488 old_eip = c->eip;
1489 c->eip = c->src.val;
1490 c->src.val = old_eip;
79168fd1 1491 emulate_push(ctxt, ops);
d19292e4
MG		 1492 break;
1493 }
8cdbd2c9 1494 case 4: /* jmp abs */
fd60754e 1495 c->eip = c->src.val;
8cdbd2c9
LV		 1496 break;
1497 case 6: /* push */
79168fd1 1498 emulate_push(ctxt, ops);
8cdbd2c9 1499 break;
8cdbd2c9 1500 }
1b30eaa8 1501 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1502}
1503
1504static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
69f55cb1 1505 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1506{
1507 struct decode_cache *c = &ctxt->decode;
16518d5a 1508 u64 old = c->dst.orig_val64;
8cdbd2c9
LV		 1509
1510 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1511 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
8cdbd2c9
LV		 1512 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1513 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1514 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 1515 } else {
16518d5a
AK		 1516 c->dst.val64 = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1517 (u32) c->regs[VCPU_REGS_RBX];
8cdbd2c9 1518
05f086f8 1519 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 1520 }
1b30eaa8 1521 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1522}
1523
a77ab5ea
AK		 1524static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1525 struct x86_emulate_ops *ops)
1526{
1527 struct decode_cache *c = &ctxt->decode;
1528 int rc;
1529 unsigned long cs;
1530
1531 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1b30eaa8 1532 if (rc != X86EMUL_CONTINUE)
a77ab5ea
AK		 1533 return rc;
1534 if (c->op_bytes == 4)
1535 c->eip = (u32)c->eip;
1536 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1b30eaa8 1537 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1538 return rc;
2e873022 1539 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 1540 return rc;
1541}
1542
09b5f4d3
WY		 1543static int emulate_load_segment(struct x86_emulate_ctxt *ctxt,
1544 struct x86_emulate_ops *ops, int seg)
1545{
1546 struct decode_cache *c = &ctxt->decode;
1547 unsigned short sel;
1548 int rc;
1549
1550 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
1551
1552 rc = load_segment_descriptor(ctxt, ops, sel, seg);
1553 if (rc != X86EMUL_CONTINUE)
1554 return rc;
1555
1556 c->dst.val = c->src.val;
1557 return rc;
1558}
1559
e66bb2cc
AP		 1560static inline void
1561setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
79168fd1
GN		 1562 struct x86_emulate_ops *ops, struct desc_struct *cs,
1563 struct desc_struct *ss)
e66bb2cc 1564{
79168fd1 1565 memset(cs, 0, sizeof(struct desc_struct));
5601d05b 1566 ops->get_cached_descriptor(cs, NULL, VCPU_SREG_CS, ctxt->vcpu);
79168fd1 1567 memset(ss, 0, sizeof(struct desc_struct));
e66bb2cc
AP		 1568
1569 cs->l = 0; /* will be adjusted later */
79168fd1 1570 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 1571 cs->g = 1; /* 4kb granularity */
79168fd1 1572 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1573 cs->type = 0x0b; /* Read, Execute, Accessed */
1574 cs->s = 1;
1575 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 1576 cs->p = 1;
1577 cs->d = 1;
e66bb2cc 1578
79168fd1
GN		 1579 set_desc_base(ss, 0); /* flat segment */
1580 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1581 ss->g = 1; /* 4kb granularity */
1582 ss->s = 1;
1583 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 1584 ss->d = 1; /* 32bit stack segment */
e66bb2cc 1585 ss->dpl = 0;
79168fd1 1586 ss->p = 1;
e66bb2cc
AP		 1587}
1588
1589static int
3fb1b5db 1590emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
e66bb2cc
AP		 1591{
1592 struct decode_cache *c = &ctxt->decode;
79168fd1 1593 struct desc_struct cs, ss;
e66bb2cc 1594 u64 msr_data;
79168fd1 1595 u16 cs_sel, ss_sel;
e66bb2cc
AP		 1596
1597 /* syscall is not available in real mode */
2e901c4c 1598 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 1599 ctxt->mode == X86EMUL_MODE_VM86)
1600 return emulate_ud(ctxt);
e66bb2cc 1601
79168fd1 1602 setup_syscalls_segments(ctxt, ops, &cs, &ss);
e66bb2cc 1603
3fb1b5db 1604 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
e66bb2cc 1605 msr_data >>= 32;
79168fd1
GN		 1606 cs_sel = (u16)(msr_data & 0xfffc);
1607 ss_sel = (u16)(msr_data + 8);
e66bb2cc
AP		 1608
1609 if (is_long_mode(ctxt->vcpu)) {
79168fd1 1610 cs.d = 0;
e66bb2cc
AP		 1611 cs.l = 1;
1612 }
5601d05b 1613 ops->set_cached_descriptor(&cs, 0, VCPU_SREG_CS, ctxt->vcpu);
79168fd1 1614 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
5601d05b 1615 ops->set_cached_descriptor(&ss, 0, VCPU_SREG_SS, ctxt->vcpu);
79168fd1 1616 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
e66bb2cc
AP		 1617
1618 c->regs[VCPU_REGS_RCX] = c->eip;
1619 if (is_long_mode(ctxt->vcpu)) {
1620#ifdef CONFIG_X86_64
1621 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
1622
3fb1b5db
GN		 1623 ops->get_msr(ctxt->vcpu,
1624 ctxt->mode == X86EMUL_MODE_PROT64 ?
1625 MSR_LSTAR : MSR_CSTAR, &msr_data);
e66bb2cc
AP		 1626 c->eip = msr_data;
1627
3fb1b5db 1628 ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 1629 ctxt->eflags &= ~(msr_data | EFLG_RF);
1630#endif
1631 } else {
1632 /* legacy mode */
3fb1b5db 1633 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
e66bb2cc
AP		 1634 c->eip = (u32)msr_data;
1635
1636 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1637 }
1638
e54cfa97 1639 return X86EMUL_CONTINUE;
e66bb2cc
AP		 1640}
1641
8c604352 1642static int
3fb1b5db 1643emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8c604352
AP		 1644{
1645 struct decode_cache *c = &ctxt->decode;
79168fd1 1646 struct desc_struct cs, ss;
8c604352 1647 u64 msr_data;
79168fd1 1648 u16 cs_sel, ss_sel;
8c604352 1649
a0044755 1650 /* inject #GP if in real mode */
35d3d4a1
AK		 1651 if (ctxt->mode == X86EMUL_MODE_REAL)
1652 return emulate_gp(ctxt, 0);
8c604352
AP		 1653
1654 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1655 * Therefore, we inject an #UD.
1656 */
35d3d4a1
AK		 1657 if (ctxt->mode == X86EMUL_MODE_PROT64)
1658 return emulate_ud(ctxt);
8c604352 1659
79168fd1 1660 setup_syscalls_segments(ctxt, ops, &cs, &ss);
8c604352 1661
3fb1b5db 1662 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 1663 switch (ctxt->mode) {
1664 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 1665 if ((msr_data & 0xfffc) == 0x0)
1666 return emulate_gp(ctxt, 0);
8c604352
AP		 1667 break;
1668 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 1669 if (msr_data == 0x0)
1670 return emulate_gp(ctxt, 0);
8c604352
AP		 1671 break;
1672 }
1673
1674 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 1675 cs_sel = (u16)msr_data;
1676 cs_sel &= ~SELECTOR_RPL_MASK;
1677 ss_sel = cs_sel + 8;
1678 ss_sel &= ~SELECTOR_RPL_MASK;
8c604352
AP		 1679 if (ctxt->mode == X86EMUL_MODE_PROT64
1680 || is_long_mode(ctxt->vcpu)) {
79168fd1 1681 cs.d = 0;
8c604352
AP		 1682 cs.l = 1;
1683 }
1684
5601d05b 1685 ops->set_cached_descriptor(&cs, 0, VCPU_SREG_CS, ctxt->vcpu);
79168fd1 1686 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
5601d05b 1687 ops->set_cached_descriptor(&ss, 0, VCPU_SREG_SS, ctxt->vcpu);
79168fd1 1688 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
8c604352 1689
3fb1b5db 1690 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data);
8c604352
AP		 1691 c->eip = msr_data;
1692
3fb1b5db 1693 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data);
8c604352
AP		 1694 c->regs[VCPU_REGS_RSP] = msr_data;
1695
e54cfa97 1696 return X86EMUL_CONTINUE;
8c604352
AP		 1697}
1698
4668f050 1699static int
3fb1b5db 1700emulate_sysexit(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
4668f050
AP		 1701{
1702 struct decode_cache *c = &ctxt->decode;
79168fd1 1703 struct desc_struct cs, ss;
4668f050
AP		 1704 u64 msr_data;
1705 int usermode;
79168fd1 1706 u16 cs_sel, ss_sel;
4668f050 1707
a0044755
GN		 1708 /* inject #GP if in real mode or Virtual 8086 mode */
1709 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 1710 ctxt->mode == X86EMUL_MODE_VM86)
1711 return emulate_gp(ctxt, 0);
4668f050 1712
79168fd1 1713 setup_syscalls_segments(ctxt, ops, &cs, &ss);
4668f050
AP		 1714
1715 if ((c->rex_prefix & 0x8) != 0x0)
1716 usermode = X86EMUL_MODE_PROT64;
1717 else
1718 usermode = X86EMUL_MODE_PROT32;
1719
1720 cs.dpl = 3;
1721 ss.dpl = 3;
3fb1b5db 1722 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 1723 switch (usermode) {
1724 case X86EMUL_MODE_PROT32:
79168fd1 1725 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 1726 if ((msr_data & 0xfffc) == 0x0)
1727 return emulate_gp(ctxt, 0);
79168fd1 1728 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 1729 break;
1730 case X86EMUL_MODE_PROT64:
79168fd1 1731 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 1732 if (msr_data == 0x0)
1733 return emulate_gp(ctxt, 0);
79168fd1
GN		 1734 ss_sel = cs_sel + 8;
1735 cs.d = 0;
4668f050
AP		 1736 cs.l = 1;
1737 break;
1738 }
79168fd1
GN		 1739 cs_sel |= SELECTOR_RPL_MASK;
1740 ss_sel |= SELECTOR_RPL_MASK;
4668f050 1741
5601d05b 1742 ops->set_cached_descriptor(&cs, 0, VCPU_SREG_CS, ctxt->vcpu);
79168fd1 1743 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
5601d05b 1744 ops->set_cached_descriptor(&ss, 0, VCPU_SREG_SS, ctxt->vcpu);
79168fd1 1745 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
4668f050 1746
bdb475a3
GN		 1747 c->eip = c->regs[VCPU_REGS_RDX];
1748 c->regs[VCPU_REGS_RSP] = c->regs[VCPU_REGS_RCX];
4668f050 1749
e54cfa97 1750 return X86EMUL_CONTINUE;
4668f050
AP		 1751}
1752
9c537244
GN		 1753static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt,
1754 struct x86_emulate_ops *ops)
f850e2e6
GN		 1755{
1756 int iopl;
1757 if (ctxt->mode == X86EMUL_MODE_REAL)
1758 return false;
1759 if (ctxt->mode == X86EMUL_MODE_VM86)
1760 return true;
1761 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
9c537244 1762 return ops->cpl(ctxt->vcpu) > iopl;
f850e2e6
GN		 1763}
1764
1765static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
1766 struct x86_emulate_ops *ops,
1767 u16 port, u16 len)
1768{
79168fd1 1769 struct desc_struct tr_seg;
5601d05b 1770 u32 base3;
f850e2e6
GN		 1771 int r;
1772 u16 io_bitmap_ptr;
1773 u8 perm, bit_idx = port & 0x7;
1774 unsigned mask = (1 << len) - 1;
5601d05b 1775 unsigned long base;
f850e2e6 1776
5601d05b 1777 ops->get_cached_descriptor(&tr_seg, &base3, VCPU_SREG_TR, ctxt->vcpu);
79168fd1 1778 if (!tr_seg.p)
f850e2e6 1779 return false;
79168fd1 1780 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 1781 return false;
5601d05b
GN		 1782 base = get_desc_base(&tr_seg);
1783#ifdef CONFIG_X86_64
1784 base |= ((u64)base3) << 32;
1785#endif
1786 r = ops->read_std(base + 102, &io_bitmap_ptr, 2, ctxt->vcpu, NULL);
f850e2e6
GN		 1787 if (r != X86EMUL_CONTINUE)
1788 return false;
79168fd1 1789 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 1790 return false;
5601d05b
GN		 1791 r = ops->read_std(base + io_bitmap_ptr + port/8, &perm, 1, ctxt->vcpu,
1792 NULL);
f850e2e6
GN		 1793 if (r != X86EMUL_CONTINUE)
1794 return false;
1795 if ((perm >> bit_idx) & mask)
1796 return false;
1797 return true;
1798}
1799
1800static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
1801 struct x86_emulate_ops *ops,
1802 u16 port, u16 len)
1803{
4fc40f07
GN		 1804 if (ctxt->perm_ok)
1805 return true;
1806
9c537244 1807 if (emulator_bad_iopl(ctxt, ops))
f850e2e6
GN		 1808 if (!emulator_io_port_access_allowed(ctxt, ops, port, len))
1809 return false;
4fc40f07
GN		 1810
1811 ctxt->perm_ok = true;
1812
f850e2e6
GN		 1813 return true;
1814}
1815
38ba30ba
GN		 1816static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
1817 struct x86_emulate_ops *ops,
1818 struct tss_segment_16 *tss)
1819{
1820 struct decode_cache *c = &ctxt->decode;
1821
1822 tss->ip = c->eip;
1823 tss->flag = ctxt->eflags;
1824 tss->ax = c->regs[VCPU_REGS_RAX];
1825 tss->cx = c->regs[VCPU_REGS_RCX];
1826 tss->dx = c->regs[VCPU_REGS_RDX];
1827 tss->bx = c->regs[VCPU_REGS_RBX];
1828 tss->sp = c->regs[VCPU_REGS_RSP];
1829 tss->bp = c->regs[VCPU_REGS_RBP];
1830 tss->si = c->regs[VCPU_REGS_RSI];
1831 tss->di = c->regs[VCPU_REGS_RDI];
1832
1833 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
1834 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
1835 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
1836 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
1837 tss->ldt = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
1838}
1839
1840static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
1841 struct x86_emulate_ops *ops,
1842 struct tss_segment_16 *tss)
1843{
1844 struct decode_cache *c = &ctxt->decode;
1845 int ret;
1846
1847 c->eip = tss->ip;
1848 ctxt->eflags = tss->flag | 2;
1849 c->regs[VCPU_REGS_RAX] = tss->ax;
1850 c->regs[VCPU_REGS_RCX] = tss->cx;
1851 c->regs[VCPU_REGS_RDX] = tss->dx;
1852 c->regs[VCPU_REGS_RBX] = tss->bx;
1853 c->regs[VCPU_REGS_RSP] = tss->sp;
1854 c->regs[VCPU_REGS_RBP] = tss->bp;
1855 c->regs[VCPU_REGS_RSI] = tss->si;
1856 c->regs[VCPU_REGS_RDI] = tss->di;
1857
1858 /*
1859 * SDM says that segment selectors are loaded before segment
1860 * descriptors
1861 */
1862 ops->set_segment_selector(tss->ldt, VCPU_SREG_LDTR, ctxt->vcpu);
1863 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
1864 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
1865 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
1866 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
1867
1868 /*
1869 * Now load segment descriptors. If fault happenes at this stage
1870 * it is handled in a context of new task
1871 */
1872 ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR);
1873 if (ret != X86EMUL_CONTINUE)
1874 return ret;
1875 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
1876 if (ret != X86EMUL_CONTINUE)
1877 return ret;
1878 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
1879 if (ret != X86EMUL_CONTINUE)
1880 return ret;
1881 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
1882 if (ret != X86EMUL_CONTINUE)
1883 return ret;
1884 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
1885 if (ret != X86EMUL_CONTINUE)
1886 return ret;
1887
1888 return X86EMUL_CONTINUE;
1889}
1890
1891static int task_switch_16(struct x86_emulate_ctxt *ctxt,
1892 struct x86_emulate_ops *ops,
1893 u16 tss_selector, u16 old_tss_sel,
1894 ulong old_tss_base, struct desc_struct *new_desc)
1895{
1896 struct tss_segment_16 tss_seg;
1897 int ret;
bcc55cba 1898 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba
GN		 1899
1900 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
bcc55cba 1901 &ctxt->exception);
db297e3d 1902 if (ret != X86EMUL_CONTINUE)
38ba30ba 1903 /* FIXME: need to provide precise fault address */
38ba30ba 1904 return ret;
38ba30ba
GN		 1905
1906 save_state_to_tss16(ctxt, ops, &tss_seg);
1907
1908 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
bcc55cba 1909 &ctxt->exception);
db297e3d 1910 if (ret != X86EMUL_CONTINUE)
38ba30ba 1911 /* FIXME: need to provide precise fault address */
38ba30ba 1912 return ret;
38ba30ba
GN		 1913
1914 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
bcc55cba 1915 &ctxt->exception);
db297e3d 1916 if (ret != X86EMUL_CONTINUE)
38ba30ba 1917 /* FIXME: need to provide precise fault address */
38ba30ba 1918 return ret;
38ba30ba
GN		 1919
1920 if (old_tss_sel != 0xffff) {
1921 tss_seg.prev_task_link = old_tss_sel;
1922
1923 ret = ops->write_std(new_tss_base,
1924 &tss_seg.prev_task_link,
1925 sizeof tss_seg.prev_task_link,
bcc55cba 1926 ctxt->vcpu, &ctxt->exception);
db297e3d 1927 if (ret != X86EMUL_CONTINUE)
38ba30ba 1928 /* FIXME: need to provide precise fault address */
38ba30ba 1929 return ret;
38ba30ba
GN		 1930 }
1931
1932 return load_state_from_tss16(ctxt, ops, &tss_seg);
1933}
1934
1935static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
1936 struct x86_emulate_ops *ops,
1937 struct tss_segment_32 *tss)
1938{
1939 struct decode_cache *c = &ctxt->decode;
1940
1941 tss->cr3 = ops->get_cr(3, ctxt->vcpu);
1942 tss->eip = c->eip;
1943 tss->eflags = ctxt->eflags;
1944 tss->eax = c->regs[VCPU_REGS_RAX];
1945 tss->ecx = c->regs[VCPU_REGS_RCX];
1946 tss->edx = c->regs[VCPU_REGS_RDX];
1947 tss->ebx = c->regs[VCPU_REGS_RBX];
1948 tss->esp = c->regs[VCPU_REGS_RSP];
1949 tss->ebp = c->regs[VCPU_REGS_RBP];
1950 tss->esi = c->regs[VCPU_REGS_RSI];
1951 tss->edi = c->regs[VCPU_REGS_RDI];
1952
1953 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
1954 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
1955 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
1956 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
1957 tss->fs = ops->get_segment_selector(VCPU_SREG_FS, ctxt->vcpu);
1958 tss->gs = ops->get_segment_selector(VCPU_SREG_GS, ctxt->vcpu);
1959 tss->ldt_selector = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
1960}
1961
1962static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
1963 struct x86_emulate_ops *ops,
1964 struct tss_segment_32 *tss)
1965{
1966 struct decode_cache *c = &ctxt->decode;
1967 int ret;
1968
35d3d4a1
AK		 1969 if (ops->set_cr(3, tss->cr3, ctxt->vcpu))
1970 return emulate_gp(ctxt, 0);
38ba30ba
GN		 1971 c->eip = tss->eip;
1972 ctxt->eflags = tss->eflags | 2;
1973 c->regs[VCPU_REGS_RAX] = tss->eax;
1974 c->regs[VCPU_REGS_RCX] = tss->ecx;
1975 c->regs[VCPU_REGS_RDX] = tss->edx;
1976 c->regs[VCPU_REGS_RBX] = tss->ebx;
1977 c->regs[VCPU_REGS_RSP] = tss->esp;
1978 c->regs[VCPU_REGS_RBP] = tss->ebp;
1979 c->regs[VCPU_REGS_RSI] = tss->esi;
1980 c->regs[VCPU_REGS_RDI] = tss->edi;
1981
1982 /*
1983 * SDM says that segment selectors are loaded before segment
1984 * descriptors
1985 */
1986 ops->set_segment_selector(tss->ldt_selector, VCPU_SREG_LDTR, ctxt->vcpu);
1987 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
1988 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
1989 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
1990 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
1991 ops->set_segment_selector(tss->fs, VCPU_SREG_FS, ctxt->vcpu);
1992 ops->set_segment_selector(tss->gs, VCPU_SREG_GS, ctxt->vcpu);
1993
1994 /*
1995 * Now load segment descriptors. If fault happenes at this stage
1996 * it is handled in a context of new task
1997 */
1998 ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR);
1999 if (ret != X86EMUL_CONTINUE)
2000 return ret;
2001 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2002 if (ret != X86EMUL_CONTINUE)
2003 return ret;
2004 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2005 if (ret != X86EMUL_CONTINUE)
2006 return ret;
2007 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2008 if (ret != X86EMUL_CONTINUE)
2009 return ret;
2010 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2011 if (ret != X86EMUL_CONTINUE)
2012 return ret;
2013 ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS);
2014 if (ret != X86EMUL_CONTINUE)
2015 return ret;
2016 ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS);
2017 if (ret != X86EMUL_CONTINUE)
2018 return ret;
2019
2020 return X86EMUL_CONTINUE;
2021}
2022
2023static int task_switch_32(struct x86_emulate_ctxt *ctxt,
2024 struct x86_emulate_ops *ops,
2025 u16 tss_selector, u16 old_tss_sel,
2026 ulong old_tss_base, struct desc_struct *new_desc)
2027{
2028 struct tss_segment_32 tss_seg;
2029 int ret;
bcc55cba 2030 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba
GN		 2031
2032 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
bcc55cba 2033 &ctxt->exception);
db297e3d 2034 if (ret != X86EMUL_CONTINUE)
38ba30ba 2035 /* FIXME: need to provide precise fault address */
38ba30ba 2036 return ret;
38ba30ba
GN		 2037
2038 save_state_to_tss32(ctxt, ops, &tss_seg);
2039
2040 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
bcc55cba 2041 &ctxt->exception);
db297e3d 2042 if (ret != X86EMUL_CONTINUE)
38ba30ba 2043 /* FIXME: need to provide precise fault address */
38ba30ba 2044 return ret;
38ba30ba
GN		 2045
2046 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
bcc55cba 2047 &ctxt->exception);
db297e3d 2048 if (ret != X86EMUL_CONTINUE)
38ba30ba 2049 /* FIXME: need to provide precise fault address */
38ba30ba 2050 return ret;
38ba30ba
GN		 2051
2052 if (old_tss_sel != 0xffff) {
2053 tss_seg.prev_task_link = old_tss_sel;
2054
2055 ret = ops->write_std(new_tss_base,
2056 &tss_seg.prev_task_link,
2057 sizeof tss_seg.prev_task_link,
bcc55cba 2058 ctxt->vcpu, &ctxt->exception);
db297e3d 2059 if (ret != X86EMUL_CONTINUE)
38ba30ba 2060 /* FIXME: need to provide precise fault address */
38ba30ba 2061 return ret;
38ba30ba
GN		 2062 }
2063
2064 return load_state_from_tss32(ctxt, ops, &tss_seg);
2065}
2066
2067static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2068 struct x86_emulate_ops *ops,
2069 u16 tss_selector, int reason,
2070 bool has_error_code, u32 error_code)
38ba30ba
GN		 2071{
2072 struct desc_struct curr_tss_desc, next_tss_desc;
2073 int ret;
2074 u16 old_tss_sel = ops->get_segment_selector(VCPU_SREG_TR, ctxt->vcpu);
2075 ulong old_tss_base =
5951c442 2076 ops->get_cached_segment_base(VCPU_SREG_TR, ctxt->vcpu);
ceffb459 2077 u32 desc_limit;
38ba30ba
GN		 2078
2079 /* FIXME: old_tss_base == ~0 ? */
2080
2081 ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc);
2082 if (ret != X86EMUL_CONTINUE)
2083 return ret;
2084 ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc);
2085 if (ret != X86EMUL_CONTINUE)
2086 return ret;
2087
2088 /* FIXME: check that next_tss_desc is tss */
2089
2090 if (reason != TASK_SWITCH_IRET) {
2091 if ((tss_selector & 3) > next_tss_desc.dpl ||
35d3d4a1
AK		 2092 ops->cpl(ctxt->vcpu) > next_tss_desc.dpl)
2093 return emulate_gp(ctxt, 0);
38ba30ba
GN		 2094 }
2095
ceffb459
GN		 2096 desc_limit = desc_limit_scaled(&next_tss_desc);
2097 if (!next_tss_desc.p ||
2098 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2099 desc_limit < 0x2b)) {
54b8486f 2100 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2101 return X86EMUL_PROPAGATE_FAULT;
2102 }
2103
2104 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2105 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2106 write_segment_descriptor(ctxt, ops, old_tss_sel,
2107 &curr_tss_desc);
2108 }
2109
2110 if (reason == TASK_SWITCH_IRET)
2111 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2112
2113 /* set back link to prev task only if NT bit is set in eflags
2114 note that old_tss_sel is not used afetr this point */
2115 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2116 old_tss_sel = 0xffff;
2117
2118 if (next_tss_desc.type & 8)
2119 ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel,
2120 old_tss_base, &next_tss_desc);
2121 else
2122 ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel,
2123 old_tss_base, &next_tss_desc);
0760d448
JK		 2124 if (ret != X86EMUL_CONTINUE)
2125 return ret;
38ba30ba
GN		 2126
2127 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2128 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2129
2130 if (reason != TASK_SWITCH_IRET) {
2131 next_tss_desc.type |= (1 << 1); /* set busy flag */
2132 write_segment_descriptor(ctxt, ops, tss_selector,
2133 &next_tss_desc);
2134 }
2135
2136 ops->set_cr(0, ops->get_cr(0, ctxt->vcpu) | X86_CR0_TS, ctxt->vcpu);
5601d05b 2137 ops->set_cached_descriptor(&next_tss_desc, 0, VCPU_SREG_TR, ctxt->vcpu);
38ba30ba
GN		 2138 ops->set_segment_selector(tss_selector, VCPU_SREG_TR, ctxt->vcpu);
2139
e269fb21
JK		 2140 if (has_error_code) {
2141 struct decode_cache *c = &ctxt->decode;
2142
2143 c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2144 c->lock_prefix = 0;
2145 c->src.val = (unsigned long) error_code;
79168fd1 2146 emulate_push(ctxt, ops);
e269fb21
JK		 2147 }
2148
38ba30ba
GN		 2149 return ret;
2150}
2151
2152int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2153 u16 tss_selector, int reason,
2154 bool has_error_code, u32 error_code)
38ba30ba 2155{
9aabc88f 2156 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2157 struct decode_cache *c = &ctxt->decode;
2158 int rc;
2159
38ba30ba 2160 c->eip = ctxt->eip;
e269fb21 2161 c->dst.type = OP_NONE;
38ba30ba 2162
e269fb21
JK		 2163 rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason,
2164 has_error_code, error_code);
38ba30ba
GN		 2165
2166 if (rc == X86EMUL_CONTINUE) {
e269fb21 2167 rc = writeback(ctxt, ops);
95c55886
GN		 2168 if (rc == X86EMUL_CONTINUE)
2169 ctxt->eip = c->eip;
38ba30ba
GN		 2170 }
2171
19d04437 2172 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
38ba30ba
GN		 2173}
2174
90de84f5 2175static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned seg,
d9271123 2176 int reg, struct operand *op)
a682e354
GN		 2177{
2178 struct decode_cache *c = &ctxt->decode;
2179 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2180
d9271123 2181 register_address_increment(c, &c->regs[reg], df * op->bytes);
90de84f5
AK		 2182 op->addr.mem.ea = register_address(c, c->regs[reg]);
2183 op->addr.mem.seg = seg;
a682e354
GN		 2184}
2185
63540382
AK		 2186static int em_push(struct x86_emulate_ctxt *ctxt)
2187{
2188 emulate_push(ctxt, ctxt->ops);
2189 return X86EMUL_CONTINUE;
2190}
2191
7af04fc0
AK		 2192static int em_das(struct x86_emulate_ctxt *ctxt)
2193{
2194 struct decode_cache *c = &ctxt->decode;
2195 u8 al, old_al;
2196 bool af, cf, old_cf;
2197
2198 cf = ctxt->eflags & X86_EFLAGS_CF;
2199 al = c->dst.val;
2200
2201 old_al = al;
2202 old_cf = cf;
2203 cf = false;
2204 af = ctxt->eflags & X86_EFLAGS_AF;
2205 if ((al & 0x0f) > 9 || af) {
2206 al -= 6;
2207 cf = old_cf | (al >= 250);
2208 af = true;
2209 } else {
2210 af = false;
2211 }
2212 if (old_al > 0x99 || old_cf) {
2213 al -= 0x60;
2214 cf = true;
2215 }
2216
2217 c->dst.val = al;
2218 /* Set PF, ZF, SF */
2219 c->src.type = OP_IMM;
2220 c->src.val = 0;
2221 c->src.bytes = 1;
2222 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
2223 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2224 if (cf)
2225 ctxt->eflags |= X86_EFLAGS_CF;
2226 if (af)
2227 ctxt->eflags |= X86_EFLAGS_AF;
2228 return X86EMUL_CONTINUE;
2229}
2230
0ef753b8
AK		 2231static int em_call_far(struct x86_emulate_ctxt *ctxt)
2232{
2233 struct decode_cache *c = &ctxt->decode;
2234 u16 sel, old_cs;
2235 ulong old_eip;
2236 int rc;
2237
2238 old_cs = ctxt->ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2239 old_eip = c->eip;
2240
2241 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
2242 if (load_segment_descriptor(ctxt, ctxt->ops, sel, VCPU_SREG_CS))
2243 return X86EMUL_CONTINUE;
2244
2245 c->eip = 0;
2246 memcpy(&c->eip, c->src.valptr, c->op_bytes);
2247
2248 c->src.val = old_cs;
2249 emulate_push(ctxt, ctxt->ops);
2250 rc = writeback(ctxt, ctxt->ops);
2251 if (rc != X86EMUL_CONTINUE)
2252 return rc;
2253
2254 c->src.val = old_eip;
2255 emulate_push(ctxt, ctxt->ops);
2256 rc = writeback(ctxt, ctxt->ops);
2257 if (rc != X86EMUL_CONTINUE)
2258 return rc;
2259
2260 c->dst.type = OP_NONE;
2261
2262 return X86EMUL_CONTINUE;
2263}
2264
40ece7c7
AK		 2265static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2266{
2267 struct decode_cache *c = &ctxt->decode;
2268 int rc;
2269
2270 c->dst.type = OP_REG;
2271 c->dst.addr.reg = &c->eip;
2272 c->dst.bytes = c->op_bytes;
2273 rc = emulate_pop(ctxt, ctxt->ops, &c->dst.val, c->op_bytes);
2274 if (rc != X86EMUL_CONTINUE)
2275 return rc;
2276 register_address_increment(c, &c->regs[VCPU_REGS_RSP], c->src.val);
2277 return X86EMUL_CONTINUE;
2278}
2279
5c82aa29 2280static int em_imul(struct x86_emulate_ctxt *ctxt)
f3a1b9f4
AK		 2281{
2282 struct decode_cache *c = &ctxt->decode;
2283
f3a1b9f4
AK		 2284 emulate_2op_SrcV_nobyte("imul", c->src, c->dst, ctxt->eflags);
2285 return X86EMUL_CONTINUE;
2286}
2287
5c82aa29
AK		 2288static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2289{
2290 struct decode_cache *c = &ctxt->decode;
2291
2292 c->dst.val = c->src2.val;
2293 return em_imul(ctxt);
2294}
2295
61429142
AK		 2296static int em_cwd(struct x86_emulate_ctxt *ctxt)
2297{
2298 struct decode_cache *c = &ctxt->decode;
2299
2300 c->dst.type = OP_REG;
2301 c->dst.bytes = c->src.bytes;
2302 c->dst.addr.reg = &c->regs[VCPU_REGS_RDX];
2303 c->dst.val = ~((c->src.val >> (c->src.bytes * 8 - 1)) - 1);
2304
2305 return X86EMUL_CONTINUE;
2306}
2307
48bb5d3c
AK		 2308static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2309{
2310 unsigned cpl = ctxt->ops->cpl(ctxt->vcpu);
2311 struct decode_cache *c = &ctxt->decode;
2312 u64 tsc = 0;
2313
35d3d4a1
AK		 2314 if (cpl > 0 && (ctxt->ops->get_cr(4, ctxt->vcpu) & X86_CR4_TSD))
2315 return emulate_gp(ctxt, 0);
48bb5d3c
AK		 2316 ctxt->ops->get_msr(ctxt->vcpu, MSR_IA32_TSC, &tsc);
2317 c->regs[VCPU_REGS_RAX] = (u32)tsc;
2318 c->regs[VCPU_REGS_RDX] = tsc >> 32;
2319 return X86EMUL_CONTINUE;
2320}
2321
b9eac5f4
AK		 2322static int em_mov(struct x86_emulate_ctxt *ctxt)
2323{
2324 struct decode_cache *c = &ctxt->decode;
2325 c->dst.val = c->src.val;
2326 return X86EMUL_CONTINUE;
2327}
2328
73fba5f4
AK		 2329#define D(_y) { .flags = (_y) }
2330#define N D(0)
2331#define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) }
2332#define GD(_f, _g) { .flags = ((_f) | Group | GroupDual), .u.gdual = (_g) }
2333#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
2334
8d8f4e9f
AK		 2335#define D2bv(_f) D((_f) | ByteOp), D(_f)
2336#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
2337
6230f7fc
AK		 2338#define D6ALU(_f) D2bv((_f) | DstMem | SrcReg | ModRM), \
2339 D2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock), \
2340 D2bv(((_f) & ~Lock) | DstAcc | SrcImm)
2341
2342
73fba5f4
AK		 2343static struct opcode group1[] = {
2344 X7(D(Lock)), N
2345};
2346
2347static struct opcode group1A[] = {
2348 D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N,
2349};
2350
2351static struct opcode group3[] = {
2352 D(DstMem | SrcImm | ModRM), D(DstMem | SrcImm | ModRM),
2353 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
3f9f53b0 2354 X4(D(SrcMem | ModRM)),
73fba5f4
AK		 2355};
2356
2357static struct opcode group4[] = {
2358 D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock),
2359 N, N, N, N, N, N,
2360};
2361
2362static struct opcode group5[] = {
2363 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
0ef753b8
AK		 2364 D(SrcMem | ModRM | Stack),
2365 I(SrcMemFAddr | ModRM | ImplicitOps | Stack, em_call_far),
73fba5f4
AK		 2366 D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps),
2367 D(SrcMem | ModRM | Stack), N,
2368};
2369
2370static struct group_dual group7 = { {
2371 N, N, D(ModRM | SrcMem | Priv), D(ModRM | SrcMem | Priv),
2372 D(SrcNone | ModRM | DstMem | Mov), N,
5a506b12
AK		 2373 D(SrcMem16 | ModRM | Mov | Priv),
2374 D(SrcMem | ModRM | ByteOp | Priv | NoAccess),
73fba5f4 2375}, {
d867162c
AK		 2376 D(SrcNone | ModRM | Priv | VendorSpecific), N,
2377 N, D(SrcNone | ModRM | Priv | VendorSpecific),
73fba5f4
AK		 2378 D(SrcNone | ModRM | DstMem | Mov), N,
2379 D(SrcMem16 | ModRM | Mov | Priv), N,
2380} };
2381
2382static struct opcode group8[] = {
2383 N, N, N, N,
2384 D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock),
2385 D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock),
2386};
2387
2388static struct group_dual group9 = { {
2389 N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N,
2390}, {
2391 N, N, N, N, N, N, N, N,
2392} };
2393
a4d4a7c1
AK		 2394static struct opcode group11[] = {
2395 I(DstMem | SrcImm | ModRM | Mov, em_mov), X7(D(Undefined)),
2396};
2397
73fba5f4
AK		 2398static struct opcode opcode_table[256] = {
2399 /* 0x00 - 0x07 */
6230f7fc 2400 D6ALU(Lock),
73fba5f4
AK		 2401 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2402 /* 0x08 - 0x0F */
6230f7fc 2403 D6ALU(Lock),
73fba5f4
AK		 2404 D(ImplicitOps | Stack | No64), N,
2405 /* 0x10 - 0x17 */
6230f7fc 2406 D6ALU(Lock),
73fba5f4
AK		 2407 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2408 /* 0x18 - 0x1F */
6230f7fc 2409 D6ALU(Lock),
73fba5f4
AK		 2410 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2411 /* 0x20 - 0x27 */
6230f7fc 2412 D6ALU(Lock), N, N,
73fba5f4 2413 /* 0x28 - 0x2F */
6230f7fc 2414 D6ALU(Lock), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 2415 /* 0x30 - 0x37 */
6230f7fc 2416 D6ALU(Lock), N, N,
73fba5f4 2417 /* 0x38 - 0x3F */
6230f7fc 2418 D6ALU(0), N, N,
73fba5f4
AK		 2419 /* 0x40 - 0x4F */
2420 X16(D(DstReg)),
2421 /* 0x50 - 0x57 */
63540382 2422 X8(I(SrcReg | Stack, em_push)),
73fba5f4
AK		 2423 /* 0x58 - 0x5F */
2424 X8(D(DstReg | Stack)),
2425 /* 0x60 - 0x67 */
2426 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2427 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
2428 N, N, N, N,
2429 /* 0x68 - 0x6F */
d46164db
AK		 2430 I(SrcImm | Mov | Stack, em_push),
2431 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 2432 I(SrcImmByte | Mov | Stack, em_push),
2433 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
48fe67b5
AK		 2434 D2bv(DstDI | Mov | String), /* insb, insw/insd */
2435 D2bv(SrcSI | ImplicitOps | String), /* outsb, outsw/outsd */
73fba5f4
AK		 2436 /* 0x70 - 0x7F */
2437 X16(D(SrcImmByte)),
2438 /* 0x80 - 0x87 */
2439 G(ByteOp | DstMem | SrcImm | ModRM | Group, group1),
2440 G(DstMem | SrcImm | ModRM | Group, group1),
2441 G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1),
2442 G(DstMem | SrcImmByte | ModRM | Group, group1),
76e8e68d 2443 D2bv(DstMem | SrcReg | ModRM), D2bv(DstMem | SrcReg | ModRM | Lock),
73fba5f4 2444 /* 0x88 - 0x8F */
b9eac5f4
AK		 2445 I2bv(DstMem | SrcReg | ModRM | Mov, em_mov),
2446 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
342fc630 2447 D(DstMem | SrcNone | ModRM | Mov), D(ModRM | SrcMem | NoAccess | DstReg),
73fba5f4
AK		 2448 D(ImplicitOps | SrcMem16 | ModRM), G(0, group1A),
2449 /* 0x90 - 0x97 */
3d9e77df 2450 X8(D(SrcAcc | DstReg)),
73fba5f4 2451 /* 0x98 - 0x9F */
61429142 2452 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 2453 I(SrcImmFAddr | No64, em_call_far), N,
73fba5f4
AK		 2454 D(ImplicitOps | Stack), D(ImplicitOps | Stack), N, N,
2455 /* 0xA0 - 0xA7 */
b9eac5f4
AK		 2456 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
2457 I2bv(DstMem | SrcAcc | Mov | MemAbs, em_mov),
2458 I2bv(SrcSI | DstDI | Mov | String, em_mov),
2459 D2bv(SrcSI | DstDI | String),
73fba5f4 2460 /* 0xA8 - 0xAF */
50748613 2461 D2bv(DstAcc | SrcImm),
b9eac5f4
AK		 2462 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
2463 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
48fe67b5 2464 D2bv(SrcAcc | DstDI | String),
73fba5f4 2465 /* 0xB0 - 0xB7 */
b9eac5f4 2466 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 2467 /* 0xB8 - 0xBF */
b9eac5f4 2468 X8(I(DstReg | SrcImm | Mov, em_mov)),
73fba5f4 2469 /* 0xC0 - 0xC7 */
d2c6c7ad 2470 D2bv(DstMem | SrcImmByte | ModRM),
40ece7c7
AK		 2471 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
2472 D(ImplicitOps | Stack),
09b5f4d3 2473 D(DstReg | SrcMemFAddr | ModRM | No64), D(DstReg | SrcMemFAddr | ModRM | No64),
a4d4a7c1 2474 G(ByteOp, group11), G(0, group11),
73fba5f4
AK		 2475 /* 0xC8 - 0xCF */
2476 N, N, N, D(ImplicitOps | Stack),
2477 D(ImplicitOps), D(SrcImmByte), D(ImplicitOps | No64), D(ImplicitOps),
2478 /* 0xD0 - 0xD7 */
d2c6c7ad 2479 D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM),
73fba5f4
AK		 2480 N, N, N, N,
2481 /* 0xD8 - 0xDF */
2482 N, N, N, N, N, N, N, N,
2483 /* 0xE0 - 0xE7 */
e4abac67 2484 X4(D(SrcImmByte)),
d269e396 2485 D2bv(SrcImmUByte | DstAcc), D2bv(SrcAcc | DstImmUByte),
73fba5f4
AK		 2486 /* 0xE8 - 0xEF */
2487 D(SrcImm | Stack), D(SrcImm | ImplicitOps),
2488 D(SrcImmFAddr | No64), D(SrcImmByte | ImplicitOps),
d269e396 2489 D2bv(SrcNone | DstAcc), D2bv(SrcAcc | ImplicitOps),
73fba5f4
AK		 2490 /* 0xF0 - 0xF7 */
2491 N, N, N, N,
2492 D(ImplicitOps | Priv), D(ImplicitOps), G(ByteOp, group3), G(0, group3),
2493 /* 0xF8 - 0xFF */
8744aa9a 2494 D(ImplicitOps), D(ImplicitOps), D(ImplicitOps), D(ImplicitOps),
73fba5f4
AK		 2495 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
2496};
2497
2498static struct opcode twobyte_table[256] = {
2499 /* 0x00 - 0x0F */
2500 N, GD(0, &group7), N, N,
d867162c 2501 N, D(ImplicitOps | VendorSpecific), D(ImplicitOps | Priv), N,
73fba5f4
AK		 2502 D(ImplicitOps | Priv), D(ImplicitOps | Priv), N, N,
2503 N, D(ImplicitOps | ModRM), N, N,
2504 /* 0x10 - 0x1F */
2505 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
2506 /* 0x20 - 0x2F */
b27f3856
AK		 2507 D(ModRM | DstMem | Priv | Op3264), D(ModRM | DstMem | Priv | Op3264),
2508 D(ModRM | SrcMem | Priv | Op3264), D(ModRM | SrcMem | Priv | Op3264),
73fba5f4
AK		 2509 N, N, N, N,
2510 N, N, N, N, N, N, N, N,
2511 /* 0x30 - 0x3F */
48bb5d3c
AK		 2512 D(ImplicitOps | Priv), I(ImplicitOps, em_rdtsc),
2513 D(ImplicitOps | Priv), N,
d867162c
AK		 2514 D(ImplicitOps | VendorSpecific), D(ImplicitOps | Priv | VendorSpecific),
2515 N, N,
73fba5f4
AK		 2516 N, N, N, N, N, N, N, N,
2517 /* 0x40 - 0x4F */
2518 X16(D(DstReg | SrcMem | ModRM | Mov)),
2519 /* 0x50 - 0x5F */
2520 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2521 /* 0x60 - 0x6F */
2522 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2523 /* 0x70 - 0x7F */
2524 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2525 /* 0x80 - 0x8F */
2526 X16(D(SrcImm)),
2527 /* 0x90 - 0x9F */
ee45b58e 2528 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4
AK		 2529 /* 0xA0 - 0xA7 */
2530 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
2531 N, D(DstMem | SrcReg | ModRM | BitOp),
2532 D(DstMem | SrcReg | Src2ImmByte | ModRM),
2533 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
2534 /* 0xA8 - 0xAF */
2535 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
2536 N, D(DstMem | SrcReg | ModRM | BitOp | Lock),
2537 D(DstMem | SrcReg | Src2ImmByte | ModRM),
2538 D(DstMem | SrcReg | Src2CL | ModRM),
5c82aa29 2539 D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 2540 /* 0xB0 - 0xB7 */
739ae406 2541 D2bv(DstMem | SrcReg | ModRM | Lock),
09b5f4d3
WY		 2542 D(DstReg | SrcMemFAddr | ModRM), D(DstMem | SrcReg | ModRM | BitOp | Lock),
2543 D(DstReg | SrcMemFAddr | ModRM), D(DstReg | SrcMemFAddr | ModRM),
2544 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 2545 /* 0xB8 - 0xBF */
2546 N, N,
ba7ff2b7 2547 G(BitOp, group8), D(DstMem | SrcReg | ModRM | BitOp | Lock),
d9574a25
WY		 2548 D(DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2549 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4 2550 /* 0xC0 - 0xCF */
739ae406 2551 D2bv(DstMem | SrcReg | ModRM | Lock),
92f738a5 2552 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4
AK		 2553 N, N, N, GD(0, &group9),
2554 N, N, N, N, N, N, N, N,
2555 /* 0xD0 - 0xDF */
2556 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2557 /* 0xE0 - 0xEF */
2558 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2559 /* 0xF0 - 0xFF */
2560 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
2561};
2562
2563#undef D
2564#undef N
2565#undef G
2566#undef GD
2567#undef I
2568
8d8f4e9f
AK		 2569#undef D2bv
2570#undef I2bv
6230f7fc 2571#undef D6ALU
8d8f4e9f 2572
39f21ee5
AK		 2573static unsigned imm_size(struct decode_cache *c)
2574{
2575 unsigned size;
2576
2577 size = (c->d & ByteOp) ? 1 : c->op_bytes;
2578 if (size == 8)
2579 size = 4;
2580 return size;
2581}
2582
2583static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
2584 unsigned size, bool sign_extension)
2585{
2586 struct decode_cache *c = &ctxt->decode;
2587 struct x86_emulate_ops *ops = ctxt->ops;
2588 int rc = X86EMUL_CONTINUE;
2589
2590 op->type = OP_IMM;
2591 op->bytes = size;
90de84f5 2592 op->addr.mem.ea = c->eip;
39f21ee5
AK		 2593 /* NB. Immediates are sign-extended as necessary. */
2594 switch (op->bytes) {
2595 case 1:
2596 op->val = insn_fetch(s8, 1, c->eip);
2597 break;
2598 case 2:
2599 op->val = insn_fetch(s16, 2, c->eip);
2600 break;
2601 case 4:
2602 op->val = insn_fetch(s32, 4, c->eip);
2603 break;
2604 }
2605 if (!sign_extension) {
2606 switch (op->bytes) {
2607 case 1:
2608 op->val &= 0xff;
2609 break;
2610 case 2:
2611 op->val &= 0xffff;
2612 break;
2613 case 4:
2614 op->val &= 0xffffffff;
2615 break;
2616 }
2617 }
2618done:
2619 return rc;
2620}
2621
dde7e6d1 2622int
dc25e89e 2623x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1
AK		 2624{
2625 struct x86_emulate_ops *ops = ctxt->ops;
2626 struct decode_cache *c = &ctxt->decode;
2627 int rc = X86EMUL_CONTINUE;
2628 int mode = ctxt->mode;
2629 int def_op_bytes, def_ad_bytes, dual, goffset;
2630 struct opcode opcode, *g_mod012, *g_mod3;
2dbd0dd7 2631 struct operand memop = { .type = OP_NONE };
dde7e6d1 2632
dde7e6d1 2633 c->eip = ctxt->eip;
dc25e89e
AP		 2634 c->fetch.start = c->eip;
2635 c->fetch.end = c->fetch.start + insn_len;
2636 if (insn_len > 0)
2637 memcpy(c->fetch.data, insn, insn_len);
dde7e6d1
AK		 2638 ctxt->cs_base = seg_base(ctxt, ops, VCPU_SREG_CS);
2639
2640 switch (mode) {
2641 case X86EMUL_MODE_REAL:
2642 case X86EMUL_MODE_VM86:
2643 case X86EMUL_MODE_PROT16:
2644 def_op_bytes = def_ad_bytes = 2;
2645 break;
2646 case X86EMUL_MODE_PROT32:
2647 def_op_bytes = def_ad_bytes = 4;
2648 break;
2649#ifdef CONFIG_X86_64
2650 case X86EMUL_MODE_PROT64:
2651 def_op_bytes = 4;
2652 def_ad_bytes = 8;
2653 break;
2654#endif
2655 default:
2656 return -1;
2657 }
2658
2659 c->op_bytes = def_op_bytes;
2660 c->ad_bytes = def_ad_bytes;
2661
2662 /* Legacy prefixes. */
2663 for (;;) {
2664 switch (c->b = insn_fetch(u8, 1, c->eip)) {
2665 case 0x66: /* operand-size override */
2666 /* switch between 2/4 bytes */
2667 c->op_bytes = def_op_bytes ^ 6;
2668 break;
2669 case 0x67: /* address-size override */
2670 if (mode == X86EMUL_MODE_PROT64)
2671 /* switch between 4/8 bytes */
2672 c->ad_bytes = def_ad_bytes ^ 12;
2673 else
2674 /* switch between 2/4 bytes */
2675 c->ad_bytes = def_ad_bytes ^ 6;
2676 break;
2677 case 0x26: /* ES override */
2678 case 0x2e: /* CS override */
2679 case 0x36: /* SS override */
2680 case 0x3e: /* DS override */
2681 set_seg_override(c, (c->b >> 3) & 3);
2682 break;
2683 case 0x64: /* FS override */
2684 case 0x65: /* GS override */
2685 set_seg_override(c, c->b & 7);
2686 break;
2687 case 0x40 ... 0x4f: /* REX */
2688 if (mode != X86EMUL_MODE_PROT64)
2689 goto done_prefixes;
2690 c->rex_prefix = c->b;
2691 continue;
2692 case 0xf0: /* LOCK */
2693 c->lock_prefix = 1;
2694 break;
2695 case 0xf2: /* REPNE/REPNZ */
2696 c->rep_prefix = REPNE_PREFIX;
2697 break;
2698 case 0xf3: /* REP/REPE/REPZ */
2699 c->rep_prefix = REPE_PREFIX;
2700 break;
2701 default:
2702 goto done_prefixes;
2703 }
2704
2705 /* Any legacy prefix after a REX prefix nullifies its effect. */
2706
2707 c->rex_prefix = 0;
2708 }
2709
2710done_prefixes:
2711
2712 /* REX prefix. */
1e87e3ef
AK		 2713 if (c->rex_prefix & 8)
2714 c->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 2715
2716 /* Opcode byte(s). */
2717 opcode = opcode_table[c->b];
d3ad6243
WY		 2718 /* Two-byte opcode? */
2719 if (c->b == 0x0f) {
2720 c->twobyte = 1;
2721 c->b = insn_fetch(u8, 1, c->eip);
2722 opcode = twobyte_table[c->b];
dde7e6d1
AK		 2723 }
2724 c->d = opcode.flags;
2725
2726 if (c->d & Group) {
2727 dual = c->d & GroupDual;
2728 c->modrm = insn_fetch(u8, 1, c->eip);
2729 --c->eip;
2730
2731 if (c->d & GroupDual) {
2732 g_mod012 = opcode.u.gdual->mod012;
2733 g_mod3 = opcode.u.gdual->mod3;
2734 } else
2735 g_mod012 = g_mod3 = opcode.u.group;
2736
2737 c->d &= ~(Group | GroupDual);
2738
2739 goffset = (c->modrm >> 3) & 7;
2740
2741 if ((c->modrm >> 6) == 3)
2742 opcode = g_mod3[goffset];
2743 else
2744 opcode = g_mod012[goffset];
2745 c->d |= opcode.flags;
2746 }
2747
2748 c->execute = opcode.u.execute;
2749
2750 /* Unrecognised? */
d53db5ef 2751 if (c->d == 0 || (c->d & Undefined))
dde7e6d1 2752 return -1;
dde7e6d1 2753
d867162c
AK		 2754 if (!(c->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
2755 return -1;
2756
dde7e6d1
AK		 2757 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
2758 c->op_bytes = 8;
2759
7f9b4b75
AK		 2760 if (c->d & Op3264) {
2761 if (mode == X86EMUL_MODE_PROT64)
2762 c->op_bytes = 8;
2763 else
2764 c->op_bytes = 4;
2765 }
2766
dde7e6d1 2767 /* ModRM and SIB bytes. */
09ee57cd 2768 if (c->d & ModRM) {
2dbd0dd7 2769 rc = decode_modrm(ctxt, ops, &memop);
09ee57cd
AK		 2770 if (!c->has_seg_override)
2771 set_seg_override(c, c->modrm_seg);
2772 } else if (c->d & MemAbs)
2dbd0dd7 2773 rc = decode_abs(ctxt, ops, &memop);
dde7e6d1
AK		 2774 if (rc != X86EMUL_CONTINUE)
2775 goto done;
2776
2777 if (!c->has_seg_override)
2778 set_seg_override(c, VCPU_SREG_DS);
2779
90de84f5 2780 memop.addr.mem.seg = seg_override(ctxt, ops, c);
dde7e6d1 2781
2dbd0dd7 2782 if (memop.type == OP_MEM && c->ad_bytes != 8)
90de84f5 2783 memop.addr.mem.ea = (u32)memop.addr.mem.ea;
dde7e6d1 2784
2dbd0dd7 2785 if (memop.type == OP_MEM && c->rip_relative)
90de84f5 2786 memop.addr.mem.ea += c->eip;
dde7e6d1
AK		 2787
2788 /*
2789 * Decode and fetch the source operand: register, memory
2790 * or immediate.
2791 */
2792 switch (c->d & SrcMask) {
2793 case SrcNone:
2794 break;
2795 case SrcReg:
2796 decode_register_operand(&c->src, c, 0);
2797 break;
2798 case SrcMem16:
2dbd0dd7 2799 memop.bytes = 2;
dde7e6d1
AK		 2800 goto srcmem_common;
2801 case SrcMem32:
2dbd0dd7 2802 memop.bytes = 4;
dde7e6d1
AK		 2803 goto srcmem_common;
2804 case SrcMem:
2dbd0dd7 2805 memop.bytes = (c->d & ByteOp) ? 1 :
dde7e6d1 2806 c->op_bytes;
dde7e6d1 2807 srcmem_common:
2dbd0dd7 2808 c->src = memop;
dde7e6d1 2809 break;
b250e605 2810 case SrcImmU16:
39f21ee5
AK		 2811 rc = decode_imm(ctxt, &c->src, 2, false);
2812 break;
dde7e6d1 2813 case SrcImm:
39f21ee5
AK		 2814 rc = decode_imm(ctxt, &c->src, imm_size(c), true);
2815 break;
dde7e6d1 2816 case SrcImmU:
39f21ee5 2817 rc = decode_imm(ctxt, &c->src, imm_size(c), false);
dde7e6d1
AK		 2818 break;
2819 case SrcImmByte:
39f21ee5
AK		 2820 rc = decode_imm(ctxt, &c->src, 1, true);
2821 break;
dde7e6d1 2822 case SrcImmUByte:
39f21ee5 2823 rc = decode_imm(ctxt, &c->src, 1, false);
dde7e6d1
AK		 2824 break;
2825 case SrcAcc:
2826 c->src.type = OP_REG;
2827 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1a6440ae 2828 c->src.addr.reg = &c->regs[VCPU_REGS_RAX];
91ff3cb4 2829 fetch_register_operand(&c->src);
dde7e6d1
AK		 2830 break;
2831 case SrcOne:
2832 c->src.bytes = 1;
2833 c->src.val = 1;
2834 break;
2835 case SrcSI:
2836 c->src.type = OP_MEM;
2837 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
90de84f5
AK		 2838 c->src.addr.mem.ea =
2839 register_address(c, c->regs[VCPU_REGS_RSI]);
2840 c->src.addr.mem.seg = seg_override(ctxt, ops, c),
dde7e6d1
AK		 2841 c->src.val = 0;
2842 break;
2843 case SrcImmFAddr:
2844 c->src.type = OP_IMM;
90de84f5 2845 c->src.addr.mem.ea = c->eip;
dde7e6d1
AK		 2846 c->src.bytes = c->op_bytes + 2;
2847 insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip);
2848 break;
2849 case SrcMemFAddr:
2dbd0dd7
AK		 2850 memop.bytes = c->op_bytes + 2;
2851 goto srcmem_common;
dde7e6d1
AK		 2852 break;
2853 }
2854
39f21ee5
AK		 2855 if (rc != X86EMUL_CONTINUE)
2856 goto done;
2857
dde7e6d1
AK		 2858 /*
2859 * Decode and fetch the second source operand: register, memory
2860 * or immediate.
2861 */
2862 switch (c->d & Src2Mask) {
2863 case Src2None:
2864 break;
2865 case Src2CL:
2866 c->src2.bytes = 1;
2867 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
2868 break;
2869 case Src2ImmByte:
39f21ee5 2870 rc = decode_imm(ctxt, &c->src2, 1, true);
dde7e6d1
AK		 2871 break;
2872 case Src2One:
2873 c->src2.bytes = 1;
2874 c->src2.val = 1;
2875 break;
7db41eb7
AK		 2876 case Src2Imm:
2877 rc = decode_imm(ctxt, &c->src2, imm_size(c), true);
2878 break;
dde7e6d1
AK		 2879 }
2880
39f21ee5
AK		 2881 if (rc != X86EMUL_CONTINUE)
2882 goto done;
2883
dde7e6d1
AK		 2884 /* Decode and fetch the destination operand: register or memory. */
2885 switch (c->d & DstMask) {
dde7e6d1
AK		 2886 case DstReg:
2887 decode_register_operand(&c->dst, c,
2888 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
2889 break;
943858e2
WY		 2890 case DstImmUByte:
2891 c->dst.type = OP_IMM;
90de84f5 2892 c->dst.addr.mem.ea = c->eip;
943858e2
WY		 2893 c->dst.bytes = 1;
2894 c->dst.val = insn_fetch(u8, 1, c->eip);
2895 break;
dde7e6d1
AK		 2896 case DstMem:
2897 case DstMem64:
2dbd0dd7 2898 c->dst = memop;
dde7e6d1
AK		 2899 if ((c->d & DstMask) == DstMem64)
2900 c->dst.bytes = 8;
2901 else
2902 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
35c843c4
WY		 2903 if (c->d & BitOp)
2904 fetch_bit_operand(c);
2dbd0dd7 2905 c->dst.orig_val = c->dst.val;
dde7e6d1
AK		 2906 break;
2907 case DstAcc:
2908 c->dst.type = OP_REG;
2909 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1a6440ae 2910 c->dst.addr.reg = &c->regs[VCPU_REGS_RAX];
91ff3cb4 2911 fetch_register_operand(&c->dst);
dde7e6d1
AK		 2912 c->dst.orig_val = c->dst.val;
2913 break;
2914 case DstDI:
2915 c->dst.type = OP_MEM;
2916 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
90de84f5
AK		 2917 c->dst.addr.mem.ea =
2918 register_address(c, c->regs[VCPU_REGS_RDI]);
2919 c->dst.addr.mem.seg = VCPU_SREG_ES;
dde7e6d1
AK		 2920 c->dst.val = 0;
2921 break;
36089fed
WY		 2922 case ImplicitOps:
2923 /* Special instructions do their own operand decoding. */
2924 default:
2925 c->dst.type = OP_NONE; /* Disable writeback. */
2926 return 0;
dde7e6d1
AK		 2927 }
2928
2929done:
2930 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
2931}
2932
3e2f65d5
GN		 2933static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
2934{
2935 struct decode_cache *c = &ctxt->decode;
2936
2937 /* The second termination condition only applies for REPE
2938 * and REPNE. Test if the repeat string operation prefix is
2939 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
2940 * corresponding termination condition according to:
2941 * - if REPE/REPZ and ZF = 0 then done
2942 * - if REPNE/REPNZ and ZF = 1 then done
2943 */
2944 if (((c->b == 0xa6) || (c->b == 0xa7) ||
2945 (c->b == 0xae) || (c->b == 0xaf))
2946 && (((c->rep_prefix == REPE_PREFIX) &&
2947 ((ctxt->eflags & EFLG_ZF) == 0))
2948 || ((c->rep_prefix == REPNE_PREFIX) &&
2949 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
2950 return true;
2951
2952 return false;
2953}
2954
8b4caf66 2955int
9aabc88f 2956x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 2957{
9aabc88f 2958 struct x86_emulate_ops *ops = ctxt->ops;
8b4caf66 2959 u64 msr_data;
8b4caf66 2960 struct decode_cache *c = &ctxt->decode;
1b30eaa8 2961 int rc = X86EMUL_CONTINUE;
5cd21917 2962 int saved_dst_type = c->dst.type;
6e154e56 2963 int irq; /* Used for int 3, int, and into */
8b4caf66 2964
9de41573 2965 ctxt->decode.mem_read.pos = 0;
310b5d30 2966
1161624f 2967 if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
35d3d4a1 2968 rc = emulate_ud(ctxt);
1161624f
GN		 2969 goto done;
2970 }
2971
d380a5e4 2972 /* LOCK prefix is allowed only with some instructions */
a41ffb75 2973 if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) {
35d3d4a1 2974 rc = emulate_ud(ctxt);
d380a5e4
GN		 2975 goto done;
2976 }
2977
081bca0e 2978 if ((c->d & SrcMask) == SrcMemFAddr && c->src.type != OP_MEM) {
35d3d4a1 2979 rc = emulate_ud(ctxt);
081bca0e
AK		 2980 goto done;
2981 }
2982
e92805ac 2983 /* Privileged instruction can be executed only in CPL=0 */
9c537244 2984 if ((c->d & Priv) && ops->cpl(ctxt->vcpu)) {
35d3d4a1 2985 rc = emulate_gp(ctxt, 0);
e92805ac
GN		 2986 goto done;
2987 }
2988
b9fa9d6b
AK		 2989 if (c->rep_prefix && (c->d & String)) {
2990 /* All REP prefixes have the same first termination condition */
c73e197b 2991 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) {
95c55886 2992 ctxt->eip = c->eip;
b9fa9d6b
AK		 2993 goto done;
2994 }
b9fa9d6b
AK		 2995 }
2996
c483c02a 2997 if ((c->src.type == OP_MEM) && !(c->d & NoAccess)) {
90de84f5 2998 rc = read_emulated(ctxt, ops, linear(ctxt, c->src.addr.mem),
414e6277 2999 c->src.valptr, c->src.bytes);
b60d513c 3000 if (rc != X86EMUL_CONTINUE)
8b4caf66 3001 goto done;
16518d5a 3002 c->src.orig_val64 = c->src.val64;
8b4caf66
LV		 3003 }
3004
e35b7b9c 3005 if (c->src2.type == OP_MEM) {
90de84f5 3006 rc = read_emulated(ctxt, ops, linear(ctxt, c->src2.addr.mem),
9de41573 3007 &c->src2.val, c->src2.bytes);
e35b7b9c
GN		 3008 if (rc != X86EMUL_CONTINUE)
3009 goto done;
3010 }
3011
8b4caf66
LV		 3012 if ((c->d & DstMask) == ImplicitOps)
3013 goto special_insn;
3014
3015
69f55cb1
GN		 3016 if ((c->dst.type == OP_MEM) && !(c->d & Mov)) {
3017 /* optimisation - avoid slow emulated read if Mov */
90de84f5 3018 rc = read_emulated(ctxt, ops, linear(ctxt, c->dst.addr.mem),
9de41573 3019 &c->dst.val, c->dst.bytes);
69f55cb1
GN		 3020 if (rc != X86EMUL_CONTINUE)
3021 goto done;
038e51de 3022 }
e4e03ded 3023 c->dst.orig_val = c->dst.val;
038e51de 3024
018a98db
AK		 3025special_insn:
3026
ef65c889
AK		 3027 if (c->execute) {
3028 rc = c->execute(ctxt);
3029 if (rc != X86EMUL_CONTINUE)
3030 goto done;
3031 goto writeback;
3032 }
3033
e4e03ded 3034 if (c->twobyte)
6aa8b732
AK		 3035 goto twobyte_insn;
3036
e4e03ded 3037 switch (c->b) {
6aa8b732
AK		 3038 case 0x00 ... 0x05:
3039 add: /* add */
05f086f8 3040 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
6aa8b732 3041 break;
0934ac9d 3042 case 0x06: /* push es */
79168fd1 3043 emulate_push_sreg(ctxt, ops, VCPU_SREG_ES);
0934ac9d
MG		 3044 break;
3045 case 0x07: /* pop es */
0934ac9d 3046 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
0934ac9d 3047 break;
6aa8b732
AK		 3048 case 0x08 ... 0x0d:
3049 or: /* or */
05f086f8 3050 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
6aa8b732 3051 break;
0934ac9d 3052 case 0x0e: /* push cs */
79168fd1 3053 emulate_push_sreg(ctxt, ops, VCPU_SREG_CS);
0934ac9d 3054 break;
6aa8b732
AK		 3055 case 0x10 ... 0x15:
3056 adc: /* adc */
05f086f8 3057 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
6aa8b732 3058 break;
0934ac9d 3059 case 0x16: /* push ss */
79168fd1 3060 emulate_push_sreg(ctxt, ops, VCPU_SREG_SS);
0934ac9d
MG		 3061 break;
3062 case 0x17: /* pop ss */
0934ac9d 3063 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
0934ac9d 3064 break;
6aa8b732
AK		 3065 case 0x18 ... 0x1d:
3066 sbb: /* sbb */
05f086f8 3067 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
6aa8b732 3068 break;
0934ac9d 3069 case 0x1e: /* push ds */
79168fd1 3070 emulate_push_sreg(ctxt, ops, VCPU_SREG_DS);
0934ac9d
MG		 3071 break;
3072 case 0x1f: /* pop ds */
0934ac9d 3073 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
0934ac9d 3074 break;
aa3a816b 3075 case 0x20 ... 0x25:
6aa8b732 3076 and: /* and */
05f086f8 3077 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 3078 break;
3079 case 0x28 ... 0x2d:
3080 sub: /* sub */
05f086f8 3081 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 3082 break;
3083 case 0x30 ... 0x35:
3084 xor: /* xor */
05f086f8 3085 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 3086 break;
3087 case 0x38 ... 0x3d:
3088 cmp: /* cmp */
05f086f8 3089 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
6aa8b732 3090 break;
33615aa9
AK		 3091 case 0x40 ... 0x47: /* inc r16/r32 */
3092 emulate_1op("inc", c->dst, ctxt->eflags);
3093 break;
3094 case 0x48 ... 0x4f: /* dec r16/r32 */
3095 emulate_1op("dec", c->dst, ctxt->eflags);
3096 break;
33615aa9
AK		 3097 case 0x58 ... 0x5f: /* pop reg */
3098 pop_instruction:
350f69dc 3099 rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes);
33615aa9 3100 break;
abcf14b5 3101 case 0x60: /* pusha */
c37eda13 3102 rc = emulate_pusha(ctxt, ops);
abcf14b5
MG		 3103 break;
3104 case 0x61: /* popa */
3105 rc = emulate_popa(ctxt, ops);
abcf14b5 3106 break;
6aa8b732 3107 case 0x63: /* movsxd */
8b4caf66 3108 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 3109 goto cannot_emulate;
e4e03ded 3110 c->dst.val = (s32) c->src.val;
6aa8b732 3111 break;
018a98db
AK		 3112 case 0x6c: /* insb */
3113 case 0x6d: /* insw/insd */
a13a63fa
WY		 3114 c->src.val = c->regs[VCPU_REGS_RDX];
3115 goto do_io_in;
018a98db
AK		 3116 case 0x6e: /* outsb */
3117 case 0x6f: /* outsw/outsd */
a13a63fa
WY		 3118 c->dst.val = c->regs[VCPU_REGS_RDX];
3119 goto do_io_out;
7972995b 3120 break;
b2833e3c 3121 case 0x70 ... 0x7f: /* jcc (short) */
018a98db 3122 if (test_cc(c->b, ctxt->eflags))
b2833e3c 3123 jmp_rel(c, c->src.val);
018a98db 3124 break;
6aa8b732 3125 case 0x80 ... 0x83: /* Grp1 */
e4e03ded 3126 switch (c->modrm_reg) {
6aa8b732
AK		 3127 case 0:
3128 goto add;
3129 case 1:
3130 goto or;
3131 case 2:
3132 goto adc;
3133 case 3:
3134 goto sbb;
3135 case 4:
3136 goto and;
3137 case 5:
3138 goto sub;
3139 case 6:
3140 goto xor;
3141 case 7:
3142 goto cmp;
3143 }
3144 break;
3145 case 0x84 ... 0x85:
dfb507c4 3146 test:
05f086f8 3147 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 3148 break;
3149 case 0x86 ... 0x87: /* xchg */
b13354f8 3150 xchg:
6aa8b732 3151 /* Write back the register source. */
31be40b3
WY		 3152 c->src.val = c->dst.val;
3153 write_register_operand(&c->src);
6aa8b732
AK		 3154 /*
3155 * Write back the memory destination with implicit LOCK
3156 * prefix.
3157 */
31be40b3 3158 c->dst.val = c->src.orig_val;
e4e03ded 3159 c->lock_prefix = 1;
6aa8b732 3160 break;
79168fd1
GN		 3161 case 0x8c: /* mov r/m, sreg */
3162 if (c->modrm_reg > VCPU_SREG_GS) {
35d3d4a1 3163 rc = emulate_ud(ctxt);
5e3ae6c5 3164 goto done;
38d5bc6d 3165 }
79168fd1 3166 c->dst.val = ops->get_segment_selector(c->modrm_reg, ctxt->vcpu);
38d5bc6d 3167 break;
7e0b54b1 3168 case 0x8d: /* lea r16/r32, m */
90de84f5 3169 c->dst.val = c->src.addr.mem.ea;
7e0b54b1 3170 break;
4257198a
GT		 3171 case 0x8e: { /* mov seg, r/m16 */
3172 uint16_t sel;
4257198a
GT		 3173
3174 sel = c->src.val;
8b9f4414 3175
c697518a
GN		 3176 if (c->modrm_reg == VCPU_SREG_CS ||
3177 c->modrm_reg > VCPU_SREG_GS) {
35d3d4a1 3178 rc = emulate_ud(ctxt);
8b9f4414
GN		 3179 goto done;
3180 }
3181
310b5d30 3182 if (c->modrm_reg == VCPU_SREG_SS)
95cb2295 3183 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
310b5d30 3184
2e873022 3185 rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg);
4257198a
GT		 3186
3187 c->dst.type = OP_NONE; /* Disable writeback. */
3188 break;
3189 }
6aa8b732 3190 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9 3191 rc = emulate_grp1a(ctxt, ops);
6aa8b732 3192 break;
3d9e77df
AK		 3193 case 0x90 ... 0x97: /* nop / xchg reg, rax */
3194 if (c->dst.addr.reg == &c->regs[VCPU_REGS_RAX])
34698d8c 3195 break;
b13354f8 3196 goto xchg;
e8b6fa70
WY		 3197 case 0x98: /* cbw/cwde/cdqe */
3198 switch (c->op_bytes) {
3199 case 2: c->dst.val = (s8)c->dst.val; break;
3200 case 4: c->dst.val = (s16)c->dst.val; break;
3201 case 8: c->dst.val = (s32)c->dst.val; break;
3202 }
3203 break;
fd2a7608 3204 case 0x9c: /* pushf */
05f086f8 3205 c->src.val = (unsigned long) ctxt->eflags;
79168fd1 3206 emulate_push(ctxt, ops);
8cdbd2c9 3207 break;
535eabcf 3208 case 0x9d: /* popf */
2b48cc75 3209 c->dst.type = OP_REG;
1a6440ae 3210 c->dst.addr.reg = &ctxt->eflags;
2b48cc75 3211 c->dst.bytes = c->op_bytes;
d4c6a154 3212 rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes);
d4c6a154 3213 break;
6aa8b732 3214 case 0xa6 ... 0xa7: /* cmps */
d7e5117a 3215 c->dst.type = OP_NONE; /* Disable writeback. */
a682e354 3216 goto cmp;
dfb507c4
MG		 3217 case 0xa8 ... 0xa9: /* test ax, imm */
3218 goto test;
6aa8b732 3219 case 0xae ... 0xaf: /* scas */
f6b33fc5 3220 goto cmp;
018a98db
AK		 3221 case 0xc0 ... 0xc1:
3222 emulate_grp2(ctxt);
3223 break;
111de5d6 3224 case 0xc3: /* ret */
cf5de4f8 3225 c->dst.type = OP_REG;
1a6440ae 3226 c->dst.addr.reg = &c->eip;
cf5de4f8 3227 c->dst.bytes = c->op_bytes;
111de5d6 3228 goto pop_instruction;
09b5f4d3
WY		 3229 case 0xc4: /* les */
3230 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_ES);
09b5f4d3
WY		 3231 break;
3232 case 0xc5: /* lds */
3233 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_DS);
09b5f4d3 3234 break;
a77ab5ea
AK		 3235 case 0xcb: /* ret far */
3236 rc = emulate_ret_far(ctxt, ops);
62bd430e 3237 break;
6e154e56
MG		 3238 case 0xcc: /* int3 */
3239 irq = 3;
3240 goto do_interrupt;
3241 case 0xcd: /* int n */
3242 irq = c->src.val;
3243 do_interrupt:
3244 rc = emulate_int(ctxt, ops, irq);
6e154e56
MG		 3245 break;
3246 case 0xce: /* into */
3247 if (ctxt->eflags & EFLG_OF) {
3248 irq = 4;
3249 goto do_interrupt;
3250 }
3251 break;
62bd430e
MG		 3252 case 0xcf: /* iret */
3253 rc = emulate_iret(ctxt, ops);
a77ab5ea 3254 break;
018a98db 3255 case 0xd0 ... 0xd1: /* Grp2 */
018a98db
AK		 3256 emulate_grp2(ctxt);
3257 break;
3258 case 0xd2 ... 0xd3: /* Grp2 */
3259 c->src.val = c->regs[VCPU_REGS_RCX];
3260 emulate_grp2(ctxt);
3261 break;
f2f31845
WY		 3262 case 0xe0 ... 0xe2: /* loop/loopz/loopnz */
3263 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
3264 if (address_mask(c, c->regs[VCPU_REGS_RCX]) != 0 &&
3265 (c->b == 0xe2 || test_cc(c->b ^ 0x5, ctxt->eflags)))
3266 jmp_rel(c, c->src.val);
3267 break;
e4abac67
WY		 3268 case 0xe3: /* jcxz/jecxz/jrcxz */
3269 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0)
3270 jmp_rel(c, c->src.val);
3271 break;
a6a3034c
MG		 3272 case 0xe4: /* inb */
3273 case 0xe5: /* in */
cf8f70bf 3274 goto do_io_in;
a6a3034c
MG		 3275 case 0xe6: /* outb */
3276 case 0xe7: /* out */
cf8f70bf 3277 goto do_io_out;
1a52e051 3278 case 0xe8: /* call (near) */ {
d53c4777 3279 long int rel = c->src.val;
e4e03ded 3280 c->src.val = (unsigned long) c->eip;
7a957275 3281 jmp_rel(c, rel);
79168fd1 3282 emulate_push(ctxt, ops);
8cdbd2c9 3283 break;
1a52e051
NK		 3284 }
3285 case 0xe9: /* jmp rel */
954cd36f 3286 goto jmp;
414e6277
GN		 3287 case 0xea: { /* jmp far */
3288 unsigned short sel;
ea79849d 3289 jump_far:
414e6277
GN		 3290 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
3291
3292 if (load_segment_descriptor(ctxt, ops, sel, VCPU_SREG_CS))
c697518a 3293 goto done;
954cd36f 3294
414e6277
GN		 3295 c->eip = 0;
3296 memcpy(&c->eip, c->src.valptr, c->op_bytes);
954cd36f 3297 break;
414e6277 3298 }
954cd36f
GT		 3299 case 0xeb:
3300 jmp: /* jmp rel short */
7a957275 3301 jmp_rel(c, c->src.val);
a01af5ec 3302 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 3303 break;
a6a3034c
MG		 3304 case 0xec: /* in al,dx */
3305 case 0xed: /* in (e/r)ax,dx */
cf8f70bf
GN		 3306 c->src.val = c->regs[VCPU_REGS_RDX];
3307 do_io_in:
3308 c->dst.bytes = min(c->dst.bytes, 4u);
3309 if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) {
35d3d4a1 3310 rc = emulate_gp(ctxt, 0);
cf8f70bf
GN		 3311 goto done;
3312 }
7b262e90
GN		 3313 if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val,
3314 &c->dst.val))
cf8f70bf
GN		 3315 goto done; /* IO is needed */
3316 break;
ce7a0ad3
WY		 3317 case 0xee: /* out dx,al */
3318 case 0xef: /* out dx,(e/r)ax */
41167be5 3319 c->dst.val = c->regs[VCPU_REGS_RDX];
cf8f70bf 3320 do_io_out:
41167be5
WY		 3321 c->src.bytes = min(c->src.bytes, 4u);
3322 if (!emulator_io_permited(ctxt, ops, c->dst.val,
3323 c->src.bytes)) {
35d3d4a1 3324 rc = emulate_gp(ctxt, 0);
f850e2e6
GN		 3325 goto done;
3326 }
41167be5
WY		 3327 ops->pio_out_emulated(c->src.bytes, c->dst.val,
3328 &c->src.val, 1, ctxt->vcpu);
cf8f70bf 3329 c->dst.type = OP_NONE; /* Disable writeback. */
e93f36bc 3330 break;
111de5d6 3331 case 0xf4: /* hlt */
ad312c7c 3332 ctxt->vcpu->arch.halt_request = 1;
19fdfa0d 3333 break;
111de5d6
AK		 3334 case 0xf5: /* cmc */
3335 /* complement carry flag from eflags reg */
3336 ctxt->eflags ^= EFLG_CF;
111de5d6 3337 break;
018a98db 3338 case 0xf6 ... 0xf7: /* Grp3 */
34d1f490 3339 rc = emulate_grp3(ctxt, ops);
018a98db 3340 break;
111de5d6
AK		 3341 case 0xf8: /* clc */
3342 ctxt->eflags &= ~EFLG_CF;
111de5d6 3343 break;
8744aa9a
MG		 3344 case 0xf9: /* stc */
3345 ctxt->eflags |= EFLG_CF;
3346 break;
111de5d6 3347 case 0xfa: /* cli */
07cbc6c1 3348 if (emulator_bad_iopl(ctxt, ops)) {
35d3d4a1 3349 rc = emulate_gp(ctxt, 0);
07cbc6c1 3350 goto done;
36089fed 3351 } else
f850e2e6 3352 ctxt->eflags &= ~X86_EFLAGS_IF;
111de5d6
AK		 3353 break;
3354 case 0xfb: /* sti */
07cbc6c1 3355 if (emulator_bad_iopl(ctxt, ops)) {
35d3d4a1 3356 rc = emulate_gp(ctxt, 0);
07cbc6c1
WY		 3357 goto done;
3358 } else {
95cb2295 3359 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
f850e2e6 3360 ctxt->eflags |= X86_EFLAGS_IF;
f850e2e6 3361 }
111de5d6 3362 break;
fb4616f4
MG		 3363 case 0xfc: /* cld */
3364 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 3365 break;
3366 case 0xfd: /* std */
3367 ctxt->eflags |= EFLG_DF;
fb4616f4 3368 break;
ea79849d
GN		 3369 case 0xfe: /* Grp4 */
3370 grp45:
018a98db 3371 rc = emulate_grp45(ctxt, ops);
018a98db 3372 break;
ea79849d
GN		 3373 case 0xff: /* Grp5 */
3374 if (c->modrm_reg == 5)
3375 goto jump_far;
3376 goto grp45;
91269b8f
AK		 3377 default:
3378 goto cannot_emulate;
6aa8b732 3379 }
018a98db 3380
7d9ddaed
AK		 3381 if (rc != X86EMUL_CONTINUE)
3382 goto done;
3383
018a98db
AK		 3384writeback:
3385 rc = writeback(ctxt, ops);
1b30eaa8 3386 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 3387 goto done;
3388
5cd21917
GN		 3389 /*
3390 * restore dst type in case the decoding will be reused
3391 * (happens for string instruction )
3392 */
3393 c->dst.type = saved_dst_type;
3394
a682e354 3395 if ((c->d & SrcMask) == SrcSI)
90de84f5 3396 string_addr_inc(ctxt, seg_override(ctxt, ops, c),
79168fd1 3397 VCPU_REGS_RSI, &c->src);
a682e354
GN		 3398
3399 if ((c->d & DstMask) == DstDI)
90de84f5 3400 string_addr_inc(ctxt, VCPU_SREG_ES, VCPU_REGS_RDI,
79168fd1 3401 &c->dst);
d9271123 3402
5cd21917 3403 if (c->rep_prefix && (c->d & String)) {
6e2fb2ca 3404 struct read_cache *r = &ctxt->decode.io_read;
d9271123 3405 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
3e2f65d5 3406
d2ddd1c4
GN		 3407 if (!string_insn_completed(ctxt)) {
3408 /*
3409 * Re-enter guest when pio read ahead buffer is empty
3410 * or, if it is not used, after each 1024 iteration.
3411 */
3412 if ((r->end != 0 || c->regs[VCPU_REGS_RCX] & 0x3ff) &&
3413 (r->end == 0 || r->end != r->pos)) {
3414 /*
3415 * Reset read cache. Usually happens before
3416 * decode, but since instruction is restarted
3417 * we have to do it here.
3418 */
3419 ctxt->decode.mem_read.end = 0;
3420 return EMULATION_RESTART;
3421 }
3422 goto done; /* skip rip writeback */
0fa6ccbd 3423 }
5cd21917 3424 }
d2ddd1c4
GN		 3425
3426 ctxt->eip = c->eip;
018a98db
AK		 3427
3428done:
da9cb575
AK		 3429 if (rc == X86EMUL_PROPAGATE_FAULT)
3430 ctxt->have_exception = true;
d2ddd1c4 3431 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 3432
3433twobyte_insn:
e4e03ded 3434 switch (c->b) {
6aa8b732 3435 case 0x01: /* lgdt, lidt, lmsw */
e4e03ded 3436 switch (c->modrm_reg) {
6aa8b732
AK		 3437 u16 size;
3438 unsigned long address;
3439
aca7f966 3440 case 0: /* vmcall */
e4e03ded 3441 if (c->modrm_mod != 3 || c->modrm_rm != 1)
aca7f966
AL		 3442 goto cannot_emulate;
3443
7aa81cc0 3444 rc = kvm_fix_hypercall(ctxt->vcpu);
1b30eaa8 3445 if (rc != X86EMUL_CONTINUE)
7aa81cc0
AL		 3446 goto done;
3447
33e3885d 3448 /* Let the processor re-execute the fixed hypercall */
063db061 3449 c->eip = ctxt->eip;
16286d08
AK		 3450 /* Disable writeback. */
3451 c->dst.type = OP_NONE;
aca7f966 3452 break;
6aa8b732 3453 case 2: /* lgdt */
1a6440ae 3454 rc = read_descriptor(ctxt, ops, c->src.addr.mem,
e4e03ded 3455 &size, &address, c->op_bytes);
1b30eaa8 3456 if (rc != X86EMUL_CONTINUE)
6aa8b732
AK		 3457 goto done;
3458 realmode_lgdt(ctxt->vcpu, size, address);
16286d08
AK		 3459 /* Disable writeback. */
3460 c->dst.type = OP_NONE;
6aa8b732 3461 break;
aca7f966 3462 case 3: /* lidt/vmmcall */
2b3d2a20
AK		 3463 if (c->modrm_mod == 3) {
3464 switch (c->modrm_rm) {
3465 case 1:
3466 rc = kvm_fix_hypercall(ctxt->vcpu);
2b3d2a20
AK		 3467 break;
3468 default:
3469 goto cannot_emulate;
3470 }
aca7f966 3471 } else {
1a6440ae 3472 rc = read_descriptor(ctxt, ops, c->src.addr.mem,
aca7f966 3473 &size, &address,
e4e03ded 3474 c->op_bytes);
1b30eaa8 3475 if (rc != X86EMUL_CONTINUE)
aca7f966
AL		 3476 goto done;
3477 realmode_lidt(ctxt->vcpu, size, address);
3478 }
16286d08
AK		 3479 /* Disable writeback. */
3480 c->dst.type = OP_NONE;
6aa8b732
AK		 3481 break;
3482 case 4: /* smsw */
16286d08 3483 c->dst.bytes = 2;
52a46617 3484 c->dst.val = ops->get_cr(0, ctxt->vcpu);
6aa8b732
AK		 3485 break;
3486 case 6: /* lmsw */
9928ff60 3487 ops->set_cr(0, (ops->get_cr(0, ctxt->vcpu) & ~0x0eul) |
93a152be 3488 (c->src.val & 0x0f), ctxt->vcpu);
dc7457ea 3489 c->dst.type = OP_NONE;
6aa8b732 3490 break;
6e1e5ffe 3491 case 5: /* not defined */
54b8486f 3492 emulate_ud(ctxt);
da9cb575 3493 rc = X86EMUL_PROPAGATE_FAULT;
6e1e5ffe 3494 goto done;
6aa8b732 3495 case 7: /* invlpg*/
90de84f5
AK		 3496 emulate_invlpg(ctxt->vcpu,
3497 linear(ctxt, c->src.addr.mem));
16286d08
AK		 3498 /* Disable writeback. */
3499 c->dst.type = OP_NONE;
6aa8b732
AK		 3500 break;
3501 default:
3502 goto cannot_emulate;
3503 }
3504 break;
e99f0507 3505 case 0x05: /* syscall */
3fb1b5db 3506 rc = emulate_syscall(ctxt, ops);
e99f0507 3507 break;
018a98db
AK		 3508 case 0x06:
3509 emulate_clts(ctxt->vcpu);
018a98db 3510 break;
018a98db 3511 case 0x09: /* wbinvd */
f5f48ee1 3512 kvm_emulate_wbinvd(ctxt->vcpu);
f5f48ee1
SY		 3513 break;
3514 case 0x08: /* invd */
018a98db
AK		 3515 case 0x0d: /* GrpP (prefetch) */
3516 case 0x18: /* Grp16 (prefetch/nop) */
018a98db
AK		 3517 break;
3518 case 0x20: /* mov cr, reg */
6aebfa6e
GN		 3519 switch (c->modrm_reg) {
3520 case 1:
3521 case 5 ... 7:
3522 case 9 ... 15:
54b8486f 3523 emulate_ud(ctxt);
da9cb575 3524 rc = X86EMUL_PROPAGATE_FAULT;
6aebfa6e
GN		 3525 goto done;
3526 }
1a0c7d44 3527 c->dst.val = ops->get_cr(c->modrm_reg, ctxt->vcpu);
018a98db 3528 break;
6aa8b732 3529 case 0x21: /* mov from dr to reg */
1e470be5
GN		 3530 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3531 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
54b8486f 3532 emulate_ud(ctxt);
da9cb575 3533 rc = X86EMUL_PROPAGATE_FAULT;
1e470be5
GN		 3534 goto done;
3535 }
b27f3856 3536 ops->get_dr(c->modrm_reg, &c->dst.val, ctxt->vcpu);
6aa8b732 3537 break;
018a98db 3538 case 0x22: /* mov reg, cr */
1a0c7d44 3539 if (ops->set_cr(c->modrm_reg, c->src.val, ctxt->vcpu)) {
54b8486f 3540 emulate_gp(ctxt, 0);
da9cb575 3541 rc = X86EMUL_PROPAGATE_FAULT;
0f12244f
GN		 3542 goto done;
3543 }
018a98db
AK		 3544 c->dst.type = OP_NONE;
3545 break;
6aa8b732 3546 case 0x23: /* mov from reg to dr */
1e470be5
GN		 3547 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3548 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
54b8486f 3549 emulate_ud(ctxt);
da9cb575 3550 rc = X86EMUL_PROPAGATE_FAULT;
1e470be5
GN		 3551 goto done;
3552 }
35aa5375 3553
b27f3856 3554 if (ops->set_dr(c->modrm_reg, c->src.val &
338dbc97
GN		 3555 ((ctxt->mode == X86EMUL_MODE_PROT64) ?
3556 ~0ULL : ~0U), ctxt->vcpu) < 0) {
3557 /* #UD condition is already handled by the code above */
54b8486f 3558 emulate_gp(ctxt, 0);
da9cb575 3559 rc = X86EMUL_PROPAGATE_FAULT;
338dbc97
GN		 3560 goto done;
3561 }
3562
a01af5ec 3563 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3564 break;
018a98db
AK		 3565 case 0x30:
3566 /* wrmsr */
3567 msr_data = (u32)c->regs[VCPU_REGS_RAX]
3568 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
3fb1b5db 3569 if (ops->set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data)) {
54b8486f 3570 emulate_gp(ctxt, 0);
da9cb575 3571 rc = X86EMUL_PROPAGATE_FAULT;
fd525365 3572 goto done;
018a98db
AK		 3573 }
3574 rc = X86EMUL_CONTINUE;
018a98db
AK		 3575 break;
3576 case 0x32:
3577 /* rdmsr */
3fb1b5db 3578 if (ops->get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data)) {
54b8486f 3579 emulate_gp(ctxt, 0);
da9cb575 3580 rc = X86EMUL_PROPAGATE_FAULT;
fd525365 3581 goto done;
018a98db
AK		 3582 } else {
3583 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
3584 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
3585 }
3586 rc = X86EMUL_CONTINUE;
018a98db 3587 break;
e99f0507 3588 case 0x34: /* sysenter */
3fb1b5db 3589 rc = emulate_sysenter(ctxt, ops);
e99f0507
AP		 3590 break;
3591 case 0x35: /* sysexit */
3fb1b5db 3592 rc = emulate_sysexit(ctxt, ops);
e99f0507 3593 break;
6aa8b732 3594 case 0x40 ... 0x4f: /* cmov */
e4e03ded 3595 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 3596 if (!test_cc(c->b, ctxt->eflags))
3597 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3598 break;
b2833e3c 3599 case 0x80 ... 0x8f: /* jnz rel, etc*/
018a98db 3600 if (test_cc(c->b, ctxt->eflags))
b2833e3c 3601 jmp_rel(c, c->src.val);
018a98db 3602 break;
ee45b58e
WY		 3603 case 0x90 ... 0x9f: /* setcc r/m8 */
3604 c->dst.val = test_cc(c->b, ctxt->eflags);
3605 break;
0934ac9d 3606 case 0xa0: /* push fs */
79168fd1 3607 emulate_push_sreg(ctxt, ops, VCPU_SREG_FS);
0934ac9d
MG		 3608 break;
3609 case 0xa1: /* pop fs */
3610 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
0934ac9d 3611 break;
7de75248
NK		 3612 case 0xa3:
3613 bt: /* bt */
e4f8e039 3614 c->dst.type = OP_NONE;
e4e03ded
LV		 3615 /* only subword offset */
3616 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3617 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248 3618 break;
9bf8ea42
GT		 3619 case 0xa4: /* shld imm8, r, r/m */
3620 case 0xa5: /* shld cl, r, r/m */
3621 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
3622 break;
0934ac9d 3623 case 0xa8: /* push gs */
79168fd1 3624 emulate_push_sreg(ctxt, ops, VCPU_SREG_GS);
0934ac9d
MG		 3625 break;
3626 case 0xa9: /* pop gs */
3627 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
0934ac9d 3628 break;
7de75248
NK		 3629 case 0xab:
3630 bts: /* bts */
05f086f8 3631 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 3632 break;
9bf8ea42
GT		 3633 case 0xac: /* shrd imm8, r, r/m */
3634 case 0xad: /* shrd cl, r, r/m */
3635 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
3636 break;
2a7c5b8b
GC		 3637 case 0xae: /* clflush */
3638 break;
6aa8b732
AK		 3639 case 0xb0 ... 0xb1: /* cmpxchg */
3640 /*
3641 * Save real source value, then compare EAX against
3642 * destination.
3643 */
e4e03ded
LV		 3644 c->src.orig_val = c->src.val;
3645 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 3646 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
3647 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 3648 /* Success: write back to memory. */
e4e03ded 3649 c->dst.val = c->src.orig_val;
6aa8b732
AK		 3650 } else {
3651 /* Failure: write the value we saw to EAX. */
e4e03ded 3652 c->dst.type = OP_REG;
1a6440ae 3653 c->dst.addr.reg = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 3654 }
3655 break;
09b5f4d3
WY		 3656 case 0xb2: /* lss */
3657 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_SS);
09b5f4d3 3658 break;
6aa8b732
AK		 3659 case 0xb3:
3660 btr: /* btr */
05f086f8 3661 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 3662 break;
09b5f4d3
WY		 3663 case 0xb4: /* lfs */
3664 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_FS);
09b5f4d3
WY		 3665 break;
3666 case 0xb5: /* lgs */
3667 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_GS);
09b5f4d3 3668 break;
6aa8b732 3669 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 3670 c->dst.bytes = c->op_bytes;
3671 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
3672 : (u16) c->src.val;
6aa8b732 3673 break;
6aa8b732 3674 case 0xba: /* Grp8 */
e4e03ded 3675 switch (c->modrm_reg & 3) {
6aa8b732
AK		 3676 case 0:
3677 goto bt;
3678 case 1:
3679 goto bts;
3680 case 2:
3681 goto btr;
3682 case 3:
3683 goto btc;
3684 }
3685 break;
7de75248
NK		 3686 case 0xbb:
3687 btc: /* btc */
05f086f8 3688 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 3689 break;
d9574a25
WY		 3690 case 0xbc: { /* bsf */
3691 u8 zf;
3692 __asm__ ("bsf %2, %0; setz %1"
3693 : "=r"(c->dst.val), "=q"(zf)
3694 : "r"(c->src.val));
3695 ctxt->eflags &= ~X86_EFLAGS_ZF;
3696 if (zf) {
3697 ctxt->eflags |= X86_EFLAGS_ZF;
3698 c->dst.type = OP_NONE; /* Disable writeback. */
3699 }
3700 break;
3701 }
3702 case 0xbd: { /* bsr */
3703 u8 zf;
3704 __asm__ ("bsr %2, %0; setz %1"
3705 : "=r"(c->dst.val), "=q"(zf)
3706 : "r"(c->src.val));
3707 ctxt->eflags &= ~X86_EFLAGS_ZF;
3708 if (zf) {
3709 ctxt->eflags |= X86_EFLAGS_ZF;
3710 c->dst.type = OP_NONE; /* Disable writeback. */
3711 }
3712 break;
3713 }
6aa8b732 3714 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 3715 c->dst.bytes = c->op_bytes;
3716 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
3717 (s16) c->src.val;
6aa8b732 3718 break;
92f738a5
WY		 3719 case 0xc0 ... 0xc1: /* xadd */
3720 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
3721 /* Write back the register source. */
3722 c->src.val = c->dst.orig_val;
3723 write_register_operand(&c->src);
3724 break;
a012e65a 3725 case 0xc3: /* movnti */
e4e03ded
LV		 3726 c->dst.bytes = c->op_bytes;
3727 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
3728 (u64) c->src.val;
a012e65a 3729 break;
6aa8b732 3730 case 0xc7: /* Grp9 (cmpxchg8b) */
69f55cb1 3731 rc = emulate_grp9(ctxt, ops);
8cdbd2c9 3732 break;
91269b8f
AK		 3733 default:
3734 goto cannot_emulate;
6aa8b732 3735 }
7d9ddaed
AK		 3736
3737 if (rc != X86EMUL_CONTINUE)
3738 goto done;
3739
6aa8b732
AK		 3740 goto writeback;
3741
3742cannot_emulate:
6aa8b732
AK		 3743 return -1;
3744}
Linux 6.x block layer and io_uring tree(s)