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KVM: x86: use kvm_read_guest_page for emulator accesses
[linux-2.6-block.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
b7d491e7 27#include <linux/stringify.h>
6aa8b732 28
3eeb3288 29#include "x86.h"
38ba30ba 30#include "tss.h"
e99f0507 31
a9945549
AK		 32/*
33 * Operand types
34 */
b1ea50b2
AK		 35#define OpNone 0ull
36#define OpImplicit 1ull /* No generic decode */
37#define OpReg 2ull /* Register */
38#define OpMem 3ull /* Memory */
39#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
40#define OpDI 5ull /* ES:DI/EDI/RDI */
41#define OpMem64 6ull /* Memory, 64-bit */
42#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
43#define OpDX 8ull /* DX register */
4dd6a57d
AK		 44#define OpCL 9ull /* CL register (for shifts) */
45#define OpImmByte 10ull /* 8-bit sign extended immediate */
46#define OpOne 11ull /* Implied 1 */
5e2c6883 47#define OpImm 12ull /* Sign extended up to 32-bit immediate */
0fe59128
AK		 48#define OpMem16 13ull /* Memory operand (16-bit). */
49#define OpMem32 14ull /* Memory operand (32-bit). */
50#define OpImmU 15ull /* Immediate operand, zero extended */
51#define OpSI 16ull /* SI/ESI/RSI */
52#define OpImmFAddr 17ull /* Immediate far address */
53#define OpMemFAddr 18ull /* Far address in memory */
54#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 55#define OpES 20ull /* ES */
56#define OpCS 21ull /* CS */
57#define OpSS 22ull /* SS */
58#define OpDS 23ull /* DS */
59#define OpFS 24ull /* FS */
60#define OpGS 25ull /* GS */
28867cee 61#define OpMem8 26ull /* 8-bit zero extended memory operand */
5e2c6883 62#define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
7fa57952 63#define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */
820207c8
AK		 64#define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */
65#define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */
0fe59128
AK		 66
67#define OpBits 5 /* Width of operand field */
b1ea50b2 68#define OpMask ((1ull << OpBits) - 1)
a9945549 69
6aa8b732
AK		 70/*
71 * Opcode effective-address decode tables.
72 * Note that we only emulate instructions that have at least one memory
73 * operand (excluding implicit stack references). We assume that stack
74 * references and instruction fetches will never occur in special memory
75 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
76 * not be handled.
77 */
78
79/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 80#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 81/* Destination operand type. */
a9945549
AK		 82#define DstShift 1
83#define ImplicitOps (OpImplicit << DstShift)
84#define DstReg (OpReg << DstShift)
85#define DstMem (OpMem << DstShift)
86#define DstAcc (OpAcc << DstShift)
87#define DstDI (OpDI << DstShift)
88#define DstMem64 (OpMem64 << DstShift)
89#define DstImmUByte (OpImmUByte << DstShift)
90#define DstDX (OpDX << DstShift)
820207c8 91#define DstAccLo (OpAccLo << DstShift)
a9945549 92#define DstMask (OpMask << DstShift)
6aa8b732 93/* Source operand type. */
0fe59128
AK		 94#define SrcShift 6
95#define SrcNone (OpNone << SrcShift)
96#define SrcReg (OpReg << SrcShift)
97#define SrcMem (OpMem << SrcShift)
98#define SrcMem16 (OpMem16 << SrcShift)
99#define SrcMem32 (OpMem32 << SrcShift)
100#define SrcImm (OpImm << SrcShift)
101#define SrcImmByte (OpImmByte << SrcShift)
102#define SrcOne (OpOne << SrcShift)
103#define SrcImmUByte (OpImmUByte << SrcShift)
104#define SrcImmU (OpImmU << SrcShift)
105#define SrcSI (OpSI << SrcShift)
7fa57952 106#define SrcXLat (OpXLat << SrcShift)
0fe59128
AK		 107#define SrcImmFAddr (OpImmFAddr << SrcShift)
108#define SrcMemFAddr (OpMemFAddr << SrcShift)
109#define SrcAcc (OpAcc << SrcShift)
110#define SrcImmU16 (OpImmU16 << SrcShift)
5e2c6883 111#define SrcImm64 (OpImm64 << SrcShift)
0fe59128 112#define SrcDX (OpDX << SrcShift)
28867cee 113#define SrcMem8 (OpMem8 << SrcShift)
820207c8 114#define SrcAccHi (OpAccHi << SrcShift)
0fe59128 115#define SrcMask (OpMask << SrcShift)
221192bd
MT		 116#define BitOp (1<<11)
117#define MemAbs (1<<12) /* Memory operand is absolute displacement */
118#define String (1<<13) /* String instruction (rep capable) */
119#define Stack (1<<14) /* Stack instruction (push/pop) */
120#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
121#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
122#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
123#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
124#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
045a282c 125#define Escape (5<<15) /* Escape to coprocessor instruction */
221192bd 126#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 127/* Generic ModRM decode. */
128#define ModRM (1<<19)
129/* Destination is only written; never read. */
130#define Mov (1<<20)
d8769fed 131/* Misc flags */
8ea7d6ae 132#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
b51e974f 133#define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */
5a506b12 134#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 135#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 136#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 137#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 138#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 139#define No64 (1<<28)
d5ae7ce8 140#define PageTable (1 << 29) /* instruction used to write page table */
0b789eee 141#define NotImpl (1 << 30) /* instruction is not implemented */
0dc8d10f 142/* Source 2 operand type */
0b789eee 143#define Src2Shift (31)
4dd6a57d 144#define Src2None (OpNone << Src2Shift)
ab2c5ce6 145#define Src2Mem (OpMem << Src2Shift)
4dd6a57d
AK		 146#define Src2CL (OpCL << Src2Shift)
147#define Src2ImmByte (OpImmByte << Src2Shift)
148#define Src2One (OpOne << Src2Shift)
149#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 150#define Src2ES (OpES << Src2Shift)
151#define Src2CS (OpCS << Src2Shift)
152#define Src2SS (OpSS << Src2Shift)
153#define Src2DS (OpDS << Src2Shift)
154#define Src2FS (OpFS << Src2Shift)
155#define Src2GS (OpGS << Src2Shift)
4dd6a57d 156#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 157#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
1c11b376
AK		 158#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
159#define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
160#define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
e28bbd44 161#define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
b6744dc3 162#define NoWrite ((u64)1 << 45) /* No writeback */
fb32b1ed 163#define SrcWrite ((u64)1 << 46) /* Write back src operand */
9b88ae99 164#define NoMod ((u64)1 << 47) /* Mod field is ignored */
d40a6898
PB		 165#define Intercept ((u64)1 << 48) /* Has valid intercept field */
166#define CheckPerm ((u64)1 << 49) /* Has valid check_perm field */
6aa8b732 167
820207c8 168#define DstXacc (DstAccLo | SrcAccHi | SrcWrite)
6aa8b732 169
d0e53325
AK		 170#define X2(x...) x, x
171#define X3(x...) X2(x), x
172#define X4(x...) X2(x), X2(x)
173#define X5(x...) X4(x), x
174#define X6(x...) X4(x), X2(x)
175#define X7(x...) X4(x), X3(x)
176#define X8(x...) X4(x), X4(x)
177#define X16(x...) X8(x), X8(x)
83babbca 178
e28bbd44
AK		 179#define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
180#define FASTOP_SIZE 8
181
182/*
183 * fastop functions have a special calling convention:
184 *
017da7b6
AK		 185 * dst: rax (in/out)
186 * src: rdx (in/out)
e28bbd44
AK		 187 * src2: rcx (in)
188 * flags: rflags (in/out)
b8c0b6ae 189 * ex: rsi (in:fastop pointer, out:zero if exception)
e28bbd44
AK		 190 *
191 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
192 * different operand sizes can be reached by calculation, rather than a jump
193 * table (which would be bigger than the code).
194 *
195 * fastop functions are declared as taking a never-defined fastop parameter,
196 * so they can't be called from C directly.
197 */
198
199struct fastop;
200
d65b1dee 201struct opcode {
b1ea50b2
AK		 202 u64 flags : 56;
203 u64 intercept : 8;
120df890 204 union {
ef65c889 205 int (*execute)(struct x86_emulate_ctxt *ctxt);
fd0a0d82
MK		 206 const struct opcode *group;
207 const struct group_dual *gdual;
208 const struct gprefix *gprefix;
045a282c 209 const struct escape *esc;
e28bbd44 210 void (*fastop)(struct fastop *fake);
120df890 211 } u;
d09beabd 212 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 213};
214
215struct group_dual {
216 struct opcode mod012[8];
217 struct opcode mod3[8];
d65b1dee
AK		 218};
219
0d7cdee8
AK		 220struct gprefix {
221 struct opcode pfx_no;
222 struct opcode pfx_66;
223 struct opcode pfx_f2;
224 struct opcode pfx_f3;
225};
226
045a282c
GN		 227struct escape {
228 struct opcode op[8];
229 struct opcode high[64];
230};
231
6aa8b732 232/* EFLAGS bit definitions. */
d4c6a154
GN		 233#define EFLG_ID (1<<21)
234#define EFLG_VIP (1<<20)
235#define EFLG_VIF (1<<19)
236#define EFLG_AC (1<<18)
b1d86143
AP		 237#define EFLG_VM (1<<17)
238#define EFLG_RF (1<<16)
d4c6a154
GN		 239#define EFLG_IOPL (3<<12)
240#define EFLG_NT (1<<14)
6aa8b732
AK		 241#define EFLG_OF (1<<11)
242#define EFLG_DF (1<<10)
b1d86143 243#define EFLG_IF (1<<9)
d4c6a154 244#define EFLG_TF (1<<8)
6aa8b732
AK		 245#define EFLG_SF (1<<7)
246#define EFLG_ZF (1<<6)
247#define EFLG_AF (1<<4)
248#define EFLG_PF (1<<2)
249#define EFLG_CF (1<<0)
250
62bd430e
MG		 251#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
252#define EFLG_RESERVED_ONE_MASK 2
253
dd856efa
AK		 254static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
255{
256 if (!(ctxt->regs_valid & (1 << nr))) {
257 ctxt->regs_valid |= 1 << nr;
258 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
259 }
260 return ctxt->_regs[nr];
261}
262
263static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
264{
265 ctxt->regs_valid |= 1 << nr;
266 ctxt->regs_dirty |= 1 << nr;
267 return &ctxt->_regs[nr];
268}
269
270static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
271{
272 reg_read(ctxt, nr);
273 return reg_write(ctxt, nr);
274}
275
276static void writeback_registers(struct x86_emulate_ctxt *ctxt)
277{
278 unsigned reg;
279
280 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
281 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
282}
283
284static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
285{
286 ctxt->regs_dirty = 0;
287 ctxt->regs_valid = 0;
288}
289
6aa8b732
AK		 290/*
291 * These EFLAGS bits are restored from saved value during emulation, and
292 * any changes are written back to the saved value after emulation.
293 */
294#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
295
dda96d8f
AK		 296#ifdef CONFIG_X86_64
297#define ON64(x) x
298#else
299#define ON64(x)
300#endif
301
4d758349
AK		 302static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));
303
b7d491e7
AK		 304#define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t"
305#define FOP_RET "ret \n\t"
306
307#define FOP_START(op) \
308 extern void em_##op(struct fastop *fake); \
309 asm(".pushsection .text, \"ax\" \n\t" \
310 ".global em_" #op " \n\t" \
311 FOP_ALIGN \
312 "em_" #op ": \n\t"
313
314#define FOP_END \
315 ".popsection")
316
0bdea068
AK		 317#define FOPNOP() FOP_ALIGN FOP_RET
318
b7d491e7 319#define FOP1E(op, dst) \
b8c0b6ae
AK		 320 FOP_ALIGN "10: " #op " %" #dst " \n\t" FOP_RET
321
322#define FOP1EEX(op, dst) \
323 FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception)
b7d491e7
AK		 324
325#define FASTOP1(op) \
326 FOP_START(op) \
327 FOP1E(op##b, al) \
328 FOP1E(op##w, ax) \
329 FOP1E(op##l, eax) \
330 ON64(FOP1E(op##q, rax)) \
331 FOP_END
332
b9fa409b
AK		 333/* 1-operand, using src2 (for MUL/DIV r/m) */
334#define FASTOP1SRC2(op, name) \
335 FOP_START(name) \
336 FOP1E(op, cl) \
337 FOP1E(op, cx) \
338 FOP1E(op, ecx) \
339 ON64(FOP1E(op, rcx)) \
340 FOP_END
341
b8c0b6ae
AK		 342/* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */
343#define FASTOP1SRC2EX(op, name) \
344 FOP_START(name) \
345 FOP1EEX(op, cl) \
346 FOP1EEX(op, cx) \
347 FOP1EEX(op, ecx) \
348 ON64(FOP1EEX(op, rcx)) \
349 FOP_END
350
f7857f35
AK		 351#define FOP2E(op, dst, src) \
352 FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET
353
354#define FASTOP2(op) \
355 FOP_START(op) \
017da7b6
AK		 356 FOP2E(op##b, al, dl) \
357 FOP2E(op##w, ax, dx) \
358 FOP2E(op##l, eax, edx) \
359 ON64(FOP2E(op##q, rax, rdx)) \
f7857f35
AK		 360 FOP_END
361
11c363ba
AK		 362/* 2 operand, word only */
363#define FASTOP2W(op) \
364 FOP_START(op) \
365 FOPNOP() \
017da7b6
AK		 366 FOP2E(op##w, ax, dx) \
367 FOP2E(op##l, eax, edx) \
368 ON64(FOP2E(op##q, rax, rdx)) \
11c363ba
AK		 369 FOP_END
370
007a3b54
AK		 371/* 2 operand, src is CL */
372#define FASTOP2CL(op) \
373 FOP_START(op) \
374 FOP2E(op##b, al, cl) \
375 FOP2E(op##w, ax, cl) \
376 FOP2E(op##l, eax, cl) \
377 ON64(FOP2E(op##q, rax, cl)) \
378 FOP_END
379
0bdea068
AK		 380#define FOP3E(op, dst, src, src2) \
381 FOP_ALIGN #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET
382
383/* 3-operand, word-only, src2=cl */
384#define FASTOP3WCL(op) \
385 FOP_START(op) \
386 FOPNOP() \
017da7b6
AK		 387 FOP3E(op##w, ax, dx, cl) \
388 FOP3E(op##l, eax, edx, cl) \
389 ON64(FOP3E(op##q, rax, rdx, cl)) \
0bdea068
AK		 390 FOP_END
391
9ae9feba
AK		 392/* Special case for SETcc - 1 instruction per cc */
393#define FOP_SETCC(op) ".align 4; " #op " %al; ret \n\t"
394
b8c0b6ae
AK		 395asm(".global kvm_fastop_exception \n"
396 "kvm_fastop_exception: xor %esi, %esi; ret");
397
9ae9feba
AK		 398FOP_START(setcc)
399FOP_SETCC(seto)
400FOP_SETCC(setno)
401FOP_SETCC(setc)
402FOP_SETCC(setnc)
403FOP_SETCC(setz)
404FOP_SETCC(setnz)
405FOP_SETCC(setbe)
406FOP_SETCC(setnbe)
407FOP_SETCC(sets)
408FOP_SETCC(setns)
409FOP_SETCC(setp)
410FOP_SETCC(setnp)
411FOP_SETCC(setl)
412FOP_SETCC(setnl)
413FOP_SETCC(setle)
414FOP_SETCC(setnle)
415FOP_END;
416
326f578f
PB		 417FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET
418FOP_END;
419
8a76d7f2
JR		 420static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
421 enum x86_intercept intercept,
422 enum x86_intercept_stage stage)
423{
424 struct x86_instruction_info info = {
425 .intercept = intercept,
9dac77fa
AK		 426 .rep_prefix = ctxt->rep_prefix,
427 .modrm_mod = ctxt->modrm_mod,
428 .modrm_reg = ctxt->modrm_reg,
429 .modrm_rm = ctxt->modrm_rm,
430 .src_val = ctxt->src.val64,
6cbc5f5a 431 .dst_val = ctxt->dst.val64,
9dac77fa
AK		 432 .src_bytes = ctxt->src.bytes,
433 .dst_bytes = ctxt->dst.bytes,
434 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 435 .next_rip = ctxt->eip,
436 };
437
2953538e 438 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 439}
440
f47cfa31
AK		 441static void assign_masked(ulong *dest, ulong src, ulong mask)
442{
443 *dest = (*dest & ~mask) | (src & mask);
444}
445
9dac77fa 446static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 447{
9dac77fa 448 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 449}
450
f47cfa31
AK		 451static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
452{
453 u16 sel;
454 struct desc_struct ss;
455
456 if (ctxt->mode == X86EMUL_MODE_PROT64)
457 return ~0UL;
458 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
459 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
460}
461
612e89f0
AK		 462static int stack_size(struct x86_emulate_ctxt *ctxt)
463{
464 return (__fls(stack_mask(ctxt)) + 1) >> 3;
465}
466
6aa8b732 467/* Access/update address held in a register, based on addressing mode. */
e4706772 468static inline unsigned long
9dac77fa 469address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 470{
9dac77fa 471 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 472 return reg;
473 else
9dac77fa 474 return reg & ad_mask(ctxt);
e4706772
HH		 475}
476
477static inline unsigned long
9dac77fa 478register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 479{
9dac77fa 480 return address_mask(ctxt, reg);
e4706772
HH		 481}
482
5ad105e5
AK		 483static void masked_increment(ulong *reg, ulong mask, int inc)
484{
485 assign_masked(reg, *reg + inc, mask);
486}
487
7a957275 488static inline void
9dac77fa 489register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
7a957275 490{
5ad105e5
AK		 491 ulong mask;
492
9dac77fa 493 if (ctxt->ad_bytes == sizeof(unsigned long))
5ad105e5 494 mask = ~0UL;
7a957275 495 else
5ad105e5
AK		 496 mask = ad_mask(ctxt);
497 masked_increment(reg, mask, inc);
498}
499
500static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
501{
dd856efa 502 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
7a957275 503}
6aa8b732 504
9dac77fa 505static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
7a957275 506{
9dac77fa 507 register_address_increment(ctxt, &ctxt->_eip, rel);
7a957275 508}
098c937b 509
56697687
AK		 510static u32 desc_limit_scaled(struct desc_struct *desc)
511{
512 u32 limit = get_desc_limit(desc);
513
514 return desc->g ? (limit << 12) | 0xfff : limit;
515}
516
7b105ca2 517static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 518{
519 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
520 return 0;
521
7b105ca2 522 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 523}
524
35d3d4a1
AK		 525static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
526 u32 error, bool valid)
54b8486f 527{
da9cb575
AK		 528 ctxt->exception.vector = vec;
529 ctxt->exception.error_code = error;
530 ctxt->exception.error_code_valid = valid;
35d3d4a1 531 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 532}
533
3b88e41a
JR		 534static int emulate_db(struct x86_emulate_ctxt *ctxt)
535{
536 return emulate_exception(ctxt, DB_VECTOR, 0, false);
537}
538
35d3d4a1 539static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 540{
35d3d4a1 541 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 542}
543
618ff15d
AK		 544static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
545{
546 return emulate_exception(ctxt, SS_VECTOR, err, true);
547}
548
35d3d4a1 549static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 550{
35d3d4a1 551 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 552}
553
35d3d4a1 554static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 555{
35d3d4a1 556 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 557}
558
34d1f490
AK		 559static int emulate_de(struct x86_emulate_ctxt *ctxt)
560{
35d3d4a1 561 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 562}
563
1253791d
AK		 564static int emulate_nm(struct x86_emulate_ctxt *ctxt)
565{
566 return emulate_exception(ctxt, NM_VECTOR, 0, false);
567}
568
1aa36616
AK		 569static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
570{
571 u16 selector;
572 struct desc_struct desc;
573
574 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
575 return selector;
576}
577
578static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
579 unsigned seg)
580{
581 u16 dummy;
582 u32 base3;
583 struct desc_struct desc;
584
585 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
586 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
587}
588
1c11b376
AK		 589/*
590 * x86 defines three classes of vector instructions: explicitly
591 * aligned, explicitly unaligned, and the rest, which change behaviour
592 * depending on whether they're AVX encoded or not.
593 *
594 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
595 * subject to the same check.
596 */
597static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
598{
599 if (likely(size < 16))
600 return false;
601
602 if (ctxt->d & Aligned)
603 return true;
604 else if (ctxt->d & Unaligned)
605 return false;
606 else if (ctxt->d & Avx)
607 return false;
608 else
609 return true;
610}
611
3d9b938e 612static int __linearize(struct x86_emulate_ctxt *ctxt,
52fd8b44 613 struct segmented_address addr,
3d9b938e 614 unsigned size, bool write, bool fetch,
52fd8b44
AK		 615 ulong *linear)
616{
618ff15d
AK		 617 struct desc_struct desc;
618 bool usable;
52fd8b44 619 ulong la;
618ff15d 620 u32 lim;
1aa36616 621 u16 sel;
3a78a4f4 622 unsigned cpl;
52fd8b44 623
7b105ca2 624 la = seg_base(ctxt, addr.seg) + addr.ea;
618ff15d 625 switch (ctxt->mode) {
618ff15d
AK		 626 case X86EMUL_MODE_PROT64:
627 if (((signed long)la << 16) >> 16 != la)
628 return emulate_gp(ctxt, 0);
629 break;
630 default:
1aa36616
AK		 631 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
632 addr.seg);
618ff15d
AK		 633 if (!usable)
634 goto bad;
58b7825b
GN		 635 /* code segment in protected mode or read-only data segment */
636 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
637 || !(desc.type & 2)) && write)
618ff15d
AK		 638 goto bad;
639 /* unreadable code segment */
3d9b938e 640 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 641 goto bad;
642 lim = desc_limit_scaled(&desc);
643 if ((desc.type & 8) || !(desc.type & 4)) {
644 /* expand-up segment */
645 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
646 goto bad;
647 } else {
fc058680 648 /* expand-down segment */
618ff15d
AK		 649 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
650 goto bad;
651 lim = desc.d ? 0xffffffff : 0xffff;
652 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
653 goto bad;
654 }
717746e3 655 cpl = ctxt->ops->cpl(ctxt);
618ff15d
AK		 656 if (!(desc.type & 8)) {
657 /* data segment */
658 if (cpl > desc.dpl)
659 goto bad;
660 } else if ((desc.type & 8) && !(desc.type & 4)) {
661 /* nonconforming code segment */
662 if (cpl != desc.dpl)
663 goto bad;
664 } else if ((desc.type & 8) && (desc.type & 4)) {
665 /* conforming code segment */
666 if (cpl < desc.dpl)
667 goto bad;
668 }
669 break;
670 }
9dac77fa 671 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
52fd8b44 672 la &= (u32)-1;
1c11b376
AK		 673 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
674 return emulate_gp(ctxt, 0);
52fd8b44
AK		 675 *linear = la;
676 return X86EMUL_CONTINUE;
618ff15d
AK		 677bad:
678 if (addr.seg == VCPU_SREG_SS)
0afbe2f8 679 return emulate_ss(ctxt, sel);
618ff15d 680 else
0afbe2f8 681 return emulate_gp(ctxt, sel);
52fd8b44
AK		 682}
683
3d9b938e
NE		 684static int linearize(struct x86_emulate_ctxt *ctxt,
685 struct segmented_address addr,
686 unsigned size, bool write,
687 ulong *linear)
688{
689 return __linearize(ctxt, addr, size, write, false, linear);
690}
691
692
3ca3ac4d
AK		 693static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
694 struct segmented_address addr,
695 void *data,
696 unsigned size)
697{
9fa088f4
AK		 698 int rc;
699 ulong linear;
700
83b8795a 701 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 702 if (rc != X86EMUL_CONTINUE)
703 return rc;
0f65dd70 704 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 705}
706
807941b1 707/*
285ca9e9 708 * Prefetch the remaining bytes of the instruction without crossing page
807941b1
TY		 709 * boundary if they are not in fetch_cache yet.
710 */
9506d57d 711static int __do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, int op_size)
62266869 712{
62266869 713 int rc;
719d5a9b 714 unsigned size;
285ca9e9 715 unsigned long linear;
17052f16 716 int cur_size = ctxt->fetch.end - ctxt->fetch.data;
285ca9e9 717 struct segmented_address addr = { .seg = VCPU_SREG_CS,
17052f16
PB		 718 .ea = ctxt->eip + cur_size };
719
719d5a9b
PB		 720 size = 15UL ^ cur_size;
721 rc = __linearize(ctxt, addr, size, false, true, &linear);
722 if (unlikely(rc != X86EMUL_CONTINUE))
723 return rc;
724
725 size = min_t(unsigned, size, PAGE_SIZE - offset_in_page(linear));
5cfc7e0f
PB		 726
727 /*
728 * One instruction can only straddle two pages,
729 * and one has been loaded at the beginning of
730 * x86_decode_insn. So, if not enough bytes
731 * still, we must have hit the 15-byte boundary.
732 */
733 if (unlikely(size < op_size))
285ca9e9 734 return X86EMUL_UNHANDLEABLE;
17052f16 735 rc = ctxt->ops->fetch(ctxt, linear, ctxt->fetch.end,
285ca9e9
PB		 736 size, &ctxt->exception);
737 if (unlikely(rc != X86EMUL_CONTINUE))
738 return rc;
17052f16 739 ctxt->fetch.end += size;
3e2815e9 740 return X86EMUL_CONTINUE;
62266869
AK		 741}
742
9506d57d
PB		 743static __always_inline int do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt,
744 unsigned size)
62266869 745{
17052f16 746 if (unlikely(ctxt->fetch.end - ctxt->fetch.ptr < size))
9506d57d
PB		 747 return __do_insn_fetch_bytes(ctxt, size);
748 else
749 return X86EMUL_CONTINUE;
62266869
AK		 750}
751
67cbc90d 752/* Fetch next part of the instruction being emulated. */
e85a1085 753#define insn_fetch(_type, _ctxt) \
9506d57d 754({ _type _x; \
9506d57d
PB		 755 \
756 rc = do_insn_fetch_bytes(_ctxt, sizeof(_type)); \
67cbc90d
TY		 757 if (rc != X86EMUL_CONTINUE) \
758 goto done; \
9506d57d 759 ctxt->_eip += sizeof(_type); \
17052f16
PB		 760 _x = *(_type __aligned(1) *) ctxt->fetch.ptr; \
761 ctxt->fetch.ptr += sizeof(_type); \
9506d57d 762 _x; \
67cbc90d
TY		 763})
764
807941b1 765#define insn_fetch_arr(_arr, _size, _ctxt) \
9506d57d 766({ \
9506d57d 767 rc = do_insn_fetch_bytes(_ctxt, _size); \
67cbc90d
TY		 768 if (rc != X86EMUL_CONTINUE) \
769 goto done; \
9506d57d 770 ctxt->_eip += (_size); \
17052f16
PB		 771 memcpy(_arr, ctxt->fetch.ptr, _size); \
772 ctxt->fetch.ptr += (_size); \
67cbc90d
TY		 773})
774
1e3c5cb0
RR		 775/*
776 * Given the 'reg' portion of a ModRM byte, and a register block, return a
777 * pointer into the block that addresses the relevant register.
778 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
779 */
dd856efa 780static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
aa9ac1a6 781 int byteop)
6aa8b732
AK		 782{
783 void *p;
aa9ac1a6 784 int highbyte_regs = (ctxt->rex_prefix == 0) && byteop;
6aa8b732 785
6aa8b732 786 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
dd856efa
AK		 787 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
788 else
789 p = reg_rmw(ctxt, modrm_reg);
6aa8b732
AK		 790 return p;
791}
792
793static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 794 struct segmented_address addr,
6aa8b732
AK		 795 u16 *size, unsigned long *address, int op_bytes)
796{
797 int rc;
798
799 if (op_bytes == 2)
800 op_bytes = 3;
801 *address = 0;
3ca3ac4d 802 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 803 if (rc != X86EMUL_CONTINUE)
6aa8b732 804 return rc;
30b31ab6 805 addr.ea += 2;
3ca3ac4d 806 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 807 return rc;
808}
809
34b77652
AK		 810FASTOP2(add);
811FASTOP2(or);
812FASTOP2(adc);
813FASTOP2(sbb);
814FASTOP2(and);
815FASTOP2(sub);
816FASTOP2(xor);
817FASTOP2(cmp);
818FASTOP2(test);
819
b9fa409b
AK		 820FASTOP1SRC2(mul, mul_ex);
821FASTOP1SRC2(imul, imul_ex);
b8c0b6ae
AK		 822FASTOP1SRC2EX(div, div_ex);
823FASTOP1SRC2EX(idiv, idiv_ex);
b9fa409b 824
34b77652
AK		 825FASTOP3WCL(shld);
826FASTOP3WCL(shrd);
827
828FASTOP2W(imul);
829
830FASTOP1(not);
831FASTOP1(neg);
832FASTOP1(inc);
833FASTOP1(dec);
834
835FASTOP2CL(rol);
836FASTOP2CL(ror);
837FASTOP2CL(rcl);
838FASTOP2CL(rcr);
839FASTOP2CL(shl);
840FASTOP2CL(shr);
841FASTOP2CL(sar);
842
843FASTOP2W(bsf);
844FASTOP2W(bsr);
845FASTOP2W(bt);
846FASTOP2W(bts);
847FASTOP2W(btr);
848FASTOP2W(btc);
849
e47a5f5f
AK		 850FASTOP2(xadd);
851
9ae9feba 852static u8 test_cc(unsigned int condition, unsigned long flags)
bbe9abbd 853{
9ae9feba
AK		 854 u8 rc;
855 void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
bbe9abbd 856
9ae9feba 857 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
3f0c3d0b 858 asm("push %[flags]; popf; call *%[fastop]"
9ae9feba
AK		 859 : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags));
860 return rc;
bbe9abbd
NK		 861}
862
91ff3cb4
AK		 863static void fetch_register_operand(struct operand *op)
864{
865 switch (op->bytes) {
866 case 1:
867 op->val = *(u8 *)op->addr.reg;
868 break;
869 case 2:
870 op->val = *(u16 *)op->addr.reg;
871 break;
872 case 4:
873 op->val = *(u32 *)op->addr.reg;
874 break;
875 case 8:
876 op->val = *(u64 *)op->addr.reg;
877 break;
878 }
879}
880
1253791d
AK		 881static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
882{
883 ctxt->ops->get_fpu(ctxt);
884 switch (reg) {
89a87c67
MK		 885 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
886 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
887 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
888 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
889 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
890 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
891 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
892 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
1253791d 893#ifdef CONFIG_X86_64
89a87c67
MK		 894 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
895 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
896 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
897 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
898 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
899 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
900 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
901 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
1253791d
AK		 902#endif
903 default: BUG();
904 }
905 ctxt->ops->put_fpu(ctxt);
906}
907
908static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
909 int reg)
910{
911 ctxt->ops->get_fpu(ctxt);
912 switch (reg) {
89a87c67
MK		 913 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
914 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
915 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
916 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
917 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
918 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
919 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
920 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
1253791d 921#ifdef CONFIG_X86_64
89a87c67
MK		 922 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
923 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
924 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
925 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
926 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
927 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
928 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
929 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
1253791d
AK		 930#endif
931 default: BUG();
932 }
933 ctxt->ops->put_fpu(ctxt);
934}
935
cbe2c9d3
AK		 936static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
937{
938 ctxt->ops->get_fpu(ctxt);
939 switch (reg) {
940 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
941 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
942 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
943 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
944 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
945 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
946 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
947 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
948 default: BUG();
949 }
950 ctxt->ops->put_fpu(ctxt);
951}
952
953static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
954{
955 ctxt->ops->get_fpu(ctxt);
956 switch (reg) {
957 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
958 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
959 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
960 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
961 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
962 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
963 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
964 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
965 default: BUG();
966 }
967 ctxt->ops->put_fpu(ctxt);
968}
969
045a282c
GN		 970static int em_fninit(struct x86_emulate_ctxt *ctxt)
971{
972 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
973 return emulate_nm(ctxt);
974
975 ctxt->ops->get_fpu(ctxt);
976 asm volatile("fninit");
977 ctxt->ops->put_fpu(ctxt);
978 return X86EMUL_CONTINUE;
979}
980
981static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
982{
983 u16 fcw;
984
985 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
986 return emulate_nm(ctxt);
987
988 ctxt->ops->get_fpu(ctxt);
989 asm volatile("fnstcw %0": "+m"(fcw));
990 ctxt->ops->put_fpu(ctxt);
991
992 /* force 2 byte destination */
993 ctxt->dst.bytes = 2;
994 ctxt->dst.val = fcw;
995
996 return X86EMUL_CONTINUE;
997}
998
999static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
1000{
1001 u16 fsw;
1002
1003 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1004 return emulate_nm(ctxt);
1005
1006 ctxt->ops->get_fpu(ctxt);
1007 asm volatile("fnstsw %0": "+m"(fsw));
1008 ctxt->ops->put_fpu(ctxt);
1009
1010 /* force 2 byte destination */
1011 ctxt->dst.bytes = 2;
1012 ctxt->dst.val = fsw;
1013
1014 return X86EMUL_CONTINUE;
1015}
1016
1253791d 1017static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 1018 struct operand *op)
3c118e24 1019{
9dac77fa 1020 unsigned reg = ctxt->modrm_reg;
33615aa9 1021
9dac77fa
AK		 1022 if (!(ctxt->d & ModRM))
1023 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 1024
9dac77fa 1025 if (ctxt->d & Sse) {
1253791d
AK		 1026 op->type = OP_XMM;
1027 op->bytes = 16;
1028 op->addr.xmm = reg;
1029 read_sse_reg(ctxt, &op->vec_val, reg);
1030 return;
1031 }
cbe2c9d3
AK		 1032 if (ctxt->d & Mmx) {
1033 reg &= 7;
1034 op->type = OP_MM;
1035 op->bytes = 8;
1036 op->addr.mm = reg;
1037 return;
1038 }
1253791d 1039
3c118e24 1040 op->type = OP_REG;
6d4d85ec
GN		 1041 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1042 op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp);
1043
91ff3cb4 1044 fetch_register_operand(op);
3c118e24
AK		 1045 op->orig_val = op->val;
1046}
1047
a6e3407b
AK		 1048static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1049{
1050 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1051 ctxt->modrm_seg = VCPU_SREG_SS;
1052}
1053
1c73ef66 1054static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1055 struct operand *op)
1c73ef66 1056{
1c73ef66 1057 u8 sib;
02357bdc 1058 int index_reg, base_reg, scale;
3e2815e9 1059 int rc = X86EMUL_CONTINUE;
2dbd0dd7 1060 ulong modrm_ea = 0;
1c73ef66 1061
02357bdc
BD		 1062 ctxt->modrm_reg = ((ctxt->rex_prefix << 1) & 8); /* REX.R */
1063 index_reg = (ctxt->rex_prefix << 2) & 8; /* REX.X */
1064 base_reg = (ctxt->rex_prefix << 3) & 8; /* REX.B */
1c73ef66 1065
02357bdc 1066 ctxt->modrm_mod = (ctxt->modrm & 0xc0) >> 6;
9dac77fa 1067 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
02357bdc 1068 ctxt->modrm_rm = base_reg | (ctxt->modrm & 0x07);
9dac77fa 1069 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 1070
9b88ae99 1071 if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) {
2dbd0dd7 1072 op->type = OP_REG;
9dac77fa 1073 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
8acb4207 1074 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm,
aa9ac1a6 1075 ctxt->d & ByteOp);
9dac77fa 1076 if (ctxt->d & Sse) {
1253791d
AK		 1077 op->type = OP_XMM;
1078 op->bytes = 16;
9dac77fa
AK		 1079 op->addr.xmm = ctxt->modrm_rm;
1080 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 1081 return rc;
1082 }
cbe2c9d3
AK		 1083 if (ctxt->d & Mmx) {
1084 op->type = OP_MM;
1085 op->bytes = 8;
bdc90722 1086 op->addr.mm = ctxt->modrm_rm & 7;
cbe2c9d3
AK		 1087 return rc;
1088 }
2dbd0dd7 1089 fetch_register_operand(op);
1c73ef66
AK		 1090 return rc;
1091 }
1092
2dbd0dd7
AK		 1093 op->type = OP_MEM;
1094
9dac77fa 1095 if (ctxt->ad_bytes == 2) {
dd856efa
AK		 1096 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1097 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1098 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1099 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1c73ef66
AK		 1100
1101 /* 16-bit ModR/M decode. */
9dac77fa 1102 switch (ctxt->modrm_mod) {
1c73ef66 1103 case 0:
9dac77fa 1104 if (ctxt->modrm_rm == 6)
e85a1085 1105 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1106 break;
1107 case 1:
e85a1085 1108 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1109 break;
1110 case 2:
e85a1085 1111 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1112 break;
1113 }
9dac77fa 1114 switch (ctxt->modrm_rm) {
1c73ef66 1115 case 0:
2dbd0dd7 1116 modrm_ea += bx + si;
1c73ef66
AK		 1117 break;
1118 case 1:
2dbd0dd7 1119 modrm_ea += bx + di;
1c73ef66
AK		 1120 break;
1121 case 2:
2dbd0dd7 1122 modrm_ea += bp + si;
1c73ef66
AK		 1123 break;
1124 case 3:
2dbd0dd7 1125 modrm_ea += bp + di;
1c73ef66
AK		 1126 break;
1127 case 4:
2dbd0dd7 1128 modrm_ea += si;
1c73ef66
AK		 1129 break;
1130 case 5:
2dbd0dd7 1131 modrm_ea += di;
1c73ef66
AK		 1132 break;
1133 case 6:
9dac77fa 1134 if (ctxt->modrm_mod != 0)
2dbd0dd7 1135 modrm_ea += bp;
1c73ef66
AK		 1136 break;
1137 case 7:
2dbd0dd7 1138 modrm_ea += bx;
1c73ef66
AK		 1139 break;
1140 }
9dac77fa
AK		 1141 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1142 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1143 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1144 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1145 } else {
1146 /* 32/64-bit ModR/M decode. */
9dac77fa 1147 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1148 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1149 index_reg |= (sib >> 3) & 7;
1150 base_reg |= sib & 7;
1151 scale = sib >> 6;
1152
9dac77fa 1153 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1154 modrm_ea += insn_fetch(s32, ctxt);
a6e3407b 1155 else {
dd856efa 1156 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1157 adjust_modrm_seg(ctxt, base_reg);
1158 }
dc71d0f1 1159 if (index_reg != 4)
dd856efa 1160 modrm_ea += reg_read(ctxt, index_reg) << scale;
9dac77fa 1161 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
84411d85 1162 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1163 ctxt->rip_relative = 1;
a6e3407b
AK		 1164 } else {
1165 base_reg = ctxt->modrm_rm;
dd856efa 1166 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1167 adjust_modrm_seg(ctxt, base_reg);
1168 }
9dac77fa 1169 switch (ctxt->modrm_mod) {
1c73ef66 1170 case 0:
9dac77fa 1171 if (ctxt->modrm_rm == 5)
e85a1085 1172 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1173 break;
1174 case 1:
e85a1085 1175 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1176 break;
1177 case 2:
e85a1085 1178 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1179 break;
1180 }
1181 }
90de84f5 1182 op->addr.mem.ea = modrm_ea;
41061cdb
BD		 1183 if (ctxt->ad_bytes != 8)
1184 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
1185
1c73ef66
AK		 1186done:
1187 return rc;
1188}
1189
1190static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1191 struct operand *op)
1c73ef66 1192{
3e2815e9 1193 int rc = X86EMUL_CONTINUE;
1c73ef66 1194
2dbd0dd7 1195 op->type = OP_MEM;
9dac77fa 1196 switch (ctxt->ad_bytes) {
1c73ef66 1197 case 2:
e85a1085 1198 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1199 break;
1200 case 4:
e85a1085 1201 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1202 break;
1203 case 8:
e85a1085 1204 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1205 break;
1206 }
1207done:
1208 return rc;
1209}
1210
9dac77fa 1211static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1212{
7129eeca 1213 long sv = 0, mask;
35c843c4 1214
9dac77fa 1215 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
7dec5603 1216 mask = ~((long)ctxt->dst.bytes * 8 - 1);
35c843c4 1217
9dac77fa
AK		 1218 if (ctxt->src.bytes == 2)
1219 sv = (s16)ctxt->src.val & (s16)mask;
1220 else if (ctxt->src.bytes == 4)
1221 sv = (s32)ctxt->src.val & (s32)mask;
7dec5603
NA		 1222 else
1223 sv = (s64)ctxt->src.val & (s64)mask;
35c843c4 1224
9dac77fa 1225 ctxt->dst.addr.mem.ea += (sv >> 3);
35c843c4 1226 }
ba7ff2b7
WY		 1227
1228 /* only subword offset */
9dac77fa 1229 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1230}
1231
dde7e6d1 1232static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1233 unsigned long addr, void *dest, unsigned size)
6aa8b732 1234{
dde7e6d1 1235 int rc;
9dac77fa 1236 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1237
f23b070e
XG		 1238 if (mc->pos < mc->end)
1239 goto read_cached;
6aa8b732 1240
f23b070e
XG		 1241 WARN_ON((mc->end + size) >= sizeof(mc->data));
1242
1243 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1244 &ctxt->exception);
1245 if (rc != X86EMUL_CONTINUE)
1246 return rc;
1247
1248 mc->end += size;
1249
1250read_cached:
1251 memcpy(dest, mc->data + mc->pos, size);
1252 mc->pos += size;
dde7e6d1
AK		 1253 return X86EMUL_CONTINUE;
1254}
6aa8b732 1255
3ca3ac4d
AK		 1256static int segmented_read(struct x86_emulate_ctxt *ctxt,
1257 struct segmented_address addr,
1258 void *data,
1259 unsigned size)
1260{
9fa088f4
AK		 1261 int rc;
1262 ulong linear;
1263
83b8795a 1264 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1265 if (rc != X86EMUL_CONTINUE)
1266 return rc;
7b105ca2 1267 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1268}
1269
1270static int segmented_write(struct x86_emulate_ctxt *ctxt,
1271 struct segmented_address addr,
1272 const void *data,
1273 unsigned size)
1274{
9fa088f4
AK		 1275 int rc;
1276 ulong linear;
1277
83b8795a 1278 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1279 if (rc != X86EMUL_CONTINUE)
1280 return rc;
0f65dd70
AK		 1281 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1282 &ctxt->exception);
3ca3ac4d
AK		 1283}
1284
1285static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1286 struct segmented_address addr,
1287 const void *orig_data, const void *data,
1288 unsigned size)
1289{
9fa088f4
AK		 1290 int rc;
1291 ulong linear;
1292
83b8795a 1293 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1294 if (rc != X86EMUL_CONTINUE)
1295 return rc;
0f65dd70
AK		 1296 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1297 size, &ctxt->exception);
3ca3ac4d
AK		 1298}
1299
dde7e6d1 1300static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1301 unsigned int size, unsigned short port,
1302 void *dest)
1303{
9dac77fa 1304 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1305
dde7e6d1 1306 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1307 unsigned int in_page, n;
9dac77fa 1308 unsigned int count = ctxt->rep_prefix ?
dd856efa 1309 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
dde7e6d1 1310 in_page = (ctxt->eflags & EFLG_DF) ?
dd856efa
AK		 1311 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1312 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
dde7e6d1
AK		 1313 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1314 count);
1315 if (n == 0)
1316 n = 1;
1317 rc->pos = rc->end = 0;
7b105ca2 1318 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1319 return 0;
1320 rc->end = n * size;
6aa8b732
AK		 1321 }
1322
e6e39f04
NA		 1323 if (ctxt->rep_prefix && (ctxt->d & String) &&
1324 !(ctxt->eflags & EFLG_DF)) {
b3356bf0
GN		 1325 ctxt->dst.data = rc->data + rc->pos;
1326 ctxt->dst.type = OP_MEM_STR;
1327 ctxt->dst.count = (rc->end - rc->pos) / size;
1328 rc->pos = rc->end;
1329 } else {
1330 memcpy(dest, rc->data + rc->pos, size);
1331 rc->pos += size;
1332 }
dde7e6d1
AK		 1333 return 1;
1334}
6aa8b732 1335
7f3d35fd
KW		 1336static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1337 u16 index, struct desc_struct *desc)
1338{
1339 struct desc_ptr dt;
1340 ulong addr;
1341
1342 ctxt->ops->get_idt(ctxt, &dt);
1343
1344 if (dt.size < index * 8 + 7)
1345 return emulate_gp(ctxt, index << 3 | 0x2);
1346
1347 addr = dt.address + index * 8;
1348 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1349 &ctxt->exception);
1350}
1351
dde7e6d1 1352static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1353 u16 selector, struct desc_ptr *dt)
1354{
0225fb50 1355 const struct x86_emulate_ops *ops = ctxt->ops;
2eedcac8 1356 u32 base3 = 0;
7b105ca2 1357
dde7e6d1
AK		 1358 if (selector & 1 << 2) {
1359 struct desc_struct desc;
1aa36616
AK		 1360 u16 sel;
1361
dde7e6d1 1362 memset (dt, 0, sizeof *dt);
2eedcac8
NA		 1363 if (!ops->get_segment(ctxt, &sel, &desc, &base3,
1364 VCPU_SREG_LDTR))
dde7e6d1 1365 return;
e09d082c 1366
dde7e6d1 1367 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
2eedcac8 1368 dt->address = get_desc_base(&desc) | ((u64)base3 << 32);
dde7e6d1 1369 } else
4bff1e86 1370 ops->get_gdt(ctxt, dt);
dde7e6d1 1371}
120df890 1372
dde7e6d1
AK		 1373/* allowed just for 8 bytes segments */
1374static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
e919464b
AK		 1375 u16 selector, struct desc_struct *desc,
1376 ulong *desc_addr_p)
dde7e6d1
AK		 1377{
1378 struct desc_ptr dt;
1379 u16 index = selector >> 3;
dde7e6d1 1380 ulong addr;
120df890 1381
7b105ca2 1382 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1383
35d3d4a1
AK		 1384 if (dt.size < index * 8 + 7)
1385 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1386
e919464b 1387 *desc_addr_p = addr = dt.address + index * 8;
7b105ca2
TY		 1388 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1389 &ctxt->exception);
dde7e6d1 1390}
ef65c889 1391
dde7e6d1
AK		 1392/* allowed just for 8 bytes segments */
1393static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1394 u16 selector, struct desc_struct *desc)
1395{
1396 struct desc_ptr dt;
1397 u16 index = selector >> 3;
dde7e6d1 1398 ulong addr;
6aa8b732 1399
7b105ca2 1400 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1401
35d3d4a1
AK		 1402 if (dt.size < index * 8 + 7)
1403 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1404
dde7e6d1 1405 addr = dt.address + index * 8;
7b105ca2
TY		 1406 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1407 &ctxt->exception);
dde7e6d1 1408}
c7e75a3d 1409
5601d05b 1410/* Does not support long mode */
2356aaeb 1411static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
5045b468 1412 u16 selector, int seg, u8 cpl, bool in_task_switch)
dde7e6d1 1413{
869be99c 1414 struct desc_struct seg_desc, old_desc;
2356aaeb 1415 u8 dpl, rpl;
dde7e6d1
AK		 1416 unsigned err_vec = GP_VECTOR;
1417 u32 err_code = 0;
1418 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
e919464b 1419 ulong desc_addr;
dde7e6d1 1420 int ret;
03ebebeb 1421 u16 dummy;
e37a75a1 1422 u32 base3 = 0;
69f55cb1 1423
dde7e6d1 1424 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1425
f8da94e9
KW		 1426 if (ctxt->mode == X86EMUL_MODE_REAL) {
1427 /* set real mode segment descriptor (keep limit etc. for
1428 * unreal mode) */
03ebebeb 1429 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
dde7e6d1 1430 set_desc_base(&seg_desc, selector << 4);
dde7e6d1 1431 goto load;
f8da94e9
KW		 1432 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
1433 /* VM86 needs a clean new segment descriptor */
1434 set_desc_base(&seg_desc, selector << 4);
1435 set_desc_limit(&seg_desc, 0xffff);
1436 seg_desc.type = 3;
1437 seg_desc.p = 1;
1438 seg_desc.s = 1;
1439 seg_desc.dpl = 3;
1440 goto load;
dde7e6d1
AK		 1441 }
1442
79d5b4c3 1443 rpl = selector & 3;
79d5b4c3
AK		 1444
1445 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1446 if ((seg == VCPU_SREG_CS
1447 || (seg == VCPU_SREG_SS
1448 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1449 || seg == VCPU_SREG_TR)
dde7e6d1
AK		 1450 && null_selector)
1451 goto exception;
1452
1453 /* TR should be in GDT only */
1454 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1455 goto exception;
1456
1457 if (null_selector) /* for NULL selector skip all following checks */
1458 goto load;
1459
e919464b 1460 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
dde7e6d1
AK		 1461 if (ret != X86EMUL_CONTINUE)
1462 return ret;
1463
1464 err_code = selector & 0xfffc;
1465 err_vec = GP_VECTOR;
1466
fc058680 1467 /* can't load system descriptor into segment selector */
dde7e6d1
AK		 1468 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1469 goto exception;
1470
1471 if (!seg_desc.p) {
1472 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1473 goto exception;
1474 }
1475
dde7e6d1 1476 dpl = seg_desc.dpl;
dde7e6d1
AK		 1477
1478 switch (seg) {
1479 case VCPU_SREG_SS:
1480 /*
1481 * segment is not a writable data segment or segment
1482 * selector's RPL != CPL or segment selector's RPL != CPL
1483 */
1484 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1485 goto exception;
6aa8b732 1486 break;
dde7e6d1 1487 case VCPU_SREG_CS:
5045b468
PB		 1488 if (in_task_switch && rpl != dpl)
1489 goto exception;
1490
dde7e6d1
AK		 1491 if (!(seg_desc.type & 8))
1492 goto exception;
1493
1494 if (seg_desc.type & 4) {
1495 /* conforming */
1496 if (dpl > cpl)
1497 goto exception;
1498 } else {
1499 /* nonconforming */
1500 if (rpl > cpl || dpl != cpl)
1501 goto exception;
1502 }
1503 /* CS(RPL) <- CPL */
1504 selector = (selector & 0xfffc) | cpl;
6aa8b732 1505 break;
dde7e6d1
AK		 1506 case VCPU_SREG_TR:
1507 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1508 goto exception;
869be99c
AK		 1509 old_desc = seg_desc;
1510 seg_desc.type |= 2; /* busy */
1511 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1512 sizeof(seg_desc), &ctxt->exception);
1513 if (ret != X86EMUL_CONTINUE)
1514 return ret;
dde7e6d1
AK		 1515 break;
1516 case VCPU_SREG_LDTR:
1517 if (seg_desc.s || seg_desc.type != 2)
1518 goto exception;
1519 break;
1520 default: /* DS, ES, FS, or GS */
4e62417b 1521 /*
dde7e6d1
AK		 1522 * segment is not a data or readable code segment or
1523 * ((segment is a data or nonconforming code segment)
1524 * and (both RPL and CPL > DPL))
4e62417b 1525 */
dde7e6d1
AK		 1526 if ((seg_desc.type & 0xa) == 0x8 ||
1527 (((seg_desc.type & 0xc) != 0xc) &&
1528 (rpl > dpl && cpl > dpl)))
1529 goto exception;
6aa8b732 1530 break;
dde7e6d1
AK		 1531 }
1532
1533 if (seg_desc.s) {
1534 /* mark segment as accessed */
1535 seg_desc.type |= 1;
7b105ca2 1536 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1537 if (ret != X86EMUL_CONTINUE)
1538 return ret;
e37a75a1
NA		 1539 } else if (ctxt->mode == X86EMUL_MODE_PROT64) {
1540 ret = ctxt->ops->read_std(ctxt, desc_addr+8, &base3,
1541 sizeof(base3), &ctxt->exception);
1542 if (ret != X86EMUL_CONTINUE)
1543 return ret;
dde7e6d1
AK		 1544 }
1545load:
e37a75a1 1546 ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg);
dde7e6d1
AK		 1547 return X86EMUL_CONTINUE;
1548exception:
1549 emulate_exception(ctxt, err_vec, err_code, true);
1550 return X86EMUL_PROPAGATE_FAULT;
1551}
1552
2356aaeb
PB		 1553static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1554 u16 selector, int seg)
1555{
1556 u8 cpl = ctxt->ops->cpl(ctxt);
5045b468 1557 return __load_segment_descriptor(ctxt, selector, seg, cpl, false);
2356aaeb
PB		 1558}
1559
31be40b3
WY		 1560static void write_register_operand(struct operand *op)
1561{
1562 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1563 switch (op->bytes) {
1564 case 1:
1565 *(u8 *)op->addr.reg = (u8)op->val;
1566 break;
1567 case 2:
1568 *(u16 *)op->addr.reg = (u16)op->val;
1569 break;
1570 case 4:
1571 *op->addr.reg = (u32)op->val;
1572 break; /* 64b: zero-extend */
1573 case 8:
1574 *op->addr.reg = op->val;
1575 break;
1576 }
1577}
1578
fb32b1ed 1579static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
dde7e6d1 1580{
fb32b1ed 1581 switch (op->type) {
dde7e6d1 1582 case OP_REG:
fb32b1ed 1583 write_register_operand(op);
6aa8b732 1584 break;
dde7e6d1 1585 case OP_MEM:
9dac77fa 1586 if (ctxt->lock_prefix)
f5f87dfb
PB		 1587 return segmented_cmpxchg(ctxt,
1588 op->addr.mem,
1589 &op->orig_val,
1590 &op->val,
1591 op->bytes);
1592 else
1593 return segmented_write(ctxt,
fb32b1ed 1594 op->addr.mem,
fb32b1ed
AK		 1595 &op->val,
1596 op->bytes);
a682e354 1597 break;
b3356bf0 1598 case OP_MEM_STR:
f5f87dfb
PB		 1599 return segmented_write(ctxt,
1600 op->addr.mem,
1601 op->data,
1602 op->bytes * op->count);
b3356bf0 1603 break;
1253791d 1604 case OP_XMM:
fb32b1ed 1605 write_sse_reg(ctxt, &op->vec_val, op->addr.xmm);
1253791d 1606 break;
cbe2c9d3 1607 case OP_MM:
fb32b1ed 1608 write_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
cbe2c9d3 1609 break;
dde7e6d1
AK		 1610 case OP_NONE:
1611 /* no writeback */
414e6277 1612 break;
dde7e6d1 1613 default:
414e6277 1614 break;
6aa8b732 1615 }
dde7e6d1
AK		 1616 return X86EMUL_CONTINUE;
1617}
6aa8b732 1618
51ddff50 1619static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
dde7e6d1 1620{
4179bb02 1621 struct segmented_address addr;
0dc8d10f 1622
5ad105e5 1623 rsp_increment(ctxt, -bytes);
dd856efa 1624 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
4179bb02
TY		 1625 addr.seg = VCPU_SREG_SS;
1626
51ddff50
AK		 1627 return segmented_write(ctxt, addr, data, bytes);
1628}
1629
1630static int em_push(struct x86_emulate_ctxt *ctxt)
1631{
4179bb02 1632 /* Disable writeback. */
9dac77fa 1633 ctxt->dst.type = OP_NONE;
51ddff50 1634 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1635}
69f55cb1 1636
dde7e6d1 1637static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1638 void *dest, int len)
1639{
dde7e6d1 1640 int rc;
90de84f5 1641 struct segmented_address addr;
8b4caf66 1642
dd856efa 1643 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
90de84f5 1644 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1645 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1646 if (rc != X86EMUL_CONTINUE)
1647 return rc;
1648
5ad105e5 1649 rsp_increment(ctxt, len);
dde7e6d1 1650 return rc;
8b4caf66
LV		 1651}
1652
c54fe504
TY		 1653static int em_pop(struct x86_emulate_ctxt *ctxt)
1654{
9dac77fa 1655 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1656}
1657
dde7e6d1 1658static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1659 void *dest, int len)
9de41573
GN		 1660{
1661 int rc;
dde7e6d1
AK		 1662 unsigned long val, change_mask;
1663 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1664 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1665
3b9be3bf 1666 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1667 if (rc != X86EMUL_CONTINUE)
1668 return rc;
9de41573 1669
dde7e6d1
AK		 1670 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1671 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1672
dde7e6d1
AK		 1673 switch(ctxt->mode) {
1674 case X86EMUL_MODE_PROT64:
1675 case X86EMUL_MODE_PROT32:
1676 case X86EMUL_MODE_PROT16:
1677 if (cpl == 0)
1678 change_mask |= EFLG_IOPL;
1679 if (cpl <= iopl)
1680 change_mask |= EFLG_IF;
1681 break;
1682 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1683 if (iopl < 3)
1684 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1685 change_mask |= EFLG_IF;
1686 break;
1687 default: /* real mode */
1688 change_mask |= (EFLG_IOPL | EFLG_IF);
1689 break;
9de41573 1690 }
dde7e6d1
AK		 1691
1692 *(unsigned long *)dest =
1693 (ctxt->eflags & ~change_mask) | (val & change_mask);
1694
1695 return rc;
9de41573
GN		 1696}
1697
62aaa2f0
TY		 1698static int em_popf(struct x86_emulate_ctxt *ctxt)
1699{
9dac77fa
AK		 1700 ctxt->dst.type = OP_REG;
1701 ctxt->dst.addr.reg = &ctxt->eflags;
1702 ctxt->dst.bytes = ctxt->op_bytes;
1703 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1704}
1705
612e89f0
AK		 1706static int em_enter(struct x86_emulate_ctxt *ctxt)
1707{
1708 int rc;
1709 unsigned frame_size = ctxt->src.val;
1710 unsigned nesting_level = ctxt->src2.val & 31;
dd856efa 1711 ulong rbp;
612e89f0
AK		 1712
1713 if (nesting_level)
1714 return X86EMUL_UNHANDLEABLE;
1715
dd856efa
AK		 1716 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1717 rc = push(ctxt, &rbp, stack_size(ctxt));
612e89f0
AK		 1718 if (rc != X86EMUL_CONTINUE)
1719 return rc;
dd856efa 1720 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
612e89f0 1721 stack_mask(ctxt));
dd856efa
AK		 1722 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1723 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
612e89f0
AK		 1724 stack_mask(ctxt));
1725 return X86EMUL_CONTINUE;
1726}
1727
f47cfa31
AK		 1728static int em_leave(struct x86_emulate_ctxt *ctxt)
1729{
dd856efa 1730 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
f47cfa31 1731 stack_mask(ctxt));
dd856efa 1732 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
f47cfa31
AK		 1733}
1734
1cd196ea 1735static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1736{
1cd196ea
AK		 1737 int seg = ctxt->src2.val;
1738
9dac77fa 1739 ctxt->src.val = get_segment_selector(ctxt, seg);
7b262e90 1740
4487b3b4 1741 return em_push(ctxt);
7b262e90
GN		 1742}
1743
1cd196ea 1744static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1745{
1cd196ea 1746 int seg = ctxt->src2.val;
dde7e6d1
AK		 1747 unsigned long selector;
1748 int rc;
38ba30ba 1749
9dac77fa 1750 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
dde7e6d1
AK		 1751 if (rc != X86EMUL_CONTINUE)
1752 return rc;
1753
a5457e7b
PB		 1754 if (ctxt->modrm_reg == VCPU_SREG_SS)
1755 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
1756
7b105ca2 1757 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1758 return rc;
38ba30ba
GN		 1759}
1760
b96a7fad 1761static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1762{
dd856efa 1763 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
dde7e6d1
AK		 1764 int rc = X86EMUL_CONTINUE;
1765 int reg = VCPU_REGS_RAX;
38ba30ba 1766
dde7e6d1
AK		 1767 while (reg <= VCPU_REGS_RDI) {
1768 (reg == VCPU_REGS_RSP) ?
dd856efa 1769 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
38ba30ba 1770
4487b3b4 1771 rc = em_push(ctxt);
dde7e6d1
AK		 1772 if (rc != X86EMUL_CONTINUE)
1773 return rc;
38ba30ba 1774
dde7e6d1 1775 ++reg;
38ba30ba 1776 }
38ba30ba 1777
dde7e6d1 1778 return rc;
38ba30ba
GN		 1779}
1780
62aaa2f0
TY		 1781static int em_pushf(struct x86_emulate_ctxt *ctxt)
1782{
9dac77fa 1783 ctxt->src.val = (unsigned long)ctxt->eflags;
62aaa2f0
TY		 1784 return em_push(ctxt);
1785}
1786
b96a7fad 1787static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1788{
dde7e6d1
AK		 1789 int rc = X86EMUL_CONTINUE;
1790 int reg = VCPU_REGS_RDI;
38ba30ba 1791
dde7e6d1
AK		 1792 while (reg >= VCPU_REGS_RAX) {
1793 if (reg == VCPU_REGS_RSP) {
5ad105e5 1794 rsp_increment(ctxt, ctxt->op_bytes);
dde7e6d1
AK		 1795 --reg;
1796 }
38ba30ba 1797
dd856efa 1798 rc = emulate_pop(ctxt, reg_rmw(ctxt, reg), ctxt->op_bytes);
dde7e6d1
AK		 1799 if (rc != X86EMUL_CONTINUE)
1800 break;
1801 --reg;
38ba30ba 1802 }
dde7e6d1 1803 return rc;
38ba30ba
GN		 1804}
1805
dd856efa 1806static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1807{
0225fb50 1808 const struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1809 int rc;
6e154e56
MG		 1810 struct desc_ptr dt;
1811 gva_t cs_addr;
1812 gva_t eip_addr;
1813 u16 cs, eip;
6e154e56
MG		 1814
1815 /* TODO: Add limit checks */
9dac77fa 1816 ctxt->src.val = ctxt->eflags;
4487b3b4 1817 rc = em_push(ctxt);
5c56e1cf
AK		 1818 if (rc != X86EMUL_CONTINUE)
1819 return rc;
6e154e56
MG		 1820
1821 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1822
9dac77fa 1823 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1824 rc = em_push(ctxt);
5c56e1cf
AK		 1825 if (rc != X86EMUL_CONTINUE)
1826 return rc;
6e154e56 1827
9dac77fa 1828 ctxt->src.val = ctxt->_eip;
4487b3b4 1829 rc = em_push(ctxt);
5c56e1cf
AK		 1830 if (rc != X86EMUL_CONTINUE)
1831 return rc;
1832
4bff1e86 1833 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1834
1835 eip_addr = dt.address + (irq << 2);
1836 cs_addr = dt.address + (irq << 2) + 2;
1837
0f65dd70 1838 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1839 if (rc != X86EMUL_CONTINUE)
1840 return rc;
1841
0f65dd70 1842 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1843 if (rc != X86EMUL_CONTINUE)
1844 return rc;
1845
7b105ca2 1846 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1847 if (rc != X86EMUL_CONTINUE)
1848 return rc;
1849
9dac77fa 1850 ctxt->_eip = eip;
6e154e56
MG		 1851
1852 return rc;
1853}
1854
dd856efa
AK		 1855int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
1856{
1857 int rc;
1858
1859 invalidate_registers(ctxt);
1860 rc = __emulate_int_real(ctxt, irq);
1861 if (rc == X86EMUL_CONTINUE)
1862 writeback_registers(ctxt);
1863 return rc;
1864}
1865
7b105ca2 1866static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 1867{
1868 switch(ctxt->mode) {
1869 case X86EMUL_MODE_REAL:
dd856efa 1870 return __emulate_int_real(ctxt, irq);
6e154e56
MG		 1871 case X86EMUL_MODE_VM86:
1872 case X86EMUL_MODE_PROT16:
1873 case X86EMUL_MODE_PROT32:
1874 case X86EMUL_MODE_PROT64:
1875 default:
1876 /* Protected mode interrupts unimplemented yet */
1877 return X86EMUL_UNHANDLEABLE;
1878 }
1879}
1880
7b105ca2 1881static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 1882{
dde7e6d1
AK		 1883 int rc = X86EMUL_CONTINUE;
1884 unsigned long temp_eip = 0;
1885 unsigned long temp_eflags = 0;
1886 unsigned long cs = 0;
1887 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1888 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1889 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1890 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1891
dde7e6d1 1892 /* TODO: Add stack limit check */
38ba30ba 1893
9dac77fa 1894 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 1895
dde7e6d1
AK		 1896 if (rc != X86EMUL_CONTINUE)
1897 return rc;
38ba30ba 1898
35d3d4a1
AK		 1899 if (temp_eip & ~0xffff)
1900 return emulate_gp(ctxt, 0);
38ba30ba 1901
9dac77fa 1902 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 1903
dde7e6d1
AK		 1904 if (rc != X86EMUL_CONTINUE)
1905 return rc;
38ba30ba 1906
9dac77fa 1907 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 1908
dde7e6d1
AK		 1909 if (rc != X86EMUL_CONTINUE)
1910 return rc;
38ba30ba 1911
7b105ca2 1912 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 1913
dde7e6d1
AK		 1914 if (rc != X86EMUL_CONTINUE)
1915 return rc;
38ba30ba 1916
9dac77fa 1917 ctxt->_eip = temp_eip;
38ba30ba 1918
38ba30ba 1919
9dac77fa 1920 if (ctxt->op_bytes == 4)
dde7e6d1 1921 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 1922 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 1923 ctxt->eflags &= ~0xffff;
1924 ctxt->eflags |= temp_eflags;
38ba30ba 1925 }
dde7e6d1
AK		 1926
1927 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1928 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1929
1930 return rc;
38ba30ba
GN		 1931}
1932
e01991e7 1933static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 1934{
dde7e6d1
AK		 1935 switch(ctxt->mode) {
1936 case X86EMUL_MODE_REAL:
7b105ca2 1937 return emulate_iret_real(ctxt);
dde7e6d1
AK		 1938 case X86EMUL_MODE_VM86:
1939 case X86EMUL_MODE_PROT16:
1940 case X86EMUL_MODE_PROT32:
1941 case X86EMUL_MODE_PROT64:
c37eda13 1942 default:
dde7e6d1
AK		 1943 /* iret from protected mode unimplemented yet */
1944 return X86EMUL_UNHANDLEABLE;
c37eda13 1945 }
c37eda13
WY		 1946}
1947
d2f62766
TY		 1948static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
1949{
d2f62766
TY		 1950 int rc;
1951 unsigned short sel;
1952
9dac77fa 1953 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 1954
7b105ca2 1955 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS);
d2f62766
TY		 1956 if (rc != X86EMUL_CONTINUE)
1957 return rc;
1958
9dac77fa
AK		 1959 ctxt->_eip = 0;
1960 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
d2f62766
TY		 1961 return X86EMUL_CONTINUE;
1962}
1963
51187683 1964static int em_grp45(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1965{
4179bb02 1966 int rc = X86EMUL_CONTINUE;
8cdbd2c9 1967
9dac77fa 1968 switch (ctxt->modrm_reg) {
d19292e4
MG		 1969 case 2: /* call near abs */ {
1970 long int old_eip;
9dac77fa
AK		 1971 old_eip = ctxt->_eip;
1972 ctxt->_eip = ctxt->src.val;
1973 ctxt->src.val = old_eip;
4487b3b4 1974 rc = em_push(ctxt);
d19292e4
MG		 1975 break;
1976 }
8cdbd2c9 1977 case 4: /* jmp abs */
9dac77fa 1978 ctxt->_eip = ctxt->src.val;
8cdbd2c9 1979 break;
d2f62766
TY		 1980 case 5: /* jmp far */
1981 rc = em_jmp_far(ctxt);
1982 break;
8cdbd2c9 1983 case 6: /* push */
4487b3b4 1984 rc = em_push(ctxt);
8cdbd2c9 1985 break;
8cdbd2c9 1986 }
4179bb02 1987 return rc;
8cdbd2c9
LV		 1988}
1989
e0dac408 1990static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1991{
9dac77fa 1992 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 1993
aaa05f24
NA		 1994 if (ctxt->dst.bytes == 16)
1995 return X86EMUL_UNHANDLEABLE;
1996
dd856efa
AK		 1997 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
1998 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
1999 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
2000 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
05f086f8 2001 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 2002 } else {
dd856efa
AK		 2003 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2004 (u32) reg_read(ctxt, VCPU_REGS_RBX);
8cdbd2c9 2005
05f086f8 2006 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 2007 }
1b30eaa8 2008 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2009}
2010
ebda02c2
TY		 2011static int em_ret(struct x86_emulate_ctxt *ctxt)
2012{
9dac77fa
AK		 2013 ctxt->dst.type = OP_REG;
2014 ctxt->dst.addr.reg = &ctxt->_eip;
2015 ctxt->dst.bytes = ctxt->op_bytes;
ebda02c2
TY		 2016 return em_pop(ctxt);
2017}
2018
e01991e7 2019static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 2020{
a77ab5ea
AK		 2021 int rc;
2022 unsigned long cs;
9e8919ae 2023 int cpl = ctxt->ops->cpl(ctxt);
a77ab5ea 2024
9dac77fa 2025 rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes);
1b30eaa8 2026 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2027 return rc;
9dac77fa
AK		 2028 if (ctxt->op_bytes == 4)
2029 ctxt->_eip = (u32)ctxt->_eip;
2030 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 2031 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2032 return rc;
9e8919ae
NA		 2033 /* Outer-privilege level return is not implemented */
2034 if (ctxt->mode >= X86EMUL_MODE_PROT16 && (cs & 3) > cpl)
2035 return X86EMUL_UNHANDLEABLE;
7b105ca2 2036 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 2037 return rc;
2038}
2039
3261107e
BR		 2040static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt)
2041{
2042 int rc;
2043
2044 rc = em_ret_far(ctxt);
2045 if (rc != X86EMUL_CONTINUE)
2046 return rc;
2047 rsp_increment(ctxt, ctxt->src.val);
2048 return X86EMUL_CONTINUE;
2049}
2050
e940b5c2
TY		 2051static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2052{
2053 /* Save real source value, then compare EAX against destination. */
37c564f2
NA		 2054 ctxt->dst.orig_val = ctxt->dst.val;
2055 ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX);
e940b5c2 2056 ctxt->src.orig_val = ctxt->src.val;
37c564f2 2057 ctxt->src.val = ctxt->dst.orig_val;
158de57f 2058 fastop(ctxt, em_cmp);
e940b5c2
TY		 2059
2060 if (ctxt->eflags & EFLG_ZF) {
2061 /* Success: write back to memory. */
2062 ctxt->dst.val = ctxt->src.orig_val;
2063 } else {
2064 /* Failure: write the value we saw to EAX. */
2065 ctxt->dst.type = OP_REG;
dd856efa 2066 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
37c564f2 2067 ctxt->dst.val = ctxt->dst.orig_val;
e940b5c2
TY		 2068 }
2069 return X86EMUL_CONTINUE;
2070}
2071
d4b4325f 2072static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 2073{
d4b4325f 2074 int seg = ctxt->src2.val;
09b5f4d3
WY		 2075 unsigned short sel;
2076 int rc;
2077
9dac77fa 2078 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 2079
7b105ca2 2080 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 2081 if (rc != X86EMUL_CONTINUE)
2082 return rc;
2083
9dac77fa 2084 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 2085 return rc;
2086}
2087
7b105ca2 2088static void
e66bb2cc 2089setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 2090 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 2091{
e66bb2cc 2092 cs->l = 0; /* will be adjusted later */
79168fd1 2093 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 2094 cs->g = 1; /* 4kb granularity */
79168fd1 2095 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2096 cs->type = 0x0b; /* Read, Execute, Accessed */
2097 cs->s = 1;
2098 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 2099 cs->p = 1;
2100 cs->d = 1;
99245b50 2101 cs->avl = 0;
e66bb2cc 2102
79168fd1
GN		 2103 set_desc_base(ss, 0); /* flat segment */
2104 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2105 ss->g = 1; /* 4kb granularity */
2106 ss->s = 1;
2107 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2108 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2109 ss->dpl = 0;
79168fd1 2110 ss->p = 1;
99245b50
GN		 2111 ss->l = 0;
2112 ss->avl = 0;
e66bb2cc
AP		 2113}
2114
1a18a69b
AK		 2115static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2116{
2117 u32 eax, ebx, ecx, edx;
2118
2119 eax = ecx = 0;
0017f93a
AK		 2120 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2121 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1a18a69b
AK		 2122 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2123 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2124}
2125
c2226fc9
SB		 2126static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2127{
0225fb50 2128 const struct x86_emulate_ops *ops = ctxt->ops;
c2226fc9
SB		 2129 u32 eax, ebx, ecx, edx;
2130
2131 /*
2132 * syscall should always be enabled in longmode - so only become
2133 * vendor specific (cpuid) if other modes are active...
2134 */
2135 if (ctxt->mode == X86EMUL_MODE_PROT64)
2136 return true;
2137
2138 eax = 0x00000000;
2139 ecx = 0x00000000;
0017f93a
AK		 2140 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2141 /*
2142 * Intel ("GenuineIntel")
2143 * remark: Intel CPUs only support "syscall" in 64bit
2144 * longmode. Also an 64bit guest with a
2145 * 32bit compat-app running will #UD !! While this
2146 * behaviour can be fixed (by emulating) into AMD
2147 * response - CPUs of AMD can't behave like Intel.
2148 */
2149 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2150 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2151 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2152 return false;
2153
2154 /* AMD ("AuthenticAMD") */
2155 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2156 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2157 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2158 return true;
2159
2160 /* AMD ("AMDisbetter!") */
2161 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2162 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2163 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2164 return true;
c2226fc9
SB		 2165
2166 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2167 return false;
2168}
2169
e01991e7 2170static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2171{
0225fb50 2172 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2173 struct desc_struct cs, ss;
e66bb2cc 2174 u64 msr_data;
79168fd1 2175 u16 cs_sel, ss_sel;
c2ad2bb3 2176 u64 efer = 0;
e66bb2cc
AP		 2177
2178 /* syscall is not available in real mode */
2e901c4c 2179 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2180 ctxt->mode == X86EMUL_MODE_VM86)
2181 return emulate_ud(ctxt);
e66bb2cc 2182
c2226fc9
SB		 2183 if (!(em_syscall_is_enabled(ctxt)))
2184 return emulate_ud(ctxt);
2185
c2ad2bb3 2186 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2187 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2188
c2226fc9
SB		 2189 if (!(efer & EFER_SCE))
2190 return emulate_ud(ctxt);
2191
717746e3 2192 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2193 msr_data >>= 32;
79168fd1
GN		 2194 cs_sel = (u16)(msr_data & 0xfffc);
2195 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2196
c2ad2bb3 2197 if (efer & EFER_LMA) {
79168fd1 2198 cs.d = 0;
e66bb2cc
AP		 2199 cs.l = 1;
2200 }
1aa36616
AK		 2201 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2202 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2203
dd856efa 2204 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
c2ad2bb3 2205 if (efer & EFER_LMA) {
e66bb2cc 2206#ifdef CONFIG_X86_64
dd856efa 2207 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags & ~EFLG_RF;
e66bb2cc 2208
717746e3 2209 ops->get_msr(ctxt,
3fb1b5db
GN		 2210 ctxt->mode == X86EMUL_MODE_PROT64 ?
2211 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2212 ctxt->_eip = msr_data;
e66bb2cc 2213
717746e3 2214 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 2215 ctxt->eflags &= ~(msr_data | EFLG_RF);
2216#endif
2217 } else {
2218 /* legacy mode */
717746e3 2219 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2220 ctxt->_eip = (u32)msr_data;
e66bb2cc
AP		 2221
2222 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
2223 }
2224
e54cfa97 2225 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2226}
2227
e01991e7 2228static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2229{
0225fb50 2230 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2231 struct desc_struct cs, ss;
8c604352 2232 u64 msr_data;
79168fd1 2233 u16 cs_sel, ss_sel;
c2ad2bb3 2234 u64 efer = 0;
8c604352 2235
7b105ca2 2236 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2237 /* inject #GP if in real mode */
35d3d4a1
AK		 2238 if (ctxt->mode == X86EMUL_MODE_REAL)
2239 return emulate_gp(ctxt, 0);
8c604352 2240
1a18a69b
AK		 2241 /*
2242 * Not recognized on AMD in compat mode (but is recognized in legacy
2243 * mode).
2244 */
2245 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
2246 && !vendor_intel(ctxt))
2247 return emulate_ud(ctxt);
2248
8c604352
AP		 2249 /* XXX sysenter/sysexit have not been tested in 64bit mode.
2250 * Therefore, we inject an #UD.
2251 */
35d3d4a1
AK		 2252 if (ctxt->mode == X86EMUL_MODE_PROT64)
2253 return emulate_ud(ctxt);
8c604352 2254
7b105ca2 2255 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2256
717746e3 2257 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2258 switch (ctxt->mode) {
2259 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 2260 if ((msr_data & 0xfffc) == 0x0)
2261 return emulate_gp(ctxt, 0);
8c604352
AP		 2262 break;
2263 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 2264 if (msr_data == 0x0)
2265 return emulate_gp(ctxt, 0);
8c604352 2266 break;
9d1b39a9
GN		 2267 default:
2268 break;
8c604352
AP		 2269 }
2270
2271 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 2272 cs_sel = (u16)msr_data;
2273 cs_sel &= ~SELECTOR_RPL_MASK;
2274 ss_sel = cs_sel + 8;
2275 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 2276 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 2277 cs.d = 0;
8c604352
AP		 2278 cs.l = 1;
2279 }
2280
1aa36616
AK		 2281 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2282 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2283
717746e3 2284 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 2285 ctxt->_eip = msr_data;
8c604352 2286
717746e3 2287 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
dd856efa 2288 *reg_write(ctxt, VCPU_REGS_RSP) = msr_data;
8c604352 2289
e54cfa97 2290 return X86EMUL_CONTINUE;
8c604352
AP		 2291}
2292
e01991e7 2293static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2294{
0225fb50 2295 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2296 struct desc_struct cs, ss;
4668f050
AP		 2297 u64 msr_data;
2298 int usermode;
1249b96e 2299 u16 cs_sel = 0, ss_sel = 0;
4668f050 2300
a0044755
GN		 2301 /* inject #GP if in real mode or Virtual 8086 mode */
2302 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2303 ctxt->mode == X86EMUL_MODE_VM86)
2304 return emulate_gp(ctxt, 0);
4668f050 2305
7b105ca2 2306 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2307
9dac77fa 2308 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2309 usermode = X86EMUL_MODE_PROT64;
2310 else
2311 usermode = X86EMUL_MODE_PROT32;
2312
2313 cs.dpl = 3;
2314 ss.dpl = 3;
717746e3 2315 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2316 switch (usermode) {
2317 case X86EMUL_MODE_PROT32:
79168fd1 2318 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2319 if ((msr_data & 0xfffc) == 0x0)
2320 return emulate_gp(ctxt, 0);
79168fd1 2321 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2322 break;
2323 case X86EMUL_MODE_PROT64:
79168fd1 2324 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2325 if (msr_data == 0x0)
2326 return emulate_gp(ctxt, 0);
79168fd1
GN		 2327 ss_sel = cs_sel + 8;
2328 cs.d = 0;
4668f050
AP		 2329 cs.l = 1;
2330 break;
2331 }
79168fd1
GN		 2332 cs_sel |= SELECTOR_RPL_MASK;
2333 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2334
1aa36616
AK		 2335 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2336 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2337
dd856efa
AK		 2338 ctxt->_eip = reg_read(ctxt, VCPU_REGS_RDX);
2339 *reg_write(ctxt, VCPU_REGS_RSP) = reg_read(ctxt, VCPU_REGS_RCX);
4668f050 2340
e54cfa97 2341 return X86EMUL_CONTINUE;
4668f050
AP		 2342}
2343
7b105ca2 2344static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2345{
2346 int iopl;
2347 if (ctxt->mode == X86EMUL_MODE_REAL)
2348 return false;
2349 if (ctxt->mode == X86EMUL_MODE_VM86)
2350 return true;
2351 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2352 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2353}
2354
2355static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2356 u16 port, u16 len)
2357{
0225fb50 2358 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2359 struct desc_struct tr_seg;
5601d05b 2360 u32 base3;
f850e2e6 2361 int r;
1aa36616 2362 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2363 unsigned mask = (1 << len) - 1;
5601d05b 2364 unsigned long base;
f850e2e6 2365
1aa36616 2366 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2367 if (!tr_seg.p)
f850e2e6 2368 return false;
79168fd1 2369 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2370 return false;
5601d05b
GN		 2371 base = get_desc_base(&tr_seg);
2372#ifdef CONFIG_X86_64
2373 base |= ((u64)base3) << 32;
2374#endif
0f65dd70 2375 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2376 if (r != X86EMUL_CONTINUE)
2377 return false;
79168fd1 2378 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2379 return false;
0f65dd70 2380 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2381 if (r != X86EMUL_CONTINUE)
2382 return false;
2383 if ((perm >> bit_idx) & mask)
2384 return false;
2385 return true;
2386}
2387
2388static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2389 u16 port, u16 len)
2390{
4fc40f07
GN		 2391 if (ctxt->perm_ok)
2392 return true;
2393
7b105ca2
TY		 2394 if (emulator_bad_iopl(ctxt))
2395 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2396 return false;
4fc40f07
GN		 2397
2398 ctxt->perm_ok = true;
2399
f850e2e6
GN		 2400 return true;
2401}
2402
38ba30ba 2403static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2404 struct tss_segment_16 *tss)
2405{
9dac77fa 2406 tss->ip = ctxt->_eip;
38ba30ba 2407 tss->flag = ctxt->eflags;
dd856efa
AK		 2408 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2409 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2410 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2411 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2412 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2413 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2414 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2415 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2416
1aa36616
AK		 2417 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2418 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2419 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2420 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2421 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2422}
2423
2424static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2425 struct tss_segment_16 *tss)
2426{
38ba30ba 2427 int ret;
2356aaeb 2428 u8 cpl;
38ba30ba 2429
9dac77fa 2430 ctxt->_eip = tss->ip;
38ba30ba 2431 ctxt->eflags = tss->flag | 2;
dd856efa
AK		 2432 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
2433 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
2434 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
2435 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
2436 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
2437 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
2438 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
2439 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
38ba30ba
GN		 2440
2441 /*
2442 * SDM says that segment selectors are loaded before segment
2443 * descriptors
2444 */
1aa36616
AK		 2445 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2446 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2447 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2448 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2449 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba 2450
2356aaeb
PB		 2451 cpl = tss->cs & 3;
2452
38ba30ba 2453 /*
fc058680 2454 * Now load segment descriptors. If fault happens at this stage
38ba30ba
GN		 2455 * it is handled in a context of new task
2456 */
5045b468 2457 ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl, true);
38ba30ba
GN		 2458 if (ret != X86EMUL_CONTINUE)
2459 return ret;
5045b468 2460 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl, true);
38ba30ba
GN		 2461 if (ret != X86EMUL_CONTINUE)
2462 return ret;
5045b468 2463 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl, true);
38ba30ba
GN		 2464 if (ret != X86EMUL_CONTINUE)
2465 return ret;
5045b468 2466 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl, true);
38ba30ba
GN		 2467 if (ret != X86EMUL_CONTINUE)
2468 return ret;
5045b468 2469 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl, true);
38ba30ba
GN		 2470 if (ret != X86EMUL_CONTINUE)
2471 return ret;
2472
2473 return X86EMUL_CONTINUE;
2474}
2475
2476static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2477 u16 tss_selector, u16 old_tss_sel,
2478 ulong old_tss_base, struct desc_struct *new_desc)
2479{
0225fb50 2480 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2481 struct tss_segment_16 tss_seg;
2482 int ret;
bcc55cba 2483 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2484
0f65dd70 2485 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2486 &ctxt->exception);
db297e3d 2487 if (ret != X86EMUL_CONTINUE)
38ba30ba 2488 /* FIXME: need to provide precise fault address */
38ba30ba 2489 return ret;
38ba30ba 2490
7b105ca2 2491 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2492
0f65dd70 2493 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2494 &ctxt->exception);
db297e3d 2495 if (ret != X86EMUL_CONTINUE)
38ba30ba 2496 /* FIXME: need to provide precise fault address */
38ba30ba 2497 return ret;
38ba30ba 2498
0f65dd70 2499 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2500 &ctxt->exception);
db297e3d 2501 if (ret != X86EMUL_CONTINUE)
38ba30ba 2502 /* FIXME: need to provide precise fault address */
38ba30ba 2503 return ret;
38ba30ba
GN		 2504
2505 if (old_tss_sel != 0xffff) {
2506 tss_seg.prev_task_link = old_tss_sel;
2507
0f65dd70 2508 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2509 &tss_seg.prev_task_link,
2510 sizeof tss_seg.prev_task_link,
0f65dd70 2511 &ctxt->exception);
db297e3d 2512 if (ret != X86EMUL_CONTINUE)
38ba30ba 2513 /* FIXME: need to provide precise fault address */
38ba30ba 2514 return ret;
38ba30ba
GN		 2515 }
2516
7b105ca2 2517 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2518}
2519
2520static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2521 struct tss_segment_32 *tss)
2522{
5c7411e2 2523 /* CR3 and ldt selector are not saved intentionally */
9dac77fa 2524 tss->eip = ctxt->_eip;
38ba30ba 2525 tss->eflags = ctxt->eflags;
dd856efa
AK		 2526 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
2527 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
2528 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
2529 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
2530 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
2531 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
2532 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
2533 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2534
1aa36616
AK		 2535 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2536 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2537 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2538 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2539 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2540 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
38ba30ba
GN		 2541}
2542
2543static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2544 struct tss_segment_32 *tss)
2545{
38ba30ba 2546 int ret;
2356aaeb 2547 u8 cpl;
38ba30ba 2548
7b105ca2 2549 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2550 return emulate_gp(ctxt, 0);
9dac77fa 2551 ctxt->_eip = tss->eip;
38ba30ba 2552 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 2553
2554 /* General purpose registers */
dd856efa
AK		 2555 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
2556 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
2557 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
2558 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
2559 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
2560 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
2561 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
2562 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
38ba30ba
GN		 2563
2564 /*
2565 * SDM says that segment selectors are loaded before segment
2356aaeb
PB		 2566 * descriptors. This is important because CPL checks will
2567 * use CS.RPL.
38ba30ba 2568 */
1aa36616
AK		 2569 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2570 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2571 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2572 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2573 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2574 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2575 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 2576
4cee4798
KW		 2577 /*
2578 * If we're switching between Protected Mode and VM86, we need to make
2579 * sure to update the mode before loading the segment descriptors so
2580 * that the selectors are interpreted correctly.
4cee4798 2581 */
2356aaeb 2582 if (ctxt->eflags & X86_EFLAGS_VM) {
4cee4798 2583 ctxt->mode = X86EMUL_MODE_VM86;
2356aaeb
PB		 2584 cpl = 3;
2585 } else {
4cee4798 2586 ctxt->mode = X86EMUL_MODE_PROT32;
2356aaeb
PB		 2587 cpl = tss->cs & 3;
2588 }
4cee4798 2589
38ba30ba
GN		 2590 /*
2591 * Now load segment descriptors. If fault happenes at this stage
2592 * it is handled in a context of new task
2593 */
5045b468 2594 ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR, cpl, true);
38ba30ba
GN		 2595 if (ret != X86EMUL_CONTINUE)
2596 return ret;
5045b468 2597 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl, true);
38ba30ba
GN		 2598 if (ret != X86EMUL_CONTINUE)
2599 return ret;
5045b468 2600 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl, true);
38ba30ba
GN		 2601 if (ret != X86EMUL_CONTINUE)
2602 return ret;
5045b468 2603 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl, true);
38ba30ba
GN		 2604 if (ret != X86EMUL_CONTINUE)
2605 return ret;
5045b468 2606 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl, true);
38ba30ba
GN		 2607 if (ret != X86EMUL_CONTINUE)
2608 return ret;
5045b468 2609 ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl, true);
38ba30ba
GN		 2610 if (ret != X86EMUL_CONTINUE)
2611 return ret;
5045b468 2612 ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl, true);
38ba30ba
GN		 2613 if (ret != X86EMUL_CONTINUE)
2614 return ret;
2615
2616 return X86EMUL_CONTINUE;
2617}
2618
2619static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2620 u16 tss_selector, u16 old_tss_sel,
2621 ulong old_tss_base, struct desc_struct *new_desc)
2622{
0225fb50 2623 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2624 struct tss_segment_32 tss_seg;
2625 int ret;
bcc55cba 2626 u32 new_tss_base = get_desc_base(new_desc);
5c7411e2
NA		 2627 u32 eip_offset = offsetof(struct tss_segment_32, eip);
2628 u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector);
38ba30ba 2629
0f65dd70 2630 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2631 &ctxt->exception);
db297e3d 2632 if (ret != X86EMUL_CONTINUE)
38ba30ba 2633 /* FIXME: need to provide precise fault address */
38ba30ba 2634 return ret;
38ba30ba 2635
7b105ca2 2636 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2637
5c7411e2
NA		 2638 /* Only GP registers and segment selectors are saved */
2639 ret = ops->write_std(ctxt, old_tss_base + eip_offset, &tss_seg.eip,
2640 ldt_sel_offset - eip_offset, &ctxt->exception);
db297e3d 2641 if (ret != X86EMUL_CONTINUE)
38ba30ba 2642 /* FIXME: need to provide precise fault address */
38ba30ba 2643 return ret;
38ba30ba 2644
0f65dd70 2645 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2646 &ctxt->exception);
db297e3d 2647 if (ret != X86EMUL_CONTINUE)
38ba30ba 2648 /* FIXME: need to provide precise fault address */
38ba30ba 2649 return ret;
38ba30ba
GN		 2650
2651 if (old_tss_sel != 0xffff) {
2652 tss_seg.prev_task_link = old_tss_sel;
2653
0f65dd70 2654 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2655 &tss_seg.prev_task_link,
2656 sizeof tss_seg.prev_task_link,
0f65dd70 2657 &ctxt->exception);
db297e3d 2658 if (ret != X86EMUL_CONTINUE)
38ba30ba 2659 /* FIXME: need to provide precise fault address */
38ba30ba 2660 return ret;
38ba30ba
GN		 2661 }
2662
7b105ca2 2663 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2664}
2665
2666static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2667 u16 tss_selector, int idt_index, int reason,
e269fb21 2668 bool has_error_code, u32 error_code)
38ba30ba 2669{
0225fb50 2670 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2671 struct desc_struct curr_tss_desc, next_tss_desc;
2672 int ret;
1aa36616 2673 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2674 ulong old_tss_base =
4bff1e86 2675 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2676 u32 desc_limit;
e919464b 2677 ulong desc_addr;
38ba30ba
GN		 2678
2679 /* FIXME: old_tss_base == ~0 ? */
2680
e919464b 2681 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
38ba30ba
GN		 2682 if (ret != X86EMUL_CONTINUE)
2683 return ret;
e919464b 2684 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
38ba30ba
GN		 2685 if (ret != X86EMUL_CONTINUE)
2686 return ret;
2687
2688 /* FIXME: check that next_tss_desc is tss */
2689
7f3d35fd
KW		 2690 /*
2691 * Check privileges. The three cases are task switch caused by...
2692 *
2693 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2694 * 2. Exception/IRQ/iret: No check is performed
fc058680 2695 * 3. jmp/call to TSS: Check against DPL of the TSS
7f3d35fd
KW		 2696 */
2697 if (reason == TASK_SWITCH_GATE) {
2698 if (idt_index != -1) {
2699 /* Software interrupts */
2700 struct desc_struct task_gate_desc;
2701 int dpl;
2702
2703 ret = read_interrupt_descriptor(ctxt, idt_index,
2704 &task_gate_desc);
2705 if (ret != X86EMUL_CONTINUE)
2706 return ret;
2707
2708 dpl = task_gate_desc.dpl;
2709 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2710 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2711 }
2712 } else if (reason != TASK_SWITCH_IRET) {
2713 int dpl = next_tss_desc.dpl;
2714 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2715 return emulate_gp(ctxt, tss_selector);
38ba30ba
GN		 2716 }
2717
7f3d35fd 2718
ceffb459
GN		 2719 desc_limit = desc_limit_scaled(&next_tss_desc);
2720 if (!next_tss_desc.p ||
2721 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2722 desc_limit < 0x2b)) {
54b8486f 2723 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2724 return X86EMUL_PROPAGATE_FAULT;
2725 }
2726
2727 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2728 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2729 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2730 }
2731
2732 if (reason == TASK_SWITCH_IRET)
2733 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2734
2735 /* set back link to prev task only if NT bit is set in eflags
fc058680 2736 note that old_tss_sel is not used after this point */
38ba30ba
GN		 2737 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2738 old_tss_sel = 0xffff;
2739
2740 if (next_tss_desc.type & 8)
7b105ca2 2741 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2742 old_tss_base, &next_tss_desc);
2743 else
7b105ca2 2744 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2745 old_tss_base, &next_tss_desc);
0760d448
JK		 2746 if (ret != X86EMUL_CONTINUE)
2747 return ret;
38ba30ba
GN		 2748
2749 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2750 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2751
2752 if (reason != TASK_SWITCH_IRET) {
2753 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2754 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2755 }
2756
717746e3 2757 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2758 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2759
e269fb21 2760 if (has_error_code) {
9dac77fa
AK		 2761 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2762 ctxt->lock_prefix = 0;
2763 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2764 ret = em_push(ctxt);
e269fb21
JK		 2765 }
2766
38ba30ba
GN		 2767 return ret;
2768}
2769
2770int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2771 u16 tss_selector, int idt_index, int reason,
e269fb21 2772 bool has_error_code, u32 error_code)
38ba30ba 2773{
38ba30ba
GN		 2774 int rc;
2775
dd856efa 2776 invalidate_registers(ctxt);
9dac77fa
AK		 2777 ctxt->_eip = ctxt->eip;
2778 ctxt->dst.type = OP_NONE;
38ba30ba 2779
7f3d35fd 2780 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 2781 has_error_code, error_code);
38ba30ba 2782
dd856efa 2783 if (rc == X86EMUL_CONTINUE) {
9dac77fa 2784 ctxt->eip = ctxt->_eip;
dd856efa
AK		 2785 writeback_registers(ctxt);
2786 }
38ba30ba 2787
a0c0ab2f 2788 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2789}
2790
f3bd64c6
GN		 2791static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
2792 struct operand *op)
a682e354 2793{
b3356bf0 2794 int df = (ctxt->eflags & EFLG_DF) ? -op->count : op->count;
a682e354 2795
dd856efa
AK		 2796 register_address_increment(ctxt, reg_rmw(ctxt, reg), df * op->bytes);
2797 op->addr.mem.ea = register_address(ctxt, reg_read(ctxt, reg));
a682e354
GN		 2798}
2799
7af04fc0
AK		 2800static int em_das(struct x86_emulate_ctxt *ctxt)
2801{
7af04fc0
AK		 2802 u8 al, old_al;
2803 bool af, cf, old_cf;
2804
2805 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2806 al = ctxt->dst.val;
7af04fc0
AK		 2807
2808 old_al = al;
2809 old_cf = cf;
2810 cf = false;
2811 af = ctxt->eflags & X86_EFLAGS_AF;
2812 if ((al & 0x0f) > 9 || af) {
2813 al -= 6;
2814 cf = old_cf | (al >= 250);
2815 af = true;
2816 } else {
2817 af = false;
2818 }
2819 if (old_al > 0x99 || old_cf) {
2820 al -= 0x60;
2821 cf = true;
2822 }
2823
9dac77fa 2824 ctxt->dst.val = al;
7af04fc0 2825 /* Set PF, ZF, SF */
9dac77fa
AK		 2826 ctxt->src.type = OP_IMM;
2827 ctxt->src.val = 0;
2828 ctxt->src.bytes = 1;
158de57f 2829 fastop(ctxt, em_or);
7af04fc0
AK		 2830 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2831 if (cf)
2832 ctxt->eflags |= X86_EFLAGS_CF;
2833 if (af)
2834 ctxt->eflags |= X86_EFLAGS_AF;
2835 return X86EMUL_CONTINUE;
2836}
2837
a035d5c6
PB		 2838static int em_aam(struct x86_emulate_ctxt *ctxt)
2839{
2840 u8 al, ah;
2841
2842 if (ctxt->src.val == 0)
2843 return emulate_de(ctxt);
2844
2845 al = ctxt->dst.val & 0xff;
2846 ah = al / ctxt->src.val;
2847 al %= ctxt->src.val;
2848
2849 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);
2850
2851 /* Set PF, ZF, SF */
2852 ctxt->src.type = OP_IMM;
2853 ctxt->src.val = 0;
2854 ctxt->src.bytes = 1;
2855 fastop(ctxt, em_or);
2856
2857 return X86EMUL_CONTINUE;
2858}
2859
7f662273
GN		 2860static int em_aad(struct x86_emulate_ctxt *ctxt)
2861{
2862 u8 al = ctxt->dst.val & 0xff;
2863 u8 ah = (ctxt->dst.val >> 8) & 0xff;
2864
2865 al = (al + (ah * ctxt->src.val)) & 0xff;
2866
2867 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
2868
f583c29b
GN		 2869 /* Set PF, ZF, SF */
2870 ctxt->src.type = OP_IMM;
2871 ctxt->src.val = 0;
2872 ctxt->src.bytes = 1;
2873 fastop(ctxt, em_or);
7f662273
GN		 2874
2875 return X86EMUL_CONTINUE;
2876}
2877
d4ddafcd
TY		 2878static int em_call(struct x86_emulate_ctxt *ctxt)
2879{
2880 long rel = ctxt->src.val;
2881
2882 ctxt->src.val = (unsigned long)ctxt->_eip;
2883 jmp_rel(ctxt, rel);
2884 return em_push(ctxt);
2885}
2886
0ef753b8
AK		 2887static int em_call_far(struct x86_emulate_ctxt *ctxt)
2888{
0ef753b8
AK		 2889 u16 sel, old_cs;
2890 ulong old_eip;
2891 int rc;
2892
1aa36616 2893 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
9dac77fa 2894 old_eip = ctxt->_eip;
0ef753b8 2895
9dac77fa 2896 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
7b105ca2 2897 if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS))
0ef753b8
AK		 2898 return X86EMUL_CONTINUE;
2899
9dac77fa
AK		 2900 ctxt->_eip = 0;
2901 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
0ef753b8 2902
9dac77fa 2903 ctxt->src.val = old_cs;
4487b3b4 2904 rc = em_push(ctxt);
0ef753b8
AK		 2905 if (rc != X86EMUL_CONTINUE)
2906 return rc;
2907
9dac77fa 2908 ctxt->src.val = old_eip;
4487b3b4 2909 return em_push(ctxt);
0ef753b8
AK		 2910}
2911
40ece7c7
AK		 2912static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2913{
40ece7c7
AK		 2914 int rc;
2915
9dac77fa
AK		 2916 ctxt->dst.type = OP_REG;
2917 ctxt->dst.addr.reg = &ctxt->_eip;
2918 ctxt->dst.bytes = ctxt->op_bytes;
2919 rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
40ece7c7
AK		 2920 if (rc != X86EMUL_CONTINUE)
2921 return rc;
5ad105e5 2922 rsp_increment(ctxt, ctxt->src.val);
40ece7c7
AK		 2923 return X86EMUL_CONTINUE;
2924}
2925
e4f973ae
TY		 2926static int em_xchg(struct x86_emulate_ctxt *ctxt)
2927{
e4f973ae 2928 /* Write back the register source. */
9dac77fa
AK		 2929 ctxt->src.val = ctxt->dst.val;
2930 write_register_operand(&ctxt->src);
e4f973ae
TY		 2931
2932 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 2933 ctxt->dst.val = ctxt->src.orig_val;
2934 ctxt->lock_prefix = 1;
e4f973ae
TY		 2935 return X86EMUL_CONTINUE;
2936}
2937
5c82aa29
AK		 2938static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2939{
9dac77fa 2940 ctxt->dst.val = ctxt->src2.val;
4d758349 2941 return fastop(ctxt, em_imul);
5c82aa29
AK		 2942}
2943
61429142
AK		 2944static int em_cwd(struct x86_emulate_ctxt *ctxt)
2945{
9dac77fa
AK		 2946 ctxt->dst.type = OP_REG;
2947 ctxt->dst.bytes = ctxt->src.bytes;
dd856efa 2948 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
9dac77fa 2949 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 2950
2951 return X86EMUL_CONTINUE;
2952}
2953
48bb5d3c
AK		 2954static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2955{
48bb5d3c
AK		 2956 u64 tsc = 0;
2957
717746e3 2958 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
dd856efa
AK		 2959 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
2960 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
48bb5d3c
AK		 2961 return X86EMUL_CONTINUE;
2962}
2963
222d21aa
AK		 2964static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
2965{
2966 u64 pmc;
2967
dd856efa 2968 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
222d21aa 2969 return emulate_gp(ctxt, 0);
dd856efa
AK		 2970 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
2971 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
222d21aa
AK		 2972 return X86EMUL_CONTINUE;
2973}
2974
b9eac5f4
AK		 2975static int em_mov(struct x86_emulate_ctxt *ctxt)
2976{
54cfdb3e 2977 memcpy(ctxt->dst.valptr, ctxt->src.valptr, sizeof(ctxt->src.valptr));
b9eac5f4
AK		 2978 return X86EMUL_CONTINUE;
2979}
2980
84cffe49
BP		 2981#define FFL(x) bit(X86_FEATURE_##x)
2982
2983static int em_movbe(struct x86_emulate_ctxt *ctxt)
2984{
2985 u32 ebx, ecx, edx, eax = 1;
2986 u16 tmp;
2987
2988 /*
2989 * Check MOVBE is set in the guest-visible CPUID leaf.
2990 */
2991 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2992 if (!(ecx & FFL(MOVBE)))
2993 return emulate_ud(ctxt);
2994
2995 switch (ctxt->op_bytes) {
2996 case 2:
2997 /*
2998 * From MOVBE definition: "...When the operand size is 16 bits,
2999 * the upper word of the destination register remains unchanged
3000 * ..."
3001 *
3002 * Both casting ->valptr and ->val to u16 breaks strict aliasing
3003 * rules so we have to do the operation almost per hand.
3004 */
3005 tmp = (u16)ctxt->src.val;
3006 ctxt->dst.val &= ~0xffffUL;
3007 ctxt->dst.val |= (unsigned long)swab16(tmp);
3008 break;
3009 case 4:
3010 ctxt->dst.val = swab32((u32)ctxt->src.val);
3011 break;
3012 case 8:
3013 ctxt->dst.val = swab64(ctxt->src.val);
3014 break;
3015 default:
3016 return X86EMUL_PROPAGATE_FAULT;
3017 }
3018 return X86EMUL_CONTINUE;
3019}
3020
bc00f8d2
TY		 3021static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3022{
3023 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
3024 return emulate_gp(ctxt, 0);
3025
3026 /* Disable writeback. */
3027 ctxt->dst.type = OP_NONE;
3028 return X86EMUL_CONTINUE;
3029}
3030
3031static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3032{
3033 unsigned long val;
3034
3035 if (ctxt->mode == X86EMUL_MODE_PROT64)
3036 val = ctxt->src.val & ~0ULL;
3037 else
3038 val = ctxt->src.val & ~0U;
3039
3040 /* #UD condition is already handled. */
3041 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3042 return emulate_gp(ctxt, 0);
3043
3044 /* Disable writeback. */
3045 ctxt->dst.type = OP_NONE;
3046 return X86EMUL_CONTINUE;
3047}
3048
e1e210b0
TY		 3049static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3050{
3051 u64 msr_data;
3052
dd856efa
AK		 3053 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3054 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3055 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
e1e210b0
TY		 3056 return emulate_gp(ctxt, 0);
3057
3058 return X86EMUL_CONTINUE;
3059}
3060
3061static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3062{
3063 u64 msr_data;
3064
dd856efa 3065 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
e1e210b0
TY		 3066 return emulate_gp(ctxt, 0);
3067
dd856efa
AK		 3068 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3069 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
e1e210b0
TY		 3070 return X86EMUL_CONTINUE;
3071}
3072
1bd5f469
TY		 3073static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3074{
9dac77fa 3075 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3076 return emulate_ud(ctxt);
3077
9dac77fa 3078 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
1bd5f469
TY		 3079 return X86EMUL_CONTINUE;
3080}
3081
3082static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3083{
9dac77fa 3084 u16 sel = ctxt->src.val;
1bd5f469 3085
9dac77fa 3086 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3087 return emulate_ud(ctxt);
3088
9dac77fa 3089 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 3090 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3091
3092 /* Disable writeback. */
9dac77fa
AK		 3093 ctxt->dst.type = OP_NONE;
3094 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 3095}
3096
a14e579f
AK		 3097static int em_lldt(struct x86_emulate_ctxt *ctxt)
3098{
3099 u16 sel = ctxt->src.val;
3100
3101 /* Disable writeback. */
3102 ctxt->dst.type = OP_NONE;
3103 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3104}
3105
80890006
AK		 3106static int em_ltr(struct x86_emulate_ctxt *ctxt)
3107{
3108 u16 sel = ctxt->src.val;
3109
3110 /* Disable writeback. */
3111 ctxt->dst.type = OP_NONE;
3112 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3113}
3114
38503911
AK		 3115static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3116{
9fa088f4
AK		 3117 int rc;
3118 ulong linear;
3119
9dac77fa 3120 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 3121 if (rc == X86EMUL_CONTINUE)
3cb16fe7 3122 ctxt->ops->invlpg(ctxt, linear);
38503911 3123 /* Disable writeback. */
9dac77fa 3124 ctxt->dst.type = OP_NONE;
38503911
AK		 3125 return X86EMUL_CONTINUE;
3126}
3127
2d04a05b
AK		 3128static int em_clts(struct x86_emulate_ctxt *ctxt)
3129{
3130 ulong cr0;
3131
3132 cr0 = ctxt->ops->get_cr(ctxt, 0);
3133 cr0 &= ~X86_CR0_TS;
3134 ctxt->ops->set_cr(ctxt, 0, cr0);
3135 return X86EMUL_CONTINUE;
3136}
3137
26d05cc7
AK		 3138static int em_vmcall(struct x86_emulate_ctxt *ctxt)
3139{
26d05cc7
AK		 3140 int rc;
3141
9dac77fa 3142 if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1)
26d05cc7
AK		 3143 return X86EMUL_UNHANDLEABLE;
3144
3145 rc = ctxt->ops->fix_hypercall(ctxt);
3146 if (rc != X86EMUL_CONTINUE)
3147 return rc;
3148
3149 /* Let the processor re-execute the fixed hypercall */
9dac77fa 3150 ctxt->_eip = ctxt->eip;
26d05cc7 3151 /* Disable writeback. */
9dac77fa 3152 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3153 return X86EMUL_CONTINUE;
3154}
3155
96051572
AK		 3156static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3157 void (*get)(struct x86_emulate_ctxt *ctxt,
3158 struct desc_ptr *ptr))
3159{
3160 struct desc_ptr desc_ptr;
3161
3162 if (ctxt->mode == X86EMUL_MODE_PROT64)
3163 ctxt->op_bytes = 8;
3164 get(ctxt, &desc_ptr);
3165 if (ctxt->op_bytes == 2) {
3166 ctxt->op_bytes = 4;
3167 desc_ptr.address &= 0x00ffffff;
3168 }
3169 /* Disable writeback. */
3170 ctxt->dst.type = OP_NONE;
3171 return segmented_write(ctxt, ctxt->dst.addr.mem,
3172 &desc_ptr, 2 + ctxt->op_bytes);
3173}
3174
3175static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3176{
3177 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3178}
3179
3180static int em_sidt(struct x86_emulate_ctxt *ctxt)
3181{
3182 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3183}
3184
26d05cc7
AK		 3185static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3186{
26d05cc7
AK		 3187 struct desc_ptr desc_ptr;
3188 int rc;
3189
510425ff
AK		 3190 if (ctxt->mode == X86EMUL_MODE_PROT64)
3191 ctxt->op_bytes = 8;
9dac77fa 3192 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3193 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3194 ctxt->op_bytes);
26d05cc7
AK		 3195 if (rc != X86EMUL_CONTINUE)
3196 return rc;
3197 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3198 /* Disable writeback. */
9dac77fa 3199 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3200 return X86EMUL_CONTINUE;
3201}
3202
5ef39c71 3203static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3204{
26d05cc7
AK		 3205 int rc;
3206
5ef39c71
AK		 3207 rc = ctxt->ops->fix_hypercall(ctxt);
3208
26d05cc7 3209 /* Disable writeback. */
9dac77fa 3210 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3211 return rc;
3212}
3213
3214static int em_lidt(struct x86_emulate_ctxt *ctxt)
3215{
26d05cc7
AK		 3216 struct desc_ptr desc_ptr;
3217 int rc;
3218
510425ff
AK		 3219 if (ctxt->mode == X86EMUL_MODE_PROT64)
3220 ctxt->op_bytes = 8;
9dac77fa 3221 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
509cf9fe 3222 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3223 ctxt->op_bytes);
26d05cc7
AK		 3224 if (rc != X86EMUL_CONTINUE)
3225 return rc;
3226 ctxt->ops->set_idt(ctxt, &desc_ptr);
3227 /* Disable writeback. */
9dac77fa 3228 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3229 return X86EMUL_CONTINUE;
3230}
3231
3232static int em_smsw(struct x86_emulate_ctxt *ctxt)
3233{
32e94d06
NA		 3234 if (ctxt->dst.type == OP_MEM)
3235 ctxt->dst.bytes = 2;
9dac77fa 3236 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3237 return X86EMUL_CONTINUE;
3238}
3239
3240static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3241{
26d05cc7 3242 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3243 | (ctxt->src.val & 0x0f));
3244 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3245 return X86EMUL_CONTINUE;
3246}
3247
d06e03ad
TY		 3248static int em_loop(struct x86_emulate_ctxt *ctxt)
3249{
dd856efa
AK		 3250 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX), -1);
3251 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
9dac77fa
AK		 3252 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
3253 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3254
3255 return X86EMUL_CONTINUE;
3256}
3257
3258static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3259{
dd856efa 3260 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
9dac77fa 3261 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3262
3263 return X86EMUL_CONTINUE;
3264}
3265
d7841a4b
TY		 3266static int em_in(struct x86_emulate_ctxt *ctxt)
3267{
3268 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3269 &ctxt->dst.val))
3270 return X86EMUL_IO_NEEDED;
3271
3272 return X86EMUL_CONTINUE;
3273}
3274
3275static int em_out(struct x86_emulate_ctxt *ctxt)
3276{
3277 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3278 &ctxt->src.val, 1);
3279 /* Disable writeback. */
3280 ctxt->dst.type = OP_NONE;
3281 return X86EMUL_CONTINUE;
3282}
3283
f411e6cd
TY		 3284static int em_cli(struct x86_emulate_ctxt *ctxt)
3285{
3286 if (emulator_bad_iopl(ctxt))
3287 return emulate_gp(ctxt, 0);
3288
3289 ctxt->eflags &= ~X86_EFLAGS_IF;
3290 return X86EMUL_CONTINUE;
3291}
3292
3293static int em_sti(struct x86_emulate_ctxt *ctxt)
3294{
3295 if (emulator_bad_iopl(ctxt))
3296 return emulate_gp(ctxt, 0);
3297
3298 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3299 ctxt->eflags |= X86_EFLAGS_IF;
3300 return X86EMUL_CONTINUE;
3301}
3302
6d6eede4
AK		 3303static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3304{
3305 u32 eax, ebx, ecx, edx;
3306
dd856efa
AK		 3307 eax = reg_read(ctxt, VCPU_REGS_RAX);
3308 ecx = reg_read(ctxt, VCPU_REGS_RCX);
6d6eede4 3309 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
dd856efa
AK		 3310 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3311 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3312 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3313 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
6d6eede4
AK		 3314 return X86EMUL_CONTINUE;
3315}
3316
98f73630
PB		 3317static int em_sahf(struct x86_emulate_ctxt *ctxt)
3318{
3319 u32 flags;
3320
3321 flags = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF;
3322 flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8;
3323
3324 ctxt->eflags &= ~0xffUL;
3325 ctxt->eflags |= flags | X86_EFLAGS_FIXED;
3326 return X86EMUL_CONTINUE;
3327}
3328
2dd7caa0
AK		 3329static int em_lahf(struct x86_emulate_ctxt *ctxt)
3330{
dd856efa
AK		 3331 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3332 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
2dd7caa0
AK		 3333 return X86EMUL_CONTINUE;
3334}
3335
9299836e
AK		 3336static int em_bswap(struct x86_emulate_ctxt *ctxt)
3337{
3338 switch (ctxt->op_bytes) {
3339#ifdef CONFIG_X86_64
3340 case 8:
3341 asm("bswap %0" : "+r"(ctxt->dst.val));
3342 break;
3343#endif
3344 default:
3345 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3346 break;
3347 }
3348 return X86EMUL_CONTINUE;
3349}
3350
cfec82cb
JR		 3351static bool valid_cr(int nr)
3352{
3353 switch (nr) {
3354 case 0:
3355 case 2 ... 4:
3356 case 8:
3357 return true;
3358 default:
3359 return false;
3360 }
3361}
3362
3363static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3364{
9dac77fa 3365 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 3366 return emulate_ud(ctxt);
3367
3368 return X86EMUL_CONTINUE;
3369}
3370
3371static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3372{
9dac77fa
AK		 3373 u64 new_val = ctxt->src.val64;
3374 int cr = ctxt->modrm_reg;
c2ad2bb3 3375 u64 efer = 0;
cfec82cb
JR		 3376
3377 static u64 cr_reserved_bits[] = {
3378 0xffffffff00000000ULL,
3379 0, 0, 0, /* CR3 checked later */
3380 CR4_RESERVED_BITS,
3381 0, 0, 0,
3382 CR8_RESERVED_BITS,
3383 };
3384
3385 if (!valid_cr(cr))
3386 return emulate_ud(ctxt);
3387
3388 if (new_val & cr_reserved_bits[cr])
3389 return emulate_gp(ctxt, 0);
3390
3391 switch (cr) {
3392 case 0: {
c2ad2bb3 3393 u64 cr4;
cfec82cb
JR		 3394 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3395 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3396 return emulate_gp(ctxt, 0);
3397
717746e3
AK		 3398 cr4 = ctxt->ops->get_cr(ctxt, 4);
3399 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3400
3401 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3402 !(cr4 & X86_CR4_PAE))
3403 return emulate_gp(ctxt, 0);
3404
3405 break;
3406 }
3407 case 3: {
3408 u64 rsvd = 0;
3409
c2ad2bb3
AK		 3410 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3411 if (efer & EFER_LMA)
cfec82cb 3412 rsvd = CR3_L_MODE_RESERVED_BITS;
cfec82cb
JR		 3413
3414 if (new_val & rsvd)
3415 return emulate_gp(ctxt, 0);
3416
3417 break;
3418 }
3419 case 4: {
717746e3 3420 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3421
3422 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3423 return emulate_gp(ctxt, 0);
3424
3425 break;
3426 }
3427 }
3428
3429 return X86EMUL_CONTINUE;
3430}
3431
3b88e41a
JR		 3432static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3433{
3434 unsigned long dr7;
3435
717746e3 3436 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 3437
3438 /* Check if DR7.Global_Enable is set */
3439 return dr7 & (1 << 13);
3440}
3441
3442static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3443{
9dac77fa 3444 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3445 u64 cr4;
3446
3447 if (dr > 7)
3448 return emulate_ud(ctxt);
3449
717746e3 3450 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 3451 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3452 return emulate_ud(ctxt);
3453
3454 if (check_dr7_gd(ctxt))
3455 return emulate_db(ctxt);
3456
3457 return X86EMUL_CONTINUE;
3458}
3459
3460static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3461{
9dac77fa
AK		 3462 u64 new_val = ctxt->src.val64;
3463 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3464
3465 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3466 return emulate_gp(ctxt, 0);
3467
3468 return check_dr_read(ctxt);
3469}
3470
01de8b09
JR		 3471static int check_svme(struct x86_emulate_ctxt *ctxt)
3472{
3473 u64 efer;
3474
717746e3 3475 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 3476
3477 if (!(efer & EFER_SVME))
3478 return emulate_ud(ctxt);
3479
3480 return X86EMUL_CONTINUE;
3481}
3482
3483static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3484{
dd856efa 3485 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
01de8b09
JR		 3486
3487 /* Valid physical address? */
d4224449 3488 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 3489 return emulate_gp(ctxt, 0);
3490
3491 return check_svme(ctxt);
3492}
3493
d7eb8203
JR		 3494static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3495{
717746e3 3496 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 3497
717746e3 3498 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 3499 return emulate_ud(ctxt);
3500
3501 return X86EMUL_CONTINUE;
3502}
3503
8061252e
JR		 3504static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3505{
717746e3 3506 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
dd856efa 3507 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
8061252e 3508
717746e3 3509 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
67f4d428 3510 ctxt->ops->check_pmc(ctxt, rcx))
8061252e
JR		 3511 return emulate_gp(ctxt, 0);
3512
3513 return X86EMUL_CONTINUE;
3514}
3515
f6511935
JR		 3516static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3517{
9dac77fa
AK		 3518 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3519 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 3520 return emulate_gp(ctxt, 0);
3521
3522 return X86EMUL_CONTINUE;
3523}
3524
3525static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3526{
9dac77fa
AK		 3527 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3528 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 3529 return emulate_gp(ctxt, 0);
3530
3531 return X86EMUL_CONTINUE;
3532}
3533
73fba5f4 3534#define D(_y) { .flags = (_y) }
d40a6898
PB		 3535#define DI(_y, _i) { .flags = (_y)|Intercept, .intercept = x86_intercept_##_i }
3536#define DIP(_y, _i, _p) { .flags = (_y)|Intercept|CheckPerm, \
3537 .intercept = x86_intercept_##_i, .check_perm = (_p) }
0b789eee 3538#define N D(NotImpl)
01de8b09 3539#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 3540#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3541#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
045a282c 3542#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
73fba5f4 3543#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
e28bbd44 3544#define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
c4f035c6 3545#define II(_f, _e, _i) \
d40a6898 3546 { .flags = (_f)|Intercept, .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd 3547#define IIP(_f, _e, _i, _p) \
d40a6898
PB		 3548 { .flags = (_f)|Intercept|CheckPerm, .u.execute = (_e), \
3549 .intercept = x86_intercept_##_i, .check_perm = (_p) }
aa97bb48 3550#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3551
8d8f4e9f 3552#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3553#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 3554#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
f7857f35 3555#define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e)
d7841a4b
TY		 3556#define I2bvIP(_f, _e, _i, _p) \
3557 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 3558
fb864fbc
AK		 3559#define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3560 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3561 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3562
fd0a0d82 3563static const struct opcode group7_rm1[] = {
1c2545be
TY		 3564 DI(SrcNone | Priv, monitor),
3565 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 3566 N, N, N, N, N, N,
3567};
3568
fd0a0d82 3569static const struct opcode group7_rm3[] = {
1c2545be 3570 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
b51e974f 3571 II(SrcNone | Prot | EmulateOnUD, em_vmmcall, vmmcall),
1c2545be
TY		 3572 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3573 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3574 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3575 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3576 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3577 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 3578};
6230f7fc 3579
fd0a0d82 3580static const struct opcode group7_rm7[] = {
d7eb8203 3581 N,
1c2545be 3582 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 3583 N, N, N, N, N, N,
3584};
d67fc27a 3585
fd0a0d82 3586static const struct opcode group1[] = {
fb864fbc
AK		 3587 F(Lock, em_add),
3588 F(Lock | PageTable, em_or),
3589 F(Lock, em_adc),
3590 F(Lock, em_sbb),
3591 F(Lock | PageTable, em_and),
3592 F(Lock, em_sub),
3593 F(Lock, em_xor),
3594 F(NoWrite, em_cmp),
73fba5f4
AK		 3595};
3596
fd0a0d82 3597static const struct opcode group1A[] = {
1c2545be 3598 I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 3599};
3600
007a3b54
AK		 3601static const struct opcode group2[] = {
3602 F(DstMem | ModRM, em_rol),
3603 F(DstMem | ModRM, em_ror),
3604 F(DstMem | ModRM, em_rcl),
3605 F(DstMem | ModRM, em_rcr),
3606 F(DstMem | ModRM, em_shl),
3607 F(DstMem | ModRM, em_shr),
3608 F(DstMem | ModRM, em_shl),
3609 F(DstMem | ModRM, em_sar),
3610};
3611
fd0a0d82 3612static const struct opcode group3[] = {
fb864fbc
AK		 3613 F(DstMem | SrcImm | NoWrite, em_test),
3614 F(DstMem | SrcImm | NoWrite, em_test),
45a1467d
AK		 3615 F(DstMem | SrcNone | Lock, em_not),
3616 F(DstMem | SrcNone | Lock, em_neg),
b9fa409b
AK		 3617 F(DstXacc | Src2Mem, em_mul_ex),
3618 F(DstXacc | Src2Mem, em_imul_ex),
b8c0b6ae
AK		 3619 F(DstXacc | Src2Mem, em_div_ex),
3620 F(DstXacc | Src2Mem, em_idiv_ex),
73fba5f4
AK		 3621};
3622
fd0a0d82 3623static const struct opcode group4[] = {
95413dc4
AK		 3624 F(ByteOp | DstMem | SrcNone | Lock, em_inc),
3625 F(ByteOp | DstMem | SrcNone | Lock, em_dec),
73fba5f4
AK		 3626 N, N, N, N, N, N,
3627};
3628
fd0a0d82 3629static const struct opcode group5[] = {
95413dc4
AK		 3630 F(DstMem | SrcNone | Lock, em_inc),
3631 F(DstMem | SrcNone | Lock, em_dec),
1c2545be
TY		 3632 I(SrcMem | Stack, em_grp45),
3633 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far),
3634 I(SrcMem | Stack, em_grp45),
3635 I(SrcMemFAddr | ImplicitOps, em_grp45),
188424ba 3636 I(SrcMem | Stack, em_grp45), D(Undefined),
73fba5f4
AK		 3637};
3638
fd0a0d82 3639static const struct opcode group6[] = {
1c2545be
TY		 3640 DI(Prot, sldt),
3641 DI(Prot, str),
a14e579f 3642 II(Prot | Priv | SrcMem16, em_lldt, lldt),
80890006 3643 II(Prot | Priv | SrcMem16, em_ltr, ltr),
dee6bb70
JR		 3644 N, N, N, N,
3645};
3646
fd0a0d82 3647static const struct group_dual group7 = { {
606b1c3e
NA		 3648 II(Mov | DstMem, em_sgdt, sgdt),
3649 II(Mov | DstMem, em_sidt, sidt),
1c2545be
TY		 3650 II(SrcMem | Priv, em_lgdt, lgdt),
3651 II(SrcMem | Priv, em_lidt, lidt),
3652 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3653 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3654 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3655}, {
b51e974f 3656 I(SrcNone | Priv | EmulateOnUD, em_vmcall),
5ef39c71 3657 EXT(0, group7_rm1),
01de8b09 3658 N, EXT(0, group7_rm3),
1c2545be
TY		 3659 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3660 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3661 EXT(0, group7_rm7),
73fba5f4
AK		 3662} };
3663
fd0a0d82 3664static const struct opcode group8[] = {
73fba5f4 3665 N, N, N, N,
11c363ba
AK		 3666 F(DstMem | SrcImmByte | NoWrite, em_bt),
3667 F(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3668 F(DstMem | SrcImmByte | Lock, em_btr),
3669 F(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 3670};
3671
fd0a0d82 3672static const struct group_dual group9 = { {
1c2545be 3673 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 3674}, {
3675 N, N, N, N, N, N, N, N,
3676} };
3677
fd0a0d82 3678static const struct opcode group11[] = {
1c2545be 3679 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 3680 X7(D(Undefined)),
a4d4a7c1
AK		 3681};
3682
fd0a0d82 3683static const struct gprefix pfx_0f_6f_0f_7f = {
e5971755 3684 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 3685};
3686
fd0a0d82 3687static const struct gprefix pfx_vmovntpx = {
3e114eb4
AK		 3688 I(0, em_mov), N, N, N,
3689};
3690
27ce8258 3691static const struct gprefix pfx_0f_28_0f_29 = {
6fec27d8 3692 I(Aligned, em_mov), I(Aligned, em_mov), N, N,
27ce8258
IM		 3693};
3694
045a282c
GN		 3695static const struct escape escape_d9 = { {
3696 N, N, N, N, N, N, N, I(DstMem, em_fnstcw),
3697}, {
3698 /* 0xC0 - 0xC7 */
3699 N, N, N, N, N, N, N, N,
3700 /* 0xC8 - 0xCF */
3701 N, N, N, N, N, N, N, N,
3702 /* 0xD0 - 0xC7 */
3703 N, N, N, N, N, N, N, N,
3704 /* 0xD8 - 0xDF */
3705 N, N, N, N, N, N, N, N,
3706 /* 0xE0 - 0xE7 */
3707 N, N, N, N, N, N, N, N,
3708 /* 0xE8 - 0xEF */
3709 N, N, N, N, N, N, N, N,
3710 /* 0xF0 - 0xF7 */
3711 N, N, N, N, N, N, N, N,
3712 /* 0xF8 - 0xFF */
3713 N, N, N, N, N, N, N, N,
3714} };
3715
3716static const struct escape escape_db = { {
3717 N, N, N, N, N, N, N, N,
3718}, {
3719 /* 0xC0 - 0xC7 */
3720 N, N, N, N, N, N, N, N,
3721 /* 0xC8 - 0xCF */
3722 N, N, N, N, N, N, N, N,
3723 /* 0xD0 - 0xC7 */
3724 N, N, N, N, N, N, N, N,
3725 /* 0xD8 - 0xDF */
3726 N, N, N, N, N, N, N, N,
3727 /* 0xE0 - 0xE7 */
3728 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
3729 /* 0xE8 - 0xEF */
3730 N, N, N, N, N, N, N, N,
3731 /* 0xF0 - 0xF7 */
3732 N, N, N, N, N, N, N, N,
3733 /* 0xF8 - 0xFF */
3734 N, N, N, N, N, N, N, N,
3735} };
3736
3737static const struct escape escape_dd = { {
3738 N, N, N, N, N, N, N, I(DstMem, em_fnstsw),
3739}, {
3740 /* 0xC0 - 0xC7 */
3741 N, N, N, N, N, N, N, N,
3742 /* 0xC8 - 0xCF */
3743 N, N, N, N, N, N, N, N,
3744 /* 0xD0 - 0xC7 */
3745 N, N, N, N, N, N, N, N,
3746 /* 0xD8 - 0xDF */
3747 N, N, N, N, N, N, N, N,
3748 /* 0xE0 - 0xE7 */
3749 N, N, N, N, N, N, N, N,
3750 /* 0xE8 - 0xEF */
3751 N, N, N, N, N, N, N, N,
3752 /* 0xF0 - 0xF7 */
3753 N, N, N, N, N, N, N, N,
3754 /* 0xF8 - 0xFF */
3755 N, N, N, N, N, N, N, N,
3756} };
3757
fd0a0d82 3758static const struct opcode opcode_table[256] = {
73fba5f4 3759 /* 0x00 - 0x07 */
fb864fbc 3760 F6ALU(Lock, em_add),
1cd196ea
AK		 3761 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3762 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 3763 /* 0x08 - 0x0F */
fb864fbc 3764 F6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 3765 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3766 N,
73fba5f4 3767 /* 0x10 - 0x17 */
fb864fbc 3768 F6ALU(Lock, em_adc),
1cd196ea
AK		 3769 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3770 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 3771 /* 0x18 - 0x1F */
fb864fbc 3772 F6ALU(Lock, em_sbb),
1cd196ea
AK		 3773 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3774 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 3775 /* 0x20 - 0x27 */
fb864fbc 3776 F6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 3777 /* 0x28 - 0x2F */
fb864fbc 3778 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3779 /* 0x30 - 0x37 */
fb864fbc 3780 F6ALU(Lock, em_xor), N, N,
73fba5f4 3781 /* 0x38 - 0x3F */
fb864fbc 3782 F6ALU(NoWrite, em_cmp), N, N,
73fba5f4 3783 /* 0x40 - 0x4F */
95413dc4 3784 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
73fba5f4 3785 /* 0x50 - 0x57 */
63540382 3786 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3787 /* 0x58 - 0x5F */
c54fe504 3788 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3789 /* 0x60 - 0x67 */
b96a7fad
TY		 3790 I(ImplicitOps | Stack | No64, em_pusha),
3791 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3792 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3793 N, N, N, N,
3794 /* 0x68 - 0x6F */
d46164db
AK		 3795 I(SrcImm | Mov | Stack, em_push),
3796 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3797 I(SrcImmByte | Mov | Stack, em_push),
3798 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
b3356bf0 3799 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
2b5e97e1 3800 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4
AK		 3801 /* 0x70 - 0x7F */
3802 X16(D(SrcImmByte)),
3803 /* 0x80 - 0x87 */
1c2545be
TY		 3804 G(ByteOp | DstMem | SrcImm, group1),
3805 G(DstMem | SrcImm, group1),
3806 G(ByteOp | DstMem | SrcImm | No64, group1),
3807 G(DstMem | SrcImmByte, group1),
fb864fbc 3808 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
d5ae7ce8 3809 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 3810 /* 0x88 - 0x8F */
d5ae7ce8 3811 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 3812 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 3813 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 3814 D(ModRM | SrcMem | NoAccess | DstReg),
3815 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3816 G(0, group1A),
73fba5f4 3817 /* 0x90 - 0x97 */
bf608f88 3818 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3819 /* 0x98 - 0x9F */
61429142 3820 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3821 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0 3822 II(ImplicitOps | Stack, em_pushf, pushf),
98f73630
PB		 3823 II(ImplicitOps | Stack, em_popf, popf),
3824 I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf),
73fba5f4 3825 /* 0xA0 - 0xA7 */
b9eac5f4 3826 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 3827 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 3828 I2bv(SrcSI | DstDI | Mov | String, em_mov),
fb864fbc 3829 F2bv(SrcSI | DstDI | String | NoWrite, em_cmp),
73fba5f4 3830 /* 0xA8 - 0xAF */
fb864fbc 3831 F2bv(DstAcc | SrcImm | NoWrite, em_test),
b9eac5f4
AK		 3832 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3833 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
fb864fbc 3834 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp),
73fba5f4 3835 /* 0xB0 - 0xB7 */
b9eac5f4 3836 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3837 /* 0xB8 - 0xBF */
5e2c6883 3838 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
73fba5f4 3839 /* 0xC0 - 0xC7 */
007a3b54 3840 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
40ece7c7 3841 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
ebda02c2 3842 I(ImplicitOps | Stack, em_ret),
d4b4325f
AK		 3843 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
3844 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 3845 G(ByteOp, group11), G(0, group11),
73fba5f4 3846 /* 0xC8 - 0xCF */
612e89f0 3847 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
3261107e
BR		 3848 I(ImplicitOps | Stack | SrcImmU16, em_ret_far_imm),
3849 I(ImplicitOps | Stack, em_ret_far),
3c6e276f 3850 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 3851 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 3852 /* 0xD0 - 0xD7 */
007a3b54
AK		 3853 G(Src2One | ByteOp, group2), G(Src2One, group2),
3854 G(Src2CL | ByteOp, group2), G(Src2CL, group2),
a035d5c6 3855 I(DstAcc | SrcImmUByte | No64, em_aam),
326f578f
PB		 3856 I(DstAcc | SrcImmUByte | No64, em_aad),
3857 F(DstAcc | ByteOp | No64, em_salc),
7fa57952 3858 I(DstAcc | SrcXLat | ByteOp, em_mov),
73fba5f4 3859 /* 0xD8 - 0xDF */
045a282c 3860 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
73fba5f4 3861 /* 0xE0 - 0xE7 */
d06e03ad
TY		 3862 X3(I(SrcImmByte, em_loop)),
3863 I(SrcImmByte, em_jcxz),
d7841a4b
TY		 3864 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
3865 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 3866 /* 0xE8 - 0xEF */
d4ddafcd 3867 I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps),
db5b0762 3868 I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
d7841a4b
TY		 3869 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
3870 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 3871 /* 0xF0 - 0xF7 */
bf608f88 3872 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 3873 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3874 G(ByteOp, group3), G(0, group3),
73fba5f4 3875 /* 0xF8 - 0xFF */
f411e6cd
TY		 3876 D(ImplicitOps), D(ImplicitOps),
3877 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 3878 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3879};
3880
fd0a0d82 3881static const struct opcode twobyte_table[256] = {
73fba5f4 3882 /* 0x00 - 0x0F */
dee6bb70 3883 G(0, group6), GD(0, &group7), N, N,
b51e974f 3884 N, I(ImplicitOps | EmulateOnUD, em_syscall),
db5b0762 3885 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 3886 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK		 3887 N, D(ImplicitOps | ModRM), N, N,
3888 /* 0x10 - 0x1F */
103f98ea
PB		 3889 N, N, N, N, N, N, N, N,
3890 D(ImplicitOps | ModRM), N, N, N, N, N, N, D(ImplicitOps | ModRM),
73fba5f4 3891 /* 0x20 - 0x2F */
9b88ae99
NA		 3892 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_read),
3893 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read),
3894 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write,
3895 check_cr_write),
3896 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write,
3897 check_dr_write),
73fba5f4 3898 N, N, N, N,
27ce8258
IM		 3899 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29),
3900 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29),
3901 N, GP(ModRM | DstMem | SrcReg | Sse | Mov | Aligned, &pfx_vmovntpx),
3e114eb4 3902 N, N, N, N,
73fba5f4 3903 /* 0x30 - 0x3F */
e1e210b0 3904 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 3905 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 3906 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 3907 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
b51e974f
BP		 3908 I(ImplicitOps | EmulateOnUD, em_sysenter),
3909 I(ImplicitOps | Priv | EmulateOnUD, em_sysexit),
d867162c 3910 N, N,
73fba5f4
AK		 3911 N, N, N, N, N, N, N, N,
3912 /* 0x40 - 0x4F */
140bad89 3913 X16(D(DstReg | SrcMem | ModRM)),
73fba5f4
AK		 3914 /* 0x50 - 0x5F */
3915 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3916 /* 0x60 - 0x6F */
aa97bb48
AK		 3917 N, N, N, N,
3918 N, N, N, N,
3919 N, N, N, N,
3920 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 3921 /* 0x70 - 0x7F */
aa97bb48
AK		 3922 N, N, N, N,
3923 N, N, N, N,
3924 N, N, N, N,
3925 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK		 3926 /* 0x80 - 0x8F */
3927 X16(D(SrcImm)),
3928 /* 0x90 - 0x9F */
ee45b58e 3929 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 3930 /* 0xA0 - 0xA7 */
1cd196ea 3931 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
11c363ba
AK		 3932 II(ImplicitOps, em_cpuid, cpuid),
3933 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
0bdea068
AK		 3934 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
3935 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
73fba5f4 3936 /* 0xA8 - 0xAF */
1cd196ea 3937 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
d5ae7ce8 3938 DI(ImplicitOps, rsm),
11c363ba 3939 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
0bdea068
AK		 3940 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
3941 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
4d758349 3942 D(ModRM), F(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 3943 /* 0xB0 - 0xB7 */
e940b5c2 3944 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
d4b4325f 3945 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
11c363ba 3946 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 3947 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
3948 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 3949 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 3950 /* 0xB8 - 0xBF */
3951 N, N,
ce7faab2 3952 G(BitOp, group8),
11c363ba
AK		 3953 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
3954 F(DstReg | SrcMem | ModRM, em_bsf), F(DstReg | SrcMem | ModRM, em_bsr),
2adb5ad9 3955 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
9299836e 3956 /* 0xC0 - 0xC7 */
e47a5f5f 3957 F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd),
92f738a5 3958 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4 3959 N, N, N, GD(0, &group9),
9299836e
AK		 3960 /* 0xC8 - 0xCF */
3961 X8(I(DstReg, em_bswap)),
73fba5f4
AK		 3962 /* 0xD0 - 0xDF */
3963 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3964 /* 0xE0 - 0xEF */
3965 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3966 /* 0xF0 - 0xFF */
3967 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
3968};
3969
0bc5eedb 3970static const struct gprefix three_byte_0f_38_f0 = {
84cffe49 3971 I(DstReg | SrcMem | Mov, em_movbe), N, N, N
0bc5eedb
BP		 3972};
3973
3974static const struct gprefix three_byte_0f_38_f1 = {
84cffe49 3975 I(DstMem | SrcReg | Mov, em_movbe), N, N, N
0bc5eedb
BP		 3976};
3977
3978/*
3979 * Insns below are selected by the prefix which indexed by the third opcode
3980 * byte.
3981 */
3982static const struct opcode opcode_map_0f_38[256] = {
3983 /* 0x00 - 0x7f */
3984 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
84cffe49
BP		 3985 /* 0x80 - 0xef */
3986 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
3987 /* 0xf0 - 0xf1 */
3988 GP(EmulateOnUD | ModRM | Prefix, &three_byte_0f_38_f0),
3989 GP(EmulateOnUD | ModRM | Prefix, &three_byte_0f_38_f1),
3990 /* 0xf2 - 0xff */
3991 N, N, X4(N), X8(N)
0bc5eedb
BP		 3992};
3993
73fba5f4
AK		 3994#undef D
3995#undef N
3996#undef G
3997#undef GD
3998#undef I
aa97bb48 3999#undef GP
01de8b09 4000#undef EXT
73fba5f4 4001
8d8f4e9f 4002#undef D2bv
f6511935 4003#undef D2bvIP
8d8f4e9f 4004#undef I2bv
d7841a4b 4005#undef I2bvIP
d67fc27a 4006#undef I6ALU
8d8f4e9f 4007
9dac77fa 4008static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 4009{
4010 unsigned size;
4011
9dac77fa 4012 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 4013 if (size == 8)
4014 size = 4;
4015 return size;
4016}
4017
4018static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
4019 unsigned size, bool sign_extension)
4020{
39f21ee5
AK		 4021 int rc = X86EMUL_CONTINUE;
4022
4023 op->type = OP_IMM;
4024 op->bytes = size;
9dac77fa 4025 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 4026 /* NB. Immediates are sign-extended as necessary. */
4027 switch (op->bytes) {
4028 case 1:
e85a1085 4029 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 4030 break;
4031 case 2:
e85a1085 4032 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 4033 break;
4034 case 4:
e85a1085 4035 op->val = insn_fetch(s32, ctxt);
39f21ee5 4036 break;
5e2c6883
NA		 4037 case 8:
4038 op->val = insn_fetch(s64, ctxt);
4039 break;
39f21ee5
AK		 4040 }
4041 if (!sign_extension) {
4042 switch (op->bytes) {
4043 case 1:
4044 op->val &= 0xff;
4045 break;
4046 case 2:
4047 op->val &= 0xffff;
4048 break;
4049 case 4:
4050 op->val &= 0xffffffff;
4051 break;
4052 }
4053 }
4054done:
4055 return rc;
4056}
4057
a9945549
AK		 4058static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
4059 unsigned d)
4060{
4061 int rc = X86EMUL_CONTINUE;
4062
4063 switch (d) {
4064 case OpReg:
2adb5ad9 4065 decode_register_operand(ctxt, op);
a9945549
AK		 4066 break;
4067 case OpImmUByte:
608aabe3 4068 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 4069 break;
4070 case OpMem:
41ddf978 4071 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 4072 mem_common:
4073 *op = ctxt->memop;
4074 ctxt->memopp = op;
96888977 4075 if (ctxt->d & BitOp)
a9945549
AK		 4076 fetch_bit_operand(ctxt);
4077 op->orig_val = op->val;
4078 break;
41ddf978 4079 case OpMem64:
aaa05f24 4080 ctxt->memop.bytes = (ctxt->op_bytes == 8) ? 16 : 8;
41ddf978 4081 goto mem_common;
a9945549
AK		 4082 case OpAcc:
4083 op->type = OP_REG;
4084 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 4085 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
a9945549
AK		 4086 fetch_register_operand(op);
4087 op->orig_val = op->val;
4088 break;
820207c8
AK		 4089 case OpAccLo:
4090 op->type = OP_REG;
4091 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes;
4092 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4093 fetch_register_operand(op);
4094 op->orig_val = op->val;
4095 break;
4096 case OpAccHi:
4097 if (ctxt->d & ByteOp) {
4098 op->type = OP_NONE;
4099 break;
4100 }
4101 op->type = OP_REG;
4102 op->bytes = ctxt->op_bytes;
4103 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4104 fetch_register_operand(op);
4105 op->orig_val = op->val;
4106 break;
a9945549
AK		 4107 case OpDI:
4108 op->type = OP_MEM;
4109 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4110 op->addr.mem.ea =
dd856efa 4111 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RDI));
a9945549
AK		 4112 op->addr.mem.seg = VCPU_SREG_ES;
4113 op->val = 0;
b3356bf0 4114 op->count = 1;
a9945549
AK		 4115 break;
4116 case OpDX:
4117 op->type = OP_REG;
4118 op->bytes = 2;
dd856efa 4119 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
a9945549
AK		 4120 fetch_register_operand(op);
4121 break;
4dd6a57d
AK		 4122 case OpCL:
4123 op->bytes = 1;
dd856efa 4124 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4dd6a57d
AK		 4125 break;
4126 case OpImmByte:
4127 rc = decode_imm(ctxt, op, 1, true);
4128 break;
4129 case OpOne:
4130 op->bytes = 1;
4131 op->val = 1;
4132 break;
4133 case OpImm:
4134 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4135 break;
5e2c6883
NA		 4136 case OpImm64:
4137 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
4138 break;
28867cee
AK		 4139 case OpMem8:
4140 ctxt->memop.bytes = 1;
660696d1 4141 if (ctxt->memop.type == OP_REG) {
aa9ac1a6
GN		 4142 ctxt->memop.addr.reg = decode_register(ctxt,
4143 ctxt->modrm_rm, true);
660696d1
GN		 4144 fetch_register_operand(&ctxt->memop);
4145 }
28867cee 4146 goto mem_common;
0fe59128
AK		 4147 case OpMem16:
4148 ctxt->memop.bytes = 2;
4149 goto mem_common;
4150 case OpMem32:
4151 ctxt->memop.bytes = 4;
4152 goto mem_common;
4153 case OpImmU16:
4154 rc = decode_imm(ctxt, op, 2, false);
4155 break;
4156 case OpImmU:
4157 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
4158 break;
4159 case OpSI:
4160 op->type = OP_MEM;
4161 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4162 op->addr.mem.ea =
dd856efa 4163 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RSI));
573e80fe 4164 op->addr.mem.seg = ctxt->seg_override;
0fe59128 4165 op->val = 0;
b3356bf0 4166 op->count = 1;
0fe59128 4167 break;
7fa57952
PB		 4168 case OpXLat:
4169 op->type = OP_MEM;
4170 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4171 op->addr.mem.ea =
4172 register_address(ctxt,
4173 reg_read(ctxt, VCPU_REGS_RBX) +
4174 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
573e80fe 4175 op->addr.mem.seg = ctxt->seg_override;
7fa57952
PB		 4176 op->val = 0;
4177 break;
0fe59128
AK		 4178 case OpImmFAddr:
4179 op->type = OP_IMM;
4180 op->addr.mem.ea = ctxt->_eip;
4181 op->bytes = ctxt->op_bytes + 2;
4182 insn_fetch_arr(op->valptr, op->bytes, ctxt);
4183 break;
4184 case OpMemFAddr:
4185 ctxt->memop.bytes = ctxt->op_bytes + 2;
4186 goto mem_common;
c191a7a0
AK		 4187 case OpES:
4188 op->val = VCPU_SREG_ES;
4189 break;
4190 case OpCS:
4191 op->val = VCPU_SREG_CS;
4192 break;
4193 case OpSS:
4194 op->val = VCPU_SREG_SS;
4195 break;
4196 case OpDS:
4197 op->val = VCPU_SREG_DS;
4198 break;
4199 case OpFS:
4200 op->val = VCPU_SREG_FS;
4201 break;
4202 case OpGS:
4203 op->val = VCPU_SREG_GS;
4204 break;
a9945549
AK		 4205 case OpImplicit:
4206 /* Special instructions do their own operand decoding. */
4207 default:
4208 op->type = OP_NONE; /* Disable writeback. */
4209 break;
4210 }
4211
4212done:
4213 return rc;
4214}
4215
ef5d75cc 4216int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 4217{
dde7e6d1
AK		 4218 int rc = X86EMUL_CONTINUE;
4219 int mode = ctxt->mode;
46561646 4220 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 4221 bool op_prefix = false;
573e80fe 4222 bool has_seg_override = false;
46561646 4223 struct opcode opcode;
dde7e6d1 4224
f09ed83e
AK		 4225 ctxt->memop.type = OP_NONE;
4226 ctxt->memopp = NULL;
9dac77fa 4227 ctxt->_eip = ctxt->eip;
17052f16
PB		 4228 ctxt->fetch.ptr = ctxt->fetch.data;
4229 ctxt->fetch.end = ctxt->fetch.data + insn_len;
1ce19dc1 4230 ctxt->opcode_len = 1;
dc25e89e 4231 if (insn_len > 0)
9dac77fa 4232 memcpy(ctxt->fetch.data, insn, insn_len);
285ca9e9 4233 else {
9506d57d 4234 rc = __do_insn_fetch_bytes(ctxt, 1);
285ca9e9
PB		 4235 if (rc != X86EMUL_CONTINUE)
4236 return rc;
4237 }
dde7e6d1
AK		 4238
4239 switch (mode) {
4240 case X86EMUL_MODE_REAL:
4241 case X86EMUL_MODE_VM86:
4242 case X86EMUL_MODE_PROT16:
4243 def_op_bytes = def_ad_bytes = 2;
4244 break;
4245 case X86EMUL_MODE_PROT32:
4246 def_op_bytes = def_ad_bytes = 4;
4247 break;
4248#ifdef CONFIG_X86_64
4249 case X86EMUL_MODE_PROT64:
4250 def_op_bytes = 4;
4251 def_ad_bytes = 8;
4252 break;
4253#endif
4254 default:
1d2887e2 4255 return EMULATION_FAILED;
dde7e6d1
AK		 4256 }
4257
9dac77fa
AK		 4258 ctxt->op_bytes = def_op_bytes;
4259 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 4260
4261 /* Legacy prefixes. */
4262 for (;;) {
e85a1085 4263 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 4264 case 0x66: /* operand-size override */
0d7cdee8 4265 op_prefix = true;
dde7e6d1 4266 /* switch between 2/4 bytes */
9dac77fa 4267 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 4268 break;
4269 case 0x67: /* address-size override */
4270 if (mode == X86EMUL_MODE_PROT64)
4271 /* switch between 4/8 bytes */
9dac77fa 4272 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 4273 else
4274 /* switch between 2/4 bytes */
9dac77fa 4275 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 4276 break;
4277 case 0x26: /* ES override */
4278 case 0x2e: /* CS override */
4279 case 0x36: /* SS override */
4280 case 0x3e: /* DS override */
573e80fe
BD		 4281 has_seg_override = true;
4282 ctxt->seg_override = (ctxt->b >> 3) & 3;
dde7e6d1
AK		 4283 break;
4284 case 0x64: /* FS override */
4285 case 0x65: /* GS override */
573e80fe
BD		 4286 has_seg_override = true;
4287 ctxt->seg_override = ctxt->b & 7;
dde7e6d1
AK		 4288 break;
4289 case 0x40 ... 0x4f: /* REX */
4290 if (mode != X86EMUL_MODE_PROT64)
4291 goto done_prefixes;
9dac77fa 4292 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 4293 continue;
4294 case 0xf0: /* LOCK */
9dac77fa 4295 ctxt->lock_prefix = 1;
dde7e6d1
AK		 4296 break;
4297 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 4298 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 4299 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 4300 break;
4301 default:
4302 goto done_prefixes;
4303 }
4304
4305 /* Any legacy prefix after a REX prefix nullifies its effect. */
4306
9dac77fa 4307 ctxt->rex_prefix = 0;
dde7e6d1
AK		 4308 }
4309
4310done_prefixes:
4311
4312 /* REX prefix. */
9dac77fa
AK		 4313 if (ctxt->rex_prefix & 8)
4314 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 4315
4316 /* Opcode byte(s). */
9dac77fa 4317 opcode = opcode_table[ctxt->b];
d3ad6243 4318 /* Two-byte opcode? */
9dac77fa 4319 if (ctxt->b == 0x0f) {
1ce19dc1 4320 ctxt->opcode_len = 2;
e85a1085 4321 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 4322 opcode = twobyte_table[ctxt->b];
0bc5eedb
BP		 4323
4324 /* 0F_38 opcode map */
4325 if (ctxt->b == 0x38) {
4326 ctxt->opcode_len = 3;
4327 ctxt->b = insn_fetch(u8, ctxt);
4328 opcode = opcode_map_0f_38[ctxt->b];
4329 }
dde7e6d1 4330 }
9dac77fa 4331 ctxt->d = opcode.flags;
dde7e6d1 4332
9f4260e7
TY		 4333 if (ctxt->d & ModRM)
4334 ctxt->modrm = insn_fetch(u8, ctxt);
4335
7fe864dc
NA		 4336 /* vex-prefix instructions are not implemented */
4337 if (ctxt->opcode_len == 1 && (ctxt->b == 0xc5 || ctxt->b == 0xc4) &&
4338 (mode == X86EMUL_MODE_PROT64 ||
4339 (mode >= X86EMUL_MODE_PROT16 && (ctxt->modrm & 0x80)))) {
4340 ctxt->d = NotImpl;
4341 }
4342
9dac77fa
AK		 4343 while (ctxt->d & GroupMask) {
4344 switch (ctxt->d & GroupMask) {
46561646 4345 case Group:
9dac77fa 4346 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 4347 opcode = opcode.u.group[goffset];
4348 break;
4349 case GroupDual:
9dac77fa
AK		 4350 goffset = (ctxt->modrm >> 3) & 7;
4351 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 4352 opcode = opcode.u.gdual->mod3[goffset];
4353 else
4354 opcode = opcode.u.gdual->mod012[goffset];
4355 break;
4356 case RMExt:
9dac77fa 4357 goffset = ctxt->modrm & 7;
01de8b09 4358 opcode = opcode.u.group[goffset];
46561646
AK		 4359 break;
4360 case Prefix:
9dac77fa 4361 if (ctxt->rep_prefix && op_prefix)
1d2887e2 4362 return EMULATION_FAILED;
9dac77fa 4363 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 4364 switch (simd_prefix) {
4365 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4366 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4367 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4368 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4369 }
4370 break;
045a282c
GN		 4371 case Escape:
4372 if (ctxt->modrm > 0xbf)
4373 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
4374 else
4375 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
4376 break;
46561646 4377 default:
1d2887e2 4378 return EMULATION_FAILED;
0d7cdee8 4379 }
46561646 4380
b1ea50b2 4381 ctxt->d &= ~(u64)GroupMask;
9dac77fa 4382 ctxt->d |= opcode.flags;
0d7cdee8
AK		 4383 }
4384
e24186e0
PB		 4385 /* Unrecognised? */
4386 if (ctxt->d == 0)
4387 return EMULATION_FAILED;
4388
9dac77fa 4389 ctxt->execute = opcode.u.execute;
dde7e6d1 4390
d40a6898
PB		 4391 if (unlikely(ctxt->d &
4392 (NotImpl|EmulateOnUD|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm))) {
4393 /*
4394 * These are copied unconditionally here, and checked unconditionally
4395 * in x86_emulate_insn.
4396 */
4397 ctxt->check_perm = opcode.check_perm;
4398 ctxt->intercept = opcode.intercept;
dde7e6d1 4399
d40a6898
PB		 4400 if (ctxt->d & NotImpl)
4401 return EMULATION_FAILED;
d867162c 4402
d40a6898
PB		 4403 if (!(ctxt->d & EmulateOnUD) && ctxt->ud)
4404 return EMULATION_FAILED;
dde7e6d1 4405
d40a6898 4406 if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
9dac77fa 4407 ctxt->op_bytes = 8;
7f9b4b75 4408
d40a6898
PB		 4409 if (ctxt->d & Op3264) {
4410 if (mode == X86EMUL_MODE_PROT64)
4411 ctxt->op_bytes = 8;
4412 else
4413 ctxt->op_bytes = 4;
4414 }
4415
4416 if (ctxt->d & Sse)
4417 ctxt->op_bytes = 16;
4418 else if (ctxt->d & Mmx)
4419 ctxt->op_bytes = 8;
4420 }
1253791d 4421
dde7e6d1 4422 /* ModRM and SIB bytes. */
9dac77fa 4423 if (ctxt->d & ModRM) {
f09ed83e 4424 rc = decode_modrm(ctxt, &ctxt->memop);
573e80fe
BD		 4425 if (!has_seg_override) {
4426 has_seg_override = true;
4427 ctxt->seg_override = ctxt->modrm_seg;
4428 }
9dac77fa 4429 } else if (ctxt->d & MemAbs)
f09ed83e 4430 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 4431 if (rc != X86EMUL_CONTINUE)
4432 goto done;
4433
573e80fe
BD		 4434 if (!has_seg_override)
4435 ctxt->seg_override = VCPU_SREG_DS;
dde7e6d1 4436
573e80fe 4437 ctxt->memop.addr.mem.seg = ctxt->seg_override;
dde7e6d1 4438
dde7e6d1
AK		 4439 /*
4440 * Decode and fetch the source operand: register, memory
4441 * or immediate.
4442 */
0fe59128 4443 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 4444 if (rc != X86EMUL_CONTINUE)
4445 goto done;
4446
dde7e6d1
AK		 4447 /*
4448 * Decode and fetch the second source operand: register, memory
4449 * or immediate.
4450 */
4dd6a57d 4451 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 4452 if (rc != X86EMUL_CONTINUE)
4453 goto done;
4454
dde7e6d1 4455 /* Decode and fetch the destination operand: register or memory. */
a9945549 4456 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1
AK		 4457
4458done:
41061cdb 4459 if (ctxt->rip_relative)
f09ed83e 4460 ctxt->memopp->addr.mem.ea += ctxt->_eip;
cb16c348 4461
1d2887e2 4462 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 4463}
4464
1cb3f3ae
XG		 4465bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4466{
4467 return ctxt->d & PageTable;
4468}
4469
3e2f65d5
GN		 4470static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4471{
3e2f65d5
GN		 4472 /* The second termination condition only applies for REPE
4473 * and REPNE. Test if the repeat string operation prefix is
4474 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4475 * corresponding termination condition according to:
4476 * - if REPE/REPZ and ZF = 0 then done
4477 * - if REPNE/REPNZ and ZF = 1 then done
4478 */
9dac77fa
AK		 4479 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4480 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4481 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 4482 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 4483 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 4484 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
4485 return true;
4486
4487 return false;
4488}
4489
cbe2c9d3
AK		 4490static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4491{
4492 bool fault = false;
4493
4494 ctxt->ops->get_fpu(ctxt);
4495 asm volatile("1: fwait \n\t"
4496 "2: \n\t"
4497 ".pushsection .fixup,\"ax\" \n\t"
4498 "3: \n\t"
4499 "movb $1, %[fault] \n\t"
4500 "jmp 2b \n\t"
4501 ".popsection \n\t"
4502 _ASM_EXTABLE(1b, 3b)
38e8a2dd 4503 : [fault]"+qm"(fault));
cbe2c9d3
AK		 4504 ctxt->ops->put_fpu(ctxt);
4505
4506 if (unlikely(fault))
4507 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4508
4509 return X86EMUL_CONTINUE;
4510}
4511
4512static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4513 struct operand *op)
4514{
4515 if (op->type == OP_MM)
4516 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4517}
4518
e28bbd44
AK		 4519static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
4520{
4521 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
b9fa409b
AK		 4522 if (!(ctxt->d & ByteOp))
4523 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
e28bbd44 4524 asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n"
b8c0b6ae
AK		 4525 : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags),
4526 [fastop]"+S"(fop)
4527 : "c"(ctxt->src2.val));
e28bbd44 4528 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
b8c0b6ae
AK		 4529 if (!fop) /* exception is returned in fop variable */
4530 return emulate_de(ctxt);
e28bbd44
AK		 4531 return X86EMUL_CONTINUE;
4532}
dd856efa 4533
1498507a
BD		 4534void init_decode_cache(struct x86_emulate_ctxt *ctxt)
4535{
573e80fe
BD		 4536 memset(&ctxt->rip_relative, 0,
4537 (void *)&ctxt->modrm - (void *)&ctxt->rip_relative);
1498507a 4538
1498507a
BD		 4539 ctxt->io_read.pos = 0;
4540 ctxt->io_read.end = 0;
1498507a
BD		 4541 ctxt->mem_read.end = 0;
4542}
4543
7b105ca2 4544int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 4545{
0225fb50 4546 const struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 4547 int rc = X86EMUL_CONTINUE;
9dac77fa 4548 int saved_dst_type = ctxt->dst.type;
8b4caf66 4549
9dac77fa 4550 ctxt->mem_read.pos = 0;
310b5d30 4551
e24186e0
PB		 4552 /* LOCK prefix is allowed only with some instructions */
4553 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 4554 rc = emulate_ud(ctxt);
1161624f
GN		 4555 goto done;
4556 }
4557
e24186e0 4558 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 4559 rc = emulate_ud(ctxt);
d380a5e4
GN		 4560 goto done;
4561 }
4562
d40a6898
PB		 4563 if (unlikely(ctxt->d &
4564 (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) {
4565 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
4566 (ctxt->d & Undefined)) {
4567 rc = emulate_ud(ctxt);
4568 goto done;
4569 }
1253791d 4570
d40a6898
PB		 4571 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4572 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
4573 rc = emulate_ud(ctxt);
cbe2c9d3 4574 goto done;
d40a6898 4575 }
cbe2c9d3 4576
d40a6898
PB		 4577 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
4578 rc = emulate_nm(ctxt);
c4f035c6 4579 goto done;
d40a6898 4580 }
c4f035c6 4581
d40a6898
PB		 4582 if (ctxt->d & Mmx) {
4583 rc = flush_pending_x87_faults(ctxt);
4584 if (rc != X86EMUL_CONTINUE)
4585 goto done;
4586 /*
4587 * Now that we know the fpu is exception safe, we can fetch
4588 * operands from it.
4589 */
4590 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4591 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4592 if (!(ctxt->d & Mov))
4593 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4594 }
e92805ac 4595
685bbf4a 4596 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
d40a6898
PB		 4597 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4598 X86_ICPT_PRE_EXCEPT);
4599 if (rc != X86EMUL_CONTINUE)
4600 goto done;
4601 }
8ea7d6ae 4602
d40a6898
PB		 4603 /* Privileged instruction can be executed only in CPL=0 */
4604 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
4605 rc = emulate_gp(ctxt, 0);
d09beabd 4606 goto done;
d40a6898 4607 }
d09beabd 4608
d40a6898
PB		 4609 /* Instruction can only be executed in protected mode */
4610 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
4611 rc = emulate_ud(ctxt);
c4f035c6 4612 goto done;
d40a6898 4613 }
c4f035c6 4614
d40a6898 4615 /* Do instruction specific permission checks */
685bbf4a 4616 if (ctxt->d & CheckPerm) {
d40a6898
PB		 4617 rc = ctxt->check_perm(ctxt);
4618 if (rc != X86EMUL_CONTINUE)
4619 goto done;
4620 }
4621
685bbf4a 4622 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
d40a6898
PB		 4623 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4624 X86_ICPT_POST_EXCEPT);
4625 if (rc != X86EMUL_CONTINUE)
4626 goto done;
4627 }
4628
4629 if (ctxt->rep_prefix && (ctxt->d & String)) {
4630 /* All REP prefixes have the same first termination condition */
4631 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
4632 ctxt->eip = ctxt->_eip;
4633 goto done;
4634 }
b9fa9d6b 4635 }
b9fa9d6b
AK		 4636 }
4637
9dac77fa
AK		 4638 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4639 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4640 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 4641 if (rc != X86EMUL_CONTINUE)
8b4caf66 4642 goto done;
9dac77fa 4643 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 4644 }
4645
9dac77fa
AK		 4646 if (ctxt->src2.type == OP_MEM) {
4647 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4648 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 4649 if (rc != X86EMUL_CONTINUE)
4650 goto done;
4651 }
4652
9dac77fa 4653 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 4654 goto special_insn;
4655
4656
9dac77fa 4657 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 4658 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 4659 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4660 &ctxt->dst.val, ctxt->dst.bytes);
69f55cb1
GN		 4661 if (rc != X86EMUL_CONTINUE)
4662 goto done;
038e51de 4663 }
9dac77fa 4664 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 4665
018a98db
AK		 4666special_insn:
4667
685bbf4a 4668 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
9dac77fa 4669 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4670 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 4671 if (rc != X86EMUL_CONTINUE)
4672 goto done;
4673 }
4674
9dac77fa 4675 if (ctxt->execute) {
e28bbd44
AK		 4676 if (ctxt->d & Fastop) {
4677 void (*fop)(struct fastop *) = (void *)ctxt->execute;
4678 rc = fastop(ctxt, fop);
4679 if (rc != X86EMUL_CONTINUE)
4680 goto done;
4681 goto writeback;
4682 }
9dac77fa 4683 rc = ctxt->execute(ctxt);
ef65c889
AK		 4684 if (rc != X86EMUL_CONTINUE)
4685 goto done;
4686 goto writeback;
4687 }
4688
1ce19dc1 4689 if (ctxt->opcode_len == 2)
6aa8b732 4690 goto twobyte_insn;
0bc5eedb
BP		 4691 else if (ctxt->opcode_len == 3)
4692 goto threebyte_insn;
6aa8b732 4693
9dac77fa 4694 switch (ctxt->b) {
6aa8b732 4695 case 0x63: /* movsxd */
8b4caf66 4696 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 4697 goto cannot_emulate;
9dac77fa 4698 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 4699 break;
b2833e3c 4700 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa
AK		 4701 if (test_cc(ctxt->b, ctxt->eflags))
4702 jmp_rel(ctxt, ctxt->src.val);
018a98db 4703 break;
7e0b54b1 4704 case 0x8d: /* lea r16/r32, m */
9dac77fa 4705 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 4706 break;
3d9e77df 4707 case 0x90 ... 0x97: /* nop / xchg reg, rax */
dd856efa 4708 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
a825f5cc
NA		 4709 ctxt->dst.type = OP_NONE;
4710 else
4711 rc = em_xchg(ctxt);
e4f973ae 4712 break;
e8b6fa70 4713 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 4714 switch (ctxt->op_bytes) {
4715 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
4716 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
4717 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 4718 }
4719 break;
6e154e56 4720 case 0xcc: /* int3 */
5c5df76b
TY		 4721 rc = emulate_int(ctxt, 3);
4722 break;
6e154e56 4723 case 0xcd: /* int n */
9dac77fa 4724 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 4725 break;
4726 case 0xce: /* into */
5c5df76b
TY		 4727 if (ctxt->eflags & EFLG_OF)
4728 rc = emulate_int(ctxt, 4);
6e154e56 4729 break;
1a52e051 4730 case 0xe9: /* jmp rel */
db5b0762 4731 case 0xeb: /* jmp rel short */
9dac77fa
AK		 4732 jmp_rel(ctxt, ctxt->src.val);
4733 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4734 break;
111de5d6 4735 case 0xf4: /* hlt */
6c3287f7 4736 ctxt->ops->halt(ctxt);
19fdfa0d 4737 break;
111de5d6
AK		 4738 case 0xf5: /* cmc */
4739 /* complement carry flag from eflags reg */
4740 ctxt->eflags ^= EFLG_CF;
111de5d6
AK		 4741 break;
4742 case 0xf8: /* clc */
4743 ctxt->eflags &= ~EFLG_CF;
111de5d6 4744 break;
8744aa9a
MG		 4745 case 0xf9: /* stc */
4746 ctxt->eflags |= EFLG_CF;
4747 break;
fb4616f4
MG		 4748 case 0xfc: /* cld */
4749 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 4750 break;
4751 case 0xfd: /* std */
4752 ctxt->eflags |= EFLG_DF;
fb4616f4 4753 break;
91269b8f
AK		 4754 default:
4755 goto cannot_emulate;
6aa8b732 4756 }
018a98db 4757
7d9ddaed
AK		 4758 if (rc != X86EMUL_CONTINUE)
4759 goto done;
4760
018a98db 4761writeback:
fb32b1ed
AK		 4762 if (ctxt->d & SrcWrite) {
4763 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR);
4764 rc = writeback(ctxt, &ctxt->src);
4765 if (rc != X86EMUL_CONTINUE)
4766 goto done;
4767 }
ee212297
NA		 4768 if (!(ctxt->d & NoWrite)) {
4769 rc = writeback(ctxt, &ctxt->dst);
4770 if (rc != X86EMUL_CONTINUE)
4771 goto done;
4772 }
018a98db 4773
5cd21917
GN		 4774 /*
4775 * restore dst type in case the decoding will be reused
4776 * (happens for string instruction )
4777 */
9dac77fa 4778 ctxt->dst.type = saved_dst_type;
5cd21917 4779
9dac77fa 4780 if ((ctxt->d & SrcMask) == SrcSI)
f3bd64c6 4781 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
a682e354 4782
9dac77fa 4783 if ((ctxt->d & DstMask) == DstDI)
f3bd64c6 4784 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
d9271123 4785
9dac77fa 4786 if (ctxt->rep_prefix && (ctxt->d & String)) {
b3356bf0 4787 unsigned int count;
9dac77fa 4788 struct read_cache *r = &ctxt->io_read;
b3356bf0
GN		 4789 if ((ctxt->d & SrcMask) == SrcSI)
4790 count = ctxt->src.count;
4791 else
4792 count = ctxt->dst.count;
4793 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX),
4794 -count);
3e2f65d5 4795
d2ddd1c4
GN		 4796 if (!string_insn_completed(ctxt)) {
4797 /*
4798 * Re-enter guest when pio read ahead buffer is empty
4799 * or, if it is not used, after each 1024 iteration.
4800 */
dd856efa 4801 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
d2ddd1c4
GN		 4802 (r->end == 0 || r->end != r->pos)) {
4803 /*
4804 * Reset read cache. Usually happens before
4805 * decode, but since instruction is restarted
4806 * we have to do it here.
4807 */
9dac77fa 4808 ctxt->mem_read.end = 0;
dd856efa 4809 writeback_registers(ctxt);
d2ddd1c4
GN		 4810 return EMULATION_RESTART;
4811 }
4812 goto done; /* skip rip writeback */
0fa6ccbd 4813 }
5cd21917 4814 }
d2ddd1c4 4815
9dac77fa 4816 ctxt->eip = ctxt->_eip;
018a98db
AK		 4817
4818done:
da9cb575
AK		 4819 if (rc == X86EMUL_PROPAGATE_FAULT)
4820 ctxt->have_exception = true;
775fde86
JR		 4821 if (rc == X86EMUL_INTERCEPTED)
4822 return EMULATION_INTERCEPTED;
4823
dd856efa
AK		 4824 if (rc == X86EMUL_CONTINUE)
4825 writeback_registers(ctxt);
4826
d2ddd1c4 4827 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 4828
4829twobyte_insn:
9dac77fa 4830 switch (ctxt->b) {
018a98db 4831 case 0x09: /* wbinvd */
cfb22375 4832 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 4833 break;
4834 case 0x08: /* invd */
018a98db
AK		 4835 case 0x0d: /* GrpP (prefetch) */
4836 case 0x18: /* Grp16 (prefetch/nop) */
103f98ea 4837 case 0x1f: /* nop */
018a98db
AK		 4838 break;
4839 case 0x20: /* mov cr, reg */
9dac77fa 4840 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 4841 break;
6aa8b732 4842 case 0x21: /* mov from dr to reg */
9dac77fa 4843 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 4844 break;
6aa8b732 4845 case 0x40 ... 0x4f: /* cmov */
140bad89
NA		 4846 if (test_cc(ctxt->b, ctxt->eflags))
4847 ctxt->dst.val = ctxt->src.val;
4848 else if (ctxt->mode != X86EMUL_MODE_PROT64 ||
4849 ctxt->op_bytes != 4)
9dac77fa 4850 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 4851 break;
b2833e3c 4852 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa
AK		 4853 if (test_cc(ctxt->b, ctxt->eflags))
4854 jmp_rel(ctxt, ctxt->src.val);
018a98db 4855 break;
ee45b58e 4856 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 4857 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 4858 break;
2a7c5b8b
GC		 4859 case 0xae: /* clflush */
4860 break;
6aa8b732 4861 case 0xb6 ... 0xb7: /* movzx */
9dac77fa 4862 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4863 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
9dac77fa 4864 : (u16) ctxt->src.val;
6aa8b732 4865 break;
6aa8b732 4866 case 0xbe ... 0xbf: /* movsx */
9dac77fa 4867 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4868 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
9dac77fa 4869 (s16) ctxt->src.val;
6aa8b732 4870 break;
a012e65a 4871 case 0xc3: /* movnti */
9dac77fa 4872 ctxt->dst.bytes = ctxt->op_bytes;
3b32004a
NA		 4873 ctxt->dst.val = (ctxt->op_bytes == 8) ? (u64) ctxt->src.val :
4874 (u32) ctxt->src.val;
a012e65a 4875 break;
91269b8f
AK		 4876 default:
4877 goto cannot_emulate;
6aa8b732 4878 }
7d9ddaed 4879
0bc5eedb
BP		 4880threebyte_insn:
4881
7d9ddaed
AK		 4882 if (rc != X86EMUL_CONTINUE)
4883 goto done;
4884
6aa8b732
AK		 4885 goto writeback;
4886
4887cannot_emulate:
a0c0ab2f 4888 return EMULATION_FAILED;
6aa8b732 4889}
dd856efa
AK		 4890
4891void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
4892{
4893 invalidate_registers(ctxt);
4894}
4895
4896void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
4897{
4898 writeback_registers(ctxt);
4899}
Linux 6.x block layer and io_uring tree(s)