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KVM: x86: Emulator fixes for eip canonical checks on near branches
[linux-2.6-block.git] / arch / x86 / kvm / emulate.c
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6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
b7d491e7 27#include <linux/stringify.h>
6aa8b732 28
3eeb3288 29#include "x86.h"
38ba30ba 30#include "tss.h"
e99f0507 31
a9945549
AK		 32/*
33 * Operand types
34 */
b1ea50b2
AK		 35#define OpNone 0ull
36#define OpImplicit 1ull /* No generic decode */
37#define OpReg 2ull /* Register */
38#define OpMem 3ull /* Memory */
39#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
40#define OpDI 5ull /* ES:DI/EDI/RDI */
41#define OpMem64 6ull /* Memory, 64-bit */
42#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
43#define OpDX 8ull /* DX register */
4dd6a57d
AK		 44#define OpCL 9ull /* CL register (for shifts) */
45#define OpImmByte 10ull /* 8-bit sign extended immediate */
46#define OpOne 11ull /* Implied 1 */
5e2c6883 47#define OpImm 12ull /* Sign extended up to 32-bit immediate */
0fe59128
AK		 48#define OpMem16 13ull /* Memory operand (16-bit). */
49#define OpMem32 14ull /* Memory operand (32-bit). */
50#define OpImmU 15ull /* Immediate operand, zero extended */
51#define OpSI 16ull /* SI/ESI/RSI */
52#define OpImmFAddr 17ull /* Immediate far address */
53#define OpMemFAddr 18ull /* Far address in memory */
54#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 55#define OpES 20ull /* ES */
56#define OpCS 21ull /* CS */
57#define OpSS 22ull /* SS */
58#define OpDS 23ull /* DS */
59#define OpFS 24ull /* FS */
60#define OpGS 25ull /* GS */
28867cee 61#define OpMem8 26ull /* 8-bit zero extended memory operand */
5e2c6883 62#define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
7fa57952 63#define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */
820207c8
AK		 64#define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */
65#define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */
0fe59128
AK		 66
67#define OpBits 5 /* Width of operand field */
b1ea50b2 68#define OpMask ((1ull << OpBits) - 1)
a9945549 69
6aa8b732
AK		 70/*
71 * Opcode effective-address decode tables.
72 * Note that we only emulate instructions that have at least one memory
73 * operand (excluding implicit stack references). We assume that stack
74 * references and instruction fetches will never occur in special memory
75 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
76 * not be handled.
77 */
78
79/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 80#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 81/* Destination operand type. */
a9945549
AK		 82#define DstShift 1
83#define ImplicitOps (OpImplicit << DstShift)
84#define DstReg (OpReg << DstShift)
85#define DstMem (OpMem << DstShift)
86#define DstAcc (OpAcc << DstShift)
87#define DstDI (OpDI << DstShift)
88#define DstMem64 (OpMem64 << DstShift)
89#define DstImmUByte (OpImmUByte << DstShift)
90#define DstDX (OpDX << DstShift)
820207c8 91#define DstAccLo (OpAccLo << DstShift)
a9945549 92#define DstMask (OpMask << DstShift)
6aa8b732 93/* Source operand type. */
0fe59128
AK		 94#define SrcShift 6
95#define SrcNone (OpNone << SrcShift)
96#define SrcReg (OpReg << SrcShift)
97#define SrcMem (OpMem << SrcShift)
98#define SrcMem16 (OpMem16 << SrcShift)
99#define SrcMem32 (OpMem32 << SrcShift)
100#define SrcImm (OpImm << SrcShift)
101#define SrcImmByte (OpImmByte << SrcShift)
102#define SrcOne (OpOne << SrcShift)
103#define SrcImmUByte (OpImmUByte << SrcShift)
104#define SrcImmU (OpImmU << SrcShift)
105#define SrcSI (OpSI << SrcShift)
7fa57952 106#define SrcXLat (OpXLat << SrcShift)
0fe59128
AK		 107#define SrcImmFAddr (OpImmFAddr << SrcShift)
108#define SrcMemFAddr (OpMemFAddr << SrcShift)
109#define SrcAcc (OpAcc << SrcShift)
110#define SrcImmU16 (OpImmU16 << SrcShift)
5e2c6883 111#define SrcImm64 (OpImm64 << SrcShift)
0fe59128 112#define SrcDX (OpDX << SrcShift)
28867cee 113#define SrcMem8 (OpMem8 << SrcShift)
820207c8 114#define SrcAccHi (OpAccHi << SrcShift)
0fe59128 115#define SrcMask (OpMask << SrcShift)
221192bd
MT		 116#define BitOp (1<<11)
117#define MemAbs (1<<12) /* Memory operand is absolute displacement */
118#define String (1<<13) /* String instruction (rep capable) */
119#define Stack (1<<14) /* Stack instruction (push/pop) */
120#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
121#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
122#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
123#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
124#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
045a282c 125#define Escape (5<<15) /* Escape to coprocessor instruction */
221192bd 126#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 127/* Generic ModRM decode. */
128#define ModRM (1<<19)
129/* Destination is only written; never read. */
130#define Mov (1<<20)
d8769fed 131/* Misc flags */
8ea7d6ae 132#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
b51e974f 133#define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */
5a506b12 134#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 135#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 136#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 137#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 138#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 139#define No64 (1<<28)
d5ae7ce8 140#define PageTable (1 << 29) /* instruction used to write page table */
0b789eee 141#define NotImpl (1 << 30) /* instruction is not implemented */
0dc8d10f 142/* Source 2 operand type */
0b789eee 143#define Src2Shift (31)
4dd6a57d 144#define Src2None (OpNone << Src2Shift)
ab2c5ce6 145#define Src2Mem (OpMem << Src2Shift)
4dd6a57d
AK		 146#define Src2CL (OpCL << Src2Shift)
147#define Src2ImmByte (OpImmByte << Src2Shift)
148#define Src2One (OpOne << Src2Shift)
149#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 150#define Src2ES (OpES << Src2Shift)
151#define Src2CS (OpCS << Src2Shift)
152#define Src2SS (OpSS << Src2Shift)
153#define Src2DS (OpDS << Src2Shift)
154#define Src2FS (OpFS << Src2Shift)
155#define Src2GS (OpGS << Src2Shift)
4dd6a57d 156#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 157#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
1c11b376
AK		 158#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
159#define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
160#define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
e28bbd44 161#define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
b6744dc3 162#define NoWrite ((u64)1 << 45) /* No writeback */
fb32b1ed 163#define SrcWrite ((u64)1 << 46) /* Write back src operand */
9b88ae99 164#define NoMod ((u64)1 << 47) /* Mod field is ignored */
d40a6898
PB		 165#define Intercept ((u64)1 << 48) /* Has valid intercept field */
166#define CheckPerm ((u64)1 << 49) /* Has valid check_perm field */
10e38fc7 167#define NoBigReal ((u64)1 << 50) /* No big real mode */
68efa764 168#define PrivUD ((u64)1 << 51) /* #UD instead of #GP on CPL > 0 */
6aa8b732 169
820207c8 170#define DstXacc (DstAccLo | SrcAccHi | SrcWrite)
6aa8b732 171
d0e53325
AK		 172#define X2(x...) x, x
173#define X3(x...) X2(x), x
174#define X4(x...) X2(x), X2(x)
175#define X5(x...) X4(x), x
176#define X6(x...) X4(x), X2(x)
177#define X7(x...) X4(x), X3(x)
178#define X8(x...) X4(x), X4(x)
179#define X16(x...) X8(x), X8(x)
83babbca 180
e28bbd44
AK		 181#define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
182#define FASTOP_SIZE 8
183
184/*
185 * fastop functions have a special calling convention:
186 *
017da7b6
AK		 187 * dst: rax (in/out)
188 * src: rdx (in/out)
e28bbd44
AK		 189 * src2: rcx (in)
190 * flags: rflags (in/out)
b8c0b6ae 191 * ex: rsi (in:fastop pointer, out:zero if exception)
e28bbd44
AK		 192 *
193 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
194 * different operand sizes can be reached by calculation, rather than a jump
195 * table (which would be bigger than the code).
196 *
197 * fastop functions are declared as taking a never-defined fastop parameter,
198 * so they can't be called from C directly.
199 */
200
201struct fastop;
202
d65b1dee 203struct opcode {
b1ea50b2
AK		 204 u64 flags : 56;
205 u64 intercept : 8;
120df890 206 union {
ef65c889 207 int (*execute)(struct x86_emulate_ctxt *ctxt);
fd0a0d82
MK		 208 const struct opcode *group;
209 const struct group_dual *gdual;
210 const struct gprefix *gprefix;
045a282c 211 const struct escape *esc;
e28bbd44 212 void (*fastop)(struct fastop *fake);
120df890 213 } u;
d09beabd 214 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 215};
216
217struct group_dual {
218 struct opcode mod012[8];
219 struct opcode mod3[8];
d65b1dee
AK		 220};
221
0d7cdee8
AK		 222struct gprefix {
223 struct opcode pfx_no;
224 struct opcode pfx_66;
225 struct opcode pfx_f2;
226 struct opcode pfx_f3;
227};
228
045a282c
GN		 229struct escape {
230 struct opcode op[8];
231 struct opcode high[64];
232};
233
6aa8b732 234/* EFLAGS bit definitions. */
d4c6a154
GN		 235#define EFLG_ID (1<<21)
236#define EFLG_VIP (1<<20)
237#define EFLG_VIF (1<<19)
238#define EFLG_AC (1<<18)
b1d86143
AP		 239#define EFLG_VM (1<<17)
240#define EFLG_RF (1<<16)
d4c6a154
GN		 241#define EFLG_IOPL (3<<12)
242#define EFLG_NT (1<<14)
6aa8b732
AK		 243#define EFLG_OF (1<<11)
244#define EFLG_DF (1<<10)
b1d86143 245#define EFLG_IF (1<<9)
d4c6a154 246#define EFLG_TF (1<<8)
6aa8b732
AK		 247#define EFLG_SF (1<<7)
248#define EFLG_ZF (1<<6)
249#define EFLG_AF (1<<4)
250#define EFLG_PF (1<<2)
251#define EFLG_CF (1<<0)
252
62bd430e
MG		 253#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
254#define EFLG_RESERVED_ONE_MASK 2
255
dd856efa
AK		 256static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
257{
258 if (!(ctxt->regs_valid & (1 << nr))) {
259 ctxt->regs_valid |= 1 << nr;
260 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
261 }
262 return ctxt->_regs[nr];
263}
264
265static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
266{
267 ctxt->regs_valid |= 1 << nr;
268 ctxt->regs_dirty |= 1 << nr;
269 return &ctxt->_regs[nr];
270}
271
272static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
273{
274 reg_read(ctxt, nr);
275 return reg_write(ctxt, nr);
276}
277
278static void writeback_registers(struct x86_emulate_ctxt *ctxt)
279{
280 unsigned reg;
281
282 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
283 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
284}
285
286static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
287{
288 ctxt->regs_dirty = 0;
289 ctxt->regs_valid = 0;
290}
291
6aa8b732
AK		 292/*
293 * These EFLAGS bits are restored from saved value during emulation, and
294 * any changes are written back to the saved value after emulation.
295 */
296#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
297
dda96d8f
AK		 298#ifdef CONFIG_X86_64
299#define ON64(x) x
300#else
301#define ON64(x)
302#endif
303
4d758349
AK		 304static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));
305
b7d491e7
AK		 306#define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t"
307#define FOP_RET "ret \n\t"
308
309#define FOP_START(op) \
310 extern void em_##op(struct fastop *fake); \
311 asm(".pushsection .text, \"ax\" \n\t" \
312 ".global em_" #op " \n\t" \
313 FOP_ALIGN \
314 "em_" #op ": \n\t"
315
316#define FOP_END \
317 ".popsection")
318
0bdea068
AK		 319#define FOPNOP() FOP_ALIGN FOP_RET
320
b7d491e7 321#define FOP1E(op, dst) \
b8c0b6ae
AK		 322 FOP_ALIGN "10: " #op " %" #dst " \n\t" FOP_RET
323
324#define FOP1EEX(op, dst) \
325 FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception)
b7d491e7
AK		 326
327#define FASTOP1(op) \
328 FOP_START(op) \
329 FOP1E(op##b, al) \
330 FOP1E(op##w, ax) \
331 FOP1E(op##l, eax) \
332 ON64(FOP1E(op##q, rax)) \
333 FOP_END
334
b9fa409b
AK		 335/* 1-operand, using src2 (for MUL/DIV r/m) */
336#define FASTOP1SRC2(op, name) \
337 FOP_START(name) \
338 FOP1E(op, cl) \
339 FOP1E(op, cx) \
340 FOP1E(op, ecx) \
341 ON64(FOP1E(op, rcx)) \
342 FOP_END
343
b8c0b6ae
AK		 344/* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */
345#define FASTOP1SRC2EX(op, name) \
346 FOP_START(name) \
347 FOP1EEX(op, cl) \
348 FOP1EEX(op, cx) \
349 FOP1EEX(op, ecx) \
350 ON64(FOP1EEX(op, rcx)) \
351 FOP_END
352
f7857f35
AK		 353#define FOP2E(op, dst, src) \
354 FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET
355
356#define FASTOP2(op) \
357 FOP_START(op) \
017da7b6
AK		 358 FOP2E(op##b, al, dl) \
359 FOP2E(op##w, ax, dx) \
360 FOP2E(op##l, eax, edx) \
361 ON64(FOP2E(op##q, rax, rdx)) \
f7857f35
AK		 362 FOP_END
363
11c363ba
AK		 364/* 2 operand, word only */
365#define FASTOP2W(op) \
366 FOP_START(op) \
367 FOPNOP() \
017da7b6
AK		 368 FOP2E(op##w, ax, dx) \
369 FOP2E(op##l, eax, edx) \
370 ON64(FOP2E(op##q, rax, rdx)) \
11c363ba
AK		 371 FOP_END
372
007a3b54
AK		 373/* 2 operand, src is CL */
374#define FASTOP2CL(op) \
375 FOP_START(op) \
376 FOP2E(op##b, al, cl) \
377 FOP2E(op##w, ax, cl) \
378 FOP2E(op##l, eax, cl) \
379 ON64(FOP2E(op##q, rax, cl)) \
380 FOP_END
381
0bdea068
AK		 382#define FOP3E(op, dst, src, src2) \
383 FOP_ALIGN #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET
384
385/* 3-operand, word-only, src2=cl */
386#define FASTOP3WCL(op) \
387 FOP_START(op) \
388 FOPNOP() \
017da7b6
AK		 389 FOP3E(op##w, ax, dx, cl) \
390 FOP3E(op##l, eax, edx, cl) \
391 ON64(FOP3E(op##q, rax, rdx, cl)) \
0bdea068
AK		 392 FOP_END
393
9ae9feba
AK		 394/* Special case for SETcc - 1 instruction per cc */
395#define FOP_SETCC(op) ".align 4; " #op " %al; ret \n\t"
396
b8c0b6ae
AK		 397asm(".global kvm_fastop_exception \n"
398 "kvm_fastop_exception: xor %esi, %esi; ret");
399
9ae9feba
AK		 400FOP_START(setcc)
401FOP_SETCC(seto)
402FOP_SETCC(setno)
403FOP_SETCC(setc)
404FOP_SETCC(setnc)
405FOP_SETCC(setz)
406FOP_SETCC(setnz)
407FOP_SETCC(setbe)
408FOP_SETCC(setnbe)
409FOP_SETCC(sets)
410FOP_SETCC(setns)
411FOP_SETCC(setp)
412FOP_SETCC(setnp)
413FOP_SETCC(setl)
414FOP_SETCC(setnl)
415FOP_SETCC(setle)
416FOP_SETCC(setnle)
417FOP_END;
418
326f578f
PB		 419FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET
420FOP_END;
421
8a76d7f2
JR		 422static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
423 enum x86_intercept intercept,
424 enum x86_intercept_stage stage)
425{
426 struct x86_instruction_info info = {
427 .intercept = intercept,
9dac77fa
AK		 428 .rep_prefix = ctxt->rep_prefix,
429 .modrm_mod = ctxt->modrm_mod,
430 .modrm_reg = ctxt->modrm_reg,
431 .modrm_rm = ctxt->modrm_rm,
432 .src_val = ctxt->src.val64,
6cbc5f5a 433 .dst_val = ctxt->dst.val64,
9dac77fa
AK		 434 .src_bytes = ctxt->src.bytes,
435 .dst_bytes = ctxt->dst.bytes,
436 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 437 .next_rip = ctxt->eip,
438 };
439
2953538e 440 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 441}
442
f47cfa31
AK		 443static void assign_masked(ulong *dest, ulong src, ulong mask)
444{
445 *dest = (*dest & ~mask) | (src & mask);
446}
447
9dac77fa 448static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 449{
9dac77fa 450 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 451}
452
f47cfa31
AK		 453static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
454{
455 u16 sel;
456 struct desc_struct ss;
457
458 if (ctxt->mode == X86EMUL_MODE_PROT64)
459 return ~0UL;
460 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
461 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
462}
463
612e89f0
AK		 464static int stack_size(struct x86_emulate_ctxt *ctxt)
465{
466 return (__fls(stack_mask(ctxt)) + 1) >> 3;
467}
468
6aa8b732 469/* Access/update address held in a register, based on addressing mode. */
e4706772 470static inline unsigned long
9dac77fa 471address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 472{
9dac77fa 473 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 474 return reg;
475 else
9dac77fa 476 return reg & ad_mask(ctxt);
e4706772
HH		 477}
478
479static inline unsigned long
9dac77fa 480register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 481{
9dac77fa 482 return address_mask(ctxt, reg);
e4706772
HH		 483}
484
5ad105e5
AK		 485static void masked_increment(ulong *reg, ulong mask, int inc)
486{
487 assign_masked(reg, *reg + inc, mask);
488}
489
7a957275 490static inline void
9dac77fa 491register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
7a957275 492{
5ad105e5
AK		 493 ulong mask;
494
9dac77fa 495 if (ctxt->ad_bytes == sizeof(unsigned long))
5ad105e5 496 mask = ~0UL;
7a957275 497 else
5ad105e5
AK		 498 mask = ad_mask(ctxt);
499 masked_increment(reg, mask, inc);
500}
501
502static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
503{
dd856efa 504 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
7a957275 505}
6aa8b732 506
56697687
AK		 507static u32 desc_limit_scaled(struct desc_struct *desc)
508{
509 u32 limit = get_desc_limit(desc);
510
511 return desc->g ? (limit << 12) | 0xfff : limit;
512}
513
7b105ca2 514static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 515{
516 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
517 return 0;
518
7b105ca2 519 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 520}
521
35d3d4a1
AK		 522static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
523 u32 error, bool valid)
54b8486f 524{
e0ad0b47 525 WARN_ON(vec > 0x1f);
da9cb575
AK		 526 ctxt->exception.vector = vec;
527 ctxt->exception.error_code = error;
528 ctxt->exception.error_code_valid = valid;
35d3d4a1 529 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 530}
531
3b88e41a
JR		 532static int emulate_db(struct x86_emulate_ctxt *ctxt)
533{
534 return emulate_exception(ctxt, DB_VECTOR, 0, false);
535}
536
35d3d4a1 537static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 538{
35d3d4a1 539 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 540}
541
618ff15d
AK		 542static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
543{
544 return emulate_exception(ctxt, SS_VECTOR, err, true);
545}
546
35d3d4a1 547static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 548{
35d3d4a1 549 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 550}
551
35d3d4a1 552static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 553{
35d3d4a1 554 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 555}
556
34d1f490
AK		 557static int emulate_de(struct x86_emulate_ctxt *ctxt)
558{
35d3d4a1 559 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 560}
561
1253791d
AK		 562static int emulate_nm(struct x86_emulate_ctxt *ctxt)
563{
564 return emulate_exception(ctxt, NM_VECTOR, 0, false);
565}
566
234f3ce4
NA		 567static inline int assign_eip_far(struct x86_emulate_ctxt *ctxt, ulong dst,
568 int cs_l)
05c83ec9
NA		 569{
570 switch (ctxt->op_bytes) {
571 case 2:
572 ctxt->_eip = (u16)dst;
573 break;
574 case 4:
575 ctxt->_eip = (u32)dst;
576 break;
577 case 8:
234f3ce4
NA		 578 if ((cs_l && is_noncanonical_address(dst)) ||
579 (!cs_l && (dst & ~(u32)-1)))
580 return emulate_gp(ctxt, 0);
05c83ec9
NA		 581 ctxt->_eip = dst;
582 break;
583 default:
584 WARN(1, "unsupported eip assignment size\n");
585 }
234f3ce4
NA		 586 return X86EMUL_CONTINUE;
587}
588
589static inline int assign_eip_near(struct x86_emulate_ctxt *ctxt, ulong dst)
590{
591 return assign_eip_far(ctxt, dst, ctxt->mode == X86EMUL_MODE_PROT64);
05c83ec9
NA		 592}
593
234f3ce4 594static inline int jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
05c83ec9 595{
234f3ce4 596 return assign_eip_near(ctxt, ctxt->_eip + rel);
05c83ec9
NA		 597}
598
1aa36616
AK		 599static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
600{
601 u16 selector;
602 struct desc_struct desc;
603
604 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
605 return selector;
606}
607
608static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
609 unsigned seg)
610{
611 u16 dummy;
612 u32 base3;
613 struct desc_struct desc;
614
615 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
616 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
617}
618
1c11b376
AK		 619/*
620 * x86 defines three classes of vector instructions: explicitly
621 * aligned, explicitly unaligned, and the rest, which change behaviour
622 * depending on whether they're AVX encoded or not.
623 *
624 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
625 * subject to the same check.
626 */
627static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
628{
629 if (likely(size < 16))
630 return false;
631
632 if (ctxt->d & Aligned)
633 return true;
634 else if (ctxt->d & Unaligned)
635 return false;
636 else if (ctxt->d & Avx)
637 return false;
638 else
639 return true;
640}
641
3d9b938e 642static int __linearize(struct x86_emulate_ctxt *ctxt,
52fd8b44 643 struct segmented_address addr,
3d9b938e 644 unsigned size, bool write, bool fetch,
52fd8b44
AK		 645 ulong *linear)
646{
618ff15d
AK		 647 struct desc_struct desc;
648 bool usable;
52fd8b44 649 ulong la;
618ff15d 650 u32 lim;
1aa36616 651 u16 sel;
3a78a4f4 652 unsigned cpl;
52fd8b44 653
7b105ca2 654 la = seg_base(ctxt, addr.seg) + addr.ea;
618ff15d 655 switch (ctxt->mode) {
618ff15d
AK		 656 case X86EMUL_MODE_PROT64:
657 if (((signed long)la << 16) >> 16 != la)
658 return emulate_gp(ctxt, 0);
659 break;
660 default:
1aa36616
AK		 661 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
662 addr.seg);
618ff15d
AK		 663 if (!usable)
664 goto bad;
58b7825b
GN		 665 /* code segment in protected mode or read-only data segment */
666 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
667 || !(desc.type & 2)) && write)
618ff15d
AK		 668 goto bad;
669 /* unreadable code segment */
3d9b938e 670 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 671 goto bad;
672 lim = desc_limit_scaled(&desc);
10e38fc7
NA		 673 if ((ctxt->mode == X86EMUL_MODE_REAL) && !fetch &&
674 (ctxt->d & NoBigReal)) {
675 /* la is between zero and 0xffff */
676 if (la > 0xffff || (u32)(la + size - 1) > 0xffff)
677 goto bad;
678 } else if ((desc.type & 8) || !(desc.type & 4)) {
618ff15d
AK		 679 /* expand-up segment */
680 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
681 goto bad;
682 } else {
fc058680 683 /* expand-down segment */
618ff15d
AK		 684 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
685 goto bad;
686 lim = desc.d ? 0xffffffff : 0xffff;
687 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
688 goto bad;
689 }
717746e3 690 cpl = ctxt->ops->cpl(ctxt);
618ff15d
AK		 691 if (!(desc.type & 8)) {
692 /* data segment */
693 if (cpl > desc.dpl)
694 goto bad;
695 } else if ((desc.type & 8) && !(desc.type & 4)) {
696 /* nonconforming code segment */
697 if (cpl != desc.dpl)
698 goto bad;
699 } else if ((desc.type & 8) && (desc.type & 4)) {
700 /* conforming code segment */
701 if (cpl < desc.dpl)
702 goto bad;
703 }
704 break;
705 }
9dac77fa 706 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
52fd8b44 707 la &= (u32)-1;
1c11b376
AK		 708 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
709 return emulate_gp(ctxt, 0);
52fd8b44
AK		 710 *linear = la;
711 return X86EMUL_CONTINUE;
618ff15d
AK		 712bad:
713 if (addr.seg == VCPU_SREG_SS)
0afbe2f8 714 return emulate_ss(ctxt, sel);
618ff15d 715 else
0afbe2f8 716 return emulate_gp(ctxt, sel);
52fd8b44
AK		 717}
718
3d9b938e
NE		 719static int linearize(struct x86_emulate_ctxt *ctxt,
720 struct segmented_address addr,
721 unsigned size, bool write,
722 ulong *linear)
723{
724 return __linearize(ctxt, addr, size, write, false, linear);
725}
726
727
3ca3ac4d
AK		 728static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
729 struct segmented_address addr,
730 void *data,
731 unsigned size)
732{
9fa088f4
AK		 733 int rc;
734 ulong linear;
735
83b8795a 736 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 737 if (rc != X86EMUL_CONTINUE)
738 return rc;
0f65dd70 739 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 740}
741
807941b1 742/*
285ca9e9 743 * Prefetch the remaining bytes of the instruction without crossing page
807941b1
TY		 744 * boundary if they are not in fetch_cache yet.
745 */
9506d57d 746static int __do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, int op_size)
62266869 747{
62266869 748 int rc;
719d5a9b 749 unsigned size;
285ca9e9 750 unsigned long linear;
17052f16 751 int cur_size = ctxt->fetch.end - ctxt->fetch.data;
285ca9e9 752 struct segmented_address addr = { .seg = VCPU_SREG_CS,
17052f16
PB		 753 .ea = ctxt->eip + cur_size };
754
719d5a9b
PB		 755 size = 15UL ^ cur_size;
756 rc = __linearize(ctxt, addr, size, false, true, &linear);
757 if (unlikely(rc != X86EMUL_CONTINUE))
758 return rc;
759
760 size = min_t(unsigned, size, PAGE_SIZE - offset_in_page(linear));
5cfc7e0f
PB		 761
762 /*
763 * One instruction can only straddle two pages,
764 * and one has been loaded at the beginning of
765 * x86_decode_insn. So, if not enough bytes
766 * still, we must have hit the 15-byte boundary.
767 */
768 if (unlikely(size < op_size))
285ca9e9 769 return X86EMUL_UNHANDLEABLE;
17052f16 770 rc = ctxt->ops->fetch(ctxt, linear, ctxt->fetch.end,
285ca9e9
PB		 771 size, &ctxt->exception);
772 if (unlikely(rc != X86EMUL_CONTINUE))
773 return rc;
17052f16 774 ctxt->fetch.end += size;
3e2815e9 775 return X86EMUL_CONTINUE;
62266869
AK		 776}
777
9506d57d
PB		 778static __always_inline int do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt,
779 unsigned size)
62266869 780{
17052f16 781 if (unlikely(ctxt->fetch.end - ctxt->fetch.ptr < size))
9506d57d
PB		 782 return __do_insn_fetch_bytes(ctxt, size);
783 else
784 return X86EMUL_CONTINUE;
62266869
AK		 785}
786
67cbc90d 787/* Fetch next part of the instruction being emulated. */
e85a1085 788#define insn_fetch(_type, _ctxt) \
9506d57d 789({ _type _x; \
9506d57d
PB		 790 \
791 rc = do_insn_fetch_bytes(_ctxt, sizeof(_type)); \
67cbc90d
TY		 792 if (rc != X86EMUL_CONTINUE) \
793 goto done; \
9506d57d 794 ctxt->_eip += sizeof(_type); \
17052f16
PB		 795 _x = *(_type __aligned(1) *) ctxt->fetch.ptr; \
796 ctxt->fetch.ptr += sizeof(_type); \
9506d57d 797 _x; \
67cbc90d
TY		 798})
799
807941b1 800#define insn_fetch_arr(_arr, _size, _ctxt) \
9506d57d 801({ \
9506d57d 802 rc = do_insn_fetch_bytes(_ctxt, _size); \
67cbc90d
TY		 803 if (rc != X86EMUL_CONTINUE) \
804 goto done; \
9506d57d 805 ctxt->_eip += (_size); \
17052f16
PB		 806 memcpy(_arr, ctxt->fetch.ptr, _size); \
807 ctxt->fetch.ptr += (_size); \
67cbc90d
TY		 808})
809
1e3c5cb0
RR		 810/*
811 * Given the 'reg' portion of a ModRM byte, and a register block, return a
812 * pointer into the block that addresses the relevant register.
813 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
814 */
dd856efa 815static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
aa9ac1a6 816 int byteop)
6aa8b732
AK		 817{
818 void *p;
aa9ac1a6 819 int highbyte_regs = (ctxt->rex_prefix == 0) && byteop;
6aa8b732 820
6aa8b732 821 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
dd856efa
AK		 822 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
823 else
824 p = reg_rmw(ctxt, modrm_reg);
6aa8b732
AK		 825 return p;
826}
827
828static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 829 struct segmented_address addr,
6aa8b732
AK		 830 u16 *size, unsigned long *address, int op_bytes)
831{
832 int rc;
833
834 if (op_bytes == 2)
835 op_bytes = 3;
836 *address = 0;
3ca3ac4d 837 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 838 if (rc != X86EMUL_CONTINUE)
6aa8b732 839 return rc;
30b31ab6 840 addr.ea += 2;
3ca3ac4d 841 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 842 return rc;
843}
844
34b77652
AK		 845FASTOP2(add);
846FASTOP2(or);
847FASTOP2(adc);
848FASTOP2(sbb);
849FASTOP2(and);
850FASTOP2(sub);
851FASTOP2(xor);
852FASTOP2(cmp);
853FASTOP2(test);
854
b9fa409b
AK		 855FASTOP1SRC2(mul, mul_ex);
856FASTOP1SRC2(imul, imul_ex);
b8c0b6ae
AK		 857FASTOP1SRC2EX(div, div_ex);
858FASTOP1SRC2EX(idiv, idiv_ex);
b9fa409b 859
34b77652
AK		 860FASTOP3WCL(shld);
861FASTOP3WCL(shrd);
862
863FASTOP2W(imul);
864
865FASTOP1(not);
866FASTOP1(neg);
867FASTOP1(inc);
868FASTOP1(dec);
869
870FASTOP2CL(rol);
871FASTOP2CL(ror);
872FASTOP2CL(rcl);
873FASTOP2CL(rcr);
874FASTOP2CL(shl);
875FASTOP2CL(shr);
876FASTOP2CL(sar);
877
878FASTOP2W(bsf);
879FASTOP2W(bsr);
880FASTOP2W(bt);
881FASTOP2W(bts);
882FASTOP2W(btr);
883FASTOP2W(btc);
884
e47a5f5f
AK		 885FASTOP2(xadd);
886
9ae9feba 887static u8 test_cc(unsigned int condition, unsigned long flags)
bbe9abbd 888{
9ae9feba
AK		 889 u8 rc;
890 void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
bbe9abbd 891
9ae9feba 892 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
3f0c3d0b 893 asm("push %[flags]; popf; call *%[fastop]"
9ae9feba
AK		 894 : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags));
895 return rc;
bbe9abbd
NK		 896}
897
91ff3cb4
AK		 898static void fetch_register_operand(struct operand *op)
899{
900 switch (op->bytes) {
901 case 1:
902 op->val = *(u8 *)op->addr.reg;
903 break;
904 case 2:
905 op->val = *(u16 *)op->addr.reg;
906 break;
907 case 4:
908 op->val = *(u32 *)op->addr.reg;
909 break;
910 case 8:
911 op->val = *(u64 *)op->addr.reg;
912 break;
913 }
914}
915
1253791d
AK		 916static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
917{
918 ctxt->ops->get_fpu(ctxt);
919 switch (reg) {
89a87c67
MK		 920 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
921 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
922 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
923 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
924 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
925 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
926 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
927 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
1253791d 928#ifdef CONFIG_X86_64
89a87c67
MK		 929 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
930 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
931 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
932 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
933 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
934 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
935 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
936 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
1253791d
AK		 937#endif
938 default: BUG();
939 }
940 ctxt->ops->put_fpu(ctxt);
941}
942
943static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
944 int reg)
945{
946 ctxt->ops->get_fpu(ctxt);
947 switch (reg) {
89a87c67
MK		 948 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
949 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
950 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
951 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
952 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
953 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
954 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
955 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
1253791d 956#ifdef CONFIG_X86_64
89a87c67
MK		 957 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
958 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
959 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
960 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
961 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
962 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
963 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
964 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
1253791d
AK		 965#endif
966 default: BUG();
967 }
968 ctxt->ops->put_fpu(ctxt);
969}
970
cbe2c9d3
AK		 971static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
972{
973 ctxt->ops->get_fpu(ctxt);
974 switch (reg) {
975 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
976 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
977 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
978 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
979 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
980 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
981 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
982 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
983 default: BUG();
984 }
985 ctxt->ops->put_fpu(ctxt);
986}
987
988static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
989{
990 ctxt->ops->get_fpu(ctxt);
991 switch (reg) {
992 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
993 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
994 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
995 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
996 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
997 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
998 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
999 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
1000 default: BUG();
1001 }
1002 ctxt->ops->put_fpu(ctxt);
1003}
1004
045a282c
GN		 1005static int em_fninit(struct x86_emulate_ctxt *ctxt)
1006{
1007 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1008 return emulate_nm(ctxt);
1009
1010 ctxt->ops->get_fpu(ctxt);
1011 asm volatile("fninit");
1012 ctxt->ops->put_fpu(ctxt);
1013 return X86EMUL_CONTINUE;
1014}
1015
1016static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
1017{
1018 u16 fcw;
1019
1020 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1021 return emulate_nm(ctxt);
1022
1023 ctxt->ops->get_fpu(ctxt);
1024 asm volatile("fnstcw %0": "+m"(fcw));
1025 ctxt->ops->put_fpu(ctxt);
1026
1027 /* force 2 byte destination */
1028 ctxt->dst.bytes = 2;
1029 ctxt->dst.val = fcw;
1030
1031 return X86EMUL_CONTINUE;
1032}
1033
1034static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
1035{
1036 u16 fsw;
1037
1038 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1039 return emulate_nm(ctxt);
1040
1041 ctxt->ops->get_fpu(ctxt);
1042 asm volatile("fnstsw %0": "+m"(fsw));
1043 ctxt->ops->put_fpu(ctxt);
1044
1045 /* force 2 byte destination */
1046 ctxt->dst.bytes = 2;
1047 ctxt->dst.val = fsw;
1048
1049 return X86EMUL_CONTINUE;
1050}
1051
1253791d 1052static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 1053 struct operand *op)
3c118e24 1054{
9dac77fa 1055 unsigned reg = ctxt->modrm_reg;
33615aa9 1056
9dac77fa
AK		 1057 if (!(ctxt->d & ModRM))
1058 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 1059
9dac77fa 1060 if (ctxt->d & Sse) {
1253791d
AK		 1061 op->type = OP_XMM;
1062 op->bytes = 16;
1063 op->addr.xmm = reg;
1064 read_sse_reg(ctxt, &op->vec_val, reg);
1065 return;
1066 }
cbe2c9d3
AK		 1067 if (ctxt->d & Mmx) {
1068 reg &= 7;
1069 op->type = OP_MM;
1070 op->bytes = 8;
1071 op->addr.mm = reg;
1072 return;
1073 }
1253791d 1074
3c118e24 1075 op->type = OP_REG;
6d4d85ec
GN		 1076 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1077 op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp);
1078
91ff3cb4 1079 fetch_register_operand(op);
3c118e24
AK		 1080 op->orig_val = op->val;
1081}
1082
a6e3407b
AK		 1083static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1084{
1085 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1086 ctxt->modrm_seg = VCPU_SREG_SS;
1087}
1088
1c73ef66 1089static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1090 struct operand *op)
1c73ef66 1091{
1c73ef66 1092 u8 sib;
02357bdc 1093 int index_reg, base_reg, scale;
3e2815e9 1094 int rc = X86EMUL_CONTINUE;
2dbd0dd7 1095 ulong modrm_ea = 0;
1c73ef66 1096
02357bdc
BD		 1097 ctxt->modrm_reg = ((ctxt->rex_prefix << 1) & 8); /* REX.R */
1098 index_reg = (ctxt->rex_prefix << 2) & 8; /* REX.X */
1099 base_reg = (ctxt->rex_prefix << 3) & 8; /* REX.B */
1c73ef66 1100
02357bdc 1101 ctxt->modrm_mod = (ctxt->modrm & 0xc0) >> 6;
9dac77fa 1102 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
02357bdc 1103 ctxt->modrm_rm = base_reg | (ctxt->modrm & 0x07);
9dac77fa 1104 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 1105
9b88ae99 1106 if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) {
2dbd0dd7 1107 op->type = OP_REG;
9dac77fa 1108 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
8acb4207 1109 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm,
aa9ac1a6 1110 ctxt->d & ByteOp);
9dac77fa 1111 if (ctxt->d & Sse) {
1253791d
AK		 1112 op->type = OP_XMM;
1113 op->bytes = 16;
9dac77fa
AK		 1114 op->addr.xmm = ctxt->modrm_rm;
1115 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 1116 return rc;
1117 }
cbe2c9d3
AK		 1118 if (ctxt->d & Mmx) {
1119 op->type = OP_MM;
1120 op->bytes = 8;
bdc90722 1121 op->addr.mm = ctxt->modrm_rm & 7;
cbe2c9d3
AK		 1122 return rc;
1123 }
2dbd0dd7 1124 fetch_register_operand(op);
1c73ef66
AK		 1125 return rc;
1126 }
1127
2dbd0dd7
AK		 1128 op->type = OP_MEM;
1129
9dac77fa 1130 if (ctxt->ad_bytes == 2) {
dd856efa
AK		 1131 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1132 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1133 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1134 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1c73ef66
AK		 1135
1136 /* 16-bit ModR/M decode. */
9dac77fa 1137 switch (ctxt->modrm_mod) {
1c73ef66 1138 case 0:
9dac77fa 1139 if (ctxt->modrm_rm == 6)
e85a1085 1140 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1141 break;
1142 case 1:
e85a1085 1143 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1144 break;
1145 case 2:
e85a1085 1146 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1147 break;
1148 }
9dac77fa 1149 switch (ctxt->modrm_rm) {
1c73ef66 1150 case 0:
2dbd0dd7 1151 modrm_ea += bx + si;
1c73ef66
AK		 1152 break;
1153 case 1:
2dbd0dd7 1154 modrm_ea += bx + di;
1c73ef66
AK		 1155 break;
1156 case 2:
2dbd0dd7 1157 modrm_ea += bp + si;
1c73ef66
AK		 1158 break;
1159 case 3:
2dbd0dd7 1160 modrm_ea += bp + di;
1c73ef66
AK		 1161 break;
1162 case 4:
2dbd0dd7 1163 modrm_ea += si;
1c73ef66
AK		 1164 break;
1165 case 5:
2dbd0dd7 1166 modrm_ea += di;
1c73ef66
AK		 1167 break;
1168 case 6:
9dac77fa 1169 if (ctxt->modrm_mod != 0)
2dbd0dd7 1170 modrm_ea += bp;
1c73ef66
AK		 1171 break;
1172 case 7:
2dbd0dd7 1173 modrm_ea += bx;
1c73ef66
AK		 1174 break;
1175 }
9dac77fa
AK		 1176 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1177 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1178 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1179 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1180 } else {
1181 /* 32/64-bit ModR/M decode. */
9dac77fa 1182 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1183 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1184 index_reg |= (sib >> 3) & 7;
1185 base_reg |= sib & 7;
1186 scale = sib >> 6;
1187
9dac77fa 1188 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1189 modrm_ea += insn_fetch(s32, ctxt);
a6e3407b 1190 else {
dd856efa 1191 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1192 adjust_modrm_seg(ctxt, base_reg);
1193 }
dc71d0f1 1194 if (index_reg != 4)
dd856efa 1195 modrm_ea += reg_read(ctxt, index_reg) << scale;
9dac77fa 1196 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
84411d85 1197 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1198 ctxt->rip_relative = 1;
a6e3407b
AK		 1199 } else {
1200 base_reg = ctxt->modrm_rm;
dd856efa 1201 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1202 adjust_modrm_seg(ctxt, base_reg);
1203 }
9dac77fa 1204 switch (ctxt->modrm_mod) {
1c73ef66 1205 case 0:
9dac77fa 1206 if (ctxt->modrm_rm == 5)
e85a1085 1207 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1208 break;
1209 case 1:
e85a1085 1210 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1211 break;
1212 case 2:
e85a1085 1213 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1214 break;
1215 }
1216 }
90de84f5 1217 op->addr.mem.ea = modrm_ea;
41061cdb
BD		 1218 if (ctxt->ad_bytes != 8)
1219 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
1220
1c73ef66
AK		 1221done:
1222 return rc;
1223}
1224
1225static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1226 struct operand *op)
1c73ef66 1227{
3e2815e9 1228 int rc = X86EMUL_CONTINUE;
1c73ef66 1229
2dbd0dd7 1230 op->type = OP_MEM;
9dac77fa 1231 switch (ctxt->ad_bytes) {
1c73ef66 1232 case 2:
e85a1085 1233 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1234 break;
1235 case 4:
e85a1085 1236 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1237 break;
1238 case 8:
e85a1085 1239 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1240 break;
1241 }
1242done:
1243 return rc;
1244}
1245
9dac77fa 1246static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1247{
7129eeca 1248 long sv = 0, mask;
35c843c4 1249
9dac77fa 1250 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
7dec5603 1251 mask = ~((long)ctxt->dst.bytes * 8 - 1);
35c843c4 1252
9dac77fa
AK		 1253 if (ctxt->src.bytes == 2)
1254 sv = (s16)ctxt->src.val & (s16)mask;
1255 else if (ctxt->src.bytes == 4)
1256 sv = (s32)ctxt->src.val & (s32)mask;
7dec5603
NA		 1257 else
1258 sv = (s64)ctxt->src.val & (s64)mask;
35c843c4 1259
9dac77fa 1260 ctxt->dst.addr.mem.ea += (sv >> 3);
35c843c4 1261 }
ba7ff2b7
WY		 1262
1263 /* only subword offset */
9dac77fa 1264 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1265}
1266
dde7e6d1 1267static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1268 unsigned long addr, void *dest, unsigned size)
6aa8b732 1269{
dde7e6d1 1270 int rc;
9dac77fa 1271 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1272
f23b070e
XG		 1273 if (mc->pos < mc->end)
1274 goto read_cached;
6aa8b732 1275
f23b070e
XG		 1276 WARN_ON((mc->end + size) >= sizeof(mc->data));
1277
1278 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1279 &ctxt->exception);
1280 if (rc != X86EMUL_CONTINUE)
1281 return rc;
1282
1283 mc->end += size;
1284
1285read_cached:
1286 memcpy(dest, mc->data + mc->pos, size);
1287 mc->pos += size;
dde7e6d1
AK		 1288 return X86EMUL_CONTINUE;
1289}
6aa8b732 1290
3ca3ac4d
AK		 1291static int segmented_read(struct x86_emulate_ctxt *ctxt,
1292 struct segmented_address addr,
1293 void *data,
1294 unsigned size)
1295{
9fa088f4
AK		 1296 int rc;
1297 ulong linear;
1298
83b8795a 1299 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1300 if (rc != X86EMUL_CONTINUE)
1301 return rc;
7b105ca2 1302 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1303}
1304
1305static int segmented_write(struct x86_emulate_ctxt *ctxt,
1306 struct segmented_address addr,
1307 const void *data,
1308 unsigned size)
1309{
9fa088f4
AK		 1310 int rc;
1311 ulong linear;
1312
83b8795a 1313 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1314 if (rc != X86EMUL_CONTINUE)
1315 return rc;
0f65dd70
AK		 1316 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1317 &ctxt->exception);
3ca3ac4d
AK		 1318}
1319
1320static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1321 struct segmented_address addr,
1322 const void *orig_data, const void *data,
1323 unsigned size)
1324{
9fa088f4
AK		 1325 int rc;
1326 ulong linear;
1327
83b8795a 1328 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1329 if (rc != X86EMUL_CONTINUE)
1330 return rc;
0f65dd70
AK		 1331 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1332 size, &ctxt->exception);
3ca3ac4d
AK		 1333}
1334
dde7e6d1 1335static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1336 unsigned int size, unsigned short port,
1337 void *dest)
1338{
9dac77fa 1339 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1340
dde7e6d1 1341 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1342 unsigned int in_page, n;
9dac77fa 1343 unsigned int count = ctxt->rep_prefix ?
dd856efa 1344 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
dde7e6d1 1345 in_page = (ctxt->eflags & EFLG_DF) ?
dd856efa
AK		 1346 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1347 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
b55a8144 1348 n = min3(in_page, (unsigned int)sizeof(rc->data) / size, count);
dde7e6d1
AK		 1349 if (n == 0)
1350 n = 1;
1351 rc->pos = rc->end = 0;
7b105ca2 1352 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1353 return 0;
1354 rc->end = n * size;
6aa8b732
AK		 1355 }
1356
e6e39f04
NA		 1357 if (ctxt->rep_prefix && (ctxt->d & String) &&
1358 !(ctxt->eflags & EFLG_DF)) {
b3356bf0
GN		 1359 ctxt->dst.data = rc->data + rc->pos;
1360 ctxt->dst.type = OP_MEM_STR;
1361 ctxt->dst.count = (rc->end - rc->pos) / size;
1362 rc->pos = rc->end;
1363 } else {
1364 memcpy(dest, rc->data + rc->pos, size);
1365 rc->pos += size;
1366 }
dde7e6d1
AK		 1367 return 1;
1368}
6aa8b732 1369
7f3d35fd
KW		 1370static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1371 u16 index, struct desc_struct *desc)
1372{
1373 struct desc_ptr dt;
1374 ulong addr;
1375
1376 ctxt->ops->get_idt(ctxt, &dt);
1377
1378 if (dt.size < index * 8 + 7)
1379 return emulate_gp(ctxt, index << 3 | 0x2);
1380
1381 addr = dt.address + index * 8;
1382 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1383 &ctxt->exception);
1384}
1385
dde7e6d1 1386static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1387 u16 selector, struct desc_ptr *dt)
1388{
0225fb50 1389 const struct x86_emulate_ops *ops = ctxt->ops;
2eedcac8 1390 u32 base3 = 0;
7b105ca2 1391
dde7e6d1
AK		 1392 if (selector & 1 << 2) {
1393 struct desc_struct desc;
1aa36616
AK		 1394 u16 sel;
1395
dde7e6d1 1396 memset (dt, 0, sizeof *dt);
2eedcac8
NA		 1397 if (!ops->get_segment(ctxt, &sel, &desc, &base3,
1398 VCPU_SREG_LDTR))
dde7e6d1 1399 return;
e09d082c 1400
dde7e6d1 1401 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
2eedcac8 1402 dt->address = get_desc_base(&desc) | ((u64)base3 << 32);
dde7e6d1 1403 } else
4bff1e86 1404 ops->get_gdt(ctxt, dt);
dde7e6d1 1405}
120df890 1406
dde7e6d1
AK		 1407/* allowed just for 8 bytes segments */
1408static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
e919464b
AK		 1409 u16 selector, struct desc_struct *desc,
1410 ulong *desc_addr_p)
dde7e6d1
AK		 1411{
1412 struct desc_ptr dt;
1413 u16 index = selector >> 3;
dde7e6d1 1414 ulong addr;
120df890 1415
7b105ca2 1416 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1417
35d3d4a1
AK		 1418 if (dt.size < index * 8 + 7)
1419 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1420
e919464b 1421 *desc_addr_p = addr = dt.address + index * 8;
7b105ca2
TY		 1422 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1423 &ctxt->exception);
dde7e6d1 1424}
ef65c889 1425
dde7e6d1
AK		 1426/* allowed just for 8 bytes segments */
1427static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1428 u16 selector, struct desc_struct *desc)
1429{
1430 struct desc_ptr dt;
1431 u16 index = selector >> 3;
dde7e6d1 1432 ulong addr;
6aa8b732 1433
7b105ca2 1434 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1435
35d3d4a1
AK		 1436 if (dt.size < index * 8 + 7)
1437 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1438
dde7e6d1 1439 addr = dt.address + index * 8;
7b105ca2
TY		 1440 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1441 &ctxt->exception);
dde7e6d1 1442}
c7e75a3d 1443
5601d05b 1444/* Does not support long mode */
2356aaeb 1445static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
5045b468 1446 u16 selector, int seg, u8 cpl, bool in_task_switch)
dde7e6d1 1447{
869be99c 1448 struct desc_struct seg_desc, old_desc;
2356aaeb 1449 u8 dpl, rpl;
dde7e6d1
AK		 1450 unsigned err_vec = GP_VECTOR;
1451 u32 err_code = 0;
1452 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
e919464b 1453 ulong desc_addr;
dde7e6d1 1454 int ret;
03ebebeb 1455 u16 dummy;
e37a75a1 1456 u32 base3 = 0;
69f55cb1 1457
dde7e6d1 1458 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1459
f8da94e9
KW		 1460 if (ctxt->mode == X86EMUL_MODE_REAL) {
1461 /* set real mode segment descriptor (keep limit etc. for
1462 * unreal mode) */
03ebebeb 1463 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
dde7e6d1 1464 set_desc_base(&seg_desc, selector << 4);
dde7e6d1 1465 goto load;
f8da94e9
KW		 1466 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
1467 /* VM86 needs a clean new segment descriptor */
1468 set_desc_base(&seg_desc, selector << 4);
1469 set_desc_limit(&seg_desc, 0xffff);
1470 seg_desc.type = 3;
1471 seg_desc.p = 1;
1472 seg_desc.s = 1;
1473 seg_desc.dpl = 3;
1474 goto load;
dde7e6d1
AK		 1475 }
1476
79d5b4c3 1477 rpl = selector & 3;
79d5b4c3
AK		 1478
1479 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1480 if ((seg == VCPU_SREG_CS
1481 || (seg == VCPU_SREG_SS
1482 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1483 || seg == VCPU_SREG_TR)
dde7e6d1
AK		 1484 && null_selector)
1485 goto exception;
1486
1487 /* TR should be in GDT only */
1488 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1489 goto exception;
1490
1491 if (null_selector) /* for NULL selector skip all following checks */
1492 goto load;
1493
e919464b 1494 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
dde7e6d1
AK		 1495 if (ret != X86EMUL_CONTINUE)
1496 return ret;
1497
1498 err_code = selector & 0xfffc;
15fc0752 1499 err_vec = in_task_switch ? TS_VECTOR : GP_VECTOR;
dde7e6d1 1500
fc058680 1501 /* can't load system descriptor into segment selector */
dde7e6d1
AK		 1502 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1503 goto exception;
1504
1505 if (!seg_desc.p) {
1506 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1507 goto exception;
1508 }
1509
dde7e6d1 1510 dpl = seg_desc.dpl;
dde7e6d1
AK		 1511
1512 switch (seg) {
1513 case VCPU_SREG_SS:
1514 /*
1515 * segment is not a writable data segment or segment
1516 * selector's RPL != CPL or segment selector's RPL != CPL
1517 */
1518 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1519 goto exception;
6aa8b732 1520 break;
dde7e6d1
AK		 1521 case VCPU_SREG_CS:
1522 if (!(seg_desc.type & 8))
1523 goto exception;
1524
1525 if (seg_desc.type & 4) {
1526 /* conforming */
1527 if (dpl > cpl)
1528 goto exception;
1529 } else {
1530 /* nonconforming */
1531 if (rpl > cpl || dpl != cpl)
1532 goto exception;
1533 }
040c8dc8
NA		 1534 /* in long-mode d/b must be clear if l is set */
1535 if (seg_desc.d && seg_desc.l) {
1536 u64 efer = 0;
1537
1538 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
1539 if (efer & EFER_LMA)
1540 goto exception;
1541 }
1542
dde7e6d1
AK		 1543 /* CS(RPL) <- CPL */
1544 selector = (selector & 0xfffc) | cpl;
6aa8b732 1545 break;
dde7e6d1
AK		 1546 case VCPU_SREG_TR:
1547 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1548 goto exception;
869be99c
AK		 1549 old_desc = seg_desc;
1550 seg_desc.type |= 2; /* busy */
1551 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1552 sizeof(seg_desc), &ctxt->exception);
1553 if (ret != X86EMUL_CONTINUE)
1554 return ret;
dde7e6d1
AK		 1555 break;
1556 case VCPU_SREG_LDTR:
1557 if (seg_desc.s || seg_desc.type != 2)
1558 goto exception;
1559 break;
1560 default: /* DS, ES, FS, or GS */
4e62417b 1561 /*
dde7e6d1
AK		 1562 * segment is not a data or readable code segment or
1563 * ((segment is a data or nonconforming code segment)
1564 * and (both RPL and CPL > DPL))
4e62417b 1565 */
dde7e6d1
AK		 1566 if ((seg_desc.type & 0xa) == 0x8 ||
1567 (((seg_desc.type & 0xc) != 0xc) &&
1568 (rpl > dpl && cpl > dpl)))
1569 goto exception;
6aa8b732 1570 break;
dde7e6d1
AK		 1571 }
1572
1573 if (seg_desc.s) {
1574 /* mark segment as accessed */
1575 seg_desc.type |= 1;
7b105ca2 1576 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1577 if (ret != X86EMUL_CONTINUE)
1578 return ret;
e37a75a1
NA		 1579 } else if (ctxt->mode == X86EMUL_MODE_PROT64) {
1580 ret = ctxt->ops->read_std(ctxt, desc_addr+8, &base3,
1581 sizeof(base3), &ctxt->exception);
1582 if (ret != X86EMUL_CONTINUE)
1583 return ret;
dde7e6d1
AK		 1584 }
1585load:
e37a75a1 1586 ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg);
dde7e6d1
AK		 1587 return X86EMUL_CONTINUE;
1588exception:
592f0858 1589 return emulate_exception(ctxt, err_vec, err_code, true);
dde7e6d1
AK		 1590}
1591
2356aaeb
PB		 1592static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1593 u16 selector, int seg)
1594{
1595 u8 cpl = ctxt->ops->cpl(ctxt);
5045b468 1596 return __load_segment_descriptor(ctxt, selector, seg, cpl, false);
2356aaeb
PB		 1597}
1598
31be40b3
WY		 1599static void write_register_operand(struct operand *op)
1600{
1601 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1602 switch (op->bytes) {
1603 case 1:
1604 *(u8 *)op->addr.reg = (u8)op->val;
1605 break;
1606 case 2:
1607 *(u16 *)op->addr.reg = (u16)op->val;
1608 break;
1609 case 4:
1610 *op->addr.reg = (u32)op->val;
1611 break; /* 64b: zero-extend */
1612 case 8:
1613 *op->addr.reg = op->val;
1614 break;
1615 }
1616}
1617
fb32b1ed 1618static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
dde7e6d1 1619{
fb32b1ed 1620 switch (op->type) {
dde7e6d1 1621 case OP_REG:
fb32b1ed 1622 write_register_operand(op);
6aa8b732 1623 break;
dde7e6d1 1624 case OP_MEM:
9dac77fa 1625 if (ctxt->lock_prefix)
f5f87dfb
PB		 1626 return segmented_cmpxchg(ctxt,
1627 op->addr.mem,
1628 &op->orig_val,
1629 &op->val,
1630 op->bytes);
1631 else
1632 return segmented_write(ctxt,
fb32b1ed 1633 op->addr.mem,
fb32b1ed
AK		 1634 &op->val,
1635 op->bytes);
a682e354 1636 break;
b3356bf0 1637 case OP_MEM_STR:
f5f87dfb
PB		 1638 return segmented_write(ctxt,
1639 op->addr.mem,
1640 op->data,
1641 op->bytes * op->count);
b3356bf0 1642 break;
1253791d 1643 case OP_XMM:
fb32b1ed 1644 write_sse_reg(ctxt, &op->vec_val, op->addr.xmm);
1253791d 1645 break;
cbe2c9d3 1646 case OP_MM:
fb32b1ed 1647 write_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
cbe2c9d3 1648 break;
dde7e6d1
AK		 1649 case OP_NONE:
1650 /* no writeback */
414e6277 1651 break;
dde7e6d1 1652 default:
414e6277 1653 break;
6aa8b732 1654 }
dde7e6d1
AK		 1655 return X86EMUL_CONTINUE;
1656}
6aa8b732 1657
51ddff50 1658static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
dde7e6d1 1659{
4179bb02 1660 struct segmented_address addr;
0dc8d10f 1661
5ad105e5 1662 rsp_increment(ctxt, -bytes);
dd856efa 1663 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
4179bb02
TY		 1664 addr.seg = VCPU_SREG_SS;
1665
51ddff50
AK		 1666 return segmented_write(ctxt, addr, data, bytes);
1667}
1668
1669static int em_push(struct x86_emulate_ctxt *ctxt)
1670{
4179bb02 1671 /* Disable writeback. */
9dac77fa 1672 ctxt->dst.type = OP_NONE;
51ddff50 1673 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1674}
69f55cb1 1675
dde7e6d1 1676static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1677 void *dest, int len)
1678{
dde7e6d1 1679 int rc;
90de84f5 1680 struct segmented_address addr;
8b4caf66 1681
dd856efa 1682 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
90de84f5 1683 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1684 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1685 if (rc != X86EMUL_CONTINUE)
1686 return rc;
1687
5ad105e5 1688 rsp_increment(ctxt, len);
dde7e6d1 1689 return rc;
8b4caf66
LV		 1690}
1691
c54fe504
TY		 1692static int em_pop(struct x86_emulate_ctxt *ctxt)
1693{
9dac77fa 1694 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1695}
1696
dde7e6d1 1697static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1698 void *dest, int len)
9de41573
GN		 1699{
1700 int rc;
dde7e6d1
AK		 1701 unsigned long val, change_mask;
1702 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1703 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1704
3b9be3bf 1705 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1706 if (rc != X86EMUL_CONTINUE)
1707 return rc;
9de41573 1708
dde7e6d1 1709 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
163b135e 1710 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_AC | EFLG_ID;
9de41573 1711
dde7e6d1
AK		 1712 switch(ctxt->mode) {
1713 case X86EMUL_MODE_PROT64:
1714 case X86EMUL_MODE_PROT32:
1715 case X86EMUL_MODE_PROT16:
1716 if (cpl == 0)
1717 change_mask |= EFLG_IOPL;
1718 if (cpl <= iopl)
1719 change_mask |= EFLG_IF;
1720 break;
1721 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1722 if (iopl < 3)
1723 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1724 change_mask |= EFLG_IF;
1725 break;
1726 default: /* real mode */
1727 change_mask |= (EFLG_IOPL | EFLG_IF);
1728 break;
9de41573 1729 }
dde7e6d1
AK		 1730
1731 *(unsigned long *)dest =
1732 (ctxt->eflags & ~change_mask) | (val & change_mask);
1733
1734 return rc;
9de41573
GN		 1735}
1736
62aaa2f0
TY		 1737static int em_popf(struct x86_emulate_ctxt *ctxt)
1738{
9dac77fa
AK		 1739 ctxt->dst.type = OP_REG;
1740 ctxt->dst.addr.reg = &ctxt->eflags;
1741 ctxt->dst.bytes = ctxt->op_bytes;
1742 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1743}
1744
612e89f0
AK		 1745static int em_enter(struct x86_emulate_ctxt *ctxt)
1746{
1747 int rc;
1748 unsigned frame_size = ctxt->src.val;
1749 unsigned nesting_level = ctxt->src2.val & 31;
dd856efa 1750 ulong rbp;
612e89f0
AK		 1751
1752 if (nesting_level)
1753 return X86EMUL_UNHANDLEABLE;
1754
dd856efa
AK		 1755 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1756 rc = push(ctxt, &rbp, stack_size(ctxt));
612e89f0
AK		 1757 if (rc != X86EMUL_CONTINUE)
1758 return rc;
dd856efa 1759 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
612e89f0 1760 stack_mask(ctxt));
dd856efa
AK		 1761 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1762 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
612e89f0
AK		 1763 stack_mask(ctxt));
1764 return X86EMUL_CONTINUE;
1765}
1766
f47cfa31
AK		 1767static int em_leave(struct x86_emulate_ctxt *ctxt)
1768{
dd856efa 1769 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
f47cfa31 1770 stack_mask(ctxt));
dd856efa 1771 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
f47cfa31
AK		 1772}
1773
1cd196ea 1774static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1775{
1cd196ea
AK		 1776 int seg = ctxt->src2.val;
1777
9dac77fa 1778 ctxt->src.val = get_segment_selector(ctxt, seg);
7b262e90 1779
4487b3b4 1780 return em_push(ctxt);
7b262e90
GN		 1781}
1782
1cd196ea 1783static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1784{
1cd196ea 1785 int seg = ctxt->src2.val;
dde7e6d1
AK		 1786 unsigned long selector;
1787 int rc;
38ba30ba 1788
9dac77fa 1789 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
dde7e6d1
AK		 1790 if (rc != X86EMUL_CONTINUE)
1791 return rc;
1792
a5457e7b
PB		 1793 if (ctxt->modrm_reg == VCPU_SREG_SS)
1794 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
1795
7b105ca2 1796 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1797 return rc;
38ba30ba
GN		 1798}
1799
b96a7fad 1800static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1801{
dd856efa 1802 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
dde7e6d1
AK		 1803 int rc = X86EMUL_CONTINUE;
1804 int reg = VCPU_REGS_RAX;
38ba30ba 1805
dde7e6d1
AK		 1806 while (reg <= VCPU_REGS_RDI) {
1807 (reg == VCPU_REGS_RSP) ?
dd856efa 1808 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
38ba30ba 1809
4487b3b4 1810 rc = em_push(ctxt);
dde7e6d1
AK		 1811 if (rc != X86EMUL_CONTINUE)
1812 return rc;
38ba30ba 1813
dde7e6d1 1814 ++reg;
38ba30ba 1815 }
38ba30ba 1816
dde7e6d1 1817 return rc;
38ba30ba
GN		 1818}
1819
62aaa2f0
TY		 1820static int em_pushf(struct x86_emulate_ctxt *ctxt)
1821{
9dac77fa 1822 ctxt->src.val = (unsigned long)ctxt->eflags;
62aaa2f0
TY		 1823 return em_push(ctxt);
1824}
1825
b96a7fad 1826static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1827{
dde7e6d1
AK		 1828 int rc = X86EMUL_CONTINUE;
1829 int reg = VCPU_REGS_RDI;
38ba30ba 1830
dde7e6d1
AK		 1831 while (reg >= VCPU_REGS_RAX) {
1832 if (reg == VCPU_REGS_RSP) {
5ad105e5 1833 rsp_increment(ctxt, ctxt->op_bytes);
dde7e6d1
AK		 1834 --reg;
1835 }
38ba30ba 1836
dd856efa 1837 rc = emulate_pop(ctxt, reg_rmw(ctxt, reg), ctxt->op_bytes);
dde7e6d1
AK		 1838 if (rc != X86EMUL_CONTINUE)
1839 break;
1840 --reg;
38ba30ba 1841 }
dde7e6d1 1842 return rc;
38ba30ba
GN		 1843}
1844
dd856efa 1845static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1846{
0225fb50 1847 const struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1848 int rc;
6e154e56
MG		 1849 struct desc_ptr dt;
1850 gva_t cs_addr;
1851 gva_t eip_addr;
1852 u16 cs, eip;
6e154e56
MG		 1853
1854 /* TODO: Add limit checks */
9dac77fa 1855 ctxt->src.val = ctxt->eflags;
4487b3b4 1856 rc = em_push(ctxt);
5c56e1cf
AK		 1857 if (rc != X86EMUL_CONTINUE)
1858 return rc;
6e154e56
MG		 1859
1860 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1861
9dac77fa 1862 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1863 rc = em_push(ctxt);
5c56e1cf
AK		 1864 if (rc != X86EMUL_CONTINUE)
1865 return rc;
6e154e56 1866
9dac77fa 1867 ctxt->src.val = ctxt->_eip;
4487b3b4 1868 rc = em_push(ctxt);
5c56e1cf
AK		 1869 if (rc != X86EMUL_CONTINUE)
1870 return rc;
1871
4bff1e86 1872 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1873
1874 eip_addr = dt.address + (irq << 2);
1875 cs_addr = dt.address + (irq << 2) + 2;
1876
0f65dd70 1877 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1878 if (rc != X86EMUL_CONTINUE)
1879 return rc;
1880
0f65dd70 1881 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1882 if (rc != X86EMUL_CONTINUE)
1883 return rc;
1884
7b105ca2 1885 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1886 if (rc != X86EMUL_CONTINUE)
1887 return rc;
1888
9dac77fa 1889 ctxt->_eip = eip;
6e154e56
MG		 1890
1891 return rc;
1892}
1893
dd856efa
AK		 1894int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
1895{
1896 int rc;
1897
1898 invalidate_registers(ctxt);
1899 rc = __emulate_int_real(ctxt, irq);
1900 if (rc == X86EMUL_CONTINUE)
1901 writeback_registers(ctxt);
1902 return rc;
1903}
1904
7b105ca2 1905static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 1906{
1907 switch(ctxt->mode) {
1908 case X86EMUL_MODE_REAL:
dd856efa 1909 return __emulate_int_real(ctxt, irq);
6e154e56
MG		 1910 case X86EMUL_MODE_VM86:
1911 case X86EMUL_MODE_PROT16:
1912 case X86EMUL_MODE_PROT32:
1913 case X86EMUL_MODE_PROT64:
1914 default:
1915 /* Protected mode interrupts unimplemented yet */
1916 return X86EMUL_UNHANDLEABLE;
1917 }
1918}
1919
7b105ca2 1920static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 1921{
dde7e6d1
AK		 1922 int rc = X86EMUL_CONTINUE;
1923 unsigned long temp_eip = 0;
1924 unsigned long temp_eflags = 0;
1925 unsigned long cs = 0;
1926 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1927 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1928 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1929 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1930
dde7e6d1 1931 /* TODO: Add stack limit check */
38ba30ba 1932
9dac77fa 1933 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 1934
dde7e6d1
AK		 1935 if (rc != X86EMUL_CONTINUE)
1936 return rc;
38ba30ba 1937
35d3d4a1
AK		 1938 if (temp_eip & ~0xffff)
1939 return emulate_gp(ctxt, 0);
38ba30ba 1940
9dac77fa 1941 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 1942
dde7e6d1
AK		 1943 if (rc != X86EMUL_CONTINUE)
1944 return rc;
38ba30ba 1945
9dac77fa 1946 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 1947
dde7e6d1
AK		 1948 if (rc != X86EMUL_CONTINUE)
1949 return rc;
38ba30ba 1950
7b105ca2 1951 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 1952
dde7e6d1
AK		 1953 if (rc != X86EMUL_CONTINUE)
1954 return rc;
38ba30ba 1955
9dac77fa 1956 ctxt->_eip = temp_eip;
38ba30ba 1957
38ba30ba 1958
9dac77fa 1959 if (ctxt->op_bytes == 4)
dde7e6d1 1960 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 1961 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 1962 ctxt->eflags &= ~0xffff;
1963 ctxt->eflags |= temp_eflags;
38ba30ba 1964 }
dde7e6d1
AK		 1965
1966 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1967 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1968
1969 return rc;
38ba30ba
GN		 1970}
1971
e01991e7 1972static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 1973{
dde7e6d1
AK		 1974 switch(ctxt->mode) {
1975 case X86EMUL_MODE_REAL:
7b105ca2 1976 return emulate_iret_real(ctxt);
dde7e6d1
AK		 1977 case X86EMUL_MODE_VM86:
1978 case X86EMUL_MODE_PROT16:
1979 case X86EMUL_MODE_PROT32:
1980 case X86EMUL_MODE_PROT64:
c37eda13 1981 default:
dde7e6d1
AK		 1982 /* iret from protected mode unimplemented yet */
1983 return X86EMUL_UNHANDLEABLE;
c37eda13 1984 }
c37eda13
WY		 1985}
1986
d2f62766
TY		 1987static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
1988{
d2f62766
TY		 1989 int rc;
1990 unsigned short sel;
1991
9dac77fa 1992 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 1993
7b105ca2 1994 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS);
d2f62766
TY		 1995 if (rc != X86EMUL_CONTINUE)
1996 return rc;
1997
9dac77fa
AK		 1998 ctxt->_eip = 0;
1999 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
d2f62766
TY		 2000 return X86EMUL_CONTINUE;
2001}
2002
51187683 2003static int em_grp45(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2004{
4179bb02 2005 int rc = X86EMUL_CONTINUE;
8cdbd2c9 2006
9dac77fa 2007 switch (ctxt->modrm_reg) {
d19292e4
MG		 2008 case 2: /* call near abs */ {
2009 long int old_eip;
9dac77fa 2010 old_eip = ctxt->_eip;
234f3ce4
NA		 2011 rc = assign_eip_near(ctxt, ctxt->src.val);
2012 if (rc != X86EMUL_CONTINUE)
2013 break;
9dac77fa 2014 ctxt->src.val = old_eip;
4487b3b4 2015 rc = em_push(ctxt);
d19292e4
MG		 2016 break;
2017 }
8cdbd2c9 2018 case 4: /* jmp abs */
234f3ce4 2019 rc = assign_eip_near(ctxt, ctxt->src.val);
8cdbd2c9 2020 break;
d2f62766
TY		 2021 case 5: /* jmp far */
2022 rc = em_jmp_far(ctxt);
2023 break;
8cdbd2c9 2024 case 6: /* push */
4487b3b4 2025 rc = em_push(ctxt);
8cdbd2c9 2026 break;
8cdbd2c9 2027 }
4179bb02 2028 return rc;
8cdbd2c9
LV		 2029}
2030
e0dac408 2031static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2032{
9dac77fa 2033 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 2034
aaa05f24
NA		 2035 if (ctxt->dst.bytes == 16)
2036 return X86EMUL_UNHANDLEABLE;
2037
dd856efa
AK		 2038 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
2039 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
2040 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
2041 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
05f086f8 2042 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 2043 } else {
dd856efa
AK		 2044 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2045 (u32) reg_read(ctxt, VCPU_REGS_RBX);
8cdbd2c9 2046
05f086f8 2047 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 2048 }
1b30eaa8 2049 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2050}
2051
ebda02c2
TY		 2052static int em_ret(struct x86_emulate_ctxt *ctxt)
2053{
234f3ce4
NA		 2054 int rc;
2055 unsigned long eip;
2056
2057 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
2058 if (rc != X86EMUL_CONTINUE)
2059 return rc;
2060
2061 return assign_eip_near(ctxt, eip);
ebda02c2
TY		 2062}
2063
e01991e7 2064static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 2065{
a77ab5ea
AK		 2066 int rc;
2067 unsigned long cs;
9e8919ae 2068 int cpl = ctxt->ops->cpl(ctxt);
a77ab5ea 2069
9dac77fa 2070 rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes);
1b30eaa8 2071 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2072 return rc;
9dac77fa
AK		 2073 if (ctxt->op_bytes == 4)
2074 ctxt->_eip = (u32)ctxt->_eip;
2075 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 2076 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2077 return rc;
9e8919ae
NA		 2078 /* Outer-privilege level return is not implemented */
2079 if (ctxt->mode >= X86EMUL_MODE_PROT16 && (cs & 3) > cpl)
2080 return X86EMUL_UNHANDLEABLE;
7b105ca2 2081 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 2082 return rc;
2083}
2084
3261107e
BR		 2085static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt)
2086{
2087 int rc;
2088
2089 rc = em_ret_far(ctxt);
2090 if (rc != X86EMUL_CONTINUE)
2091 return rc;
2092 rsp_increment(ctxt, ctxt->src.val);
2093 return X86EMUL_CONTINUE;
2094}
2095
e940b5c2
TY		 2096static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2097{
2098 /* Save real source value, then compare EAX against destination. */
37c564f2
NA		 2099 ctxt->dst.orig_val = ctxt->dst.val;
2100 ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX);
e940b5c2 2101 ctxt->src.orig_val = ctxt->src.val;
37c564f2 2102 ctxt->src.val = ctxt->dst.orig_val;
158de57f 2103 fastop(ctxt, em_cmp);
e940b5c2
TY		 2104
2105 if (ctxt->eflags & EFLG_ZF) {
2106 /* Success: write back to memory. */
2107 ctxt->dst.val = ctxt->src.orig_val;
2108 } else {
2109 /* Failure: write the value we saw to EAX. */
2110 ctxt->dst.type = OP_REG;
dd856efa 2111 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
37c564f2 2112 ctxt->dst.val = ctxt->dst.orig_val;
e940b5c2
TY		 2113 }
2114 return X86EMUL_CONTINUE;
2115}
2116
d4b4325f 2117static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 2118{
d4b4325f 2119 int seg = ctxt->src2.val;
09b5f4d3
WY		 2120 unsigned short sel;
2121 int rc;
2122
9dac77fa 2123 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 2124
7b105ca2 2125 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 2126 if (rc != X86EMUL_CONTINUE)
2127 return rc;
2128
9dac77fa 2129 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 2130 return rc;
2131}
2132
7b105ca2 2133static void
e66bb2cc 2134setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 2135 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 2136{
e66bb2cc 2137 cs->l = 0; /* will be adjusted later */
79168fd1 2138 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 2139 cs->g = 1; /* 4kb granularity */
79168fd1 2140 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2141 cs->type = 0x0b; /* Read, Execute, Accessed */
2142 cs->s = 1;
2143 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 2144 cs->p = 1;
2145 cs->d = 1;
99245b50 2146 cs->avl = 0;
e66bb2cc 2147
79168fd1
GN		 2148 set_desc_base(ss, 0); /* flat segment */
2149 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2150 ss->g = 1; /* 4kb granularity */
2151 ss->s = 1;
2152 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2153 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2154 ss->dpl = 0;
79168fd1 2155 ss->p = 1;
99245b50
GN		 2156 ss->l = 0;
2157 ss->avl = 0;
e66bb2cc
AP		 2158}
2159
1a18a69b
AK		 2160static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2161{
2162 u32 eax, ebx, ecx, edx;
2163
2164 eax = ecx = 0;
0017f93a
AK		 2165 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2166 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1a18a69b
AK		 2167 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2168 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2169}
2170
c2226fc9
SB		 2171static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2172{
0225fb50 2173 const struct x86_emulate_ops *ops = ctxt->ops;
c2226fc9
SB		 2174 u32 eax, ebx, ecx, edx;
2175
2176 /*
2177 * syscall should always be enabled in longmode - so only become
2178 * vendor specific (cpuid) if other modes are active...
2179 */
2180 if (ctxt->mode == X86EMUL_MODE_PROT64)
2181 return true;
2182
2183 eax = 0x00000000;
2184 ecx = 0x00000000;
0017f93a
AK		 2185 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2186 /*
2187 * Intel ("GenuineIntel")
2188 * remark: Intel CPUs only support "syscall" in 64bit
2189 * longmode. Also an 64bit guest with a
2190 * 32bit compat-app running will #UD !! While this
2191 * behaviour can be fixed (by emulating) into AMD
2192 * response - CPUs of AMD can't behave like Intel.
2193 */
2194 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2195 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2196 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2197 return false;
2198
2199 /* AMD ("AuthenticAMD") */
2200 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2201 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2202 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2203 return true;
2204
2205 /* AMD ("AMDisbetter!") */
2206 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2207 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2208 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2209 return true;
c2226fc9
SB		 2210
2211 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2212 return false;
2213}
2214
e01991e7 2215static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2216{
0225fb50 2217 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2218 struct desc_struct cs, ss;
e66bb2cc 2219 u64 msr_data;
79168fd1 2220 u16 cs_sel, ss_sel;
c2ad2bb3 2221 u64 efer = 0;
e66bb2cc
AP		 2222
2223 /* syscall is not available in real mode */
2e901c4c 2224 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2225 ctxt->mode == X86EMUL_MODE_VM86)
2226 return emulate_ud(ctxt);
e66bb2cc 2227
c2226fc9
SB		 2228 if (!(em_syscall_is_enabled(ctxt)))
2229 return emulate_ud(ctxt);
2230
c2ad2bb3 2231 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2232 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2233
c2226fc9
SB		 2234 if (!(efer & EFER_SCE))
2235 return emulate_ud(ctxt);
2236
717746e3 2237 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2238 msr_data >>= 32;
79168fd1
GN		 2239 cs_sel = (u16)(msr_data & 0xfffc);
2240 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2241
c2ad2bb3 2242 if (efer & EFER_LMA) {
79168fd1 2243 cs.d = 0;
e66bb2cc
AP		 2244 cs.l = 1;
2245 }
1aa36616
AK		 2246 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2247 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2248
dd856efa 2249 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
c2ad2bb3 2250 if (efer & EFER_LMA) {
e66bb2cc 2251#ifdef CONFIG_X86_64
6c6cb69b 2252 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags;
e66bb2cc 2253
717746e3 2254 ops->get_msr(ctxt,
3fb1b5db
GN		 2255 ctxt->mode == X86EMUL_MODE_PROT64 ?
2256 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2257 ctxt->_eip = msr_data;
e66bb2cc 2258
717746e3 2259 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
6c6cb69b 2260 ctxt->eflags &= ~msr_data;
e66bb2cc
AP		 2261#endif
2262 } else {
2263 /* legacy mode */
717746e3 2264 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2265 ctxt->_eip = (u32)msr_data;
e66bb2cc 2266
6c6cb69b 2267 ctxt->eflags &= ~(EFLG_VM | EFLG_IF);
e66bb2cc
AP		 2268 }
2269
e54cfa97 2270 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2271}
2272
e01991e7 2273static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2274{
0225fb50 2275 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2276 struct desc_struct cs, ss;
8c604352 2277 u64 msr_data;
79168fd1 2278 u16 cs_sel, ss_sel;
c2ad2bb3 2279 u64 efer = 0;
8c604352 2280
7b105ca2 2281 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2282 /* inject #GP if in real mode */
35d3d4a1
AK		 2283 if (ctxt->mode == X86EMUL_MODE_REAL)
2284 return emulate_gp(ctxt, 0);
8c604352 2285
1a18a69b
AK		 2286 /*
2287 * Not recognized on AMD in compat mode (but is recognized in legacy
2288 * mode).
2289 */
2290 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
2291 && !vendor_intel(ctxt))
2292 return emulate_ud(ctxt);
2293
8c604352
AP		 2294 /* XXX sysenter/sysexit have not been tested in 64bit mode.
2295 * Therefore, we inject an #UD.
2296 */
35d3d4a1
AK		 2297 if (ctxt->mode == X86EMUL_MODE_PROT64)
2298 return emulate_ud(ctxt);
8c604352 2299
7b105ca2 2300 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2301
717746e3 2302 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2303 switch (ctxt->mode) {
2304 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 2305 if ((msr_data & 0xfffc) == 0x0)
2306 return emulate_gp(ctxt, 0);
8c604352
AP		 2307 break;
2308 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 2309 if (msr_data == 0x0)
2310 return emulate_gp(ctxt, 0);
8c604352 2311 break;
9d1b39a9
GN		 2312 default:
2313 break;
8c604352
AP		 2314 }
2315
6c6cb69b 2316 ctxt->eflags &= ~(EFLG_VM | EFLG_IF);
79168fd1
GN		 2317 cs_sel = (u16)msr_data;
2318 cs_sel &= ~SELECTOR_RPL_MASK;
2319 ss_sel = cs_sel + 8;
2320 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 2321 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 2322 cs.d = 0;
8c604352
AP		 2323 cs.l = 1;
2324 }
2325
1aa36616
AK		 2326 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2327 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2328
717746e3 2329 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 2330 ctxt->_eip = msr_data;
8c604352 2331
717746e3 2332 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
dd856efa 2333 *reg_write(ctxt, VCPU_REGS_RSP) = msr_data;
8c604352 2334
e54cfa97 2335 return X86EMUL_CONTINUE;
8c604352
AP		 2336}
2337
e01991e7 2338static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2339{
0225fb50 2340 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2341 struct desc_struct cs, ss;
234f3ce4 2342 u64 msr_data, rcx, rdx;
4668f050 2343 int usermode;
1249b96e 2344 u16 cs_sel = 0, ss_sel = 0;
4668f050 2345
a0044755
GN		 2346 /* inject #GP if in real mode or Virtual 8086 mode */
2347 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2348 ctxt->mode == X86EMUL_MODE_VM86)
2349 return emulate_gp(ctxt, 0);
4668f050 2350
7b105ca2 2351 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2352
9dac77fa 2353 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2354 usermode = X86EMUL_MODE_PROT64;
2355 else
2356 usermode = X86EMUL_MODE_PROT32;
2357
234f3ce4
NA		 2358 rcx = reg_read(ctxt, VCPU_REGS_RCX);
2359 rdx = reg_read(ctxt, VCPU_REGS_RDX);
2360
4668f050
AP		 2361 cs.dpl = 3;
2362 ss.dpl = 3;
717746e3 2363 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2364 switch (usermode) {
2365 case X86EMUL_MODE_PROT32:
79168fd1 2366 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2367 if ((msr_data & 0xfffc) == 0x0)
2368 return emulate_gp(ctxt, 0);
79168fd1 2369 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2370 break;
2371 case X86EMUL_MODE_PROT64:
79168fd1 2372 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2373 if (msr_data == 0x0)
2374 return emulate_gp(ctxt, 0);
79168fd1
GN		 2375 ss_sel = cs_sel + 8;
2376 cs.d = 0;
4668f050 2377 cs.l = 1;
234f3ce4
NA		 2378 if (is_noncanonical_address(rcx) ||
2379 is_noncanonical_address(rdx))
2380 return emulate_gp(ctxt, 0);
4668f050
AP		 2381 break;
2382 }
79168fd1
GN		 2383 cs_sel |= SELECTOR_RPL_MASK;
2384 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2385
1aa36616
AK		 2386 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2387 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2388
234f3ce4
NA		 2389 ctxt->_eip = rdx;
2390 *reg_write(ctxt, VCPU_REGS_RSP) = rcx;
4668f050 2391
e54cfa97 2392 return X86EMUL_CONTINUE;
4668f050
AP		 2393}
2394
7b105ca2 2395static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2396{
2397 int iopl;
2398 if (ctxt->mode == X86EMUL_MODE_REAL)
2399 return false;
2400 if (ctxt->mode == X86EMUL_MODE_VM86)
2401 return true;
2402 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2403 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2404}
2405
2406static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2407 u16 port, u16 len)
2408{
0225fb50 2409 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2410 struct desc_struct tr_seg;
5601d05b 2411 u32 base3;
f850e2e6 2412 int r;
1aa36616 2413 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2414 unsigned mask = (1 << len) - 1;
5601d05b 2415 unsigned long base;
f850e2e6 2416
1aa36616 2417 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2418 if (!tr_seg.p)
f850e2e6 2419 return false;
79168fd1 2420 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2421 return false;
5601d05b
GN		 2422 base = get_desc_base(&tr_seg);
2423#ifdef CONFIG_X86_64
2424 base |= ((u64)base3) << 32;
2425#endif
0f65dd70 2426 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2427 if (r != X86EMUL_CONTINUE)
2428 return false;
79168fd1 2429 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2430 return false;
0f65dd70 2431 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2432 if (r != X86EMUL_CONTINUE)
2433 return false;
2434 if ((perm >> bit_idx) & mask)
2435 return false;
2436 return true;
2437}
2438
2439static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2440 u16 port, u16 len)
2441{
4fc40f07
GN		 2442 if (ctxt->perm_ok)
2443 return true;
2444
7b105ca2
TY		 2445 if (emulator_bad_iopl(ctxt))
2446 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2447 return false;
4fc40f07
GN		 2448
2449 ctxt->perm_ok = true;
2450
f850e2e6
GN		 2451 return true;
2452}
2453
38ba30ba 2454static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2455 struct tss_segment_16 *tss)
2456{
9dac77fa 2457 tss->ip = ctxt->_eip;
38ba30ba 2458 tss->flag = ctxt->eflags;
dd856efa
AK		 2459 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2460 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2461 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2462 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2463 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2464 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2465 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2466 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2467
1aa36616
AK		 2468 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2469 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2470 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2471 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2472 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2473}
2474
2475static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2476 struct tss_segment_16 *tss)
2477{
38ba30ba 2478 int ret;
2356aaeb 2479 u8 cpl;
38ba30ba 2480
9dac77fa 2481 ctxt->_eip = tss->ip;
38ba30ba 2482 ctxt->eflags = tss->flag | 2;
dd856efa
AK		 2483 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
2484 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
2485 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
2486 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
2487 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
2488 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
2489 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
2490 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
38ba30ba
GN		 2491
2492 /*
2493 * SDM says that segment selectors are loaded before segment
2494 * descriptors
2495 */
1aa36616
AK		 2496 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2497 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2498 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2499 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2500 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba 2501
2356aaeb
PB		 2502 cpl = tss->cs & 3;
2503
38ba30ba 2504 /*
fc058680 2505 * Now load segment descriptors. If fault happens at this stage
38ba30ba
GN		 2506 * it is handled in a context of new task
2507 */
5045b468 2508 ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl, true);
38ba30ba
GN		 2509 if (ret != X86EMUL_CONTINUE)
2510 return ret;
5045b468 2511 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl, true);
38ba30ba
GN		 2512 if (ret != X86EMUL_CONTINUE)
2513 return ret;
5045b468 2514 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl, true);
38ba30ba
GN		 2515 if (ret != X86EMUL_CONTINUE)
2516 return ret;
5045b468 2517 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl, true);
38ba30ba
GN		 2518 if (ret != X86EMUL_CONTINUE)
2519 return ret;
5045b468 2520 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl, true);
38ba30ba
GN		 2521 if (ret != X86EMUL_CONTINUE)
2522 return ret;
2523
2524 return X86EMUL_CONTINUE;
2525}
2526
2527static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2528 u16 tss_selector, u16 old_tss_sel,
2529 ulong old_tss_base, struct desc_struct *new_desc)
2530{
0225fb50 2531 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2532 struct tss_segment_16 tss_seg;
2533 int ret;
bcc55cba 2534 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2535
0f65dd70 2536 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2537 &ctxt->exception);
db297e3d 2538 if (ret != X86EMUL_CONTINUE)
38ba30ba 2539 /* FIXME: need to provide precise fault address */
38ba30ba 2540 return ret;
38ba30ba 2541
7b105ca2 2542 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2543
0f65dd70 2544 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2545 &ctxt->exception);
db297e3d 2546 if (ret != X86EMUL_CONTINUE)
38ba30ba 2547 /* FIXME: need to provide precise fault address */
38ba30ba 2548 return ret;
38ba30ba 2549
0f65dd70 2550 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2551 &ctxt->exception);
db297e3d 2552 if (ret != X86EMUL_CONTINUE)
38ba30ba 2553 /* FIXME: need to provide precise fault address */
38ba30ba 2554 return ret;
38ba30ba
GN		 2555
2556 if (old_tss_sel != 0xffff) {
2557 tss_seg.prev_task_link = old_tss_sel;
2558
0f65dd70 2559 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2560 &tss_seg.prev_task_link,
2561 sizeof tss_seg.prev_task_link,
0f65dd70 2562 &ctxt->exception);
db297e3d 2563 if (ret != X86EMUL_CONTINUE)
38ba30ba 2564 /* FIXME: need to provide precise fault address */
38ba30ba 2565 return ret;
38ba30ba
GN		 2566 }
2567
7b105ca2 2568 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2569}
2570
2571static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2572 struct tss_segment_32 *tss)
2573{
5c7411e2 2574 /* CR3 and ldt selector are not saved intentionally */
9dac77fa 2575 tss->eip = ctxt->_eip;
38ba30ba 2576 tss->eflags = ctxt->eflags;
dd856efa
AK		 2577 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
2578 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
2579 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
2580 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
2581 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
2582 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
2583 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
2584 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2585
1aa36616
AK		 2586 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2587 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2588 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2589 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2590 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2591 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
38ba30ba
GN		 2592}
2593
2594static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2595 struct tss_segment_32 *tss)
2596{
38ba30ba 2597 int ret;
2356aaeb 2598 u8 cpl;
38ba30ba 2599
7b105ca2 2600 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2601 return emulate_gp(ctxt, 0);
9dac77fa 2602 ctxt->_eip = tss->eip;
38ba30ba 2603 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 2604
2605 /* General purpose registers */
dd856efa
AK		 2606 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
2607 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
2608 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
2609 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
2610 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
2611 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
2612 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
2613 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
38ba30ba
GN		 2614
2615 /*
2616 * SDM says that segment selectors are loaded before segment
2356aaeb
PB		 2617 * descriptors. This is important because CPL checks will
2618 * use CS.RPL.
38ba30ba 2619 */
1aa36616
AK		 2620 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2621 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2622 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2623 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2624 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2625 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2626 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 2627
4cee4798
KW		 2628 /*
2629 * If we're switching between Protected Mode and VM86, we need to make
2630 * sure to update the mode before loading the segment descriptors so
2631 * that the selectors are interpreted correctly.
4cee4798 2632 */
2356aaeb 2633 if (ctxt->eflags & X86_EFLAGS_VM) {
4cee4798 2634 ctxt->mode = X86EMUL_MODE_VM86;
2356aaeb
PB		 2635 cpl = 3;
2636 } else {
4cee4798 2637 ctxt->mode = X86EMUL_MODE_PROT32;
2356aaeb
PB		 2638 cpl = tss->cs & 3;
2639 }
4cee4798 2640
38ba30ba
GN		 2641 /*
2642 * Now load segment descriptors. If fault happenes at this stage
2643 * it is handled in a context of new task
2644 */
5045b468 2645 ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR, cpl, true);
38ba30ba
GN		 2646 if (ret != X86EMUL_CONTINUE)
2647 return ret;
5045b468 2648 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl, true);
38ba30ba
GN		 2649 if (ret != X86EMUL_CONTINUE)
2650 return ret;
5045b468 2651 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl, true);
38ba30ba
GN		 2652 if (ret != X86EMUL_CONTINUE)
2653 return ret;
5045b468 2654 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl, true);
38ba30ba
GN		 2655 if (ret != X86EMUL_CONTINUE)
2656 return ret;
5045b468 2657 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl, true);
38ba30ba
GN		 2658 if (ret != X86EMUL_CONTINUE)
2659 return ret;
5045b468 2660 ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl, true);
38ba30ba
GN		 2661 if (ret != X86EMUL_CONTINUE)
2662 return ret;
5045b468 2663 ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl, true);
38ba30ba
GN		 2664 if (ret != X86EMUL_CONTINUE)
2665 return ret;
2666
2667 return X86EMUL_CONTINUE;
2668}
2669
2670static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2671 u16 tss_selector, u16 old_tss_sel,
2672 ulong old_tss_base, struct desc_struct *new_desc)
2673{
0225fb50 2674 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2675 struct tss_segment_32 tss_seg;
2676 int ret;
bcc55cba 2677 u32 new_tss_base = get_desc_base(new_desc);
5c7411e2
NA		 2678 u32 eip_offset = offsetof(struct tss_segment_32, eip);
2679 u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector);
38ba30ba 2680
0f65dd70 2681 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2682 &ctxt->exception);
db297e3d 2683 if (ret != X86EMUL_CONTINUE)
38ba30ba 2684 /* FIXME: need to provide precise fault address */
38ba30ba 2685 return ret;
38ba30ba 2686
7b105ca2 2687 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2688
5c7411e2
NA		 2689 /* Only GP registers and segment selectors are saved */
2690 ret = ops->write_std(ctxt, old_tss_base + eip_offset, &tss_seg.eip,
2691 ldt_sel_offset - eip_offset, &ctxt->exception);
db297e3d 2692 if (ret != X86EMUL_CONTINUE)
38ba30ba 2693 /* FIXME: need to provide precise fault address */
38ba30ba 2694 return ret;
38ba30ba 2695
0f65dd70 2696 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2697 &ctxt->exception);
db297e3d 2698 if (ret != X86EMUL_CONTINUE)
38ba30ba 2699 /* FIXME: need to provide precise fault address */
38ba30ba 2700 return ret;
38ba30ba
GN		 2701
2702 if (old_tss_sel != 0xffff) {
2703 tss_seg.prev_task_link = old_tss_sel;
2704
0f65dd70 2705 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2706 &tss_seg.prev_task_link,
2707 sizeof tss_seg.prev_task_link,
0f65dd70 2708 &ctxt->exception);
db297e3d 2709 if (ret != X86EMUL_CONTINUE)
38ba30ba 2710 /* FIXME: need to provide precise fault address */
38ba30ba 2711 return ret;
38ba30ba
GN		 2712 }
2713
7b105ca2 2714 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2715}
2716
2717static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2718 u16 tss_selector, int idt_index, int reason,
e269fb21 2719 bool has_error_code, u32 error_code)
38ba30ba 2720{
0225fb50 2721 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2722 struct desc_struct curr_tss_desc, next_tss_desc;
2723 int ret;
1aa36616 2724 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2725 ulong old_tss_base =
4bff1e86 2726 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2727 u32 desc_limit;
e919464b 2728 ulong desc_addr;
38ba30ba
GN		 2729
2730 /* FIXME: old_tss_base == ~0 ? */
2731
e919464b 2732 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
38ba30ba
GN		 2733 if (ret != X86EMUL_CONTINUE)
2734 return ret;
e919464b 2735 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
38ba30ba
GN		 2736 if (ret != X86EMUL_CONTINUE)
2737 return ret;
2738
2739 /* FIXME: check that next_tss_desc is tss */
2740
7f3d35fd
KW		 2741 /*
2742 * Check privileges. The three cases are task switch caused by...
2743 *
2744 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2745 * 2. Exception/IRQ/iret: No check is performed
fc058680 2746 * 3. jmp/call to TSS: Check against DPL of the TSS
7f3d35fd
KW		 2747 */
2748 if (reason == TASK_SWITCH_GATE) {
2749 if (idt_index != -1) {
2750 /* Software interrupts */
2751 struct desc_struct task_gate_desc;
2752 int dpl;
2753
2754 ret = read_interrupt_descriptor(ctxt, idt_index,
2755 &task_gate_desc);
2756 if (ret != X86EMUL_CONTINUE)
2757 return ret;
2758
2759 dpl = task_gate_desc.dpl;
2760 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2761 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2762 }
2763 } else if (reason != TASK_SWITCH_IRET) {
2764 int dpl = next_tss_desc.dpl;
2765 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2766 return emulate_gp(ctxt, tss_selector);
38ba30ba
GN		 2767 }
2768
7f3d35fd 2769
ceffb459
GN		 2770 desc_limit = desc_limit_scaled(&next_tss_desc);
2771 if (!next_tss_desc.p ||
2772 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2773 desc_limit < 0x2b)) {
592f0858 2774 return emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2775 }
2776
2777 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2778 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2779 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2780 }
2781
2782 if (reason == TASK_SWITCH_IRET)
2783 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2784
2785 /* set back link to prev task only if NT bit is set in eflags
fc058680 2786 note that old_tss_sel is not used after this point */
38ba30ba
GN		 2787 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2788 old_tss_sel = 0xffff;
2789
2790 if (next_tss_desc.type & 8)
7b105ca2 2791 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2792 old_tss_base, &next_tss_desc);
2793 else
7b105ca2 2794 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2795 old_tss_base, &next_tss_desc);
0760d448
JK		 2796 if (ret != X86EMUL_CONTINUE)
2797 return ret;
38ba30ba
GN		 2798
2799 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2800 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2801
2802 if (reason != TASK_SWITCH_IRET) {
2803 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2804 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2805 }
2806
717746e3 2807 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2808 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2809
e269fb21 2810 if (has_error_code) {
9dac77fa
AK		 2811 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2812 ctxt->lock_prefix = 0;
2813 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2814 ret = em_push(ctxt);
e269fb21
JK		 2815 }
2816
38ba30ba
GN		 2817 return ret;
2818}
2819
2820int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2821 u16 tss_selector, int idt_index, int reason,
e269fb21 2822 bool has_error_code, u32 error_code)
38ba30ba 2823{
38ba30ba
GN		 2824 int rc;
2825
dd856efa 2826 invalidate_registers(ctxt);
9dac77fa
AK		 2827 ctxt->_eip = ctxt->eip;
2828 ctxt->dst.type = OP_NONE;
38ba30ba 2829
7f3d35fd 2830 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 2831 has_error_code, error_code);
38ba30ba 2832
dd856efa 2833 if (rc == X86EMUL_CONTINUE) {
9dac77fa 2834 ctxt->eip = ctxt->_eip;
dd856efa
AK		 2835 writeback_registers(ctxt);
2836 }
38ba30ba 2837
a0c0ab2f 2838 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2839}
2840
f3bd64c6
GN		 2841static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
2842 struct operand *op)
a682e354 2843{
b3356bf0 2844 int df = (ctxt->eflags & EFLG_DF) ? -op->count : op->count;
a682e354 2845
dd856efa
AK		 2846 register_address_increment(ctxt, reg_rmw(ctxt, reg), df * op->bytes);
2847 op->addr.mem.ea = register_address(ctxt, reg_read(ctxt, reg));
a682e354
GN		 2848}
2849
7af04fc0
AK		 2850static int em_das(struct x86_emulate_ctxt *ctxt)
2851{
7af04fc0
AK		 2852 u8 al, old_al;
2853 bool af, cf, old_cf;
2854
2855 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2856 al = ctxt->dst.val;
7af04fc0
AK		 2857
2858 old_al = al;
2859 old_cf = cf;
2860 cf = false;
2861 af = ctxt->eflags & X86_EFLAGS_AF;
2862 if ((al & 0x0f) > 9 || af) {
2863 al -= 6;
2864 cf = old_cf | (al >= 250);
2865 af = true;
2866 } else {
2867 af = false;
2868 }
2869 if (old_al > 0x99 || old_cf) {
2870 al -= 0x60;
2871 cf = true;
2872 }
2873
9dac77fa 2874 ctxt->dst.val = al;
7af04fc0 2875 /* Set PF, ZF, SF */
9dac77fa
AK		 2876 ctxt->src.type = OP_IMM;
2877 ctxt->src.val = 0;
2878 ctxt->src.bytes = 1;
158de57f 2879 fastop(ctxt, em_or);
7af04fc0
AK		 2880 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2881 if (cf)
2882 ctxt->eflags |= X86_EFLAGS_CF;
2883 if (af)
2884 ctxt->eflags |= X86_EFLAGS_AF;
2885 return X86EMUL_CONTINUE;
2886}
2887
a035d5c6
PB		 2888static int em_aam(struct x86_emulate_ctxt *ctxt)
2889{
2890 u8 al, ah;
2891
2892 if (ctxt->src.val == 0)
2893 return emulate_de(ctxt);
2894
2895 al = ctxt->dst.val & 0xff;
2896 ah = al / ctxt->src.val;
2897 al %= ctxt->src.val;
2898
2899 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);
2900
2901 /* Set PF, ZF, SF */
2902 ctxt->src.type = OP_IMM;
2903 ctxt->src.val = 0;
2904 ctxt->src.bytes = 1;
2905 fastop(ctxt, em_or);
2906
2907 return X86EMUL_CONTINUE;
2908}
2909
7f662273
GN		 2910static int em_aad(struct x86_emulate_ctxt *ctxt)
2911{
2912 u8 al = ctxt->dst.val & 0xff;
2913 u8 ah = (ctxt->dst.val >> 8) & 0xff;
2914
2915 al = (al + (ah * ctxt->src.val)) & 0xff;
2916
2917 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
2918
f583c29b
GN		 2919 /* Set PF, ZF, SF */
2920 ctxt->src.type = OP_IMM;
2921 ctxt->src.val = 0;
2922 ctxt->src.bytes = 1;
2923 fastop(ctxt, em_or);
7f662273
GN		 2924
2925 return X86EMUL_CONTINUE;
2926}
2927
d4ddafcd
TY		 2928static int em_call(struct x86_emulate_ctxt *ctxt)
2929{
234f3ce4 2930 int rc;
d4ddafcd
TY		 2931 long rel = ctxt->src.val;
2932
2933 ctxt->src.val = (unsigned long)ctxt->_eip;
234f3ce4
NA		 2934 rc = jmp_rel(ctxt, rel);
2935 if (rc != X86EMUL_CONTINUE)
2936 return rc;
d4ddafcd
TY		 2937 return em_push(ctxt);
2938}
2939
0ef753b8
AK		 2940static int em_call_far(struct x86_emulate_ctxt *ctxt)
2941{
0ef753b8
AK		 2942 u16 sel, old_cs;
2943 ulong old_eip;
2944 int rc;
2945
1aa36616 2946 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
9dac77fa 2947 old_eip = ctxt->_eip;
0ef753b8 2948
9dac77fa 2949 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
7b105ca2 2950 if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS))
0ef753b8
AK		 2951 return X86EMUL_CONTINUE;
2952
9dac77fa
AK		 2953 ctxt->_eip = 0;
2954 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
0ef753b8 2955
9dac77fa 2956 ctxt->src.val = old_cs;
4487b3b4 2957 rc = em_push(ctxt);
0ef753b8
AK		 2958 if (rc != X86EMUL_CONTINUE)
2959 return rc;
2960
9dac77fa 2961 ctxt->src.val = old_eip;
4487b3b4 2962 return em_push(ctxt);
0ef753b8
AK		 2963}
2964
40ece7c7
AK		 2965static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2966{
40ece7c7 2967 int rc;
234f3ce4 2968 unsigned long eip;
40ece7c7 2969
234f3ce4
NA		 2970 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
2971 if (rc != X86EMUL_CONTINUE)
2972 return rc;
2973 rc = assign_eip_near(ctxt, eip);
40ece7c7
AK		 2974 if (rc != X86EMUL_CONTINUE)
2975 return rc;
5ad105e5 2976 rsp_increment(ctxt, ctxt->src.val);
40ece7c7
AK		 2977 return X86EMUL_CONTINUE;
2978}
2979
e4f973ae
TY		 2980static int em_xchg(struct x86_emulate_ctxt *ctxt)
2981{
e4f973ae 2982 /* Write back the register source. */
9dac77fa
AK		 2983 ctxt->src.val = ctxt->dst.val;
2984 write_register_operand(&ctxt->src);
e4f973ae
TY		 2985
2986 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 2987 ctxt->dst.val = ctxt->src.orig_val;
2988 ctxt->lock_prefix = 1;
e4f973ae
TY		 2989 return X86EMUL_CONTINUE;
2990}
2991
5c82aa29
AK		 2992static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2993{
9dac77fa 2994 ctxt->dst.val = ctxt->src2.val;
4d758349 2995 return fastop(ctxt, em_imul);
5c82aa29
AK		 2996}
2997
61429142
AK		 2998static int em_cwd(struct x86_emulate_ctxt *ctxt)
2999{
9dac77fa
AK		 3000 ctxt->dst.type = OP_REG;
3001 ctxt->dst.bytes = ctxt->src.bytes;
dd856efa 3002 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
9dac77fa 3003 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 3004
3005 return X86EMUL_CONTINUE;
3006}
3007
48bb5d3c
AK		 3008static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
3009{
48bb5d3c
AK		 3010 u64 tsc = 0;
3011
717746e3 3012 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
dd856efa
AK		 3013 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
3014 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
48bb5d3c
AK		 3015 return X86EMUL_CONTINUE;
3016}
3017
222d21aa
AK		 3018static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
3019{
3020 u64 pmc;
3021
dd856efa 3022 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
222d21aa 3023 return emulate_gp(ctxt, 0);
dd856efa
AK		 3024 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
3025 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
222d21aa
AK		 3026 return X86EMUL_CONTINUE;
3027}
3028
b9eac5f4
AK		 3029static int em_mov(struct x86_emulate_ctxt *ctxt)
3030{
54cfdb3e 3031 memcpy(ctxt->dst.valptr, ctxt->src.valptr, sizeof(ctxt->src.valptr));
b9eac5f4
AK		 3032 return X86EMUL_CONTINUE;
3033}
3034
84cffe49
BP		 3035#define FFL(x) bit(X86_FEATURE_##x)
3036
3037static int em_movbe(struct x86_emulate_ctxt *ctxt)
3038{
3039 u32 ebx, ecx, edx, eax = 1;
3040 u16 tmp;
3041
3042 /*
3043 * Check MOVBE is set in the guest-visible CPUID leaf.
3044 */
3045 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
3046 if (!(ecx & FFL(MOVBE)))
3047 return emulate_ud(ctxt);
3048
3049 switch (ctxt->op_bytes) {
3050 case 2:
3051 /*
3052 * From MOVBE definition: "...When the operand size is 16 bits,
3053 * the upper word of the destination register remains unchanged
3054 * ..."
3055 *
3056 * Both casting ->valptr and ->val to u16 breaks strict aliasing
3057 * rules so we have to do the operation almost per hand.
3058 */
3059 tmp = (u16)ctxt->src.val;
3060 ctxt->dst.val &= ~0xffffUL;
3061 ctxt->dst.val |= (unsigned long)swab16(tmp);
3062 break;
3063 case 4:
3064 ctxt->dst.val = swab32((u32)ctxt->src.val);
3065 break;
3066 case 8:
3067 ctxt->dst.val = swab64(ctxt->src.val);
3068 break;
3069 default:
592f0858 3070 BUG();
84cffe49
BP		 3071 }
3072 return X86EMUL_CONTINUE;
3073}
3074
bc00f8d2
TY		 3075static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3076{
3077 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
3078 return emulate_gp(ctxt, 0);
3079
3080 /* Disable writeback. */
3081 ctxt->dst.type = OP_NONE;
3082 return X86EMUL_CONTINUE;
3083}
3084
3085static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3086{
3087 unsigned long val;
3088
3089 if (ctxt->mode == X86EMUL_MODE_PROT64)
3090 val = ctxt->src.val & ~0ULL;
3091 else
3092 val = ctxt->src.val & ~0U;
3093
3094 /* #UD condition is already handled. */
3095 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3096 return emulate_gp(ctxt, 0);
3097
3098 /* Disable writeback. */
3099 ctxt->dst.type = OP_NONE;
3100 return X86EMUL_CONTINUE;
3101}
3102
e1e210b0
TY		 3103static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3104{
3105 u64 msr_data;
3106
dd856efa
AK		 3107 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3108 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3109 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
e1e210b0
TY		 3110 return emulate_gp(ctxt, 0);
3111
3112 return X86EMUL_CONTINUE;
3113}
3114
3115static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3116{
3117 u64 msr_data;
3118
dd856efa 3119 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
e1e210b0
TY		 3120 return emulate_gp(ctxt, 0);
3121
dd856efa
AK		 3122 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3123 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
e1e210b0
TY		 3124 return X86EMUL_CONTINUE;
3125}
3126
1bd5f469
TY		 3127static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3128{
9dac77fa 3129 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3130 return emulate_ud(ctxt);
3131
9dac77fa 3132 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
1bd5f469
TY		 3133 return X86EMUL_CONTINUE;
3134}
3135
3136static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3137{
9dac77fa 3138 u16 sel = ctxt->src.val;
1bd5f469 3139
9dac77fa 3140 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3141 return emulate_ud(ctxt);
3142
9dac77fa 3143 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 3144 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3145
3146 /* Disable writeback. */
9dac77fa
AK		 3147 ctxt->dst.type = OP_NONE;
3148 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 3149}
3150
a14e579f
AK		 3151static int em_lldt(struct x86_emulate_ctxt *ctxt)
3152{
3153 u16 sel = ctxt->src.val;
3154
3155 /* Disable writeback. */
3156 ctxt->dst.type = OP_NONE;
3157 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3158}
3159
80890006
AK		 3160static int em_ltr(struct x86_emulate_ctxt *ctxt)
3161{
3162 u16 sel = ctxt->src.val;
3163
3164 /* Disable writeback. */
3165 ctxt->dst.type = OP_NONE;
3166 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3167}
3168
38503911
AK		 3169static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3170{
9fa088f4
AK		 3171 int rc;
3172 ulong linear;
3173
9dac77fa 3174 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 3175 if (rc == X86EMUL_CONTINUE)
3cb16fe7 3176 ctxt->ops->invlpg(ctxt, linear);
38503911 3177 /* Disable writeback. */
9dac77fa 3178 ctxt->dst.type = OP_NONE;
38503911
AK		 3179 return X86EMUL_CONTINUE;
3180}
3181
2d04a05b
AK		 3182static int em_clts(struct x86_emulate_ctxt *ctxt)
3183{
3184 ulong cr0;
3185
3186 cr0 = ctxt->ops->get_cr(ctxt, 0);
3187 cr0 &= ~X86_CR0_TS;
3188 ctxt->ops->set_cr(ctxt, 0, cr0);
3189 return X86EMUL_CONTINUE;
3190}
3191
26d05cc7
AK		 3192static int em_vmcall(struct x86_emulate_ctxt *ctxt)
3193{
0f54a321 3194 int rc = ctxt->ops->fix_hypercall(ctxt);
26d05cc7 3195
26d05cc7
AK		 3196 if (rc != X86EMUL_CONTINUE)
3197 return rc;
3198
3199 /* Let the processor re-execute the fixed hypercall */
9dac77fa 3200 ctxt->_eip = ctxt->eip;
26d05cc7 3201 /* Disable writeback. */
9dac77fa 3202 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3203 return X86EMUL_CONTINUE;
3204}
3205
96051572
AK		 3206static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3207 void (*get)(struct x86_emulate_ctxt *ctxt,
3208 struct desc_ptr *ptr))
3209{
3210 struct desc_ptr desc_ptr;
3211
3212 if (ctxt->mode == X86EMUL_MODE_PROT64)
3213 ctxt->op_bytes = 8;
3214 get(ctxt, &desc_ptr);
3215 if (ctxt->op_bytes == 2) {
3216 ctxt->op_bytes = 4;
3217 desc_ptr.address &= 0x00ffffff;
3218 }
3219 /* Disable writeback. */
3220 ctxt->dst.type = OP_NONE;
3221 return segmented_write(ctxt, ctxt->dst.addr.mem,
3222 &desc_ptr, 2 + ctxt->op_bytes);
3223}
3224
3225static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3226{
3227 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3228}
3229
3230static int em_sidt(struct x86_emulate_ctxt *ctxt)
3231{
3232 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3233}
3234
26d05cc7
AK		 3235static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3236{
26d05cc7
AK		 3237 struct desc_ptr desc_ptr;
3238 int rc;
3239
510425ff
AK		 3240 if (ctxt->mode == X86EMUL_MODE_PROT64)
3241 ctxt->op_bytes = 8;
9dac77fa 3242 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3243 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3244 ctxt->op_bytes);
26d05cc7
AK		 3245 if (rc != X86EMUL_CONTINUE)
3246 return rc;
3247 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3248 /* Disable writeback. */
9dac77fa 3249 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3250 return X86EMUL_CONTINUE;
3251}
3252
5ef39c71 3253static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3254{
26d05cc7
AK		 3255 int rc;
3256
5ef39c71
AK		 3257 rc = ctxt->ops->fix_hypercall(ctxt);
3258
26d05cc7 3259 /* Disable writeback. */
9dac77fa 3260 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3261 return rc;
3262}
3263
3264static int em_lidt(struct x86_emulate_ctxt *ctxt)
3265{
26d05cc7
AK		 3266 struct desc_ptr desc_ptr;
3267 int rc;
3268
510425ff
AK		 3269 if (ctxt->mode == X86EMUL_MODE_PROT64)
3270 ctxt->op_bytes = 8;
9dac77fa 3271 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
509cf9fe 3272 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3273 ctxt->op_bytes);
26d05cc7
AK		 3274 if (rc != X86EMUL_CONTINUE)
3275 return rc;
3276 ctxt->ops->set_idt(ctxt, &desc_ptr);
3277 /* Disable writeback. */
9dac77fa 3278 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3279 return X86EMUL_CONTINUE;
3280}
3281
3282static int em_smsw(struct x86_emulate_ctxt *ctxt)
3283{
32e94d06
NA		 3284 if (ctxt->dst.type == OP_MEM)
3285 ctxt->dst.bytes = 2;
9dac77fa 3286 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3287 return X86EMUL_CONTINUE;
3288}
3289
3290static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3291{
26d05cc7 3292 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3293 | (ctxt->src.val & 0x0f));
3294 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3295 return X86EMUL_CONTINUE;
3296}
3297
d06e03ad
TY		 3298static int em_loop(struct x86_emulate_ctxt *ctxt)
3299{
234f3ce4
NA		 3300 int rc = X86EMUL_CONTINUE;
3301
dd856efa
AK		 3302 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX), -1);
3303 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
9dac77fa 3304 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
234f3ce4 3305 rc = jmp_rel(ctxt, ctxt->src.val);
d06e03ad 3306
234f3ce4 3307 return rc;
d06e03ad
TY		 3308}
3309
3310static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3311{
234f3ce4
NA		 3312 int rc = X86EMUL_CONTINUE;
3313
dd856efa 3314 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
234f3ce4 3315 rc = jmp_rel(ctxt, ctxt->src.val);
d06e03ad 3316
234f3ce4 3317 return rc;
d06e03ad
TY		 3318}
3319
d7841a4b
TY		 3320static int em_in(struct x86_emulate_ctxt *ctxt)
3321{
3322 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3323 &ctxt->dst.val))
3324 return X86EMUL_IO_NEEDED;
3325
3326 return X86EMUL_CONTINUE;
3327}
3328
3329static int em_out(struct x86_emulate_ctxt *ctxt)
3330{
3331 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3332 &ctxt->src.val, 1);
3333 /* Disable writeback. */
3334 ctxt->dst.type = OP_NONE;
3335 return X86EMUL_CONTINUE;
3336}
3337
f411e6cd
TY		 3338static int em_cli(struct x86_emulate_ctxt *ctxt)
3339{
3340 if (emulator_bad_iopl(ctxt))
3341 return emulate_gp(ctxt, 0);
3342
3343 ctxt->eflags &= ~X86_EFLAGS_IF;
3344 return X86EMUL_CONTINUE;
3345}
3346
3347static int em_sti(struct x86_emulate_ctxt *ctxt)
3348{
3349 if (emulator_bad_iopl(ctxt))
3350 return emulate_gp(ctxt, 0);
3351
3352 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3353 ctxt->eflags |= X86_EFLAGS_IF;
3354 return X86EMUL_CONTINUE;
3355}
3356
6d6eede4
AK		 3357static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3358{
3359 u32 eax, ebx, ecx, edx;
3360
dd856efa
AK		 3361 eax = reg_read(ctxt, VCPU_REGS_RAX);
3362 ecx = reg_read(ctxt, VCPU_REGS_RCX);
6d6eede4 3363 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
dd856efa
AK		 3364 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3365 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3366 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3367 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
6d6eede4
AK		 3368 return X86EMUL_CONTINUE;
3369}
3370
98f73630
PB		 3371static int em_sahf(struct x86_emulate_ctxt *ctxt)
3372{
3373 u32 flags;
3374
3375 flags = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF;
3376 flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8;
3377
3378 ctxt->eflags &= ~0xffUL;
3379 ctxt->eflags |= flags | X86_EFLAGS_FIXED;
3380 return X86EMUL_CONTINUE;
3381}
3382
2dd7caa0
AK		 3383static int em_lahf(struct x86_emulate_ctxt *ctxt)
3384{
dd856efa
AK		 3385 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3386 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
2dd7caa0
AK		 3387 return X86EMUL_CONTINUE;
3388}
3389
9299836e
AK		 3390static int em_bswap(struct x86_emulate_ctxt *ctxt)
3391{
3392 switch (ctxt->op_bytes) {
3393#ifdef CONFIG_X86_64
3394 case 8:
3395 asm("bswap %0" : "+r"(ctxt->dst.val));
3396 break;
3397#endif
3398 default:
3399 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3400 break;
3401 }
3402 return X86EMUL_CONTINUE;
3403}
3404
cfec82cb
JR		 3405static bool valid_cr(int nr)
3406{
3407 switch (nr) {
3408 case 0:
3409 case 2 ... 4:
3410 case 8:
3411 return true;
3412 default:
3413 return false;
3414 }
3415}
3416
3417static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3418{
9dac77fa 3419 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 3420 return emulate_ud(ctxt);
3421
3422 return X86EMUL_CONTINUE;
3423}
3424
3425static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3426{
9dac77fa
AK		 3427 u64 new_val = ctxt->src.val64;
3428 int cr = ctxt->modrm_reg;
c2ad2bb3 3429 u64 efer = 0;
cfec82cb
JR		 3430
3431 static u64 cr_reserved_bits[] = {
3432 0xffffffff00000000ULL,
3433 0, 0, 0, /* CR3 checked later */
3434 CR4_RESERVED_BITS,
3435 0, 0, 0,
3436 CR8_RESERVED_BITS,
3437 };
3438
3439 if (!valid_cr(cr))
3440 return emulate_ud(ctxt);
3441
3442 if (new_val & cr_reserved_bits[cr])
3443 return emulate_gp(ctxt, 0);
3444
3445 switch (cr) {
3446 case 0: {
c2ad2bb3 3447 u64 cr4;
cfec82cb
JR		 3448 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3449 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3450 return emulate_gp(ctxt, 0);
3451
717746e3
AK		 3452 cr4 = ctxt->ops->get_cr(ctxt, 4);
3453 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3454
3455 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3456 !(cr4 & X86_CR4_PAE))
3457 return emulate_gp(ctxt, 0);
3458
3459 break;
3460 }
3461 case 3: {
3462 u64 rsvd = 0;
3463
c2ad2bb3
AK		 3464 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3465 if (efer & EFER_LMA)
cfec82cb 3466 rsvd = CR3_L_MODE_RESERVED_BITS;
cfec82cb
JR		 3467
3468 if (new_val & rsvd)
3469 return emulate_gp(ctxt, 0);
3470
3471 break;
3472 }
3473 case 4: {
717746e3 3474 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3475
3476 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3477 return emulate_gp(ctxt, 0);
3478
3479 break;
3480 }
3481 }
3482
3483 return X86EMUL_CONTINUE;
3484}
3485
3b88e41a
JR		 3486static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3487{
3488 unsigned long dr7;
3489
717746e3 3490 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 3491
3492 /* Check if DR7.Global_Enable is set */
3493 return dr7 & (1 << 13);
3494}
3495
3496static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3497{
9dac77fa 3498 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3499 u64 cr4;
3500
3501 if (dr > 7)
3502 return emulate_ud(ctxt);
3503
717746e3 3504 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 3505 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3506 return emulate_ud(ctxt);
3507
3508 if (check_dr7_gd(ctxt))
3509 return emulate_db(ctxt);
3510
3511 return X86EMUL_CONTINUE;
3512}
3513
3514static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3515{
9dac77fa
AK		 3516 u64 new_val = ctxt->src.val64;
3517 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3518
3519 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3520 return emulate_gp(ctxt, 0);
3521
3522 return check_dr_read(ctxt);
3523}
3524
01de8b09
JR		 3525static int check_svme(struct x86_emulate_ctxt *ctxt)
3526{
3527 u64 efer;
3528
717746e3 3529 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 3530
3531 if (!(efer & EFER_SVME))
3532 return emulate_ud(ctxt);
3533
3534 return X86EMUL_CONTINUE;
3535}
3536
3537static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3538{
dd856efa 3539 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
01de8b09
JR		 3540
3541 /* Valid physical address? */
d4224449 3542 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 3543 return emulate_gp(ctxt, 0);
3544
3545 return check_svme(ctxt);
3546}
3547
d7eb8203
JR		 3548static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3549{
717746e3 3550 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 3551
717746e3 3552 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 3553 return emulate_ud(ctxt);
3554
3555 return X86EMUL_CONTINUE;
3556}
3557
8061252e
JR		 3558static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3559{
717746e3 3560 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
dd856efa 3561 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
8061252e 3562
717746e3 3563 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
67f4d428 3564 ctxt->ops->check_pmc(ctxt, rcx))
8061252e
JR		 3565 return emulate_gp(ctxt, 0);
3566
3567 return X86EMUL_CONTINUE;
3568}
3569
f6511935
JR		 3570static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3571{
9dac77fa
AK		 3572 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3573 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 3574 return emulate_gp(ctxt, 0);
3575
3576 return X86EMUL_CONTINUE;
3577}
3578
3579static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3580{
9dac77fa
AK		 3581 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3582 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 3583 return emulate_gp(ctxt, 0);
3584
3585 return X86EMUL_CONTINUE;
3586}
3587
73fba5f4 3588#define D(_y) { .flags = (_y) }
d40a6898
PB		 3589#define DI(_y, _i) { .flags = (_y)|Intercept, .intercept = x86_intercept_##_i }
3590#define DIP(_y, _i, _p) { .flags = (_y)|Intercept|CheckPerm, \
3591 .intercept = x86_intercept_##_i, .check_perm = (_p) }
0b789eee 3592#define N D(NotImpl)
01de8b09 3593#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 3594#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3595#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
045a282c 3596#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
73fba5f4 3597#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
e28bbd44 3598#define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
c4f035c6 3599#define II(_f, _e, _i) \
d40a6898 3600 { .flags = (_f)|Intercept, .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd 3601#define IIP(_f, _e, _i, _p) \
d40a6898
PB		 3602 { .flags = (_f)|Intercept|CheckPerm, .u.execute = (_e), \
3603 .intercept = x86_intercept_##_i, .check_perm = (_p) }
aa97bb48 3604#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3605
8d8f4e9f 3606#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3607#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 3608#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
f7857f35 3609#define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e)
d7841a4b
TY		 3610#define I2bvIP(_f, _e, _i, _p) \
3611 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 3612
fb864fbc
AK		 3613#define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3614 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3615 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3616
0f54a321
NA		 3617static const struct opcode group7_rm0[] = {
3618 N,
3619 I(SrcNone | Priv | EmulateOnUD, em_vmcall),
3620 N, N, N, N, N, N,
3621};
3622
fd0a0d82 3623static const struct opcode group7_rm1[] = {
1c2545be
TY		 3624 DI(SrcNone | Priv, monitor),
3625 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 3626 N, N, N, N, N, N,
3627};
3628
fd0a0d82 3629static const struct opcode group7_rm3[] = {
1c2545be 3630 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
b51e974f 3631 II(SrcNone | Prot | EmulateOnUD, em_vmmcall, vmmcall),
1c2545be
TY		 3632 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3633 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3634 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3635 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3636 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3637 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 3638};
6230f7fc 3639
fd0a0d82 3640static const struct opcode group7_rm7[] = {
d7eb8203 3641 N,
1c2545be 3642 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 3643 N, N, N, N, N, N,
3644};
d67fc27a 3645
fd0a0d82 3646static const struct opcode group1[] = {
fb864fbc
AK		 3647 F(Lock, em_add),
3648 F(Lock | PageTable, em_or),
3649 F(Lock, em_adc),
3650 F(Lock, em_sbb),
3651 F(Lock | PageTable, em_and),
3652 F(Lock, em_sub),
3653 F(Lock, em_xor),
3654 F(NoWrite, em_cmp),
73fba5f4
AK		 3655};
3656
fd0a0d82 3657static const struct opcode group1A[] = {
1c2545be 3658 I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 3659};
3660
007a3b54
AK		 3661static const struct opcode group2[] = {
3662 F(DstMem | ModRM, em_rol),
3663 F(DstMem | ModRM, em_ror),
3664 F(DstMem | ModRM, em_rcl),
3665 F(DstMem | ModRM, em_rcr),
3666 F(DstMem | ModRM, em_shl),
3667 F(DstMem | ModRM, em_shr),
3668 F(DstMem | ModRM, em_shl),
3669 F(DstMem | ModRM, em_sar),
3670};
3671
fd0a0d82 3672static const struct opcode group3[] = {
fb864fbc
AK		 3673 F(DstMem | SrcImm | NoWrite, em_test),
3674 F(DstMem | SrcImm | NoWrite, em_test),
45a1467d
AK		 3675 F(DstMem | SrcNone | Lock, em_not),
3676 F(DstMem | SrcNone | Lock, em_neg),
b9fa409b
AK		 3677 F(DstXacc | Src2Mem, em_mul_ex),
3678 F(DstXacc | Src2Mem, em_imul_ex),
b8c0b6ae
AK		 3679 F(DstXacc | Src2Mem, em_div_ex),
3680 F(DstXacc | Src2Mem, em_idiv_ex),
73fba5f4
AK		 3681};
3682
fd0a0d82 3683static const struct opcode group4[] = {
95413dc4
AK		 3684 F(ByteOp | DstMem | SrcNone | Lock, em_inc),
3685 F(ByteOp | DstMem | SrcNone | Lock, em_dec),
73fba5f4
AK		 3686 N, N, N, N, N, N,
3687};
3688
fd0a0d82 3689static const struct opcode group5[] = {
95413dc4
AK		 3690 F(DstMem | SrcNone | Lock, em_inc),
3691 F(DstMem | SrcNone | Lock, em_dec),
1c2545be
TY		 3692 I(SrcMem | Stack, em_grp45),
3693 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far),
3694 I(SrcMem | Stack, em_grp45),
3695 I(SrcMemFAddr | ImplicitOps, em_grp45),
188424ba 3696 I(SrcMem | Stack, em_grp45), D(Undefined),
73fba5f4
AK		 3697};
3698
fd0a0d82 3699static const struct opcode group6[] = {
1c2545be
TY		 3700 DI(Prot, sldt),
3701 DI(Prot, str),
a14e579f 3702 II(Prot | Priv | SrcMem16, em_lldt, lldt),
80890006 3703 II(Prot | Priv | SrcMem16, em_ltr, ltr),
dee6bb70
JR		 3704 N, N, N, N,
3705};
3706
fd0a0d82 3707static const struct group_dual group7 = { {
606b1c3e
NA		 3708 II(Mov | DstMem, em_sgdt, sgdt),
3709 II(Mov | DstMem, em_sidt, sidt),
1c2545be
TY		 3710 II(SrcMem | Priv, em_lgdt, lgdt),
3711 II(SrcMem | Priv, em_lidt, lidt),
3712 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3713 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3714 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3715}, {
0f54a321 3716 EXT(0, group7_rm0),
5ef39c71 3717 EXT(0, group7_rm1),
01de8b09 3718 N, EXT(0, group7_rm3),
1c2545be
TY		 3719 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3720 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3721 EXT(0, group7_rm7),
73fba5f4
AK		 3722} };
3723
fd0a0d82 3724static const struct opcode group8[] = {
73fba5f4 3725 N, N, N, N,
11c363ba
AK		 3726 F(DstMem | SrcImmByte | NoWrite, em_bt),
3727 F(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3728 F(DstMem | SrcImmByte | Lock, em_btr),
3729 F(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 3730};
3731
fd0a0d82 3732static const struct group_dual group9 = { {
1c2545be 3733 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 3734}, {
3735 N, N, N, N, N, N, N, N,
3736} };
3737
fd0a0d82 3738static const struct opcode group11[] = {
1c2545be 3739 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 3740 X7(D(Undefined)),
a4d4a7c1
AK		 3741};
3742
fd0a0d82 3743static const struct gprefix pfx_0f_6f_0f_7f = {
e5971755 3744 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 3745};
3746
d5b77069
PB		 3747static const struct gprefix pfx_0f_2b = {
3748 I(0, em_mov), I(0, em_mov), N, N,
3e114eb4
AK		 3749};
3750
27ce8258 3751static const struct gprefix pfx_0f_28_0f_29 = {
6fec27d8 3752 I(Aligned, em_mov), I(Aligned, em_mov), N, N,
27ce8258
IM		 3753};
3754
0a37027e
AW		 3755static const struct gprefix pfx_0f_e7 = {
3756 N, I(Sse, em_mov), N, N,
3757};
3758
045a282c
GN		 3759static const struct escape escape_d9 = { {
3760 N, N, N, N, N, N, N, I(DstMem, em_fnstcw),
3761}, {
3762 /* 0xC0 - 0xC7 */
3763 N, N, N, N, N, N, N, N,
3764 /* 0xC8 - 0xCF */
3765 N, N, N, N, N, N, N, N,
3766 /* 0xD0 - 0xC7 */
3767 N, N, N, N, N, N, N, N,
3768 /* 0xD8 - 0xDF */
3769 N, N, N, N, N, N, N, N,
3770 /* 0xE0 - 0xE7 */
3771 N, N, N, N, N, N, N, N,
3772 /* 0xE8 - 0xEF */
3773 N, N, N, N, N, N, N, N,
3774 /* 0xF0 - 0xF7 */
3775 N, N, N, N, N, N, N, N,
3776 /* 0xF8 - 0xFF */
3777 N, N, N, N, N, N, N, N,
3778} };
3779
3780static const struct escape escape_db = { {
3781 N, N, N, N, N, N, N, N,
3782}, {
3783 /* 0xC0 - 0xC7 */
3784 N, N, N, N, N, N, N, N,
3785 /* 0xC8 - 0xCF */
3786 N, N, N, N, N, N, N, N,
3787 /* 0xD0 - 0xC7 */
3788 N, N, N, N, N, N, N, N,
3789 /* 0xD8 - 0xDF */
3790 N, N, N, N, N, N, N, N,
3791 /* 0xE0 - 0xE7 */
3792 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
3793 /* 0xE8 - 0xEF */
3794 N, N, N, N, N, N, N, N,
3795 /* 0xF0 - 0xF7 */
3796 N, N, N, N, N, N, N, N,
3797 /* 0xF8 - 0xFF */
3798 N, N, N, N, N, N, N, N,
3799} };
3800
3801static const struct escape escape_dd = { {
3802 N, N, N, N, N, N, N, I(DstMem, em_fnstsw),
3803}, {
3804 /* 0xC0 - 0xC7 */
3805 N, N, N, N, N, N, N, N,
3806 /* 0xC8 - 0xCF */
3807 N, N, N, N, N, N, N, N,
3808 /* 0xD0 - 0xC7 */
3809 N, N, N, N, N, N, N, N,
3810 /* 0xD8 - 0xDF */
3811 N, N, N, N, N, N, N, N,
3812 /* 0xE0 - 0xE7 */
3813 N, N, N, N, N, N, N, N,
3814 /* 0xE8 - 0xEF */
3815 N, N, N, N, N, N, N, N,
3816 /* 0xF0 - 0xF7 */
3817 N, N, N, N, N, N, N, N,
3818 /* 0xF8 - 0xFF */
3819 N, N, N, N, N, N, N, N,
3820} };
3821
fd0a0d82 3822static const struct opcode opcode_table[256] = {
73fba5f4 3823 /* 0x00 - 0x07 */
fb864fbc 3824 F6ALU(Lock, em_add),
1cd196ea
AK		 3825 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3826 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 3827 /* 0x08 - 0x0F */
fb864fbc 3828 F6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 3829 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3830 N,
73fba5f4 3831 /* 0x10 - 0x17 */
fb864fbc 3832 F6ALU(Lock, em_adc),
1cd196ea
AK		 3833 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3834 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 3835 /* 0x18 - 0x1F */
fb864fbc 3836 F6ALU(Lock, em_sbb),
1cd196ea
AK		 3837 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3838 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 3839 /* 0x20 - 0x27 */
fb864fbc 3840 F6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 3841 /* 0x28 - 0x2F */
fb864fbc 3842 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3843 /* 0x30 - 0x37 */
fb864fbc 3844 F6ALU(Lock, em_xor), N, N,
73fba5f4 3845 /* 0x38 - 0x3F */
fb864fbc 3846 F6ALU(NoWrite, em_cmp), N, N,
73fba5f4 3847 /* 0x40 - 0x4F */
95413dc4 3848 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
73fba5f4 3849 /* 0x50 - 0x57 */
63540382 3850 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3851 /* 0x58 - 0x5F */
c54fe504 3852 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3853 /* 0x60 - 0x67 */
b96a7fad
TY		 3854 I(ImplicitOps | Stack | No64, em_pusha),
3855 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3856 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3857 N, N, N, N,
3858 /* 0x68 - 0x6F */
d46164db
AK		 3859 I(SrcImm | Mov | Stack, em_push),
3860 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3861 I(SrcImmByte | Mov | Stack, em_push),
3862 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
b3356bf0 3863 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
2b5e97e1 3864 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4
AK		 3865 /* 0x70 - 0x7F */
3866 X16(D(SrcImmByte)),
3867 /* 0x80 - 0x87 */
1c2545be
TY		 3868 G(ByteOp | DstMem | SrcImm, group1),
3869 G(DstMem | SrcImm, group1),
3870 G(ByteOp | DstMem | SrcImm | No64, group1),
3871 G(DstMem | SrcImmByte, group1),
fb864fbc 3872 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
d5ae7ce8 3873 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 3874 /* 0x88 - 0x8F */
d5ae7ce8 3875 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 3876 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 3877 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 3878 D(ModRM | SrcMem | NoAccess | DstReg),
3879 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3880 G(0, group1A),
73fba5f4 3881 /* 0x90 - 0x97 */
bf608f88 3882 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3883 /* 0x98 - 0x9F */
61429142 3884 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3885 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0 3886 II(ImplicitOps | Stack, em_pushf, pushf),
98f73630
PB		 3887 II(ImplicitOps | Stack, em_popf, popf),
3888 I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf),
73fba5f4 3889 /* 0xA0 - 0xA7 */
b9eac5f4 3890 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 3891 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 3892 I2bv(SrcSI | DstDI | Mov | String, em_mov),
fb864fbc 3893 F2bv(SrcSI | DstDI | String | NoWrite, em_cmp),
73fba5f4 3894 /* 0xA8 - 0xAF */
fb864fbc 3895 F2bv(DstAcc | SrcImm | NoWrite, em_test),
b9eac5f4
AK		 3896 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3897 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
fb864fbc 3898 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp),
73fba5f4 3899 /* 0xB0 - 0xB7 */
b9eac5f4 3900 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3901 /* 0xB8 - 0xBF */
5e2c6883 3902 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
73fba5f4 3903 /* 0xC0 - 0xC7 */
007a3b54 3904 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
40ece7c7 3905 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
ebda02c2 3906 I(ImplicitOps | Stack, em_ret),
d4b4325f
AK		 3907 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
3908 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 3909 G(ByteOp, group11), G(0, group11),
73fba5f4 3910 /* 0xC8 - 0xCF */
612e89f0 3911 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
3261107e
BR		 3912 I(ImplicitOps | Stack | SrcImmU16, em_ret_far_imm),
3913 I(ImplicitOps | Stack, em_ret_far),
3c6e276f 3914 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 3915 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 3916 /* 0xD0 - 0xD7 */
007a3b54
AK		 3917 G(Src2One | ByteOp, group2), G(Src2One, group2),
3918 G(Src2CL | ByteOp, group2), G(Src2CL, group2),
a035d5c6 3919 I(DstAcc | SrcImmUByte | No64, em_aam),
326f578f
PB		 3920 I(DstAcc | SrcImmUByte | No64, em_aad),
3921 F(DstAcc | ByteOp | No64, em_salc),
7fa57952 3922 I(DstAcc | SrcXLat | ByteOp, em_mov),
73fba5f4 3923 /* 0xD8 - 0xDF */
045a282c 3924 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
73fba5f4 3925 /* 0xE0 - 0xE7 */
d06e03ad
TY		 3926 X3(I(SrcImmByte, em_loop)),
3927 I(SrcImmByte, em_jcxz),
d7841a4b
TY		 3928 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
3929 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 3930 /* 0xE8 - 0xEF */
d4ddafcd 3931 I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps),
db5b0762 3932 I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
d7841a4b
TY		 3933 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
3934 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 3935 /* 0xF0 - 0xF7 */
bf608f88 3936 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 3937 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3938 G(ByteOp, group3), G(0, group3),
73fba5f4 3939 /* 0xF8 - 0xFF */
f411e6cd
TY		 3940 D(ImplicitOps), D(ImplicitOps),
3941 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 3942 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3943};
3944
fd0a0d82 3945static const struct opcode twobyte_table[256] = {
73fba5f4 3946 /* 0x00 - 0x0F */
dee6bb70 3947 G(0, group6), GD(0, &group7), N, N,
b51e974f 3948 N, I(ImplicitOps | EmulateOnUD, em_syscall),
db5b0762 3949 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 3950 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK		 3951 N, D(ImplicitOps | ModRM), N, N,
3952 /* 0x10 - 0x1F */
103f98ea
PB		 3953 N, N, N, N, N, N, N, N,
3954 D(ImplicitOps | ModRM), N, N, N, N, N, N, D(ImplicitOps | ModRM),
73fba5f4 3955 /* 0x20 - 0x2F */
9b88ae99
NA		 3956 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_read),
3957 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read),
3958 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write,
3959 check_cr_write),
3960 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write,
3961 check_dr_write),
73fba5f4 3962 N, N, N, N,
27ce8258
IM		 3963 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29),
3964 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29),
d5b77069 3965 N, GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_2b),
3e114eb4 3966 N, N, N, N,
73fba5f4 3967 /* 0x30 - 0x3F */
e1e210b0 3968 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 3969 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 3970 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 3971 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
b51e974f
BP		 3972 I(ImplicitOps | EmulateOnUD, em_sysenter),
3973 I(ImplicitOps | Priv | EmulateOnUD, em_sysexit),
d867162c 3974 N, N,
73fba5f4
AK		 3975 N, N, N, N, N, N, N, N,
3976 /* 0x40 - 0x4F */
140bad89 3977 X16(D(DstReg | SrcMem | ModRM)),
73fba5f4
AK		 3978 /* 0x50 - 0x5F */
3979 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3980 /* 0x60 - 0x6F */
aa97bb48
AK		 3981 N, N, N, N,
3982 N, N, N, N,
3983 N, N, N, N,
3984 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 3985 /* 0x70 - 0x7F */
aa97bb48
AK		 3986 N, N, N, N,
3987 N, N, N, N,
3988 N, N, N, N,
3989 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK		 3990 /* 0x80 - 0x8F */
3991 X16(D(SrcImm)),
3992 /* 0x90 - 0x9F */
ee45b58e 3993 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 3994 /* 0xA0 - 0xA7 */
1cd196ea 3995 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
11c363ba
AK		 3996 II(ImplicitOps, em_cpuid, cpuid),
3997 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
0bdea068
AK		 3998 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
3999 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
73fba5f4 4000 /* 0xA8 - 0xAF */
1cd196ea 4001 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
d5ae7ce8 4002 DI(ImplicitOps, rsm),
11c363ba 4003 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
0bdea068
AK		 4004 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
4005 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
4d758349 4006 D(ModRM), F(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 4007 /* 0xB0 - 0xB7 */
e940b5c2 4008 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
d4b4325f 4009 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
11c363ba 4010 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 4011 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
4012 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 4013 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 4014 /* 0xB8 - 0xBF */
4015 N, N,
ce7faab2 4016 G(BitOp, group8),
11c363ba
AK		 4017 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
4018 F(DstReg | SrcMem | ModRM, em_bsf), F(DstReg | SrcMem | ModRM, em_bsr),
2adb5ad9 4019 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
9299836e 4020 /* 0xC0 - 0xC7 */
e47a5f5f 4021 F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd),
92f738a5 4022 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4 4023 N, N, N, GD(0, &group9),
9299836e
AK		 4024 /* 0xC8 - 0xCF */
4025 X8(I(DstReg, em_bswap)),
73fba5f4
AK		 4026 /* 0xD0 - 0xDF */
4027 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4028 /* 0xE0 - 0xEF */
0a37027e
AW		 4029 N, N, N, N, N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_e7),
4030 N, N, N, N, N, N, N, N,
73fba5f4
AK		 4031 /* 0xF0 - 0xFF */
4032 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
4033};
4034
0bc5eedb 4035static const struct gprefix three_byte_0f_38_f0 = {
84cffe49 4036 I(DstReg | SrcMem | Mov, em_movbe), N, N, N
0bc5eedb
BP		 4037};
4038
4039static const struct gprefix three_byte_0f_38_f1 = {
84cffe49 4040 I(DstMem | SrcReg | Mov, em_movbe), N, N, N
0bc5eedb
BP		 4041};
4042
4043/*
4044 * Insns below are selected by the prefix which indexed by the third opcode
4045 * byte.
4046 */
4047static const struct opcode opcode_map_0f_38[256] = {
4048 /* 0x00 - 0x7f */
4049 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
84cffe49
BP		 4050 /* 0x80 - 0xef */
4051 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
4052 /* 0xf0 - 0xf1 */
4053 GP(EmulateOnUD | ModRM | Prefix, &three_byte_0f_38_f0),
4054 GP(EmulateOnUD | ModRM | Prefix, &three_byte_0f_38_f1),
4055 /* 0xf2 - 0xff */
4056 N, N, X4(N), X8(N)
0bc5eedb
BP		 4057};
4058
73fba5f4
AK		 4059#undef D
4060#undef N
4061#undef G
4062#undef GD
4063#undef I
aa97bb48 4064#undef GP
01de8b09 4065#undef EXT
73fba5f4 4066
8d8f4e9f 4067#undef D2bv
f6511935 4068#undef D2bvIP
8d8f4e9f 4069#undef I2bv
d7841a4b 4070#undef I2bvIP
d67fc27a 4071#undef I6ALU
8d8f4e9f 4072
9dac77fa 4073static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 4074{
4075 unsigned size;
4076
9dac77fa 4077 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 4078 if (size == 8)
4079 size = 4;
4080 return size;
4081}
4082
4083static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
4084 unsigned size, bool sign_extension)
4085{
39f21ee5
AK		 4086 int rc = X86EMUL_CONTINUE;
4087
4088 op->type = OP_IMM;
4089 op->bytes = size;
9dac77fa 4090 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 4091 /* NB. Immediates are sign-extended as necessary. */
4092 switch (op->bytes) {
4093 case 1:
e85a1085 4094 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 4095 break;
4096 case 2:
e85a1085 4097 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 4098 break;
4099 case 4:
e85a1085 4100 op->val = insn_fetch(s32, ctxt);
39f21ee5 4101 break;
5e2c6883
NA		 4102 case 8:
4103 op->val = insn_fetch(s64, ctxt);
4104 break;
39f21ee5
AK		 4105 }
4106 if (!sign_extension) {
4107 switch (op->bytes) {
4108 case 1:
4109 op->val &= 0xff;
4110 break;
4111 case 2:
4112 op->val &= 0xffff;
4113 break;
4114 case 4:
4115 op->val &= 0xffffffff;
4116 break;
4117 }
4118 }
4119done:
4120 return rc;
4121}
4122
a9945549
AK		 4123static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
4124 unsigned d)
4125{
4126 int rc = X86EMUL_CONTINUE;
4127
4128 switch (d) {
4129 case OpReg:
2adb5ad9 4130 decode_register_operand(ctxt, op);
a9945549
AK		 4131 break;
4132 case OpImmUByte:
608aabe3 4133 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 4134 break;
4135 case OpMem:
41ddf978 4136 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 4137 mem_common:
4138 *op = ctxt->memop;
4139 ctxt->memopp = op;
96888977 4140 if (ctxt->d & BitOp)
a9945549
AK		 4141 fetch_bit_operand(ctxt);
4142 op->orig_val = op->val;
4143 break;
41ddf978 4144 case OpMem64:
aaa05f24 4145 ctxt->memop.bytes = (ctxt->op_bytes == 8) ? 16 : 8;
41ddf978 4146 goto mem_common;
a9945549
AK		 4147 case OpAcc:
4148 op->type = OP_REG;
4149 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 4150 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
a9945549
AK		 4151 fetch_register_operand(op);
4152 op->orig_val = op->val;
4153 break;
820207c8
AK		 4154 case OpAccLo:
4155 op->type = OP_REG;
4156 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes;
4157 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4158 fetch_register_operand(op);
4159 op->orig_val = op->val;
4160 break;
4161 case OpAccHi:
4162 if (ctxt->d & ByteOp) {
4163 op->type = OP_NONE;
4164 break;
4165 }
4166 op->type = OP_REG;
4167 op->bytes = ctxt->op_bytes;
4168 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4169 fetch_register_operand(op);
4170 op->orig_val = op->val;
4171 break;
a9945549
AK		 4172 case OpDI:
4173 op->type = OP_MEM;
4174 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4175 op->addr.mem.ea =
dd856efa 4176 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RDI));
a9945549
AK		 4177 op->addr.mem.seg = VCPU_SREG_ES;
4178 op->val = 0;
b3356bf0 4179 op->count = 1;
a9945549
AK		 4180 break;
4181 case OpDX:
4182 op->type = OP_REG;
4183 op->bytes = 2;
dd856efa 4184 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
a9945549
AK		 4185 fetch_register_operand(op);
4186 break;
4dd6a57d
AK		 4187 case OpCL:
4188 op->bytes = 1;
dd856efa 4189 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4dd6a57d
AK		 4190 break;
4191 case OpImmByte:
4192 rc = decode_imm(ctxt, op, 1, true);
4193 break;
4194 case OpOne:
4195 op->bytes = 1;
4196 op->val = 1;
4197 break;
4198 case OpImm:
4199 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4200 break;
5e2c6883
NA		 4201 case OpImm64:
4202 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
4203 break;
28867cee
AK		 4204 case OpMem8:
4205 ctxt->memop.bytes = 1;
660696d1 4206 if (ctxt->memop.type == OP_REG) {
aa9ac1a6
GN		 4207 ctxt->memop.addr.reg = decode_register(ctxt,
4208 ctxt->modrm_rm, true);
660696d1
GN		 4209 fetch_register_operand(&ctxt->memop);
4210 }
28867cee 4211 goto mem_common;
0fe59128
AK		 4212 case OpMem16:
4213 ctxt->memop.bytes = 2;
4214 goto mem_common;
4215 case OpMem32:
4216 ctxt->memop.bytes = 4;
4217 goto mem_common;
4218 case OpImmU16:
4219 rc = decode_imm(ctxt, op, 2, false);
4220 break;
4221 case OpImmU:
4222 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
4223 break;
4224 case OpSI:
4225 op->type = OP_MEM;
4226 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4227 op->addr.mem.ea =
dd856efa 4228 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RSI));
573e80fe 4229 op->addr.mem.seg = ctxt->seg_override;
0fe59128 4230 op->val = 0;
b3356bf0 4231 op->count = 1;
0fe59128 4232 break;
7fa57952
PB		 4233 case OpXLat:
4234 op->type = OP_MEM;
4235 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4236 op->addr.mem.ea =
4237 register_address(ctxt,
4238 reg_read(ctxt, VCPU_REGS_RBX) +
4239 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
573e80fe 4240 op->addr.mem.seg = ctxt->seg_override;
7fa57952
PB		 4241 op->val = 0;
4242 break;
0fe59128
AK		 4243 case OpImmFAddr:
4244 op->type = OP_IMM;
4245 op->addr.mem.ea = ctxt->_eip;
4246 op->bytes = ctxt->op_bytes + 2;
4247 insn_fetch_arr(op->valptr, op->bytes, ctxt);
4248 break;
4249 case OpMemFAddr:
4250 ctxt->memop.bytes = ctxt->op_bytes + 2;
4251 goto mem_common;
c191a7a0
AK		 4252 case OpES:
4253 op->val = VCPU_SREG_ES;
4254 break;
4255 case OpCS:
4256 op->val = VCPU_SREG_CS;
4257 break;
4258 case OpSS:
4259 op->val = VCPU_SREG_SS;
4260 break;
4261 case OpDS:
4262 op->val = VCPU_SREG_DS;
4263 break;
4264 case OpFS:
4265 op->val = VCPU_SREG_FS;
4266 break;
4267 case OpGS:
4268 op->val = VCPU_SREG_GS;
4269 break;
a9945549
AK		 4270 case OpImplicit:
4271 /* Special instructions do their own operand decoding. */
4272 default:
4273 op->type = OP_NONE; /* Disable writeback. */
4274 break;
4275 }
4276
4277done:
4278 return rc;
4279}
4280
ef5d75cc 4281int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 4282{
dde7e6d1
AK		 4283 int rc = X86EMUL_CONTINUE;
4284 int mode = ctxt->mode;
46561646 4285 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 4286 bool op_prefix = false;
573e80fe 4287 bool has_seg_override = false;
46561646 4288 struct opcode opcode;
dde7e6d1 4289
f09ed83e
AK		 4290 ctxt->memop.type = OP_NONE;
4291 ctxt->memopp = NULL;
9dac77fa 4292 ctxt->_eip = ctxt->eip;
17052f16
PB		 4293 ctxt->fetch.ptr = ctxt->fetch.data;
4294 ctxt->fetch.end = ctxt->fetch.data + insn_len;
1ce19dc1 4295 ctxt->opcode_len = 1;
dc25e89e 4296 if (insn_len > 0)
9dac77fa 4297 memcpy(ctxt->fetch.data, insn, insn_len);
285ca9e9 4298 else {
9506d57d 4299 rc = __do_insn_fetch_bytes(ctxt, 1);
285ca9e9
PB		 4300 if (rc != X86EMUL_CONTINUE)
4301 return rc;
4302 }
dde7e6d1
AK		 4303
4304 switch (mode) {
4305 case X86EMUL_MODE_REAL:
4306 case X86EMUL_MODE_VM86:
4307 case X86EMUL_MODE_PROT16:
4308 def_op_bytes = def_ad_bytes = 2;
4309 break;
4310 case X86EMUL_MODE_PROT32:
4311 def_op_bytes = def_ad_bytes = 4;
4312 break;
4313#ifdef CONFIG_X86_64
4314 case X86EMUL_MODE_PROT64:
4315 def_op_bytes = 4;
4316 def_ad_bytes = 8;
4317 break;
4318#endif
4319 default:
1d2887e2 4320 return EMULATION_FAILED;
dde7e6d1
AK		 4321 }
4322
9dac77fa
AK		 4323 ctxt->op_bytes = def_op_bytes;
4324 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 4325
4326 /* Legacy prefixes. */
4327 for (;;) {
e85a1085 4328 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 4329 case 0x66: /* operand-size override */
0d7cdee8 4330 op_prefix = true;
dde7e6d1 4331 /* switch between 2/4 bytes */
9dac77fa 4332 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 4333 break;
4334 case 0x67: /* address-size override */
4335 if (mode == X86EMUL_MODE_PROT64)
4336 /* switch between 4/8 bytes */
9dac77fa 4337 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 4338 else
4339 /* switch between 2/4 bytes */
9dac77fa 4340 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 4341 break;
4342 case 0x26: /* ES override */
4343 case 0x2e: /* CS override */
4344 case 0x36: /* SS override */
4345 case 0x3e: /* DS override */
573e80fe
BD		 4346 has_seg_override = true;
4347 ctxt->seg_override = (ctxt->b >> 3) & 3;
dde7e6d1
AK		 4348 break;
4349 case 0x64: /* FS override */
4350 case 0x65: /* GS override */
573e80fe
BD		 4351 has_seg_override = true;
4352 ctxt->seg_override = ctxt->b & 7;
dde7e6d1
AK		 4353 break;
4354 case 0x40 ... 0x4f: /* REX */
4355 if (mode != X86EMUL_MODE_PROT64)
4356 goto done_prefixes;
9dac77fa 4357 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 4358 continue;
4359 case 0xf0: /* LOCK */
9dac77fa 4360 ctxt->lock_prefix = 1;
dde7e6d1
AK		 4361 break;
4362 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 4363 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 4364 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 4365 break;
4366 default:
4367 goto done_prefixes;
4368 }
4369
4370 /* Any legacy prefix after a REX prefix nullifies its effect. */
4371
9dac77fa 4372 ctxt->rex_prefix = 0;
dde7e6d1
AK		 4373 }
4374
4375done_prefixes:
4376
4377 /* REX prefix. */
9dac77fa
AK		 4378 if (ctxt->rex_prefix & 8)
4379 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 4380
4381 /* Opcode byte(s). */
9dac77fa 4382 opcode = opcode_table[ctxt->b];
d3ad6243 4383 /* Two-byte opcode? */
9dac77fa 4384 if (ctxt->b == 0x0f) {
1ce19dc1 4385 ctxt->opcode_len = 2;
e85a1085 4386 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 4387 opcode = twobyte_table[ctxt->b];
0bc5eedb
BP		 4388
4389 /* 0F_38 opcode map */
4390 if (ctxt->b == 0x38) {
4391 ctxt->opcode_len = 3;
4392 ctxt->b = insn_fetch(u8, ctxt);
4393 opcode = opcode_map_0f_38[ctxt->b];
4394 }
dde7e6d1 4395 }
9dac77fa 4396 ctxt->d = opcode.flags;
dde7e6d1 4397
9f4260e7
TY		 4398 if (ctxt->d & ModRM)
4399 ctxt->modrm = insn_fetch(u8, ctxt);
4400
7fe864dc
NA		 4401 /* vex-prefix instructions are not implemented */
4402 if (ctxt->opcode_len == 1 && (ctxt->b == 0xc5 || ctxt->b == 0xc4) &&
4403 (mode == X86EMUL_MODE_PROT64 ||
4404 (mode >= X86EMUL_MODE_PROT16 && (ctxt->modrm & 0x80)))) {
4405 ctxt->d = NotImpl;
4406 }
4407
9dac77fa
AK		 4408 while (ctxt->d & GroupMask) {
4409 switch (ctxt->d & GroupMask) {
46561646 4410 case Group:
9dac77fa 4411 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 4412 opcode = opcode.u.group[goffset];
4413 break;
4414 case GroupDual:
9dac77fa
AK		 4415 goffset = (ctxt->modrm >> 3) & 7;
4416 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 4417 opcode = opcode.u.gdual->mod3[goffset];
4418 else
4419 opcode = opcode.u.gdual->mod012[goffset];
4420 break;
4421 case RMExt:
9dac77fa 4422 goffset = ctxt->modrm & 7;
01de8b09 4423 opcode = opcode.u.group[goffset];
46561646
AK		 4424 break;
4425 case Prefix:
9dac77fa 4426 if (ctxt->rep_prefix && op_prefix)
1d2887e2 4427 return EMULATION_FAILED;
9dac77fa 4428 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 4429 switch (simd_prefix) {
4430 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4431 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4432 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4433 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4434 }
4435 break;
045a282c
GN		 4436 case Escape:
4437 if (ctxt->modrm > 0xbf)
4438 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
4439 else
4440 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
4441 break;
46561646 4442 default:
1d2887e2 4443 return EMULATION_FAILED;
0d7cdee8 4444 }
46561646 4445
b1ea50b2 4446 ctxt->d &= ~(u64)GroupMask;
9dac77fa 4447 ctxt->d |= opcode.flags;
0d7cdee8
AK		 4448 }
4449
e24186e0
PB		 4450 /* Unrecognised? */
4451 if (ctxt->d == 0)
4452 return EMULATION_FAILED;
4453
9dac77fa 4454 ctxt->execute = opcode.u.execute;
dde7e6d1 4455
3a6095a0
NA		 4456 if (unlikely(ctxt->ud) && likely(!(ctxt->d & EmulateOnUD)))
4457 return EMULATION_FAILED;
4458
d40a6898 4459 if (unlikely(ctxt->d &
3a6095a0 4460 (NotImpl|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm))) {
d40a6898
PB		 4461 /*
4462 * These are copied unconditionally here, and checked unconditionally
4463 * in x86_emulate_insn.
4464 */
4465 ctxt->check_perm = opcode.check_perm;
4466 ctxt->intercept = opcode.intercept;
dde7e6d1 4467
d40a6898
PB		 4468 if (ctxt->d & NotImpl)
4469 return EMULATION_FAILED;
d867162c 4470
d40a6898 4471 if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
9dac77fa 4472 ctxt->op_bytes = 8;
7f9b4b75 4473
d40a6898
PB		 4474 if (ctxt->d & Op3264) {
4475 if (mode == X86EMUL_MODE_PROT64)
4476 ctxt->op_bytes = 8;
4477 else
4478 ctxt->op_bytes = 4;
4479 }
4480
4481 if (ctxt->d & Sse)
4482 ctxt->op_bytes = 16;
4483 else if (ctxt->d & Mmx)
4484 ctxt->op_bytes = 8;
4485 }
1253791d 4486
dde7e6d1 4487 /* ModRM and SIB bytes. */
9dac77fa 4488 if (ctxt->d & ModRM) {
f09ed83e 4489 rc = decode_modrm(ctxt, &ctxt->memop);
573e80fe
BD		 4490 if (!has_seg_override) {
4491 has_seg_override = true;
4492 ctxt->seg_override = ctxt->modrm_seg;
4493 }
9dac77fa 4494 } else if (ctxt->d & MemAbs)
f09ed83e 4495 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 4496 if (rc != X86EMUL_CONTINUE)
4497 goto done;
4498
573e80fe
BD		 4499 if (!has_seg_override)
4500 ctxt->seg_override = VCPU_SREG_DS;
dde7e6d1 4501
573e80fe 4502 ctxt->memop.addr.mem.seg = ctxt->seg_override;
dde7e6d1 4503
dde7e6d1
AK		 4504 /*
4505 * Decode and fetch the source operand: register, memory
4506 * or immediate.
4507 */
0fe59128 4508 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 4509 if (rc != X86EMUL_CONTINUE)
4510 goto done;
4511
dde7e6d1
AK		 4512 /*
4513 * Decode and fetch the second source operand: register, memory
4514 * or immediate.
4515 */
4dd6a57d 4516 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 4517 if (rc != X86EMUL_CONTINUE)
4518 goto done;
4519
dde7e6d1 4520 /* Decode and fetch the destination operand: register or memory. */
a9945549 4521 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1
AK		 4522
4523done:
41061cdb 4524 if (ctxt->rip_relative)
f09ed83e 4525 ctxt->memopp->addr.mem.ea += ctxt->_eip;
cb16c348 4526
1d2887e2 4527 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 4528}
4529
1cb3f3ae
XG		 4530bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4531{
4532 return ctxt->d & PageTable;
4533}
4534
3e2f65d5
GN		 4535static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4536{
3e2f65d5
GN		 4537 /* The second termination condition only applies for REPE
4538 * and REPNE. Test if the repeat string operation prefix is
4539 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4540 * corresponding termination condition according to:
4541 * - if REPE/REPZ and ZF = 0 then done
4542 * - if REPNE/REPNZ and ZF = 1 then done
4543 */
9dac77fa
AK		 4544 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4545 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4546 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 4547 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 4548 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 4549 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
4550 return true;
4551
4552 return false;
4553}
4554
cbe2c9d3
AK		 4555static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4556{
4557 bool fault = false;
4558
4559 ctxt->ops->get_fpu(ctxt);
4560 asm volatile("1: fwait \n\t"
4561 "2: \n\t"
4562 ".pushsection .fixup,\"ax\" \n\t"
4563 "3: \n\t"
4564 "movb $1, %[fault] \n\t"
4565 "jmp 2b \n\t"
4566 ".popsection \n\t"
4567 _ASM_EXTABLE(1b, 3b)
38e8a2dd 4568 : [fault]"+qm"(fault));
cbe2c9d3
AK		 4569 ctxt->ops->put_fpu(ctxt);
4570
4571 if (unlikely(fault))
4572 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4573
4574 return X86EMUL_CONTINUE;
4575}
4576
4577static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4578 struct operand *op)
4579{
4580 if (op->type == OP_MM)
4581 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4582}
4583
e28bbd44
AK		 4584static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
4585{
4586 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
b9fa409b
AK		 4587 if (!(ctxt->d & ByteOp))
4588 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
e28bbd44 4589 asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n"
b8c0b6ae
AK		 4590 : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags),
4591 [fastop]"+S"(fop)
4592 : "c"(ctxt->src2.val));
e28bbd44 4593 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
b8c0b6ae
AK		 4594 if (!fop) /* exception is returned in fop variable */
4595 return emulate_de(ctxt);
e28bbd44
AK		 4596 return X86EMUL_CONTINUE;
4597}
dd856efa 4598
1498507a
BD		 4599void init_decode_cache(struct x86_emulate_ctxt *ctxt)
4600{
573e80fe
BD		 4601 memset(&ctxt->rip_relative, 0,
4602 (void *)&ctxt->modrm - (void *)&ctxt->rip_relative);
1498507a 4603
1498507a
BD		 4604 ctxt->io_read.pos = 0;
4605 ctxt->io_read.end = 0;
1498507a
BD		 4606 ctxt->mem_read.end = 0;
4607}
4608
7b105ca2 4609int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 4610{
0225fb50 4611 const struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 4612 int rc = X86EMUL_CONTINUE;
9dac77fa 4613 int saved_dst_type = ctxt->dst.type;
8b4caf66 4614
9dac77fa 4615 ctxt->mem_read.pos = 0;
310b5d30 4616
e24186e0
PB		 4617 /* LOCK prefix is allowed only with some instructions */
4618 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 4619 rc = emulate_ud(ctxt);
1161624f
GN		 4620 goto done;
4621 }
4622
e24186e0 4623 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 4624 rc = emulate_ud(ctxt);
d380a5e4
GN		 4625 goto done;
4626 }
4627
d40a6898
PB		 4628 if (unlikely(ctxt->d &
4629 (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) {
4630 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
4631 (ctxt->d & Undefined)) {
4632 rc = emulate_ud(ctxt);
4633 goto done;
4634 }
1253791d 4635
d40a6898
PB		 4636 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4637 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
4638 rc = emulate_ud(ctxt);
cbe2c9d3 4639 goto done;
d40a6898 4640 }
cbe2c9d3 4641
d40a6898
PB		 4642 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
4643 rc = emulate_nm(ctxt);
c4f035c6 4644 goto done;
d40a6898 4645 }
c4f035c6 4646
d40a6898
PB		 4647 if (ctxt->d & Mmx) {
4648 rc = flush_pending_x87_faults(ctxt);
4649 if (rc != X86EMUL_CONTINUE)
4650 goto done;
4651 /*
4652 * Now that we know the fpu is exception safe, we can fetch
4653 * operands from it.
4654 */
4655 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4656 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4657 if (!(ctxt->d & Mov))
4658 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4659 }
e92805ac 4660
685bbf4a 4661 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
d40a6898
PB		 4662 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4663 X86_ICPT_PRE_EXCEPT);
4664 if (rc != X86EMUL_CONTINUE)
4665 goto done;
4666 }
8ea7d6ae 4667
d40a6898
PB		 4668 /* Privileged instruction can be executed only in CPL=0 */
4669 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
68efa764
NA		 4670 if (ctxt->d & PrivUD)
4671 rc = emulate_ud(ctxt);
4672 else
4673 rc = emulate_gp(ctxt, 0);
d09beabd 4674 goto done;
d40a6898 4675 }
d09beabd 4676
d40a6898
PB		 4677 /* Instruction can only be executed in protected mode */
4678 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
4679 rc = emulate_ud(ctxt);
c4f035c6 4680 goto done;
d40a6898 4681 }
c4f035c6 4682
d40a6898 4683 /* Do instruction specific permission checks */
685bbf4a 4684 if (ctxt->d & CheckPerm) {
d40a6898
PB		 4685 rc = ctxt->check_perm(ctxt);
4686 if (rc != X86EMUL_CONTINUE)
4687 goto done;
4688 }
4689
685bbf4a 4690 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
d40a6898
PB		 4691 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4692 X86_ICPT_POST_EXCEPT);
4693 if (rc != X86EMUL_CONTINUE)
4694 goto done;
4695 }
4696
4697 if (ctxt->rep_prefix && (ctxt->d & String)) {
4698 /* All REP prefixes have the same first termination condition */
4699 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
4700 ctxt->eip = ctxt->_eip;
4467c3f1 4701 ctxt->eflags &= ~EFLG_RF;
d40a6898
PB		 4702 goto done;
4703 }
b9fa9d6b 4704 }
b9fa9d6b
AK		 4705 }
4706
9dac77fa
AK		 4707 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4708 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4709 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 4710 if (rc != X86EMUL_CONTINUE)
8b4caf66 4711 goto done;
9dac77fa 4712 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 4713 }
4714
9dac77fa
AK		 4715 if (ctxt->src2.type == OP_MEM) {
4716 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4717 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 4718 if (rc != X86EMUL_CONTINUE)
4719 goto done;
4720 }
4721
9dac77fa 4722 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 4723 goto special_insn;
4724
4725
9dac77fa 4726 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 4727 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 4728 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4729 &ctxt->dst.val, ctxt->dst.bytes);
69f55cb1
GN		 4730 if (rc != X86EMUL_CONTINUE)
4731 goto done;
038e51de 4732 }
9dac77fa 4733 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 4734
018a98db
AK		 4735special_insn:
4736
685bbf4a 4737 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
9dac77fa 4738 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4739 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 4740 if (rc != X86EMUL_CONTINUE)
4741 goto done;
4742 }
4743
b9a1ecb9
NA		 4744 if (ctxt->rep_prefix && (ctxt->d & String))
4745 ctxt->eflags |= EFLG_RF;
4746 else
4747 ctxt->eflags &= ~EFLG_RF;
4467c3f1 4748
9dac77fa 4749 if (ctxt->execute) {
e28bbd44
AK		 4750 if (ctxt->d & Fastop) {
4751 void (*fop)(struct fastop *) = (void *)ctxt->execute;
4752 rc = fastop(ctxt, fop);
4753 if (rc != X86EMUL_CONTINUE)
4754 goto done;
4755 goto writeback;
4756 }
9dac77fa 4757 rc = ctxt->execute(ctxt);
ef65c889
AK		 4758 if (rc != X86EMUL_CONTINUE)
4759 goto done;
4760 goto writeback;
4761 }
4762
1ce19dc1 4763 if (ctxt->opcode_len == 2)
6aa8b732 4764 goto twobyte_insn;
0bc5eedb
BP		 4765 else if (ctxt->opcode_len == 3)
4766 goto threebyte_insn;
6aa8b732 4767
9dac77fa 4768 switch (ctxt->b) {
6aa8b732 4769 case 0x63: /* movsxd */
8b4caf66 4770 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 4771 goto cannot_emulate;
9dac77fa 4772 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 4773 break;
b2833e3c 4774 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa 4775 if (test_cc(ctxt->b, ctxt->eflags))
234f3ce4 4776 rc = jmp_rel(ctxt, ctxt->src.val);
018a98db 4777 break;
7e0b54b1 4778 case 0x8d: /* lea r16/r32, m */
9dac77fa 4779 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 4780 break;
3d9e77df 4781 case 0x90 ... 0x97: /* nop / xchg reg, rax */
dd856efa 4782 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
a825f5cc
NA		 4783 ctxt->dst.type = OP_NONE;
4784 else
4785 rc = em_xchg(ctxt);
e4f973ae 4786 break;
e8b6fa70 4787 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 4788 switch (ctxt->op_bytes) {
4789 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
4790 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
4791 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 4792 }
4793 break;
6e154e56 4794 case 0xcc: /* int3 */
5c5df76b
TY		 4795 rc = emulate_int(ctxt, 3);
4796 break;
6e154e56 4797 case 0xcd: /* int n */
9dac77fa 4798 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 4799 break;
4800 case 0xce: /* into */
5c5df76b
TY		 4801 if (ctxt->eflags & EFLG_OF)
4802 rc = emulate_int(ctxt, 4);
6e154e56 4803 break;
1a52e051 4804 case 0xe9: /* jmp rel */
db5b0762 4805 case 0xeb: /* jmp rel short */
234f3ce4 4806 rc = jmp_rel(ctxt, ctxt->src.val);
9dac77fa 4807 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4808 break;
111de5d6 4809 case 0xf4: /* hlt */
6c3287f7 4810 ctxt->ops->halt(ctxt);
19fdfa0d 4811 break;
111de5d6
AK		 4812 case 0xf5: /* cmc */
4813 /* complement carry flag from eflags reg */
4814 ctxt->eflags ^= EFLG_CF;
111de5d6
AK		 4815 break;
4816 case 0xf8: /* clc */
4817 ctxt->eflags &= ~EFLG_CF;
111de5d6 4818 break;
8744aa9a
MG		 4819 case 0xf9: /* stc */
4820 ctxt->eflags |= EFLG_CF;
4821 break;
fb4616f4
MG		 4822 case 0xfc: /* cld */
4823 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 4824 break;
4825 case 0xfd: /* std */
4826 ctxt->eflags |= EFLG_DF;
fb4616f4 4827 break;
91269b8f
AK		 4828 default:
4829 goto cannot_emulate;
6aa8b732 4830 }
018a98db 4831
7d9ddaed
AK		 4832 if (rc != X86EMUL_CONTINUE)
4833 goto done;
4834
018a98db 4835writeback:
fb32b1ed
AK		 4836 if (ctxt->d & SrcWrite) {
4837 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR);
4838 rc = writeback(ctxt, &ctxt->src);
4839 if (rc != X86EMUL_CONTINUE)
4840 goto done;
4841 }
ee212297
NA		 4842 if (!(ctxt->d & NoWrite)) {
4843 rc = writeback(ctxt, &ctxt->dst);
4844 if (rc != X86EMUL_CONTINUE)
4845 goto done;
4846 }
018a98db 4847
5cd21917
GN		 4848 /*
4849 * restore dst type in case the decoding will be reused
4850 * (happens for string instruction )
4851 */
9dac77fa 4852 ctxt->dst.type = saved_dst_type;
5cd21917 4853
9dac77fa 4854 if ((ctxt->d & SrcMask) == SrcSI)
f3bd64c6 4855 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
a682e354 4856
9dac77fa 4857 if ((ctxt->d & DstMask) == DstDI)
f3bd64c6 4858 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
d9271123 4859
9dac77fa 4860 if (ctxt->rep_prefix && (ctxt->d & String)) {
b3356bf0 4861 unsigned int count;
9dac77fa 4862 struct read_cache *r = &ctxt->io_read;
b3356bf0
GN		 4863 if ((ctxt->d & SrcMask) == SrcSI)
4864 count = ctxt->src.count;
4865 else
4866 count = ctxt->dst.count;
4867 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX),
4868 -count);
3e2f65d5 4869
d2ddd1c4
GN		 4870 if (!string_insn_completed(ctxt)) {
4871 /*
4872 * Re-enter guest when pio read ahead buffer is empty
4873 * or, if it is not used, after each 1024 iteration.
4874 */
dd856efa 4875 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
d2ddd1c4
GN		 4876 (r->end == 0 || r->end != r->pos)) {
4877 /*
4878 * Reset read cache. Usually happens before
4879 * decode, but since instruction is restarted
4880 * we have to do it here.
4881 */
9dac77fa 4882 ctxt->mem_read.end = 0;
dd856efa 4883 writeback_registers(ctxt);
d2ddd1c4
GN		 4884 return EMULATION_RESTART;
4885 }
4886 goto done; /* skip rip writeback */
0fa6ccbd 4887 }
b9a1ecb9 4888 ctxt->eflags &= ~EFLG_RF;
5cd21917 4889 }
d2ddd1c4 4890
9dac77fa 4891 ctxt->eip = ctxt->_eip;
018a98db
AK		 4892
4893done:
e0ad0b47
PB		 4894 if (rc == X86EMUL_PROPAGATE_FAULT) {
4895 WARN_ON(ctxt->exception.vector > 0x1f);
da9cb575 4896 ctxt->have_exception = true;
e0ad0b47 4897 }
775fde86
JR		 4898 if (rc == X86EMUL_INTERCEPTED)
4899 return EMULATION_INTERCEPTED;
4900
dd856efa
AK		 4901 if (rc == X86EMUL_CONTINUE)
4902 writeback_registers(ctxt);
4903
d2ddd1c4 4904 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 4905
4906twobyte_insn:
9dac77fa 4907 switch (ctxt->b) {
018a98db 4908 case 0x09: /* wbinvd */
cfb22375 4909 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 4910 break;
4911 case 0x08: /* invd */
018a98db
AK		 4912 case 0x0d: /* GrpP (prefetch) */
4913 case 0x18: /* Grp16 (prefetch/nop) */
103f98ea 4914 case 0x1f: /* nop */
018a98db
AK		 4915 break;
4916 case 0x20: /* mov cr, reg */
9dac77fa 4917 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 4918 break;
6aa8b732 4919 case 0x21: /* mov from dr to reg */
9dac77fa 4920 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 4921 break;
6aa8b732 4922 case 0x40 ... 0x4f: /* cmov */
140bad89
NA		 4923 if (test_cc(ctxt->b, ctxt->eflags))
4924 ctxt->dst.val = ctxt->src.val;
4925 else if (ctxt->mode != X86EMUL_MODE_PROT64 ||
4926 ctxt->op_bytes != 4)
9dac77fa 4927 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 4928 break;
b2833e3c 4929 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa 4930 if (test_cc(ctxt->b, ctxt->eflags))
234f3ce4 4931 rc = jmp_rel(ctxt, ctxt->src.val);
018a98db 4932 break;
ee45b58e 4933 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 4934 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 4935 break;
2a7c5b8b
GC		 4936 case 0xae: /* clflush */
4937 break;
6aa8b732 4938 case 0xb6 ... 0xb7: /* movzx */
9dac77fa 4939 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4940 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
9dac77fa 4941 : (u16) ctxt->src.val;
6aa8b732 4942 break;
6aa8b732 4943 case 0xbe ... 0xbf: /* movsx */
9dac77fa 4944 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4945 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
9dac77fa 4946 (s16) ctxt->src.val;
6aa8b732 4947 break;
a012e65a 4948 case 0xc3: /* movnti */
9dac77fa 4949 ctxt->dst.bytes = ctxt->op_bytes;
3b32004a
NA		 4950 ctxt->dst.val = (ctxt->op_bytes == 8) ? (u64) ctxt->src.val :
4951 (u32) ctxt->src.val;
a012e65a 4952 break;
91269b8f
AK		 4953 default:
4954 goto cannot_emulate;
6aa8b732 4955 }
7d9ddaed 4956
0bc5eedb
BP		 4957threebyte_insn:
4958
7d9ddaed
AK		 4959 if (rc != X86EMUL_CONTINUE)
4960 goto done;
4961
6aa8b732
AK		 4962 goto writeback;
4963
4964cannot_emulate:
a0c0ab2f 4965 return EMULATION_FAILED;
6aa8b732 4966}
dd856efa
AK		 4967
4968void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
4969{
4970 invalidate_registers(ctxt);
4971}
4972
4973void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
4974{
4975 writeback_registers(ctxt);
4976}
Linux 6.x block layer and io_uring tree(s)