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KVM: x86 emulator: add Undefined decode flag
[linux-2.6-block.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
221d059d 12 * Copyright 2010 Red Hat, Inc. and/or its affilates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
23#ifndef __KERNEL__
24#include <stdio.h>
25#include <stdint.h>
26#include <public/xen.h>
d77c26fc 27#define DPRINTF(_f, _a ...) printf(_f , ## _a)
6aa8b732 28#else
edf88417 29#include <linux/kvm_host.h>
5fdbf976 30#include "kvm_cache_regs.h"
6aa8b732
AK		 31#define DPRINTF(x...) do {} while (0)
32#endif
6aa8b732 33#include <linux/module.h>
56e82318 34#include <asm/kvm_emulate.h>
6aa8b732 35
3eeb3288 36#include "x86.h"
38ba30ba 37#include "tss.h"
e99f0507 38
6aa8b732
AK		 39/*
40 * Opcode effective-address decode tables.
41 * Note that we only emulate instructions that have at least one memory
42 * operand (excluding implicit stack references). We assume that stack
43 * references and instruction fetches will never occur in special memory
44 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
45 * not be handled.
46 */
47
48/* Operand sizes: 8-bit operands or specified/overridden size. */
2ce49536 49#define ByteOp (1<<16) /* 8-bit operands. */
6aa8b732 50/* Destination operand type. */
2ce49536
AK		 51#define ImplicitOps (1<<17) /* Implicit in opcode. No generic decode. */
52#define DstReg (2<<17) /* Register operand. */
53#define DstMem (3<<17) /* Memory operand. */
54#define DstAcc (4<<17) /* Destination Accumulator */
55#define DstDI (5<<17) /* Destination is in ES:(E)DI */
56#define DstMem64 (6<<17) /* 64bit memory operand */
57#define DstMask (7<<17)
6aa8b732 58/* Source operand type. */
9c9fddd0
GT		 59#define SrcNone (0<<4) /* No source operand. */
60#define SrcImplicit (0<<4) /* Source operand is implicit in the opcode. */
61#define SrcReg (1<<4) /* Register operand. */
62#define SrcMem (2<<4) /* Memory operand. */
63#define SrcMem16 (3<<4) /* Memory operand (16-bit). */
64#define SrcMem32 (4<<4) /* Memory operand (32-bit). */
65#define SrcImm (5<<4) /* Immediate operand. */
66#define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
bfcadf83 67#define SrcOne (7<<4) /* Implied '1' */
341de7e3 68#define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
c9eaf20f 69#define SrcImmU (9<<4) /* Immediate operand, unsigned */
a682e354 70#define SrcSI (0xa<<4) /* Source is in the DS:RSI */
414e6277
GN		 71#define SrcImmFAddr (0xb<<4) /* Source is immediate far address */
72#define SrcMemFAddr (0xc<<4) /* Source is far address in memory */
5d55f299 73#define SrcAcc (0xd<<4) /* Source Accumulator */
341de7e3 74#define SrcMask (0xf<<4)
6aa8b732 75/* Generic ModRM decode. */
341de7e3 76#define ModRM (1<<8)
6aa8b732 77/* Destination is only written; never read. */
341de7e3
GN		 78#define Mov (1<<9)
79#define BitOp (1<<10)
80#define MemAbs (1<<11) /* Memory operand is absolute displacement */
9c9fddd0
GT		 81#define String (1<<12) /* String instruction (rep capable) */
82#define Stack (1<<13) /* Stack instruction (push/pop) */
e09d082c
AK		 83#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
84#define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
2ce49536 85#define GroupMask 0x0f /* Group number stored in bits 0:3 */
d8769fed 86/* Misc flags */
047a4818 87#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 88#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 89#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 90#define No64 (1<<28)
0dc8d10f
GT		 91/* Source 2 operand type */
92#define Src2None (0<<29)
93#define Src2CL (1<<29)
94#define Src2ImmByte (2<<29)
95#define Src2One (3<<29)
96#define Src2Mask (7<<29)
6aa8b732 97
83babbca
AK		 98#define X2(x) (x), (x)
99#define X3(x) X2(x), (x)
100#define X4(x) X2(x), X2(x)
101#define X5(x) X4(x), (x)
102#define X6(x) X4(x), X2(x)
103#define X7(x) X4(x), X3(x)
104#define X8(x) X4(x), X4(x)
105#define X16(x) X8(x), X8(x)
106
43bb19cd 107enum {
1d6ad207 108 Group1_80, Group1_81, Group1_82, Group1_83,
d95058a1 109 Group1A, Group3_Byte, Group3, Group4, Group5, Group7,
60a29d4e 110 Group8, Group9,
43bb19cd
AK		 111};
112
45ed60b3 113static u32 opcode_table[256] = {
6aa8b732 114 /* 0x00 - 0x07 */
d380a5e4 115 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732 116 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
0934ac9d 117 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
d8769fed 118 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
6aa8b732 119 /* 0x08 - 0x0F */
d380a5e4 120 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732 121 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
94677e61
MG		 122 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
123 ImplicitOps | Stack | No64, 0,
6aa8b732 124 /* 0x10 - 0x17 */
d380a5e4 125 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732 126 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
0934ac9d 127 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
d8769fed 128 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
6aa8b732 129 /* 0x18 - 0x1F */
d380a5e4 130 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732 131 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
0934ac9d 132 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
d8769fed 133 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
6aa8b732 134 /* 0x20 - 0x27 */
d380a5e4 135 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732 136 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
e97e883f 137 ByteOp | DstAcc | SrcImmByte, DstAcc | SrcImm, 0, 0,
6aa8b732 138 /* 0x28 - 0x2F */
d380a5e4 139 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732 140 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
abc19083 141 ByteOp | DstAcc | SrcImmByte, DstAcc | SrcImm, 0, 0,
6aa8b732 142 /* 0x30 - 0x37 */
d380a5e4 143 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732 144 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
222b7c52 145 ByteOp | DstAcc | SrcImmByte, DstAcc | SrcImm, 0, 0,
6aa8b732
AK		 146 /* 0x38 - 0x3F */
147 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
148 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
8a9fee67
GT		 149 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
150 0, 0,
749358a6
AK		 151 /* 0x40 - 0x4F */
152 X16(DstReg),
7f0aaee0 153 /* 0x50 - 0x57 */
3849186c 154 X8(SrcReg | Stack),
7f0aaee0 155 /* 0x58 - 0x5F */
3849186c 156 X8(DstReg | Stack),
7d316911 157 /* 0x60 - 0x67 */
abcf14b5
MG		 158 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
159 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ ,
7d316911
NK		 160 0, 0, 0, 0,
161 /* 0x68 - 0x6F */
91ed7a0e 162 SrcImm | Mov | Stack, 0, SrcImmByte | Mov | Stack, 0,
7972995b
GN		 163 DstDI | ByteOp | Mov | String, DstDI | Mov | String, /* insb, insw/insd */
164 SrcSI | ByteOp | ImplicitOps | String, SrcSI | ImplicitOps | String, /* outsb, outsw/outsd */
b3ab3405
AK		 165 /* 0x70 - 0x7F */
166 X16(SrcImmByte),
6aa8b732 167 /* 0x80 - 0x87 */
1d6ad207
AK		 168 Group | Group1_80, Group | Group1_81,
169 Group | Group1_82, Group | Group1_83,
6aa8b732 170 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
d380a5e4 171 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732
AK		 172 /* 0x88 - 0x8F */
173 ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov,
174 ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
b16b2b7b 175 DstMem | SrcNone | ModRM | Mov, ModRM | DstReg,
a5046e6c 176 ImplicitOps | SrcMem16 | ModRM, Group | Group1A,
b13354f8
MG		 177 /* 0x90 - 0x97 */
178 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
179 /* 0x98 - 0x9F */
414e6277 180 0, 0, SrcImmFAddr | No64, 0,
0654169e 181 ImplicitOps | Stack, ImplicitOps | Stack, 0, 0,
6aa8b732 182 /* 0xA0 - 0xA7 */
5d55f299
WY		 183 ByteOp | DstAcc | SrcMem | Mov | MemAbs, DstAcc | SrcMem | Mov | MemAbs,
184 ByteOp | DstMem | SrcAcc | Mov | MemAbs, DstMem | SrcAcc | Mov | MemAbs,
a682e354
GN		 185 ByteOp | SrcSI | DstDI | Mov | String, SrcSI | DstDI | Mov | String,
186 ByteOp | SrcSI | DstDI | String, SrcSI | DstDI | String,
6aa8b732 187 /* 0xA8 - 0xAF */
dfb507c4 188 DstAcc | SrcImmByte | ByteOp, DstAcc | SrcImm, ByteOp | DstDI | Mov | String, DstDI | Mov | String,
a682e354
GN		 189 ByteOp | SrcSI | DstAcc | Mov | String, SrcSI | DstAcc | Mov | String,
190 ByteOp | DstDI | String, DstDI | String,
a5e2e82b 191 /* 0xB0 - 0xB7 */
b6e61538 192 X8(ByteOp | DstReg | SrcImm | Mov),
a5e2e82b 193 /* 0xB8 - 0xBF */
b6e61538 194 X8(DstReg | SrcImm | Mov),
6aa8b732 195 /* 0xC0 - 0xC7 */
d9413cd7 196 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
6e3d5dfb 197 0, ImplicitOps | Stack, 0, 0,
d9413cd7 198 ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov,
6aa8b732 199 /* 0xC8 - 0xCF */
e637b823 200 0, 0, 0, ImplicitOps | Stack,
d8769fed 201 ImplicitOps, SrcImmByte, ImplicitOps | No64, ImplicitOps,
6aa8b732
AK		 202 /* 0xD0 - 0xD7 */
203 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
204 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
205 0, 0, 0, 0,
206 /* 0xD8 - 0xDF */
207 0, 0, 0, 0, 0, 0, 0, 0,
098c937b 208 /* 0xE0 - 0xE7 */
a6a3034c 209 0, 0, 0, 0,
cf8f70bf
GN		 210 ByteOp | SrcImmUByte | DstAcc, SrcImmUByte | DstAcc,
211 ByteOp | SrcImmUByte | DstAcc, SrcImmUByte | DstAcc,
098c937b 212 /* 0xE8 - 0xEF */
d53c4777 213 SrcImm | Stack, SrcImm | ImplicitOps,
414e6277 214 SrcImmFAddr | No64, SrcImmByte | ImplicitOps,
cf8f70bf
GN		 215 SrcNone | ByteOp | DstAcc, SrcNone | DstAcc,
216 SrcNone | ByteOp | DstAcc, SrcNone | DstAcc,
6aa8b732
AK		 217 /* 0xF0 - 0xF7 */
218 0, 0, 0, 0,
e92805ac 219 ImplicitOps | Priv, ImplicitOps, Group | Group3_Byte, Group | Group3,
6aa8b732 220 /* 0xF8 - 0xFF */
b284be57 221 ImplicitOps, 0, ImplicitOps, ImplicitOps,
fb4616f4 222 ImplicitOps, ImplicitOps, Group | Group4, Group | Group5,
6aa8b732
AK		 223};
224
45ed60b3 225static u32 twobyte_table[256] = {
6aa8b732 226 /* 0x00 - 0x0F */
e92805ac
GN		 227 0, Group | GroupDual | Group7, 0, 0,
228 0, ImplicitOps, ImplicitOps | Priv, 0,
229 ImplicitOps | Priv, ImplicitOps | Priv, 0, 0,
230 0, ImplicitOps | ModRM, 0, 0,
6aa8b732
AK		 231 /* 0x10 - 0x1F */
232 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0,
233 /* 0x20 - 0x2F */
e92805ac
GN		 234 ModRM | ImplicitOps | Priv, ModRM | Priv,
235 ModRM | ImplicitOps | Priv, ModRM | Priv,
236 0, 0, 0, 0,
6aa8b732
AK		 237 0, 0, 0, 0, 0, 0, 0, 0,
238 /* 0x30 - 0x3F */
e92805ac
GN		 239 ImplicitOps | Priv, 0, ImplicitOps | Priv, 0,
240 ImplicitOps, ImplicitOps | Priv, 0, 0,
e99f0507 241 0, 0, 0, 0, 0, 0, 0, 0,
be8eacdd
AK		 242 /* 0x40 - 0x4F */
243 X16(DstReg | SrcMem | ModRM | Mov),
6aa8b732
AK		 244 /* 0x50 - 0x5F */
245 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
246 /* 0x60 - 0x6F */
247 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
248 /* 0x70 - 0x7F */
249 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
250 /* 0x80 - 0x8F */
880a1883 251 X16(SrcImm),
6aa8b732
AK		 252 /* 0x90 - 0x9F */
253 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
254 /* 0xA0 - 0xA7 */
0934ac9d
MG		 255 ImplicitOps | Stack, ImplicitOps | Stack,
256 0, DstMem | SrcReg | ModRM | BitOp,
9bf8ea42
GT		 257 DstMem | SrcReg | Src2ImmByte | ModRM,
258 DstMem | SrcReg | Src2CL | ModRM, 0, 0,
6aa8b732 259 /* 0xA8 - 0xAF */
0934ac9d 260 ImplicitOps | Stack, ImplicitOps | Stack,
d380a5e4 261 0, DstMem | SrcReg | ModRM | BitOp | Lock,
9bf8ea42
GT		 262 DstMem | SrcReg | Src2ImmByte | ModRM,
263 DstMem | SrcReg | Src2CL | ModRM,
264 ModRM, 0,
6aa8b732 265 /* 0xB0 - 0xB7 */
d380a5e4
GN		 266 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
267 0, DstMem | SrcReg | ModRM | BitOp | Lock,
6aa8b732
AK		 268 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
269 DstReg | SrcMem16 | ModRM | Mov,
270 /* 0xB8 - 0xBF */
d380a5e4
GN		 271 0, 0,
272 Group | Group8, DstMem | SrcReg | ModRM | BitOp | Lock,
6aa8b732
AK		 273 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
274 DstReg | SrcMem16 | ModRM | Mov,
275 /* 0xC0 - 0xCF */
60a29d4e
GN		 276 0, 0, 0, DstMem | SrcReg | ModRM | Mov,
277 0, 0, 0, Group | GroupDual | Group9,
a012e65a 278 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 279 /* 0xD0 - 0xDF */
280 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
281 /* 0xE0 - 0xEF */
282 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
283 /* 0xF0 - 0xFF */
284 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
285};
286
45ed60b3 287static u32 group_table[] = {
1d6ad207 288 [Group1_80*8] =
d380a5e4
GN		 289 ByteOp | DstMem | SrcImm | ModRM | Lock,
290 ByteOp | DstMem | SrcImm | ModRM | Lock,
291 ByteOp | DstMem | SrcImm | ModRM | Lock,
292 ByteOp | DstMem | SrcImm | ModRM | Lock,
293 ByteOp | DstMem | SrcImm | ModRM | Lock,
294 ByteOp | DstMem | SrcImm | ModRM | Lock,
295 ByteOp | DstMem | SrcImm | ModRM | Lock,
296 ByteOp | DstMem | SrcImm | ModRM,
1d6ad207 297 [Group1_81*8] =
d380a5e4
GN		 298 DstMem | SrcImm | ModRM | Lock,
299 DstMem | SrcImm | ModRM | Lock,
300 DstMem | SrcImm | ModRM | Lock,
301 DstMem | SrcImm | ModRM | Lock,
302 DstMem | SrcImm | ModRM | Lock,
303 DstMem | SrcImm | ModRM | Lock,
304 DstMem | SrcImm | ModRM | Lock,
305 DstMem | SrcImm | ModRM,
1d6ad207 306 [Group1_82*8] =
e424e191
GN		 307 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
308 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
309 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
310 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
311 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
312 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
313 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
314 ByteOp | DstMem | SrcImm | ModRM | No64,
1d6ad207 315 [Group1_83*8] =
d380a5e4
GN		 316 DstMem | SrcImmByte | ModRM | Lock,
317 DstMem | SrcImmByte | ModRM | Lock,
318 DstMem | SrcImmByte | ModRM | Lock,
319 DstMem | SrcImmByte | ModRM | Lock,
320 DstMem | SrcImmByte | ModRM | Lock,
321 DstMem | SrcImmByte | ModRM | Lock,
322 DstMem | SrcImmByte | ModRM | Lock,
323 DstMem | SrcImmByte | ModRM,
43bb19cd
AK		 324 [Group1A*8] =
325 DstMem | SrcNone | ModRM | Mov | Stack, 0, 0, 0, 0, 0, 0, 0,
7d858a19 326 [Group3_Byte*8] =
7d5993d6 327 ByteOp | SrcImm | DstMem | ModRM, ByteOp | SrcImm | DstMem | ModRM,
7d858a19
AK		 328 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
329 0, 0, 0, 0,
330 [Group3*8] =
7d5993d6 331 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
6eb06cb2 332 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
7d858a19 333 0, 0, 0, 0,
fd60754e 334 [Group4*8] =
c0e0608c 335 ByteOp | DstMem | SrcNone | ModRM | Lock, ByteOp | DstMem | SrcNone | ModRM | Lock,
fd60754e
AK		 336 0, 0, 0, 0, 0, 0,
337 [Group5*8] =
c0e0608c 338 DstMem | SrcNone | ModRM | Lock, DstMem | SrcNone | ModRM | Lock,
d19292e4 339 SrcMem | ModRM | Stack, 0,
414e6277 340 SrcMem | ModRM | Stack, SrcMemFAddr | ModRM | ImplicitOps,
ea79849d 341 SrcMem | ModRM | Stack, 0,
d95058a1 342 [Group7*8] =
e92805ac 343 0, 0, ModRM | SrcMem | Priv, ModRM | SrcMem | Priv,
16286d08 344 SrcNone | ModRM | DstMem | Mov, 0,
e92805ac 345 SrcMem16 | ModRM | Mov | Priv, SrcMem | ModRM | ByteOp | Priv,
2db2c2eb
GN		 346 [Group8*8] =
347 0, 0, 0, 0,
d380a5e4
GN		 348 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM | Lock,
349 DstMem | SrcImmByte | ModRM | Lock, DstMem | SrcImmByte | ModRM | Lock,
60a29d4e 350 [Group9*8] =
6550e1f1 351 0, DstMem64 | ModRM | Lock, 0, 0, 0, 0, 0, 0,
e09d082c
AK		 352};
353
45ed60b3 354static u32 group2_table[] = {
d95058a1 355 [Group7*8] =
835e6b80 356 SrcNone | ModRM | Priv, 0, 0, SrcNone | ModRM | Priv,
16286d08 357 SrcNone | ModRM | DstMem | Mov, 0,
835e6b80 358 SrcMem16 | ModRM | Mov | Priv, 0,
60a29d4e
GN		 359 [Group9*8] =
360 0, 0, 0, 0, 0, 0, 0, 0,
e09d082c
AK		 361};
362
6aa8b732 363/* EFLAGS bit definitions. */
d4c6a154
GN		 364#define EFLG_ID (1<<21)
365#define EFLG_VIP (1<<20)
366#define EFLG_VIF (1<<19)
367#define EFLG_AC (1<<18)
b1d86143
AP		 368#define EFLG_VM (1<<17)
369#define EFLG_RF (1<<16)
d4c6a154
GN		 370#define EFLG_IOPL (3<<12)
371#define EFLG_NT (1<<14)
6aa8b732
AK		 372#define EFLG_OF (1<<11)
373#define EFLG_DF (1<<10)
b1d86143 374#define EFLG_IF (1<<9)
d4c6a154 375#define EFLG_TF (1<<8)
6aa8b732
AK		 376#define EFLG_SF (1<<7)
377#define EFLG_ZF (1<<6)
378#define EFLG_AF (1<<4)
379#define EFLG_PF (1<<2)
380#define EFLG_CF (1<<0)
381
382/*
383 * Instruction emulation:
384 * Most instructions are emulated directly via a fragment of inline assembly
385 * code. This allows us to save/restore EFLAGS and thus very easily pick up
386 * any modified flags.
387 */
388
05b3e0c2 389#if defined(CONFIG_X86_64)
6aa8b732
AK		 390#define _LO32 "k" /* force 32-bit operand */
391#define _STK "%%rsp" /* stack pointer */
392#elif defined(__i386__)
393#define _LO32 "" /* force 32-bit operand */
394#define _STK "%%esp" /* stack pointer */
395#endif
396
397/*
398 * These EFLAGS bits are restored from saved value during emulation, and
399 * any changes are written back to the saved value after emulation.
400 */
401#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
402
403/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 404#define _PRE_EFLAGS(_sav, _msk, _tmp) \
405 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
406 "movl %"_sav",%"_LO32 _tmp"; " \
407 "push %"_tmp"; " \
408 "push %"_tmp"; " \
409 "movl %"_msk",%"_LO32 _tmp"; " \
410 "andl %"_LO32 _tmp",("_STK"); " \
411 "pushf; " \
412 "notl %"_LO32 _tmp"; " \
413 "andl %"_LO32 _tmp",("_STK"); " \
414 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
415 "pop %"_tmp"; " \
416 "orl %"_LO32 _tmp",("_STK"); " \
417 "popf; " \
418 "pop %"_sav"; "
6aa8b732
AK		 419
420/* After executing instruction: write-back necessary bits in EFLAGS. */
421#define _POST_EFLAGS(_sav, _msk, _tmp) \
422 /* _sav |= EFLAGS & _msk; */ \
423 "pushf; " \
424 "pop %"_tmp"; " \
425 "andl %"_msk",%"_LO32 _tmp"; " \
426 "orl %"_LO32 _tmp",%"_sav"; "
427
dda96d8f
AK		 428#ifdef CONFIG_X86_64
429#define ON64(x) x
430#else
431#define ON64(x)
432#endif
433
6b7ad61f
AK		 434#define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix) \
435 do { \
436 __asm__ __volatile__ ( \
437 _PRE_EFLAGS("0", "4", "2") \
438 _op _suffix " %"_x"3,%1; " \
439 _POST_EFLAGS("0", "4", "2") \
440 : "=m" (_eflags), "=m" ((_dst).val), \
441 "=&r" (_tmp) \
442 : _y ((_src).val), "i" (EFLAGS_MASK)); \
f3fd92fb 443 } while (0)
6b7ad61f
AK		 444
445
6aa8b732
AK		 446/* Raw emulation: instruction has two explicit operands. */
447#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 448 do { \
449 unsigned long _tmp; \
450 \
451 switch ((_dst).bytes) { \
452 case 2: \
453 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w"); \
454 break; \
455 case 4: \
456 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l"); \
457 break; \
458 case 8: \
459 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q")); \
460 break; \
461 } \
6aa8b732
AK		 462 } while (0)
463
464#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
465 do { \
6b7ad61f 466 unsigned long _tmp; \
d77c26fc 467 switch ((_dst).bytes) { \
6aa8b732 468 case 1: \
6b7ad61f 469 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b"); \
6aa8b732
AK		 470 break; \
471 default: \
472 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
473 _wx, _wy, _lx, _ly, _qx, _qy); \
474 break; \
475 } \
476 } while (0)
477
478/* Source operand is byte-sized and may be restricted to just %cl. */
479#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
480 __emulate_2op(_op, _src, _dst, _eflags, \
481 "b", "c", "b", "c", "b", "c", "b", "c")
482
483/* Source operand is byte, word, long or quad sized. */
484#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
485 __emulate_2op(_op, _src, _dst, _eflags, \
486 "b", "q", "w", "r", _LO32, "r", "", "r")
487
488/* Source operand is word, long or quad sized. */
489#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
490 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
491 "w", "r", _LO32, "r", "", "r")
492
d175226a
GT		 493/* Instruction has three operands and one operand is stored in ECX register */
494#define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
495 do { \
496 unsigned long _tmp; \
497 _type _clv = (_cl).val; \
498 _type _srcv = (_src).val; \
499 _type _dstv = (_dst).val; \
500 \
501 __asm__ __volatile__ ( \
502 _PRE_EFLAGS("0", "5", "2") \
503 _op _suffix " %4,%1 \n" \
504 _POST_EFLAGS("0", "5", "2") \
505 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
506 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
507 ); \
508 \
509 (_cl).val = (unsigned long) _clv; \
510 (_src).val = (unsigned long) _srcv; \
511 (_dst).val = (unsigned long) _dstv; \
512 } while (0)
513
514#define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
515 do { \
516 switch ((_dst).bytes) { \
517 case 2: \
518 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
519 "w", unsigned short); \
520 break; \
521 case 4: \
522 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
523 "l", unsigned int); \
524 break; \
525 case 8: \
526 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
527 "q", unsigned long)); \
528 break; \
529 } \
530 } while (0)
531
dda96d8f 532#define __emulate_1op(_op, _dst, _eflags, _suffix) \
6aa8b732
AK		 533 do { \
534 unsigned long _tmp; \
535 \
dda96d8f
AK		 536 __asm__ __volatile__ ( \
537 _PRE_EFLAGS("0", "3", "2") \
538 _op _suffix " %1; " \
539 _POST_EFLAGS("0", "3", "2") \
540 : "=m" (_eflags), "+m" ((_dst).val), \
541 "=&r" (_tmp) \
542 : "i" (EFLAGS_MASK)); \
543 } while (0)
544
545/* Instruction has only one explicit operand (no source operand). */
546#define emulate_1op(_op, _dst, _eflags) \
547 do { \
d77c26fc 548 switch ((_dst).bytes) { \
dda96d8f
AK		 549 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
550 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
551 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
552 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
6aa8b732
AK		 553 } \
554 } while (0)
555
6aa8b732
AK		 556/* Fetch next part of the instruction being emulated. */
557#define insn_fetch(_type, _size, _eip) \
558({ unsigned long _x; \
62266869 559 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
af5b4f7f 560 if (rc != X86EMUL_CONTINUE) \
6aa8b732
AK		 561 goto done; \
562 (_eip) += (_size); \
563 (_type)_x; \
564})
565
414e6277
GN		 566#define insn_fetch_arr(_arr, _size, _eip) \
567({ rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size)); \
568 if (rc != X86EMUL_CONTINUE) \
569 goto done; \
570 (_eip) += (_size); \
571})
572
ddcb2885
HH		 573static inline unsigned long ad_mask(struct decode_cache *c)
574{
575 return (1UL << (c->ad_bytes << 3)) - 1;
576}
577
6aa8b732 578/* Access/update address held in a register, based on addressing mode. */
e4706772
HH		 579static inline unsigned long
580address_mask(struct decode_cache *c, unsigned long reg)
581{
582 if (c->ad_bytes == sizeof(unsigned long))
583 return reg;
584 else
585 return reg & ad_mask(c);
586}
587
588static inline unsigned long
589register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
590{
591 return base + address_mask(c, reg);
592}
593
7a957275
HH		 594static inline void
595register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
596{
597 if (c->ad_bytes == sizeof(unsigned long))
598 *reg += inc;
599 else
600 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
601}
6aa8b732 602
7a957275
HH		 603static inline void jmp_rel(struct decode_cache *c, int rel)
604{
605 register_address_increment(c, &c->eip, rel);
606}
098c937b 607
7a5b56df
AK		 608static void set_seg_override(struct decode_cache *c, int seg)
609{
610 c->has_seg_override = true;
611 c->seg_override = seg;
612}
613
79168fd1
GN		 614static unsigned long seg_base(struct x86_emulate_ctxt *ctxt,
615 struct x86_emulate_ops *ops, int seg)
7a5b56df
AK		 616{
617 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
618 return 0;
619
79168fd1 620 return ops->get_cached_segment_base(seg, ctxt->vcpu);
7a5b56df
AK		 621}
622
623static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt,
79168fd1 624 struct x86_emulate_ops *ops,
7a5b56df
AK		 625 struct decode_cache *c)
626{
627 if (!c->has_seg_override)
628 return 0;
629
79168fd1 630 return seg_base(ctxt, ops, c->seg_override);
7a5b56df
AK		 631}
632
79168fd1
GN		 633static unsigned long es_base(struct x86_emulate_ctxt *ctxt,
634 struct x86_emulate_ops *ops)
7a5b56df 635{
79168fd1 636 return seg_base(ctxt, ops, VCPU_SREG_ES);
7a5b56df
AK		 637}
638
79168fd1
GN		 639static unsigned long ss_base(struct x86_emulate_ctxt *ctxt,
640 struct x86_emulate_ops *ops)
7a5b56df 641{
79168fd1 642 return seg_base(ctxt, ops, VCPU_SREG_SS);
7a5b56df
AK		 643}
644
54b8486f
GN		 645static void emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
646 u32 error, bool valid)
647{
648 ctxt->exception = vec;
649 ctxt->error_code = error;
650 ctxt->error_code_valid = valid;
651 ctxt->restart = false;
652}
653
654static void emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
655{
656 emulate_exception(ctxt, GP_VECTOR, err, true);
657}
658
659static void emulate_pf(struct x86_emulate_ctxt *ctxt, unsigned long addr,
660 int err)
661{
662 ctxt->cr2 = addr;
663 emulate_exception(ctxt, PF_VECTOR, err, true);
664}
665
666static void emulate_ud(struct x86_emulate_ctxt *ctxt)
667{
668 emulate_exception(ctxt, UD_VECTOR, 0, false);
669}
670
671static void emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
672{
673 emulate_exception(ctxt, TS_VECTOR, err, true);
674}
675
62266869
AK		 676static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
677 struct x86_emulate_ops *ops,
2fb53ad8 678 unsigned long eip, u8 *dest)
62266869
AK		 679{
680 struct fetch_cache *fc = &ctxt->decode.fetch;
681 int rc;
2fb53ad8 682 int size, cur_size;
62266869 683
2fb53ad8
AK		 684 if (eip == fc->end) {
685 cur_size = fc->end - fc->start;
686 size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip));
687 rc = ops->fetch(ctxt->cs_base + eip, fc->data + cur_size,
688 size, ctxt->vcpu, NULL);
3e2815e9 689 if (rc != X86EMUL_CONTINUE)
62266869 690 return rc;
2fb53ad8 691 fc->end += size;
62266869 692 }
2fb53ad8 693 *dest = fc->data[eip - fc->start];
3e2815e9 694 return X86EMUL_CONTINUE;
62266869
AK		 695}
696
697static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
698 struct x86_emulate_ops *ops,
699 unsigned long eip, void *dest, unsigned size)
700{
3e2815e9 701 int rc;
62266869 702
eb3c79e6 703 /* x86 instructions are limited to 15 bytes. */
063db061 704 if (eip + size - ctxt->eip > 15)
eb3c79e6 705 return X86EMUL_UNHANDLEABLE;
62266869
AK		 706 while (size--) {
707 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
3e2815e9 708 if (rc != X86EMUL_CONTINUE)
62266869
AK		 709 return rc;
710 }
3e2815e9 711 return X86EMUL_CONTINUE;
62266869
AK		 712}
713
1e3c5cb0
RR		 714/*
715 * Given the 'reg' portion of a ModRM byte, and a register block, return a
716 * pointer into the block that addresses the relevant register.
717 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
718 */
719static void *decode_register(u8 modrm_reg, unsigned long *regs,
720 int highbyte_regs)
6aa8b732
AK		 721{
722 void *p;
723
724 p = &regs[modrm_reg];
725 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
726 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
727 return p;
728}
729
730static int read_descriptor(struct x86_emulate_ctxt *ctxt,
731 struct x86_emulate_ops *ops,
732 void *ptr,
733 u16 *size, unsigned long *address, int op_bytes)
734{
735 int rc;
736
737 if (op_bytes == 2)
738 op_bytes = 3;
739 *address = 0;
cebff02b 740 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
1871c602 741 ctxt->vcpu, NULL);
1b30eaa8 742 if (rc != X86EMUL_CONTINUE)
6aa8b732 743 return rc;
cebff02b 744 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
1871c602 745 ctxt->vcpu, NULL);
6aa8b732
AK		 746 return rc;
747}
748
bbe9abbd
NK		 749static int test_cc(unsigned int condition, unsigned int flags)
750{
751 int rc = 0;
752
753 switch ((condition & 15) >> 1) {
754 case 0: /* o */
755 rc |= (flags & EFLG_OF);
756 break;
757 case 1: /* b/c/nae */
758 rc |= (flags & EFLG_CF);
759 break;
760 case 2: /* z/e */
761 rc |= (flags & EFLG_ZF);
762 break;
763 case 3: /* be/na */
764 rc |= (flags & (EFLG_CF|EFLG_ZF));
765 break;
766 case 4: /* s */
767 rc |= (flags & EFLG_SF);
768 break;
769 case 5: /* p/pe */
770 rc |= (flags & EFLG_PF);
771 break;
772 case 7: /* le/ng */
773 rc |= (flags & EFLG_ZF);
774 /* fall through */
775 case 6: /* l/nge */
776 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
777 break;
778 }
779
780 /* Odd condition identifiers (lsb == 1) have inverted sense. */
781 return (!!rc ^ (condition & 1));
782}
783
3c118e24
AK		 784static void decode_register_operand(struct operand *op,
785 struct decode_cache *c,
3c118e24
AK		 786 int inhibit_bytereg)
787{
33615aa9 788 unsigned reg = c->modrm_reg;
9f1ef3f8 789 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 790
791 if (!(c->d & ModRM))
792 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
3c118e24
AK		 793 op->type = OP_REG;
794 if ((c->d & ByteOp) && !inhibit_bytereg) {
33615aa9 795 op->ptr = decode_register(reg, c->regs, highbyte_regs);
3c118e24
AK		 796 op->val = *(u8 *)op->ptr;
797 op->bytes = 1;
798 } else {
33615aa9 799 op->ptr = decode_register(reg, c->regs, 0);
3c118e24
AK		 800 op->bytes = c->op_bytes;
801 switch (op->bytes) {
802 case 2:
803 op->val = *(u16 *)op->ptr;
804 break;
805 case 4:
806 op->val = *(u32 *)op->ptr;
807 break;
808 case 8:
809 op->val = *(u64 *) op->ptr;
810 break;
811 }
812 }
813 op->orig_val = op->val;
814}
815
1c73ef66
AK		 816static int decode_modrm(struct x86_emulate_ctxt *ctxt,
817 struct x86_emulate_ops *ops)
818{
819 struct decode_cache *c = &ctxt->decode;
820 u8 sib;
f5b4edcd 821 int index_reg = 0, base_reg = 0, scale;
3e2815e9 822 int rc = X86EMUL_CONTINUE;
1c73ef66
AK		 823
824 if (c->rex_prefix) {
825 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
826 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
827 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
828 }
829
830 c->modrm = insn_fetch(u8, 1, c->eip);
831 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
832 c->modrm_reg |= (c->modrm & 0x38) >> 3;
833 c->modrm_rm |= (c->modrm & 0x07);
834 c->modrm_ea = 0;
835 c->use_modrm_ea = 1;
836
837 if (c->modrm_mod == 3) {
107d6d2e
AK		 838 c->modrm_ptr = decode_register(c->modrm_rm,
839 c->regs, c->d & ByteOp);
840 c->modrm_val = *(unsigned long *)c->modrm_ptr;
1c73ef66
AK		 841 return rc;
842 }
843
844 if (c->ad_bytes == 2) {
845 unsigned bx = c->regs[VCPU_REGS_RBX];
846 unsigned bp = c->regs[VCPU_REGS_RBP];
847 unsigned si = c->regs[VCPU_REGS_RSI];
848 unsigned di = c->regs[VCPU_REGS_RDI];
849
850 /* 16-bit ModR/M decode. */
851 switch (c->modrm_mod) {
852 case 0:
853 if (c->modrm_rm == 6)
854 c->modrm_ea += insn_fetch(u16, 2, c->eip);
855 break;
856 case 1:
857 c->modrm_ea += insn_fetch(s8, 1, c->eip);
858 break;
859 case 2:
860 c->modrm_ea += insn_fetch(u16, 2, c->eip);
861 break;
862 }
863 switch (c->modrm_rm) {
864 case 0:
865 c->modrm_ea += bx + si;
866 break;
867 case 1:
868 c->modrm_ea += bx + di;
869 break;
870 case 2:
871 c->modrm_ea += bp + si;
872 break;
873 case 3:
874 c->modrm_ea += bp + di;
875 break;
876 case 4:
877 c->modrm_ea += si;
878 break;
879 case 5:
880 c->modrm_ea += di;
881 break;
882 case 6:
883 if (c->modrm_mod != 0)
884 c->modrm_ea += bp;
885 break;
886 case 7:
887 c->modrm_ea += bx;
888 break;
889 }
890 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
891 (c->modrm_rm == 6 && c->modrm_mod != 0))
7a5b56df
AK		 892 if (!c->has_seg_override)
893 set_seg_override(c, VCPU_SREG_SS);
1c73ef66
AK		 894 c->modrm_ea = (u16)c->modrm_ea;
895 } else {
896 /* 32/64-bit ModR/M decode. */
84411d85 897 if ((c->modrm_rm & 7) == 4) {
1c73ef66
AK		 898 sib = insn_fetch(u8, 1, c->eip);
899 index_reg |= (sib >> 3) & 7;
900 base_reg |= sib & 7;
901 scale = sib >> 6;
902
dc71d0f1
AK		 903 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
904 c->modrm_ea += insn_fetch(s32, 4, c->eip);
905 else
1c73ef66 906 c->modrm_ea += c->regs[base_reg];
dc71d0f1 907 if (index_reg != 4)
1c73ef66 908 c->modrm_ea += c->regs[index_reg] << scale;
84411d85
AK		 909 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
910 if (ctxt->mode == X86EMUL_MODE_PROT64)
f5b4edcd 911 c->rip_relative = 1;
84411d85 912 } else
1c73ef66 913 c->modrm_ea += c->regs[c->modrm_rm];
1c73ef66
AK		 914 switch (c->modrm_mod) {
915 case 0:
916 if (c->modrm_rm == 5)
917 c->modrm_ea += insn_fetch(s32, 4, c->eip);
918 break;
919 case 1:
920 c->modrm_ea += insn_fetch(s8, 1, c->eip);
921 break;
922 case 2:
923 c->modrm_ea += insn_fetch(s32, 4, c->eip);
924 break;
925 }
926 }
1c73ef66
AK		 927done:
928 return rc;
929}
930
931static int decode_abs(struct x86_emulate_ctxt *ctxt,
932 struct x86_emulate_ops *ops)
933{
934 struct decode_cache *c = &ctxt->decode;
3e2815e9 935 int rc = X86EMUL_CONTINUE;
1c73ef66
AK		 936
937 switch (c->ad_bytes) {
938 case 2:
939 c->modrm_ea = insn_fetch(u16, 2, c->eip);
940 break;
941 case 4:
942 c->modrm_ea = insn_fetch(u32, 4, c->eip);
943 break;
944 case 8:
945 c->modrm_ea = insn_fetch(u64, 8, c->eip);
946 break;
947 }
948done:
949 return rc;
950}
951
6aa8b732 952int
8b4caf66 953x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
6aa8b732 954{
e4e03ded 955 struct decode_cache *c = &ctxt->decode;
3e2815e9 956 int rc = X86EMUL_CONTINUE;
6aa8b732 957 int mode = ctxt->mode;
e09d082c 958 int def_op_bytes, def_ad_bytes, group;
6aa8b732 959
6aa8b732 960
5cd21917
GN		 961 /* we cannot decode insn before we complete previous rep insn */
962 WARN_ON(ctxt->restart);
963
063db061 964 c->eip = ctxt->eip;
2fb53ad8 965 c->fetch.start = c->fetch.end = c->eip;
79168fd1 966 ctxt->cs_base = seg_base(ctxt, ops, VCPU_SREG_CS);
6aa8b732
AK		 967
968 switch (mode) {
969 case X86EMUL_MODE_REAL:
a0044755 970 case X86EMUL_MODE_VM86:
6aa8b732 971 case X86EMUL_MODE_PROT16:
f21b8bf4 972 def_op_bytes = def_ad_bytes = 2;
6aa8b732
AK		 973 break;
974 case X86EMUL_MODE_PROT32:
f21b8bf4 975 def_op_bytes = def_ad_bytes = 4;
6aa8b732 976 break;
05b3e0c2 977#ifdef CONFIG_X86_64
6aa8b732 978 case X86EMUL_MODE_PROT64:
f21b8bf4
AK		 979 def_op_bytes = 4;
980 def_ad_bytes = 8;
6aa8b732
AK		 981 break;
982#endif
983 default:
984 return -1;
985 }
986
f21b8bf4
AK		 987 c->op_bytes = def_op_bytes;
988 c->ad_bytes = def_ad_bytes;
989
6aa8b732 990 /* Legacy prefixes. */
b4c6abfe 991 for (;;) {
e4e03ded 992 switch (c->b = insn_fetch(u8, 1, c->eip)) {
6aa8b732 993 case 0x66: /* operand-size override */
f21b8bf4
AK		 994 /* switch between 2/4 bytes */
995 c->op_bytes = def_op_bytes ^ 6;
6aa8b732
AK		 996 break;
997 case 0x67: /* address-size override */
998 if (mode == X86EMUL_MODE_PROT64)
e4e03ded 999 /* switch between 4/8 bytes */
f21b8bf4 1000 c->ad_bytes = def_ad_bytes ^ 12;
6aa8b732 1001 else
e4e03ded 1002 /* switch between 2/4 bytes */
f21b8bf4 1003 c->ad_bytes = def_ad_bytes ^ 6;
6aa8b732 1004 break;
7a5b56df 1005 case 0x26: /* ES override */
6aa8b732 1006 case 0x2e: /* CS override */
7a5b56df 1007 case 0x36: /* SS override */
6aa8b732 1008 case 0x3e: /* DS override */
7a5b56df 1009 set_seg_override(c, (c->b >> 3) & 3);
6aa8b732
AK		 1010 break;
1011 case 0x64: /* FS override */
6aa8b732 1012 case 0x65: /* GS override */
7a5b56df 1013 set_seg_override(c, c->b & 7);
6aa8b732 1014 break;
b4c6abfe
LV		 1015 case 0x40 ... 0x4f: /* REX */
1016 if (mode != X86EMUL_MODE_PROT64)
1017 goto done_prefixes;
33615aa9 1018 c->rex_prefix = c->b;
b4c6abfe 1019 continue;
6aa8b732 1020 case 0xf0: /* LOCK */
e4e03ded 1021 c->lock_prefix = 1;
6aa8b732 1022 break;
ae6200ba 1023 case 0xf2: /* REPNE/REPNZ */
90e0a28f
GT		 1024 c->rep_prefix = REPNE_PREFIX;
1025 break;
6aa8b732 1026 case 0xf3: /* REP/REPE/REPZ */
90e0a28f 1027 c->rep_prefix = REPE_PREFIX;
6aa8b732 1028 break;
6aa8b732
AK		 1029 default:
1030 goto done_prefixes;
1031 }
b4c6abfe
LV		 1032
1033 /* Any legacy prefix after a REX prefix nullifies its effect. */
1034
33615aa9 1035 c->rex_prefix = 0;
6aa8b732
AK		 1036 }
1037
1038done_prefixes:
1039
1040 /* REX prefix. */
1c73ef66 1041 if (c->rex_prefix)
33615aa9 1042 if (c->rex_prefix & 8)
e4e03ded 1043 c->op_bytes = 8; /* REX.W */
6aa8b732
AK		 1044
1045 /* Opcode byte(s). */
e4e03ded
LV		 1046 c->d = opcode_table[c->b];
1047 if (c->d == 0) {
6aa8b732 1048 /* Two-byte opcode? */
e4e03ded
LV		 1049 if (c->b == 0x0f) {
1050 c->twobyte = 1;
1051 c->b = insn_fetch(u8, 1, c->eip);
1052 c->d = twobyte_table[c->b];
6aa8b732 1053 }
e09d082c 1054 }
6aa8b732 1055
e09d082c
AK		 1056 if (c->d & Group) {
1057 group = c->d & GroupMask;
1058 c->modrm = insn_fetch(u8, 1, c->eip);
1059 --c->eip;
1060
1061 group = (group << 3) + ((c->modrm >> 3) & 7);
1062 if ((c->d & GroupDual) && (c->modrm >> 6) == 3)
1063 c->d = group2_table[group];
1064 else
1065 c->d = group_table[group];
1066 }
1067
1068 /* Unrecognised? */
047a4818 1069 if (c->d == 0 || (c->d & Undefined)) {
e09d082c
AK		 1070 DPRINTF("Cannot emulate %02x\n", c->b);
1071 return -1;
6aa8b732
AK		 1072 }
1073
6e3d5dfb
AK		 1074 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
1075 c->op_bytes = 8;
1076
6aa8b732 1077 /* ModRM and SIB bytes. */
1c73ef66
AK		 1078 if (c->d & ModRM)
1079 rc = decode_modrm(ctxt, ops);
1080 else if (c->d & MemAbs)
1081 rc = decode_abs(ctxt, ops);
3e2815e9 1082 if (rc != X86EMUL_CONTINUE)
1c73ef66 1083 goto done;
6aa8b732 1084
7a5b56df
AK		 1085 if (!c->has_seg_override)
1086 set_seg_override(c, VCPU_SREG_DS);
c7e75a3d 1087
7a5b56df 1088 if (!(!c->twobyte && c->b == 0x8d))
79168fd1 1089 c->modrm_ea += seg_override_base(ctxt, ops, c);
c7e75a3d
AK		 1090
1091 if (c->ad_bytes != 8)
1092 c->modrm_ea = (u32)c->modrm_ea;
69f55cb1
GN		 1093
1094 if (c->rip_relative)
1095 c->modrm_ea += c->eip;
1096
6aa8b732
AK		 1097 /*
1098 * Decode and fetch the source operand: register, memory
1099 * or immediate.
1100 */
e4e03ded 1101 switch (c->d & SrcMask) {
6aa8b732
AK		 1102 case SrcNone:
1103 break;
1104 case SrcReg:
9f1ef3f8 1105 decode_register_operand(&c->src, c, 0);
6aa8b732
AK		 1106 break;
1107 case SrcMem16:
e4e03ded 1108 c->src.bytes = 2;
6aa8b732
AK		 1109 goto srcmem_common;
1110 case SrcMem32:
e4e03ded 1111 c->src.bytes = 4;
6aa8b732
AK		 1112 goto srcmem_common;
1113 case SrcMem:
e4e03ded
LV		 1114 c->src.bytes = (c->d & ByteOp) ? 1 :
1115 c->op_bytes;
b85b9ee9 1116 /* Don't fetch the address for invlpg: it could be unmapped. */
d77c26fc 1117 if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7)
b85b9ee9 1118 break;
d77c26fc 1119 srcmem_common:
4e62417b
AJ		 1120 /*
1121 * For instructions with a ModR/M byte, switch to register
1122 * access if Mod = 3.
1123 */
e4e03ded
LV		 1124 if ((c->d & ModRM) && c->modrm_mod == 3) {
1125 c->src.type = OP_REG;
66b85505 1126 c->src.val = c->modrm_val;
107d6d2e 1127 c->src.ptr = c->modrm_ptr;
4e62417b
AJ		 1128 break;
1129 }
e4e03ded 1130 c->src.type = OP_MEM;
69f55cb1
GN		 1131 c->src.ptr = (unsigned long *)c->modrm_ea;
1132 c->src.val = 0;
6aa8b732
AK		 1133 break;
1134 case SrcImm:
c9eaf20f 1135 case SrcImmU:
e4e03ded
LV		 1136 c->src.type = OP_IMM;
1137 c->src.ptr = (unsigned long *)c->eip;
1138 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1139 if (c->src.bytes == 8)
1140 c->src.bytes = 4;
6aa8b732 1141 /* NB. Immediates are sign-extended as necessary. */
e4e03ded 1142 switch (c->src.bytes) {
6aa8b732 1143 case 1:
e4e03ded 1144 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 1145 break;
1146 case 2:
e4e03ded 1147 c->src.val = insn_fetch(s16, 2, c->eip);
6aa8b732
AK		 1148 break;
1149 case 4:
e4e03ded 1150 c->src.val = insn_fetch(s32, 4, c->eip);
6aa8b732
AK		 1151 break;
1152 }
c9eaf20f
AK		 1153 if ((c->d & SrcMask) == SrcImmU) {
1154 switch (c->src.bytes) {
1155 case 1:
1156 c->src.val &= 0xff;
1157 break;
1158 case 2:
1159 c->src.val &= 0xffff;
1160 break;
1161 case 4:
1162 c->src.val &= 0xffffffff;
1163 break;
1164 }
1165 }
6aa8b732
AK		 1166 break;
1167 case SrcImmByte:
341de7e3 1168 case SrcImmUByte:
e4e03ded
LV		 1169 c->src.type = OP_IMM;
1170 c->src.ptr = (unsigned long *)c->eip;
1171 c->src.bytes = 1;
341de7e3
GN		 1172 if ((c->d & SrcMask) == SrcImmByte)
1173 c->src.val = insn_fetch(s8, 1, c->eip);
1174 else
1175 c->src.val = insn_fetch(u8, 1, c->eip);
6aa8b732 1176 break;
5d55f299
WY		 1177 case SrcAcc:
1178 c->src.type = OP_REG;
1179 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1180 c->src.ptr = &c->regs[VCPU_REGS_RAX];
1181 switch (c->src.bytes) {
1182 case 1:
1183 c->src.val = *(u8 *)c->src.ptr;
1184 break;
1185 case 2:
1186 c->src.val = *(u16 *)c->src.ptr;
1187 break;
1188 case 4:
1189 c->src.val = *(u32 *)c->src.ptr;
1190 break;
1191 case 8:
1192 c->src.val = *(u64 *)c->src.ptr;
1193 break;
1194 }
1195 break;
bfcadf83
GT		 1196 case SrcOne:
1197 c->src.bytes = 1;
1198 c->src.val = 1;
1199 break;
a682e354
GN		 1200 case SrcSI:
1201 c->src.type = OP_MEM;
1202 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1203 c->src.ptr = (unsigned long *)
79168fd1 1204 register_address(c, seg_override_base(ctxt, ops, c),
a682e354
GN		 1205 c->regs[VCPU_REGS_RSI]);
1206 c->src.val = 0;
1207 break;
414e6277
GN		 1208 case SrcImmFAddr:
1209 c->src.type = OP_IMM;
1210 c->src.ptr = (unsigned long *)c->eip;
1211 c->src.bytes = c->op_bytes + 2;
1212 insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip);
1213 break;
1214 case SrcMemFAddr:
1215 c->src.type = OP_MEM;
1216 c->src.ptr = (unsigned long *)c->modrm_ea;
1217 c->src.bytes = c->op_bytes + 2;
1218 break;
6aa8b732
AK		 1219 }
1220
0dc8d10f
GT		 1221 /*
1222 * Decode and fetch the second source operand: register, memory
1223 * or immediate.
1224 */
1225 switch (c->d & Src2Mask) {
1226 case Src2None:
1227 break;
1228 case Src2CL:
1229 c->src2.bytes = 1;
1230 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
1231 break;
1232 case Src2ImmByte:
1233 c->src2.type = OP_IMM;
1234 c->src2.ptr = (unsigned long *)c->eip;
1235 c->src2.bytes = 1;
1236 c->src2.val = insn_fetch(u8, 1, c->eip);
1237 break;
1238 case Src2One:
1239 c->src2.bytes = 1;
1240 c->src2.val = 1;
1241 break;
1242 }
1243
038e51de 1244 /* Decode and fetch the destination operand: register or memory. */
e4e03ded 1245 switch (c->d & DstMask) {
038e51de
AK		 1246 case ImplicitOps:
1247 /* Special instructions do their own operand decoding. */
8b4caf66 1248 return 0;
038e51de 1249 case DstReg:
9f1ef3f8 1250 decode_register_operand(&c->dst, c,
3c118e24 1251 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
038e51de
AK		 1252 break;
1253 case DstMem:
6550e1f1 1254 case DstMem64:
e4e03ded 1255 if ((c->d & ModRM) && c->modrm_mod == 3) {
89c69638 1256 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4e03ded 1257 c->dst.type = OP_REG;
66b85505 1258 c->dst.val = c->dst.orig_val = c->modrm_val;
107d6d2e 1259 c->dst.ptr = c->modrm_ptr;
4e62417b
AJ		 1260 break;
1261 }
8b4caf66 1262 c->dst.type = OP_MEM;
69f55cb1 1263 c->dst.ptr = (unsigned long *)c->modrm_ea;
6550e1f1
GN		 1264 if ((c->d & DstMask) == DstMem64)
1265 c->dst.bytes = 8;
1266 else
1267 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
69f55cb1
GN		 1268 c->dst.val = 0;
1269 if (c->d & BitOp) {
1270 unsigned long mask = ~(c->dst.bytes * 8 - 1);
1271
1272 c->dst.ptr = (void *)c->dst.ptr +
1273 (c->src.val & mask) / 8;
1274 }
8b4caf66 1275 break;
9c9fddd0
GT		 1276 case DstAcc:
1277 c->dst.type = OP_REG;
d6d367d6 1278 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
9c9fddd0 1279 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
d6d367d6 1280 switch (c->dst.bytes) {
9c9fddd0
GT		 1281 case 1:
1282 c->dst.val = *(u8 *)c->dst.ptr;
1283 break;
1284 case 2:
1285 c->dst.val = *(u16 *)c->dst.ptr;
1286 break;
1287 case 4:
1288 c->dst.val = *(u32 *)c->dst.ptr;
1289 break;
d6d367d6
GN		 1290 case 8:
1291 c->dst.val = *(u64 *)c->dst.ptr;
1292 break;
9c9fddd0
GT		 1293 }
1294 c->dst.orig_val = c->dst.val;
1295 break;
a682e354
GN		 1296 case DstDI:
1297 c->dst.type = OP_MEM;
1298 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1299 c->dst.ptr = (unsigned long *)
79168fd1 1300 register_address(c, es_base(ctxt, ops),
a682e354
GN		 1301 c->regs[VCPU_REGS_RDI]);
1302 c->dst.val = 0;
1303 break;
8b4caf66
LV		 1304 }
1305
1306done:
1307 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
1308}
1309
9de41573
GN		 1310static int read_emulated(struct x86_emulate_ctxt *ctxt,
1311 struct x86_emulate_ops *ops,
1312 unsigned long addr, void *dest, unsigned size)
1313{
1314 int rc;
1315 struct read_cache *mc = &ctxt->decode.mem_read;
8fe681e9 1316 u32 err;
9de41573
GN		 1317
1318 while (size) {
1319 int n = min(size, 8u);
1320 size -= n;
1321 if (mc->pos < mc->end)
1322 goto read_cached;
1323
8fe681e9
GN		 1324 rc = ops->read_emulated(addr, mc->data + mc->end, n, &err,
1325 ctxt->vcpu);
1326 if (rc == X86EMUL_PROPAGATE_FAULT)
54b8486f 1327 emulate_pf(ctxt, addr, err);
9de41573
GN		 1328 if (rc != X86EMUL_CONTINUE)
1329 return rc;
1330 mc->end += n;
1331
1332 read_cached:
1333 memcpy(dest, mc->data + mc->pos, n);
1334 mc->pos += n;
1335 dest += n;
1336 addr += n;
1337 }
1338 return X86EMUL_CONTINUE;
1339}
1340
7b262e90
GN		 1341static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
1342 struct x86_emulate_ops *ops,
1343 unsigned int size, unsigned short port,
1344 void *dest)
1345{
1346 struct read_cache *rc = &ctxt->decode.io_read;
1347
1348 if (rc->pos == rc->end) { /* refill pio read ahead */
1349 struct decode_cache *c = &ctxt->decode;
1350 unsigned int in_page, n;
1351 unsigned int count = c->rep_prefix ?
1352 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1;
1353 in_page = (ctxt->eflags & EFLG_DF) ?
1354 offset_in_page(c->regs[VCPU_REGS_RDI]) :
1355 PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]);
1356 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1357 count);
1358 if (n == 0)
1359 n = 1;
1360 rc->pos = rc->end = 0;
1361 if (!ops->pio_in_emulated(size, port, rc->data, n, ctxt->vcpu))
1362 return 0;
1363 rc->end = n * size;
1364 }
1365
1366 memcpy(dest, rc->data + rc->pos, size);
1367 rc->pos += size;
1368 return 1;
1369}
1370
38ba30ba
GN		 1371static u32 desc_limit_scaled(struct desc_struct *desc)
1372{
1373 u32 limit = get_desc_limit(desc);
1374
1375 return desc->g ? (limit << 12) | 0xfff : limit;
1376}
1377
1378static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
1379 struct x86_emulate_ops *ops,
1380 u16 selector, struct desc_ptr *dt)
1381{
1382 if (selector & 1 << 2) {
1383 struct desc_struct desc;
1384 memset (dt, 0, sizeof *dt);
1385 if (!ops->get_cached_descriptor(&desc, VCPU_SREG_LDTR, ctxt->vcpu))
1386 return;
1387
1388 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1389 dt->address = get_desc_base(&desc);
1390 } else
1391 ops->get_gdt(dt, ctxt->vcpu);
1392}
1393
1394/* allowed just for 8 bytes segments */
1395static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1396 struct x86_emulate_ops *ops,
1397 u16 selector, struct desc_struct *desc)
1398{
1399 struct desc_ptr dt;
1400 u16 index = selector >> 3;
1401 int ret;
1402 u32 err;
1403 ulong addr;
1404
1405 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
1406
1407 if (dt.size < index * 8 + 7) {
54b8486f 1408 emulate_gp(ctxt, selector & 0xfffc);
38ba30ba
GN		 1409 return X86EMUL_PROPAGATE_FAULT;
1410 }
1411 addr = dt.address + index * 8;
1412 ret = ops->read_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
1413 if (ret == X86EMUL_PROPAGATE_FAULT)
54b8486f 1414 emulate_pf(ctxt, addr, err);
38ba30ba
GN		 1415
1416 return ret;
1417}
1418
1419/* allowed just for 8 bytes segments */
1420static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1421 struct x86_emulate_ops *ops,
1422 u16 selector, struct desc_struct *desc)
1423{
1424 struct desc_ptr dt;
1425 u16 index = selector >> 3;
1426 u32 err;
1427 ulong addr;
1428 int ret;
1429
1430 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
1431
1432 if (dt.size < index * 8 + 7) {
54b8486f 1433 emulate_gp(ctxt, selector & 0xfffc);
38ba30ba
GN		 1434 return X86EMUL_PROPAGATE_FAULT;
1435 }
1436
1437 addr = dt.address + index * 8;
1438 ret = ops->write_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
1439 if (ret == X86EMUL_PROPAGATE_FAULT)
54b8486f 1440 emulate_pf(ctxt, addr, err);
38ba30ba
GN		 1441
1442 return ret;
1443}
1444
1445static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1446 struct x86_emulate_ops *ops,
1447 u16 selector, int seg)
1448{
1449 struct desc_struct seg_desc;
1450 u8 dpl, rpl, cpl;
1451 unsigned err_vec = GP_VECTOR;
1452 u32 err_code = 0;
1453 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1454 int ret;
1455
1456 memset(&seg_desc, 0, sizeof seg_desc);
1457
1458 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1459 || ctxt->mode == X86EMUL_MODE_REAL) {
1460 /* set real mode segment descriptor */
1461 set_desc_base(&seg_desc, selector << 4);
1462 set_desc_limit(&seg_desc, 0xffff);
1463 seg_desc.type = 3;
1464 seg_desc.p = 1;
1465 seg_desc.s = 1;
1466 goto load;
1467 }
1468
1469 /* NULL selector is not valid for TR, CS and SS */
1470 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
1471 && null_selector)
1472 goto exception;
1473
1474 /* TR should be in GDT only */
1475 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1476 goto exception;
1477
1478 if (null_selector) /* for NULL selector skip all following checks */
1479 goto load;
1480
1481 ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc);
1482 if (ret != X86EMUL_CONTINUE)
1483 return ret;
1484
1485 err_code = selector & 0xfffc;
1486 err_vec = GP_VECTOR;
1487
1488 /* can't load system descriptor into segment selecor */
1489 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1490 goto exception;
1491
1492 if (!seg_desc.p) {
1493 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1494 goto exception;
1495 }
1496
1497 rpl = selector & 3;
1498 dpl = seg_desc.dpl;
1499 cpl = ops->cpl(ctxt->vcpu);
1500
1501 switch (seg) {
1502 case VCPU_SREG_SS:
1503 /*
1504 * segment is not a writable data segment or segment
1505 * selector's RPL != CPL or segment selector's RPL != CPL
1506 */
1507 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1508 goto exception;
1509 break;
1510 case VCPU_SREG_CS:
1511 if (!(seg_desc.type & 8))
1512 goto exception;
1513
1514 if (seg_desc.type & 4) {
1515 /* conforming */
1516 if (dpl > cpl)
1517 goto exception;
1518 } else {
1519 /* nonconforming */
1520 if (rpl > cpl || dpl != cpl)
1521 goto exception;
1522 }
1523 /* CS(RPL) <- CPL */
1524 selector = (selector & 0xfffc) | cpl;
1525 break;
1526 case VCPU_SREG_TR:
1527 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1528 goto exception;
1529 break;
1530 case VCPU_SREG_LDTR:
1531 if (seg_desc.s || seg_desc.type != 2)
1532 goto exception;
1533 break;
1534 default: /* DS, ES, FS, or GS */
1535 /*
1536 * segment is not a data or readable code segment or
1537 * ((segment is a data or nonconforming code segment)
1538 * and (both RPL and CPL > DPL))
1539 */
1540 if ((seg_desc.type & 0xa) == 0x8 ||
1541 (((seg_desc.type & 0xc) != 0xc) &&
1542 (rpl > dpl && cpl > dpl)))
1543 goto exception;
1544 break;
1545 }
1546
1547 if (seg_desc.s) {
1548 /* mark segment as accessed */
1549 seg_desc.type |= 1;
1550 ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc);
1551 if (ret != X86EMUL_CONTINUE)
1552 return ret;
1553 }
1554load:
1555 ops->set_segment_selector(selector, seg, ctxt->vcpu);
1556 ops->set_cached_descriptor(&seg_desc, seg, ctxt->vcpu);
1557 return X86EMUL_CONTINUE;
1558exception:
54b8486f 1559 emulate_exception(ctxt, err_vec, err_code, true);
38ba30ba
GN		 1560 return X86EMUL_PROPAGATE_FAULT;
1561}
1562
c37eda13
WY		 1563static inline int writeback(struct x86_emulate_ctxt *ctxt,
1564 struct x86_emulate_ops *ops)
1565{
1566 int rc;
1567 struct decode_cache *c = &ctxt->decode;
1568 u32 err;
1569
1570 switch (c->dst.type) {
1571 case OP_REG:
1572 /* The 4-byte case *is* correct:
1573 * in 64-bit mode we zero-extend.
1574 */
1575 switch (c->dst.bytes) {
1576 case 1:
1577 *(u8 *)c->dst.ptr = (u8)c->dst.val;
1578 break;
1579 case 2:
1580 *(u16 *)c->dst.ptr = (u16)c->dst.val;
1581 break;
1582 case 4:
1583 *c->dst.ptr = (u32)c->dst.val;
1584 break; /* 64b: zero-ext */
1585 case 8:
1586 *c->dst.ptr = c->dst.val;
1587 break;
1588 }
1589 break;
1590 case OP_MEM:
1591 if (c->lock_prefix)
1592 rc = ops->cmpxchg_emulated(
1593 (unsigned long)c->dst.ptr,
1594 &c->dst.orig_val,
1595 &c->dst.val,
1596 c->dst.bytes,
1597 &err,
1598 ctxt->vcpu);
1599 else
1600 rc = ops->write_emulated(
1601 (unsigned long)c->dst.ptr,
1602 &c->dst.val,
1603 c->dst.bytes,
1604 &err,
1605 ctxt->vcpu);
1606 if (rc == X86EMUL_PROPAGATE_FAULT)
1607 emulate_pf(ctxt,
1608 (unsigned long)c->dst.ptr, err);
1609 if (rc != X86EMUL_CONTINUE)
1610 return rc;
1611 break;
1612 case OP_NONE:
1613 /* no writeback */
1614 break;
1615 default:
1616 break;
1617 }
1618 return X86EMUL_CONTINUE;
1619}
1620
79168fd1
GN		 1621static inline void emulate_push(struct x86_emulate_ctxt *ctxt,
1622 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1623{
1624 struct decode_cache *c = &ctxt->decode;
1625
1626 c->dst.type = OP_MEM;
1627 c->dst.bytes = c->op_bytes;
1628 c->dst.val = c->src.val;
7a957275 1629 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
79168fd1 1630 c->dst.ptr = (void *) register_address(c, ss_base(ctxt, ops),
8cdbd2c9
LV		 1631 c->regs[VCPU_REGS_RSP]);
1632}
1633
faa5a3ae 1634static int emulate_pop(struct x86_emulate_ctxt *ctxt,
350f69dc
AK		 1635 struct x86_emulate_ops *ops,
1636 void *dest, int len)
8cdbd2c9
LV		 1637{
1638 struct decode_cache *c = &ctxt->decode;
1639 int rc;
1640
79168fd1 1641 rc = read_emulated(ctxt, ops, register_address(c, ss_base(ctxt, ops),
9de41573
GN		 1642 c->regs[VCPU_REGS_RSP]),
1643 dest, len);
b60d513c 1644 if (rc != X86EMUL_CONTINUE)
8cdbd2c9
LV		 1645 return rc;
1646
350f69dc 1647 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
faa5a3ae
AK		 1648 return rc;
1649}
8cdbd2c9 1650
d4c6a154
GN		 1651static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1652 struct x86_emulate_ops *ops,
1653 void *dest, int len)
1654{
1655 int rc;
1656 unsigned long val, change_mask;
1657 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
9c537244 1658 int cpl = ops->cpl(ctxt->vcpu);
d4c6a154
GN		 1659
1660 rc = emulate_pop(ctxt, ops, &val, len);
1661 if (rc != X86EMUL_CONTINUE)
1662 return rc;
1663
1664 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1665 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
1666
1667 switch(ctxt->mode) {
1668 case X86EMUL_MODE_PROT64:
1669 case X86EMUL_MODE_PROT32:
1670 case X86EMUL_MODE_PROT16:
1671 if (cpl == 0)
1672 change_mask |= EFLG_IOPL;
1673 if (cpl <= iopl)
1674 change_mask |= EFLG_IF;
1675 break;
1676 case X86EMUL_MODE_VM86:
1677 if (iopl < 3) {
54b8486f 1678 emulate_gp(ctxt, 0);
d4c6a154
GN		 1679 return X86EMUL_PROPAGATE_FAULT;
1680 }
1681 change_mask |= EFLG_IF;
1682 break;
1683 default: /* real mode */
1684 change_mask |= (EFLG_IOPL | EFLG_IF);
1685 break;
1686 }
1687
1688 *(unsigned long *)dest =
1689 (ctxt->eflags & ~change_mask) | (val & change_mask);
1690
1691 return rc;
1692}
1693
79168fd1
GN		 1694static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt,
1695 struct x86_emulate_ops *ops, int seg)
0934ac9d
MG		 1696{
1697 struct decode_cache *c = &ctxt->decode;
0934ac9d 1698
79168fd1 1699 c->src.val = ops->get_segment_selector(seg, ctxt->vcpu);
0934ac9d 1700
79168fd1 1701 emulate_push(ctxt, ops);
0934ac9d
MG		 1702}
1703
1704static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
1705 struct x86_emulate_ops *ops, int seg)
1706{
1707 struct decode_cache *c = &ctxt->decode;
1708 unsigned long selector;
1709 int rc;
1710
1711 rc = emulate_pop(ctxt, ops, &selector, c->op_bytes);
1b30eaa8 1712 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 1713 return rc;
1714
2e873022 1715 rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg);
0934ac9d
MG		 1716 return rc;
1717}
1718
c37eda13 1719static int emulate_pusha(struct x86_emulate_ctxt *ctxt,
79168fd1 1720 struct x86_emulate_ops *ops)
abcf14b5
MG		 1721{
1722 struct decode_cache *c = &ctxt->decode;
1723 unsigned long old_esp = c->regs[VCPU_REGS_RSP];
c37eda13 1724 int rc = X86EMUL_CONTINUE;
abcf14b5
MG		 1725 int reg = VCPU_REGS_RAX;
1726
1727 while (reg <= VCPU_REGS_RDI) {
1728 (reg == VCPU_REGS_RSP) ?
1729 (c->src.val = old_esp) : (c->src.val = c->regs[reg]);
1730
79168fd1 1731 emulate_push(ctxt, ops);
c37eda13
WY		 1732
1733 rc = writeback(ctxt, ops);
1734 if (rc != X86EMUL_CONTINUE)
1735 return rc;
1736
abcf14b5
MG		 1737 ++reg;
1738 }
c37eda13
WY		 1739
1740 /* Disable writeback. */
1741 c->dst.type = OP_NONE;
1742
1743 return rc;
abcf14b5
MG		 1744}
1745
1746static int emulate_popa(struct x86_emulate_ctxt *ctxt,
1747 struct x86_emulate_ops *ops)
1748{
1749 struct decode_cache *c = &ctxt->decode;
1b30eaa8 1750 int rc = X86EMUL_CONTINUE;
abcf14b5
MG		 1751 int reg = VCPU_REGS_RDI;
1752
1753 while (reg >= VCPU_REGS_RAX) {
1754 if (reg == VCPU_REGS_RSP) {
1755 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1756 c->op_bytes);
1757 --reg;
1758 }
1759
1760 rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes);
1b30eaa8 1761 if (rc != X86EMUL_CONTINUE)
abcf14b5
MG		 1762 break;
1763 --reg;
1764 }
1765 return rc;
1766}
1767
faa5a3ae
AK		 1768static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1769 struct x86_emulate_ops *ops)
1770{
1771 struct decode_cache *c = &ctxt->decode;
faa5a3ae 1772
1b30eaa8 1773 return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
8cdbd2c9
LV		 1774}
1775
05f086f8 1776static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1777{
05f086f8 1778 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1779 switch (c->modrm_reg) {
1780 case 0: /* rol */
05f086f8 1781 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1782 break;
1783 case 1: /* ror */
05f086f8 1784 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1785 break;
1786 case 2: /* rcl */
05f086f8 1787 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1788 break;
1789 case 3: /* rcr */
05f086f8 1790 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1791 break;
1792 case 4: /* sal/shl */
1793 case 6: /* sal/shl */
05f086f8 1794 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1795 break;
1796 case 5: /* shr */
05f086f8 1797 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1798 break;
1799 case 7: /* sar */
05f086f8 1800 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1801 break;
1802 }
1803}
1804
1805static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 1806 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1807{
1808 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1809
1810 switch (c->modrm_reg) {
1811 case 0 ... 1: /* test */
05f086f8 1812 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1813 break;
1814 case 2: /* not */
1815 c->dst.val = ~c->dst.val;
1816 break;
1817 case 3: /* neg */
05f086f8 1818 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1819 break;
1820 default:
aca06a83 1821 return 0;
8cdbd2c9 1822 }
aca06a83 1823 return 1;
8cdbd2c9
LV		 1824}
1825
1826static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
a01af5ec 1827 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1828{
1829 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1830
1831 switch (c->modrm_reg) {
1832 case 0: /* inc */
05f086f8 1833 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1834 break;
1835 case 1: /* dec */
05f086f8 1836 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9 1837 break;
d19292e4
MG		 1838 case 2: /* call near abs */ {
1839 long int old_eip;
1840 old_eip = c->eip;
1841 c->eip = c->src.val;
1842 c->src.val = old_eip;
79168fd1 1843 emulate_push(ctxt, ops);
d19292e4
MG		 1844 break;
1845 }
8cdbd2c9 1846 case 4: /* jmp abs */
fd60754e 1847 c->eip = c->src.val;
8cdbd2c9
LV		 1848 break;
1849 case 6: /* push */
79168fd1 1850 emulate_push(ctxt, ops);
8cdbd2c9 1851 break;
8cdbd2c9 1852 }
1b30eaa8 1853 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1854}
1855
1856static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
69f55cb1 1857 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1858{
1859 struct decode_cache *c = &ctxt->decode;
16518d5a 1860 u64 old = c->dst.orig_val64;
8cdbd2c9
LV		 1861
1862 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1863 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
8cdbd2c9
LV		 1864 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1865 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1866 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 1867 } else {
16518d5a
AK		 1868 c->dst.val64 = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1869 (u32) c->regs[VCPU_REGS_RBX];
8cdbd2c9 1870
05f086f8 1871 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 1872 }
1b30eaa8 1873 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1874}
1875
a77ab5ea
AK		 1876static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1877 struct x86_emulate_ops *ops)
1878{
1879 struct decode_cache *c = &ctxt->decode;
1880 int rc;
1881 unsigned long cs;
1882
1883 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1b30eaa8 1884 if (rc != X86EMUL_CONTINUE)
a77ab5ea
AK		 1885 return rc;
1886 if (c->op_bytes == 4)
1887 c->eip = (u32)c->eip;
1888 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1b30eaa8 1889 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1890 return rc;
2e873022 1891 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 1892 return rc;
1893}
1894
e66bb2cc
AP		 1895static inline void
1896setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
79168fd1
GN		 1897 struct x86_emulate_ops *ops, struct desc_struct *cs,
1898 struct desc_struct *ss)
e66bb2cc 1899{
79168fd1
GN		 1900 memset(cs, 0, sizeof(struct desc_struct));
1901 ops->get_cached_descriptor(cs, VCPU_SREG_CS, ctxt->vcpu);
1902 memset(ss, 0, sizeof(struct desc_struct));
e66bb2cc
AP		 1903
1904 cs->l = 0; /* will be adjusted later */
79168fd1 1905 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 1906 cs->g = 1; /* 4kb granularity */
79168fd1 1907 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1908 cs->type = 0x0b; /* Read, Execute, Accessed */
1909 cs->s = 1;
1910 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 1911 cs->p = 1;
1912 cs->d = 1;
e66bb2cc 1913
79168fd1
GN		 1914 set_desc_base(ss, 0); /* flat segment */
1915 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1916 ss->g = 1; /* 4kb granularity */
1917 ss->s = 1;
1918 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 1919 ss->d = 1; /* 32bit stack segment */
e66bb2cc 1920 ss->dpl = 0;
79168fd1 1921 ss->p = 1;
e66bb2cc
AP		 1922}
1923
1924static int
3fb1b5db 1925emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
e66bb2cc
AP		 1926{
1927 struct decode_cache *c = &ctxt->decode;
79168fd1 1928 struct desc_struct cs, ss;
e66bb2cc 1929 u64 msr_data;
79168fd1 1930 u16 cs_sel, ss_sel;
e66bb2cc
AP		 1931
1932 /* syscall is not available in real mode */
2e901c4c
GN		 1933 if (ctxt->mode == X86EMUL_MODE_REAL ||
1934 ctxt->mode == X86EMUL_MODE_VM86) {
54b8486f 1935 emulate_ud(ctxt);
2e901c4c
GN		 1936 return X86EMUL_PROPAGATE_FAULT;
1937 }
e66bb2cc 1938
79168fd1 1939 setup_syscalls_segments(ctxt, ops, &cs, &ss);
e66bb2cc 1940
3fb1b5db 1941 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
e66bb2cc 1942 msr_data >>= 32;
79168fd1
GN		 1943 cs_sel = (u16)(msr_data & 0xfffc);
1944 ss_sel = (u16)(msr_data + 8);
e66bb2cc
AP		 1945
1946 if (is_long_mode(ctxt->vcpu)) {
79168fd1 1947 cs.d = 0;
e66bb2cc
AP		 1948 cs.l = 1;
1949 }
79168fd1
GN		 1950 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
1951 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
1952 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
1953 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
e66bb2cc
AP		 1954
1955 c->regs[VCPU_REGS_RCX] = c->eip;
1956 if (is_long_mode(ctxt->vcpu)) {
1957#ifdef CONFIG_X86_64
1958 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
1959
3fb1b5db
GN		 1960 ops->get_msr(ctxt->vcpu,
1961 ctxt->mode == X86EMUL_MODE_PROT64 ?
1962 MSR_LSTAR : MSR_CSTAR, &msr_data);
e66bb2cc
AP		 1963 c->eip = msr_data;
1964
3fb1b5db 1965 ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 1966 ctxt->eflags &= ~(msr_data | EFLG_RF);
1967#endif
1968 } else {
1969 /* legacy mode */
3fb1b5db 1970 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
e66bb2cc
AP		 1971 c->eip = (u32)msr_data;
1972
1973 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1974 }
1975
e54cfa97 1976 return X86EMUL_CONTINUE;
e66bb2cc
AP		 1977}
1978
8c604352 1979static int
3fb1b5db 1980emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8c604352
AP		 1981{
1982 struct decode_cache *c = &ctxt->decode;
79168fd1 1983 struct desc_struct cs, ss;
8c604352 1984 u64 msr_data;
79168fd1 1985 u16 cs_sel, ss_sel;
8c604352 1986
a0044755
GN		 1987 /* inject #GP if in real mode */
1988 if (ctxt->mode == X86EMUL_MODE_REAL) {
54b8486f 1989 emulate_gp(ctxt, 0);
2e901c4c 1990 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 1991 }
1992
1993 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1994 * Therefore, we inject an #UD.
1995 */
2e901c4c 1996 if (ctxt->mode == X86EMUL_MODE_PROT64) {
54b8486f 1997 emulate_ud(ctxt);
2e901c4c
GN		 1998 return X86EMUL_PROPAGATE_FAULT;
1999 }
8c604352 2000
79168fd1 2001 setup_syscalls_segments(ctxt, ops, &cs, &ss);
8c604352 2002
3fb1b5db 2003 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2004 switch (ctxt->mode) {
2005 case X86EMUL_MODE_PROT32:
2006 if ((msr_data & 0xfffc) == 0x0) {
54b8486f 2007 emulate_gp(ctxt, 0);
e54cfa97 2008 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 2009 }
2010 break;
2011 case X86EMUL_MODE_PROT64:
2012 if (msr_data == 0x0) {
54b8486f 2013 emulate_gp(ctxt, 0);
e54cfa97 2014 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 2015 }
2016 break;
2017 }
2018
2019 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 2020 cs_sel = (u16)msr_data;
2021 cs_sel &= ~SELECTOR_RPL_MASK;
2022 ss_sel = cs_sel + 8;
2023 ss_sel &= ~SELECTOR_RPL_MASK;
8c604352
AP		 2024 if (ctxt->mode == X86EMUL_MODE_PROT64
2025 || is_long_mode(ctxt->vcpu)) {
79168fd1 2026 cs.d = 0;
8c604352
AP		 2027 cs.l = 1;
2028 }
2029
79168fd1
GN		 2030 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
2031 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
2032 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
2033 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
8c604352 2034
3fb1b5db 2035 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data);
8c604352
AP		 2036 c->eip = msr_data;
2037
3fb1b5db 2038 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data);
8c604352
AP		 2039 c->regs[VCPU_REGS_RSP] = msr_data;
2040
e54cfa97 2041 return X86EMUL_CONTINUE;
8c604352
AP		 2042}
2043
4668f050 2044static int
3fb1b5db 2045emulate_sysexit(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
4668f050
AP		 2046{
2047 struct decode_cache *c = &ctxt->decode;
79168fd1 2048 struct desc_struct cs, ss;
4668f050
AP		 2049 u64 msr_data;
2050 int usermode;
79168fd1 2051 u16 cs_sel, ss_sel;
4668f050 2052
a0044755
GN		 2053 /* inject #GP if in real mode or Virtual 8086 mode */
2054 if (ctxt->mode == X86EMUL_MODE_REAL ||
2055 ctxt->mode == X86EMUL_MODE_VM86) {
54b8486f 2056 emulate_gp(ctxt, 0);
2e901c4c 2057 return X86EMUL_PROPAGATE_FAULT;
4668f050
AP		 2058 }
2059
79168fd1 2060 setup_syscalls_segments(ctxt, ops, &cs, &ss);
4668f050
AP		 2061
2062 if ((c->rex_prefix & 0x8) != 0x0)
2063 usermode = X86EMUL_MODE_PROT64;
2064 else
2065 usermode = X86EMUL_MODE_PROT32;
2066
2067 cs.dpl = 3;
2068 ss.dpl = 3;
3fb1b5db 2069 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2070 switch (usermode) {
2071 case X86EMUL_MODE_PROT32:
79168fd1 2072 cs_sel = (u16)(msr_data + 16);
4668f050 2073 if ((msr_data & 0xfffc) == 0x0) {
54b8486f 2074 emulate_gp(ctxt, 0);
e54cfa97 2075 return X86EMUL_PROPAGATE_FAULT;
4668f050 2076 }
79168fd1 2077 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2078 break;
2079 case X86EMUL_MODE_PROT64:
79168fd1 2080 cs_sel = (u16)(msr_data + 32);
4668f050 2081 if (msr_data == 0x0) {
54b8486f 2082 emulate_gp(ctxt, 0);
e54cfa97 2083 return X86EMUL_PROPAGATE_FAULT;
4668f050 2084 }
79168fd1
GN		 2085 ss_sel = cs_sel + 8;
2086 cs.d = 0;
4668f050
AP		 2087 cs.l = 1;
2088 break;
2089 }
79168fd1
GN		 2090 cs_sel |= SELECTOR_RPL_MASK;
2091 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2092
79168fd1
GN		 2093 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
2094 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
2095 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
2096 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
4668f050 2097
bdb475a3
GN		 2098 c->eip = c->regs[VCPU_REGS_RDX];
2099 c->regs[VCPU_REGS_RSP] = c->regs[VCPU_REGS_RCX];
4668f050 2100
e54cfa97 2101 return X86EMUL_CONTINUE;
4668f050
AP		 2102}
2103
9c537244
GN		 2104static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt,
2105 struct x86_emulate_ops *ops)
f850e2e6
GN		 2106{
2107 int iopl;
2108 if (ctxt->mode == X86EMUL_MODE_REAL)
2109 return false;
2110 if (ctxt->mode == X86EMUL_MODE_VM86)
2111 return true;
2112 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
9c537244 2113 return ops->cpl(ctxt->vcpu) > iopl;
f850e2e6
GN		 2114}
2115
2116static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
2117 struct x86_emulate_ops *ops,
2118 u16 port, u16 len)
2119{
79168fd1 2120 struct desc_struct tr_seg;
f850e2e6
GN		 2121 int r;
2122 u16 io_bitmap_ptr;
2123 u8 perm, bit_idx = port & 0x7;
2124 unsigned mask = (1 << len) - 1;
2125
79168fd1
GN		 2126 ops->get_cached_descriptor(&tr_seg, VCPU_SREG_TR, ctxt->vcpu);
2127 if (!tr_seg.p)
f850e2e6 2128 return false;
79168fd1 2129 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2130 return false;
79168fd1
GN		 2131 r = ops->read_std(get_desc_base(&tr_seg) + 102, &io_bitmap_ptr, 2,
2132 ctxt->vcpu, NULL);
f850e2e6
GN		 2133 if (r != X86EMUL_CONTINUE)
2134 return false;
79168fd1 2135 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2136 return false;
79168fd1
GN		 2137 r = ops->read_std(get_desc_base(&tr_seg) + io_bitmap_ptr + port/8,
2138 &perm, 1, ctxt->vcpu, NULL);
f850e2e6
GN		 2139 if (r != X86EMUL_CONTINUE)
2140 return false;
2141 if ((perm >> bit_idx) & mask)
2142 return false;
2143 return true;
2144}
2145
2146static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
2147 struct x86_emulate_ops *ops,
2148 u16 port, u16 len)
2149{
9c537244 2150 if (emulator_bad_iopl(ctxt, ops))
f850e2e6
GN		 2151 if (!emulator_io_port_access_allowed(ctxt, ops, port, len))
2152 return false;
2153 return true;
2154}
2155
38ba30ba
GN		 2156static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
2157 struct x86_emulate_ops *ops,
2158 struct tss_segment_16 *tss)
2159{
2160 struct decode_cache *c = &ctxt->decode;
2161
2162 tss->ip = c->eip;
2163 tss->flag = ctxt->eflags;
2164 tss->ax = c->regs[VCPU_REGS_RAX];
2165 tss->cx = c->regs[VCPU_REGS_RCX];
2166 tss->dx = c->regs[VCPU_REGS_RDX];
2167 tss->bx = c->regs[VCPU_REGS_RBX];
2168 tss->sp = c->regs[VCPU_REGS_RSP];
2169 tss->bp = c->regs[VCPU_REGS_RBP];
2170 tss->si = c->regs[VCPU_REGS_RSI];
2171 tss->di = c->regs[VCPU_REGS_RDI];
2172
2173 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
2174 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2175 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
2176 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
2177 tss->ldt = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
2178}
2179
2180static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
2181 struct x86_emulate_ops *ops,
2182 struct tss_segment_16 *tss)
2183{
2184 struct decode_cache *c = &ctxt->decode;
2185 int ret;
2186
2187 c->eip = tss->ip;
2188 ctxt->eflags = tss->flag | 2;
2189 c->regs[VCPU_REGS_RAX] = tss->ax;
2190 c->regs[VCPU_REGS_RCX] = tss->cx;
2191 c->regs[VCPU_REGS_RDX] = tss->dx;
2192 c->regs[VCPU_REGS_RBX] = tss->bx;
2193 c->regs[VCPU_REGS_RSP] = tss->sp;
2194 c->regs[VCPU_REGS_RBP] = tss->bp;
2195 c->regs[VCPU_REGS_RSI] = tss->si;
2196 c->regs[VCPU_REGS_RDI] = tss->di;
2197
2198 /*
2199 * SDM says that segment selectors are loaded before segment
2200 * descriptors
2201 */
2202 ops->set_segment_selector(tss->ldt, VCPU_SREG_LDTR, ctxt->vcpu);
2203 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
2204 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
2205 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
2206 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
2207
2208 /*
2209 * Now load segment descriptors. If fault happenes at this stage
2210 * it is handled in a context of new task
2211 */
2212 ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR);
2213 if (ret != X86EMUL_CONTINUE)
2214 return ret;
2215 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2216 if (ret != X86EMUL_CONTINUE)
2217 return ret;
2218 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2219 if (ret != X86EMUL_CONTINUE)
2220 return ret;
2221 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2222 if (ret != X86EMUL_CONTINUE)
2223 return ret;
2224 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2225 if (ret != X86EMUL_CONTINUE)
2226 return ret;
2227
2228 return X86EMUL_CONTINUE;
2229}
2230
2231static int task_switch_16(struct x86_emulate_ctxt *ctxt,
2232 struct x86_emulate_ops *ops,
2233 u16 tss_selector, u16 old_tss_sel,
2234 ulong old_tss_base, struct desc_struct *new_desc)
2235{
2236 struct tss_segment_16 tss_seg;
2237 int ret;
2238 u32 err, new_tss_base = get_desc_base(new_desc);
2239
2240 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2241 &err);
2242 if (ret == X86EMUL_PROPAGATE_FAULT) {
2243 /* FIXME: need to provide precise fault address */
54b8486f 2244 emulate_pf(ctxt, old_tss_base, err);
38ba30ba
GN		 2245 return ret;
2246 }
2247
2248 save_state_to_tss16(ctxt, ops, &tss_seg);
2249
2250 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2251 &err);
2252 if (ret == X86EMUL_PROPAGATE_FAULT) {
2253 /* FIXME: need to provide precise fault address */
54b8486f 2254 emulate_pf(ctxt, old_tss_base, err);
38ba30ba
GN		 2255 return ret;
2256 }
2257
2258 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2259 &err);
2260 if (ret == X86EMUL_PROPAGATE_FAULT) {
2261 /* FIXME: need to provide precise fault address */
54b8486f 2262 emulate_pf(ctxt, new_tss_base, err);
38ba30ba
GN		 2263 return ret;
2264 }
2265
2266 if (old_tss_sel != 0xffff) {
2267 tss_seg.prev_task_link = old_tss_sel;
2268
2269 ret = ops->write_std(new_tss_base,
2270 &tss_seg.prev_task_link,
2271 sizeof tss_seg.prev_task_link,
2272 ctxt->vcpu, &err);
2273 if (ret == X86EMUL_PROPAGATE_FAULT) {
2274 /* FIXME: need to provide precise fault address */
54b8486f 2275 emulate_pf(ctxt, new_tss_base, err);
38ba30ba
GN		 2276 return ret;
2277 }
2278 }
2279
2280 return load_state_from_tss16(ctxt, ops, &tss_seg);
2281}
2282
2283static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
2284 struct x86_emulate_ops *ops,
2285 struct tss_segment_32 *tss)
2286{
2287 struct decode_cache *c = &ctxt->decode;
2288
2289 tss->cr3 = ops->get_cr(3, ctxt->vcpu);
2290 tss->eip = c->eip;
2291 tss->eflags = ctxt->eflags;
2292 tss->eax = c->regs[VCPU_REGS_RAX];
2293 tss->ecx = c->regs[VCPU_REGS_RCX];
2294 tss->edx = c->regs[VCPU_REGS_RDX];
2295 tss->ebx = c->regs[VCPU_REGS_RBX];
2296 tss->esp = c->regs[VCPU_REGS_RSP];
2297 tss->ebp = c->regs[VCPU_REGS_RBP];
2298 tss->esi = c->regs[VCPU_REGS_RSI];
2299 tss->edi = c->regs[VCPU_REGS_RDI];
2300
2301 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
2302 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2303 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
2304 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
2305 tss->fs = ops->get_segment_selector(VCPU_SREG_FS, ctxt->vcpu);
2306 tss->gs = ops->get_segment_selector(VCPU_SREG_GS, ctxt->vcpu);
2307 tss->ldt_selector = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
2308}
2309
2310static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
2311 struct x86_emulate_ops *ops,
2312 struct tss_segment_32 *tss)
2313{
2314 struct decode_cache *c = &ctxt->decode;
2315 int ret;
2316
0f12244f 2317 if (ops->set_cr(3, tss->cr3, ctxt->vcpu)) {
54b8486f 2318 emulate_gp(ctxt, 0);
0f12244f
GN		 2319 return X86EMUL_PROPAGATE_FAULT;
2320 }
38ba30ba
GN		 2321 c->eip = tss->eip;
2322 ctxt->eflags = tss->eflags | 2;
2323 c->regs[VCPU_REGS_RAX] = tss->eax;
2324 c->regs[VCPU_REGS_RCX] = tss->ecx;
2325 c->regs[VCPU_REGS_RDX] = tss->edx;
2326 c->regs[VCPU_REGS_RBX] = tss->ebx;
2327 c->regs[VCPU_REGS_RSP] = tss->esp;
2328 c->regs[VCPU_REGS_RBP] = tss->ebp;
2329 c->regs[VCPU_REGS_RSI] = tss->esi;
2330 c->regs[VCPU_REGS_RDI] = tss->edi;
2331
2332 /*
2333 * SDM says that segment selectors are loaded before segment
2334 * descriptors
2335 */
2336 ops->set_segment_selector(tss->ldt_selector, VCPU_SREG_LDTR, ctxt->vcpu);
2337 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
2338 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
2339 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
2340 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
2341 ops->set_segment_selector(tss->fs, VCPU_SREG_FS, ctxt->vcpu);
2342 ops->set_segment_selector(tss->gs, VCPU_SREG_GS, ctxt->vcpu);
2343
2344 /*
2345 * Now load segment descriptors. If fault happenes at this stage
2346 * it is handled in a context of new task
2347 */
2348 ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR);
2349 if (ret != X86EMUL_CONTINUE)
2350 return ret;
2351 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2352 if (ret != X86EMUL_CONTINUE)
2353 return ret;
2354 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2355 if (ret != X86EMUL_CONTINUE)
2356 return ret;
2357 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2358 if (ret != X86EMUL_CONTINUE)
2359 return ret;
2360 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2361 if (ret != X86EMUL_CONTINUE)
2362 return ret;
2363 ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS);
2364 if (ret != X86EMUL_CONTINUE)
2365 return ret;
2366 ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS);
2367 if (ret != X86EMUL_CONTINUE)
2368 return ret;
2369
2370 return X86EMUL_CONTINUE;
2371}
2372
2373static int task_switch_32(struct x86_emulate_ctxt *ctxt,
2374 struct x86_emulate_ops *ops,
2375 u16 tss_selector, u16 old_tss_sel,
2376 ulong old_tss_base, struct desc_struct *new_desc)
2377{
2378 struct tss_segment_32 tss_seg;
2379 int ret;
2380 u32 err, new_tss_base = get_desc_base(new_desc);
2381
2382 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2383 &err);
2384 if (ret == X86EMUL_PROPAGATE_FAULT) {
2385 /* FIXME: need to provide precise fault address */
54b8486f 2386 emulate_pf(ctxt, old_tss_base, err);
38ba30ba
GN		 2387 return ret;
2388 }
2389
2390 save_state_to_tss32(ctxt, ops, &tss_seg);
2391
2392 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2393 &err);
2394 if (ret == X86EMUL_PROPAGATE_FAULT) {
2395 /* FIXME: need to provide precise fault address */
54b8486f 2396 emulate_pf(ctxt, old_tss_base, err);
38ba30ba
GN		 2397 return ret;
2398 }
2399
2400 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2401 &err);
2402 if (ret == X86EMUL_PROPAGATE_FAULT) {
2403 /* FIXME: need to provide precise fault address */
54b8486f 2404 emulate_pf(ctxt, new_tss_base, err);
38ba30ba
GN		 2405 return ret;
2406 }
2407
2408 if (old_tss_sel != 0xffff) {
2409 tss_seg.prev_task_link = old_tss_sel;
2410
2411 ret = ops->write_std(new_tss_base,
2412 &tss_seg.prev_task_link,
2413 sizeof tss_seg.prev_task_link,
2414 ctxt->vcpu, &err);
2415 if (ret == X86EMUL_PROPAGATE_FAULT) {
2416 /* FIXME: need to provide precise fault address */
54b8486f 2417 emulate_pf(ctxt, new_tss_base, err);
38ba30ba
GN		 2418 return ret;
2419 }
2420 }
2421
2422 return load_state_from_tss32(ctxt, ops, &tss_seg);
2423}
2424
2425static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2426 struct x86_emulate_ops *ops,
2427 u16 tss_selector, int reason,
2428 bool has_error_code, u32 error_code)
38ba30ba
GN		 2429{
2430 struct desc_struct curr_tss_desc, next_tss_desc;
2431 int ret;
2432 u16 old_tss_sel = ops->get_segment_selector(VCPU_SREG_TR, ctxt->vcpu);
2433 ulong old_tss_base =
5951c442 2434 ops->get_cached_segment_base(VCPU_SREG_TR, ctxt->vcpu);
ceffb459 2435 u32 desc_limit;
38ba30ba
GN		 2436
2437 /* FIXME: old_tss_base == ~0 ? */
2438
2439 ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc);
2440 if (ret != X86EMUL_CONTINUE)
2441 return ret;
2442 ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc);
2443 if (ret != X86EMUL_CONTINUE)
2444 return ret;
2445
2446 /* FIXME: check that next_tss_desc is tss */
2447
2448 if (reason != TASK_SWITCH_IRET) {
2449 if ((tss_selector & 3) > next_tss_desc.dpl ||
2450 ops->cpl(ctxt->vcpu) > next_tss_desc.dpl) {
54b8486f 2451 emulate_gp(ctxt, 0);
38ba30ba
GN		 2452 return X86EMUL_PROPAGATE_FAULT;
2453 }
2454 }
2455
ceffb459
GN		 2456 desc_limit = desc_limit_scaled(&next_tss_desc);
2457 if (!next_tss_desc.p ||
2458 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2459 desc_limit < 0x2b)) {
54b8486f 2460 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2461 return X86EMUL_PROPAGATE_FAULT;
2462 }
2463
2464 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2465 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2466 write_segment_descriptor(ctxt, ops, old_tss_sel,
2467 &curr_tss_desc);
2468 }
2469
2470 if (reason == TASK_SWITCH_IRET)
2471 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2472
2473 /* set back link to prev task only if NT bit is set in eflags
2474 note that old_tss_sel is not used afetr this point */
2475 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2476 old_tss_sel = 0xffff;
2477
2478 if (next_tss_desc.type & 8)
2479 ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel,
2480 old_tss_base, &next_tss_desc);
2481 else
2482 ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel,
2483 old_tss_base, &next_tss_desc);
0760d448
JK		 2484 if (ret != X86EMUL_CONTINUE)
2485 return ret;
38ba30ba
GN		 2486
2487 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2488 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2489
2490 if (reason != TASK_SWITCH_IRET) {
2491 next_tss_desc.type |= (1 << 1); /* set busy flag */
2492 write_segment_descriptor(ctxt, ops, tss_selector,
2493 &next_tss_desc);
2494 }
2495
2496 ops->set_cr(0, ops->get_cr(0, ctxt->vcpu) | X86_CR0_TS, ctxt->vcpu);
2497 ops->set_cached_descriptor(&next_tss_desc, VCPU_SREG_TR, ctxt->vcpu);
2498 ops->set_segment_selector(tss_selector, VCPU_SREG_TR, ctxt->vcpu);
2499
e269fb21
JK		 2500 if (has_error_code) {
2501 struct decode_cache *c = &ctxt->decode;
2502
2503 c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2504 c->lock_prefix = 0;
2505 c->src.val = (unsigned long) error_code;
79168fd1 2506 emulate_push(ctxt, ops);
e269fb21
JK		 2507 }
2508
38ba30ba
GN		 2509 return ret;
2510}
2511
2512int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
2513 struct x86_emulate_ops *ops,
e269fb21
JK		 2514 u16 tss_selector, int reason,
2515 bool has_error_code, u32 error_code)
38ba30ba
GN		 2516{
2517 struct decode_cache *c = &ctxt->decode;
2518 int rc;
2519
38ba30ba 2520 c->eip = ctxt->eip;
e269fb21 2521 c->dst.type = OP_NONE;
38ba30ba 2522
e269fb21
JK		 2523 rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason,
2524 has_error_code, error_code);
38ba30ba
GN		 2525
2526 if (rc == X86EMUL_CONTINUE) {
e269fb21 2527 rc = writeback(ctxt, ops);
95c55886
GN		 2528 if (rc == X86EMUL_CONTINUE)
2529 ctxt->eip = c->eip;
38ba30ba
GN		 2530 }
2531
19d04437 2532 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
38ba30ba
GN		 2533}
2534
a682e354 2535static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned long base,
d9271123 2536 int reg, struct operand *op)
a682e354
GN		 2537{
2538 struct decode_cache *c = &ctxt->decode;
2539 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2540
d9271123
GN		 2541 register_address_increment(c, &c->regs[reg], df * op->bytes);
2542 op->ptr = (unsigned long *)register_address(c, base, c->regs[reg]);
a682e354
GN		 2543}
2544
8b4caf66 2545int
1be3aa47 2546x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8b4caf66 2547{
8b4caf66 2548 u64 msr_data;
8b4caf66 2549 struct decode_cache *c = &ctxt->decode;
1b30eaa8 2550 int rc = X86EMUL_CONTINUE;
5cd21917 2551 int saved_dst_type = c->dst.type;
8b4caf66 2552
9de41573 2553 ctxt->decode.mem_read.pos = 0;
310b5d30 2554
1161624f 2555 if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
54b8486f 2556 emulate_ud(ctxt);
1161624f
GN		 2557 goto done;
2558 }
2559
d380a5e4 2560 /* LOCK prefix is allowed only with some instructions */
a41ffb75 2561 if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) {
54b8486f 2562 emulate_ud(ctxt);
d380a5e4
GN		 2563 goto done;
2564 }
2565
e92805ac 2566 /* Privileged instruction can be executed only in CPL=0 */
9c537244 2567 if ((c->d & Priv) && ops->cpl(ctxt->vcpu)) {
54b8486f 2568 emulate_gp(ctxt, 0);
e92805ac
GN		 2569 goto done;
2570 }
2571
b9fa9d6b 2572 if (c->rep_prefix && (c->d & String)) {
5cd21917 2573 ctxt->restart = true;
b9fa9d6b 2574 /* All REP prefixes have the same first termination condition */
c73e197b 2575 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) {
5cd21917
GN		 2576 string_done:
2577 ctxt->restart = false;
95c55886 2578 ctxt->eip = c->eip;
b9fa9d6b
AK		 2579 goto done;
2580 }
2581 /* The second termination condition only applies for REPE
2582 * and REPNE. Test if the repeat string operation prefix is
2583 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
2584 * corresponding termination condition according to:
2585 * - if REPE/REPZ and ZF = 0 then done
2586 * - if REPNE/REPNZ and ZF = 1 then done
2587 */
2588 if ((c->b == 0xa6) || (c->b == 0xa7) ||
5cd21917 2589 (c->b == 0xae) || (c->b == 0xaf)) {
b9fa9d6b 2590 if ((c->rep_prefix == REPE_PREFIX) &&
5cd21917
GN		 2591 ((ctxt->eflags & EFLG_ZF) == 0))
2592 goto string_done;
b9fa9d6b 2593 if ((c->rep_prefix == REPNE_PREFIX) &&
5cd21917
GN		 2594 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))
2595 goto string_done;
b9fa9d6b 2596 }
063db061 2597 c->eip = ctxt->eip;
b9fa9d6b
AK		 2598 }
2599
8b4caf66 2600 if (c->src.type == OP_MEM) {
9de41573 2601 rc = read_emulated(ctxt, ops, (unsigned long)c->src.ptr,
414e6277 2602 c->src.valptr, c->src.bytes);
b60d513c 2603 if (rc != X86EMUL_CONTINUE)
8b4caf66 2604 goto done;
16518d5a 2605 c->src.orig_val64 = c->src.val64;
8b4caf66
LV		 2606 }
2607
e35b7b9c 2608 if (c->src2.type == OP_MEM) {
9de41573
GN		 2609 rc = read_emulated(ctxt, ops, (unsigned long)c->src2.ptr,
2610 &c->src2.val, c->src2.bytes);
e35b7b9c
GN		 2611 if (rc != X86EMUL_CONTINUE)
2612 goto done;
2613 }
2614
8b4caf66
LV		 2615 if ((c->d & DstMask) == ImplicitOps)
2616 goto special_insn;
2617
2618
69f55cb1
GN		 2619 if ((c->dst.type == OP_MEM) && !(c->d & Mov)) {
2620 /* optimisation - avoid slow emulated read if Mov */
9de41573
GN		 2621 rc = read_emulated(ctxt, ops, (unsigned long)c->dst.ptr,
2622 &c->dst.val, c->dst.bytes);
69f55cb1
GN		 2623 if (rc != X86EMUL_CONTINUE)
2624 goto done;
038e51de 2625 }
e4e03ded 2626 c->dst.orig_val = c->dst.val;
038e51de 2627
018a98db
AK		 2628special_insn:
2629
e4e03ded 2630 if (c->twobyte)
6aa8b732
AK		 2631 goto twobyte_insn;
2632
e4e03ded 2633 switch (c->b) {
6aa8b732
AK		 2634 case 0x00 ... 0x05:
2635 add: /* add */
05f086f8 2636 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
6aa8b732 2637 break;
0934ac9d 2638 case 0x06: /* push es */
79168fd1 2639 emulate_push_sreg(ctxt, ops, VCPU_SREG_ES);
0934ac9d
MG		 2640 break;
2641 case 0x07: /* pop es */
0934ac9d 2642 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
1b30eaa8 2643 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 2644 goto done;
2645 break;
6aa8b732
AK		 2646 case 0x08 ... 0x0d:
2647 or: /* or */
05f086f8 2648 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
6aa8b732 2649 break;
0934ac9d 2650 case 0x0e: /* push cs */
79168fd1 2651 emulate_push_sreg(ctxt, ops, VCPU_SREG_CS);
0934ac9d 2652 break;
6aa8b732
AK		 2653 case 0x10 ... 0x15:
2654 adc: /* adc */
05f086f8 2655 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
6aa8b732 2656 break;
0934ac9d 2657 case 0x16: /* push ss */
79168fd1 2658 emulate_push_sreg(ctxt, ops, VCPU_SREG_SS);
0934ac9d
MG		 2659 break;
2660 case 0x17: /* pop ss */
0934ac9d 2661 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
1b30eaa8 2662 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 2663 goto done;
2664 break;
6aa8b732
AK		 2665 case 0x18 ... 0x1d:
2666 sbb: /* sbb */
05f086f8 2667 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
6aa8b732 2668 break;
0934ac9d 2669 case 0x1e: /* push ds */
79168fd1 2670 emulate_push_sreg(ctxt, ops, VCPU_SREG_DS);
0934ac9d
MG		 2671 break;
2672 case 0x1f: /* pop ds */
0934ac9d 2673 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
1b30eaa8 2674 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 2675 goto done;
2676 break;
aa3a816b 2677 case 0x20 ... 0x25:
6aa8b732 2678 and: /* and */
05f086f8 2679 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2680 break;
2681 case 0x28 ... 0x2d:
2682 sub: /* sub */
05f086f8 2683 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2684 break;
2685 case 0x30 ... 0x35:
2686 xor: /* xor */
05f086f8 2687 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2688 break;
2689 case 0x38 ... 0x3d:
2690 cmp: /* cmp */
05f086f8 2691 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
6aa8b732 2692 break;
33615aa9
AK		 2693 case 0x40 ... 0x47: /* inc r16/r32 */
2694 emulate_1op("inc", c->dst, ctxt->eflags);
2695 break;
2696 case 0x48 ... 0x4f: /* dec r16/r32 */
2697 emulate_1op("dec", c->dst, ctxt->eflags);
2698 break;
2699 case 0x50 ... 0x57: /* push reg */
79168fd1 2700 emulate_push(ctxt, ops);
33615aa9
AK		 2701 break;
2702 case 0x58 ... 0x5f: /* pop reg */
2703 pop_instruction:
350f69dc 2704 rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes);
1b30eaa8 2705 if (rc != X86EMUL_CONTINUE)
33615aa9 2706 goto done;
33615aa9 2707 break;
abcf14b5 2708 case 0x60: /* pusha */
c37eda13
WY		 2709 rc = emulate_pusha(ctxt, ops);
2710 if (rc != X86EMUL_CONTINUE)
2711 goto done;
abcf14b5
MG		 2712 break;
2713 case 0x61: /* popa */
2714 rc = emulate_popa(ctxt, ops);
1b30eaa8 2715 if (rc != X86EMUL_CONTINUE)
abcf14b5
MG		 2716 goto done;
2717 break;
6aa8b732 2718 case 0x63: /* movsxd */
8b4caf66 2719 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 2720 goto cannot_emulate;
e4e03ded 2721 c->dst.val = (s32) c->src.val;
6aa8b732 2722 break;
91ed7a0e 2723 case 0x68: /* push imm */
018a98db 2724 case 0x6a: /* push imm8 */
79168fd1 2725 emulate_push(ctxt, ops);
018a98db
AK		 2726 break;
2727 case 0x6c: /* insb */
2728 case 0x6d: /* insw/insd */
7972995b 2729 c->dst.bytes = min(c->dst.bytes, 4u);
f850e2e6 2730 if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX],
7972995b 2731 c->dst.bytes)) {
54b8486f 2732 emulate_gp(ctxt, 0);
f850e2e6
GN		 2733 goto done;
2734 }
7b262e90
GN		 2735 if (!pio_in_emulated(ctxt, ops, c->dst.bytes,
2736 c->regs[VCPU_REGS_RDX], &c->dst.val))
7972995b
GN		 2737 goto done; /* IO is needed, skip writeback */
2738 break;
018a98db
AK		 2739 case 0x6e: /* outsb */
2740 case 0x6f: /* outsw/outsd */
7972995b 2741 c->src.bytes = min(c->src.bytes, 4u);
f850e2e6 2742 if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX],
7972995b 2743 c->src.bytes)) {
54b8486f 2744 emulate_gp(ctxt, 0);
f850e2e6
GN		 2745 goto done;
2746 }
7972995b
GN		 2747 ops->pio_out_emulated(c->src.bytes, c->regs[VCPU_REGS_RDX],
2748 &c->src.val, 1, ctxt->vcpu);
2749
2750 c->dst.type = OP_NONE; /* nothing to writeback */
2751 break;
b2833e3c 2752 case 0x70 ... 0x7f: /* jcc (short) */
018a98db 2753 if (test_cc(c->b, ctxt->eflags))
b2833e3c 2754 jmp_rel(c, c->src.val);
018a98db 2755 break;
6aa8b732 2756 case 0x80 ... 0x83: /* Grp1 */
e4e03ded 2757 switch (c->modrm_reg) {
6aa8b732
AK		 2758 case 0:
2759 goto add;
2760 case 1:
2761 goto or;
2762 case 2:
2763 goto adc;
2764 case 3:
2765 goto sbb;
2766 case 4:
2767 goto and;
2768 case 5:
2769 goto sub;
2770 case 6:
2771 goto xor;
2772 case 7:
2773 goto cmp;
2774 }
2775 break;
2776 case 0x84 ... 0x85:
dfb507c4 2777 test:
05f086f8 2778 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2779 break;
2780 case 0x86 ... 0x87: /* xchg */
b13354f8 2781 xchg:
6aa8b732 2782 /* Write back the register source. */
e4e03ded 2783 switch (c->dst.bytes) {
6aa8b732 2784 case 1:
e4e03ded 2785 *(u8 *) c->src.ptr = (u8) c->dst.val;
6aa8b732
AK		 2786 break;
2787 case 2:
e4e03ded 2788 *(u16 *) c->src.ptr = (u16) c->dst.val;
6aa8b732
AK		 2789 break;
2790 case 4:
e4e03ded 2791 *c->src.ptr = (u32) c->dst.val;
6aa8b732
AK		 2792 break; /* 64b reg: zero-extend */
2793 case 8:
e4e03ded 2794 *c->src.ptr = c->dst.val;
6aa8b732
AK		 2795 break;
2796 }
2797 /*
2798 * Write back the memory destination with implicit LOCK
2799 * prefix.
2800 */
e4e03ded
LV		 2801 c->dst.val = c->src.val;
2802 c->lock_prefix = 1;
6aa8b732 2803 break;
6aa8b732 2804 case 0x88 ... 0x8b: /* mov */
7de75248 2805 goto mov;
79168fd1
GN		 2806 case 0x8c: /* mov r/m, sreg */
2807 if (c->modrm_reg > VCPU_SREG_GS) {
54b8486f 2808 emulate_ud(ctxt);
5e3ae6c5 2809 goto done;
38d5bc6d 2810 }
79168fd1 2811 c->dst.val = ops->get_segment_selector(c->modrm_reg, ctxt->vcpu);
38d5bc6d 2812 break;
7e0b54b1 2813 case 0x8d: /* lea r16/r32, m */
f9b7aab3 2814 c->dst.val = c->modrm_ea;
7e0b54b1 2815 break;
4257198a
GT		 2816 case 0x8e: { /* mov seg, r/m16 */
2817 uint16_t sel;
4257198a
GT		 2818
2819 sel = c->src.val;
8b9f4414 2820
c697518a
GN		 2821 if (c->modrm_reg == VCPU_SREG_CS ||
2822 c->modrm_reg > VCPU_SREG_GS) {
54b8486f 2823 emulate_ud(ctxt);
8b9f4414
GN		 2824 goto done;
2825 }
2826
310b5d30 2827 if (c->modrm_reg == VCPU_SREG_SS)
95cb2295 2828 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
310b5d30 2829
2e873022 2830 rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg);
4257198a
GT		 2831
2832 c->dst.type = OP_NONE; /* Disable writeback. */
2833 break;
2834 }
6aa8b732 2835 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9 2836 rc = emulate_grp1a(ctxt, ops);
1b30eaa8 2837 if (rc != X86EMUL_CONTINUE)
6aa8b732 2838 goto done;
6aa8b732 2839 break;
b13354f8 2840 case 0x90: /* nop / xchg r8,rax */
b8a98945
GN		 2841 if (c->dst.ptr == (unsigned long *)&c->regs[VCPU_REGS_RAX]) {
2842 c->dst.type = OP_NONE; /* nop */
b13354f8
MG		 2843 break;
2844 }
2845 case 0x91 ... 0x97: /* xchg reg,rax */
f0c13ef1
GN		 2846 c->src.type = OP_REG;
2847 c->src.bytes = c->op_bytes;
b13354f8
MG		 2848 c->src.ptr = (unsigned long *) &c->regs[VCPU_REGS_RAX];
2849 c->src.val = *(c->src.ptr);
2850 goto xchg;
fd2a7608 2851 case 0x9c: /* pushf */
05f086f8 2852 c->src.val = (unsigned long) ctxt->eflags;
79168fd1 2853 emulate_push(ctxt, ops);
8cdbd2c9 2854 break;
535eabcf 2855 case 0x9d: /* popf */
2b48cc75 2856 c->dst.type = OP_REG;
05f086f8 2857 c->dst.ptr = (unsigned long *) &ctxt->eflags;
2b48cc75 2858 c->dst.bytes = c->op_bytes;
d4c6a154
GN		 2859 rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes);
2860 if (rc != X86EMUL_CONTINUE)
2861 goto done;
2862 break;
5d55f299 2863 case 0xa0 ... 0xa3: /* mov */
6aa8b732 2864 case 0xa4 ... 0xa5: /* movs */
a682e354 2865 goto mov;
6aa8b732 2866 case 0xa6 ... 0xa7: /* cmps */
d7e5117a 2867 c->dst.type = OP_NONE; /* Disable writeback. */
d7e5117a 2868 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr);
a682e354 2869 goto cmp;
dfb507c4
MG		 2870 case 0xa8 ... 0xa9: /* test ax, imm */
2871 goto test;
6aa8b732 2872 case 0xaa ... 0xab: /* stos */
e4e03ded 2873 c->dst.val = c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 2874 break;
2875 case 0xac ... 0xad: /* lods */
a682e354 2876 goto mov;
6aa8b732
AK		 2877 case 0xae ... 0xaf: /* scas */
2878 DPRINTF("Urk! I don't handle SCAS.\n");
2879 goto cannot_emulate;
a5e2e82b 2880 case 0xb0 ... 0xbf: /* mov r, imm */
615ac125 2881 goto mov;
018a98db
AK		 2882 case 0xc0 ... 0xc1:
2883 emulate_grp2(ctxt);
2884 break;
111de5d6 2885 case 0xc3: /* ret */
cf5de4f8 2886 c->dst.type = OP_REG;
111de5d6 2887 c->dst.ptr = &c->eip;
cf5de4f8 2888 c->dst.bytes = c->op_bytes;
111de5d6 2889 goto pop_instruction;
018a98db
AK		 2890 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
2891 mov:
2892 c->dst.val = c->src.val;
2893 break;
a77ab5ea
AK		 2894 case 0xcb: /* ret far */
2895 rc = emulate_ret_far(ctxt, ops);
1b30eaa8 2896 if (rc != X86EMUL_CONTINUE)
a77ab5ea
AK		 2897 goto done;
2898 break;
018a98db
AK		 2899 case 0xd0 ... 0xd1: /* Grp2 */
2900 c->src.val = 1;
2901 emulate_grp2(ctxt);
2902 break;
2903 case 0xd2 ... 0xd3: /* Grp2 */
2904 c->src.val = c->regs[VCPU_REGS_RCX];
2905 emulate_grp2(ctxt);
2906 break;
a6a3034c
MG		 2907 case 0xe4: /* inb */
2908 case 0xe5: /* in */
cf8f70bf 2909 goto do_io_in;
a6a3034c
MG		 2910 case 0xe6: /* outb */
2911 case 0xe7: /* out */
cf8f70bf 2912 goto do_io_out;
1a52e051 2913 case 0xe8: /* call (near) */ {
d53c4777 2914 long int rel = c->src.val;
e4e03ded 2915 c->src.val = (unsigned long) c->eip;
7a957275 2916 jmp_rel(c, rel);
79168fd1 2917 emulate_push(ctxt, ops);
8cdbd2c9 2918 break;
1a52e051
NK		 2919 }
2920 case 0xe9: /* jmp rel */
954cd36f 2921 goto jmp;
414e6277
GN		 2922 case 0xea: { /* jmp far */
2923 unsigned short sel;
ea79849d 2924 jump_far:
414e6277
GN		 2925 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
2926
2927 if (load_segment_descriptor(ctxt, ops, sel, VCPU_SREG_CS))
c697518a 2928 goto done;
954cd36f 2929
414e6277
GN		 2930 c->eip = 0;
2931 memcpy(&c->eip, c->src.valptr, c->op_bytes);
954cd36f 2932 break;
414e6277 2933 }
954cd36f
GT		 2934 case 0xeb:
2935 jmp: /* jmp rel short */
7a957275 2936 jmp_rel(c, c->src.val);
a01af5ec 2937 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 2938 break;
a6a3034c
MG		 2939 case 0xec: /* in al,dx */
2940 case 0xed: /* in (e/r)ax,dx */
cf8f70bf
GN		 2941 c->src.val = c->regs[VCPU_REGS_RDX];
2942 do_io_in:
2943 c->dst.bytes = min(c->dst.bytes, 4u);
2944 if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) {
54b8486f 2945 emulate_gp(ctxt, 0);
cf8f70bf
GN		 2946 goto done;
2947 }
7b262e90
GN		 2948 if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val,
2949 &c->dst.val))
cf8f70bf
GN		 2950 goto done; /* IO is needed */
2951 break;
ce7a0ad3
WY		 2952 case 0xee: /* out dx,al */
2953 case 0xef: /* out dx,(e/r)ax */
cf8f70bf
GN		 2954 c->src.val = c->regs[VCPU_REGS_RDX];
2955 do_io_out:
2956 c->dst.bytes = min(c->dst.bytes, 4u);
2957 if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) {
54b8486f 2958 emulate_gp(ctxt, 0);
f850e2e6
GN		 2959 goto done;
2960 }
cf8f70bf
GN		 2961 ops->pio_out_emulated(c->dst.bytes, c->src.val, &c->dst.val, 1,
2962 ctxt->vcpu);
2963 c->dst.type = OP_NONE; /* Disable writeback. */
e93f36bc 2964 break;
111de5d6 2965 case 0xf4: /* hlt */
ad312c7c 2966 ctxt->vcpu->arch.halt_request = 1;
19fdfa0d 2967 break;
111de5d6
AK		 2968 case 0xf5: /* cmc */
2969 /* complement carry flag from eflags reg */
2970 ctxt->eflags ^= EFLG_CF;
2971 c->dst.type = OP_NONE; /* Disable writeback. */
2972 break;
018a98db 2973 case 0xf6 ... 0xf7: /* Grp3 */
aca06a83
GN		 2974 if (!emulate_grp3(ctxt, ops))
2975 goto cannot_emulate;
018a98db 2976 break;
111de5d6
AK		 2977 case 0xf8: /* clc */
2978 ctxt->eflags &= ~EFLG_CF;
2979 c->dst.type = OP_NONE; /* Disable writeback. */
2980 break;
2981 case 0xfa: /* cli */
07cbc6c1 2982 if (emulator_bad_iopl(ctxt, ops)) {
54b8486f 2983 emulate_gp(ctxt, 0);
07cbc6c1
WY		 2984 goto done;
2985 } else {
f850e2e6
GN		 2986 ctxt->eflags &= ~X86_EFLAGS_IF;
2987 c->dst.type = OP_NONE; /* Disable writeback. */
2988 }
111de5d6
AK		 2989 break;
2990 case 0xfb: /* sti */
07cbc6c1 2991 if (emulator_bad_iopl(ctxt, ops)) {
54b8486f 2992 emulate_gp(ctxt, 0);
07cbc6c1
WY		 2993 goto done;
2994 } else {
95cb2295 2995 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
f850e2e6
GN		 2996 ctxt->eflags |= X86_EFLAGS_IF;
2997 c->dst.type = OP_NONE; /* Disable writeback. */
2998 }
111de5d6 2999 break;
fb4616f4
MG		 3000 case 0xfc: /* cld */
3001 ctxt->eflags &= ~EFLG_DF;
3002 c->dst.type = OP_NONE; /* Disable writeback. */
3003 break;
3004 case 0xfd: /* std */
3005 ctxt->eflags |= EFLG_DF;
3006 c->dst.type = OP_NONE; /* Disable writeback. */
3007 break;
ea79849d
GN		 3008 case 0xfe: /* Grp4 */
3009 grp45:
018a98db 3010 rc = emulate_grp45(ctxt, ops);
1b30eaa8 3011 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 3012 goto done;
3013 break;
ea79849d
GN		 3014 case 0xff: /* Grp5 */
3015 if (c->modrm_reg == 5)
3016 goto jump_far;
3017 goto grp45;
91269b8f
AK		 3018 default:
3019 goto cannot_emulate;
6aa8b732 3020 }
018a98db
AK		 3021
3022writeback:
3023 rc = writeback(ctxt, ops);
1b30eaa8 3024 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 3025 goto done;
3026
5cd21917
GN		 3027 /*
3028 * restore dst type in case the decoding will be reused
3029 * (happens for string instruction )
3030 */
3031 c->dst.type = saved_dst_type;
3032
a682e354 3033 if ((c->d & SrcMask) == SrcSI)
79168fd1
GN		 3034 string_addr_inc(ctxt, seg_override_base(ctxt, ops, c),
3035 VCPU_REGS_RSI, &c->src);
a682e354
GN		 3036
3037 if ((c->d & DstMask) == DstDI)
79168fd1
GN		 3038 string_addr_inc(ctxt, es_base(ctxt, ops), VCPU_REGS_RDI,
3039 &c->dst);
d9271123 3040
5cd21917 3041 if (c->rep_prefix && (c->d & String)) {
7b262e90 3042 struct read_cache *rc = &ctxt->decode.io_read;
d9271123 3043 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
7b262e90
GN		 3044 /*
3045 * Re-enter guest when pio read ahead buffer is empty or,
3046 * if it is not used, after each 1024 iteration.
3047 */
3048 if ((rc->end == 0 && !(c->regs[VCPU_REGS_RCX] & 0x3ff)) ||
3049 (rc->end != 0 && rc->end == rc->pos))
5cd21917
GN		 3050 ctxt->restart = false;
3051 }
9de41573
GN		 3052 /*
3053 * reset read cache here in case string instruction is restared
3054 * without decoding
3055 */
3056 ctxt->decode.mem_read.end = 0;
95c55886 3057 ctxt->eip = c->eip;
018a98db
AK		 3058
3059done:
cb404fe0 3060 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
6aa8b732
AK		 3061
3062twobyte_insn:
e4e03ded 3063 switch (c->b) {
6aa8b732 3064 case 0x01: /* lgdt, lidt, lmsw */
e4e03ded 3065 switch (c->modrm_reg) {
6aa8b732
AK		 3066 u16 size;
3067 unsigned long address;
3068
aca7f966 3069 case 0: /* vmcall */
e4e03ded 3070 if (c->modrm_mod != 3 || c->modrm_rm != 1)
aca7f966
AL		 3071 goto cannot_emulate;
3072
7aa81cc0 3073 rc = kvm_fix_hypercall(ctxt->vcpu);
1b30eaa8 3074 if (rc != X86EMUL_CONTINUE)
7aa81cc0
AL		 3075 goto done;
3076
33e3885d 3077 /* Let the processor re-execute the fixed hypercall */
063db061 3078 c->eip = ctxt->eip;
16286d08
AK		 3079 /* Disable writeback. */
3080 c->dst.type = OP_NONE;
aca7f966 3081 break;
6aa8b732 3082 case 2: /* lgdt */
e4e03ded
LV		 3083 rc = read_descriptor(ctxt, ops, c->src.ptr,
3084 &size, &address, c->op_bytes);
1b30eaa8 3085 if (rc != X86EMUL_CONTINUE)
6aa8b732
AK		 3086 goto done;
3087 realmode_lgdt(ctxt->vcpu, size, address);
16286d08
AK		 3088 /* Disable writeback. */
3089 c->dst.type = OP_NONE;
6aa8b732 3090 break;
aca7f966 3091 case 3: /* lidt/vmmcall */
2b3d2a20
AK		 3092 if (c->modrm_mod == 3) {
3093 switch (c->modrm_rm) {
3094 case 1:
3095 rc = kvm_fix_hypercall(ctxt->vcpu);
1b30eaa8 3096 if (rc != X86EMUL_CONTINUE)
2b3d2a20
AK		 3097 goto done;
3098 break;
3099 default:
3100 goto cannot_emulate;
3101 }
aca7f966 3102 } else {
e4e03ded 3103 rc = read_descriptor(ctxt, ops, c->src.ptr,
aca7f966 3104 &size, &address,
e4e03ded 3105 c->op_bytes);
1b30eaa8 3106 if (rc != X86EMUL_CONTINUE)
aca7f966
AL		 3107 goto done;
3108 realmode_lidt(ctxt->vcpu, size, address);
3109 }
16286d08
AK		 3110 /* Disable writeback. */
3111 c->dst.type = OP_NONE;
6aa8b732
AK		 3112 break;
3113 case 4: /* smsw */
16286d08 3114 c->dst.bytes = 2;
52a46617 3115 c->dst.val = ops->get_cr(0, ctxt->vcpu);
6aa8b732
AK		 3116 break;
3117 case 6: /* lmsw */
93a152be
GN		 3118 ops->set_cr(0, (ops->get_cr(0, ctxt->vcpu) & ~0x0ful) |
3119 (c->src.val & 0x0f), ctxt->vcpu);
dc7457ea 3120 c->dst.type = OP_NONE;
6aa8b732 3121 break;
6e1e5ffe 3122 case 5: /* not defined */
54b8486f 3123 emulate_ud(ctxt);
6e1e5ffe 3124 goto done;
6aa8b732 3125 case 7: /* invlpg*/
69f55cb1 3126 emulate_invlpg(ctxt->vcpu, c->modrm_ea);
16286d08
AK		 3127 /* Disable writeback. */
3128 c->dst.type = OP_NONE;
6aa8b732
AK		 3129 break;
3130 default:
3131 goto cannot_emulate;
3132 }
3133 break;
e99f0507 3134 case 0x05: /* syscall */
3fb1b5db 3135 rc = emulate_syscall(ctxt, ops);
e54cfa97
TY		 3136 if (rc != X86EMUL_CONTINUE)
3137 goto done;
e66bb2cc
AP		 3138 else
3139 goto writeback;
e99f0507 3140 break;
018a98db
AK		 3141 case 0x06:
3142 emulate_clts(ctxt->vcpu);
3143 c->dst.type = OP_NONE;
3144 break;
018a98db 3145 case 0x09: /* wbinvd */
f5f48ee1
SY		 3146 kvm_emulate_wbinvd(ctxt->vcpu);
3147 c->dst.type = OP_NONE;
3148 break;
3149 case 0x08: /* invd */
018a98db
AK		 3150 case 0x0d: /* GrpP (prefetch) */
3151 case 0x18: /* Grp16 (prefetch/nop) */
3152 c->dst.type = OP_NONE;
3153 break;
3154 case 0x20: /* mov cr, reg */
6aebfa6e
GN		 3155 switch (c->modrm_reg) {
3156 case 1:
3157 case 5 ... 7:
3158 case 9 ... 15:
54b8486f 3159 emulate_ud(ctxt);
6aebfa6e
GN		 3160 goto done;
3161 }
52a46617 3162 c->regs[c->modrm_rm] = ops->get_cr(c->modrm_reg, ctxt->vcpu);
018a98db
AK		 3163 c->dst.type = OP_NONE; /* no writeback */
3164 break;
6aa8b732 3165 case 0x21: /* mov from dr to reg */
1e470be5
GN		 3166 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3167 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
54b8486f 3168 emulate_ud(ctxt);
1e470be5
GN		 3169 goto done;
3170 }
35aa5375 3171 ops->get_dr(c->modrm_reg, &c->regs[c->modrm_rm], ctxt->vcpu);
a01af5ec 3172 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3173 break;
018a98db 3174 case 0x22: /* mov reg, cr */
0f12244f 3175 if (ops->set_cr(c->modrm_reg, c->modrm_val, ctxt->vcpu)) {
54b8486f 3176 emulate_gp(ctxt, 0);
0f12244f
GN		 3177 goto done;
3178 }
018a98db
AK		 3179 c->dst.type = OP_NONE;
3180 break;
6aa8b732 3181 case 0x23: /* mov from reg to dr */
1e470be5
GN		 3182 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3183 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
54b8486f 3184 emulate_ud(ctxt);
1e470be5
GN		 3185 goto done;
3186 }
35aa5375 3187
338dbc97
GN		 3188 if (ops->set_dr(c->modrm_reg, c->regs[c->modrm_rm] &
3189 ((ctxt->mode == X86EMUL_MODE_PROT64) ?
3190 ~0ULL : ~0U), ctxt->vcpu) < 0) {
3191 /* #UD condition is already handled by the code above */
54b8486f 3192 emulate_gp(ctxt, 0);
338dbc97
GN		 3193 goto done;
3194 }
3195
a01af5ec 3196 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3197 break;
018a98db
AK		 3198 case 0x30:
3199 /* wrmsr */
3200 msr_data = (u32)c->regs[VCPU_REGS_RAX]
3201 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
3fb1b5db 3202 if (ops->set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data)) {
54b8486f 3203 emulate_gp(ctxt, 0);
fd525365 3204 goto done;
018a98db
AK		 3205 }
3206 rc = X86EMUL_CONTINUE;
3207 c->dst.type = OP_NONE;
3208 break;
3209 case 0x32:
3210 /* rdmsr */
3fb1b5db 3211 if (ops->get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data)) {
54b8486f 3212 emulate_gp(ctxt, 0);
fd525365 3213 goto done;
018a98db
AK		 3214 } else {
3215 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
3216 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
3217 }
3218 rc = X86EMUL_CONTINUE;
3219 c->dst.type = OP_NONE;
3220 break;
e99f0507 3221 case 0x34: /* sysenter */
3fb1b5db 3222 rc = emulate_sysenter(ctxt, ops);
e54cfa97
TY		 3223 if (rc != X86EMUL_CONTINUE)
3224 goto done;
8c604352
AP		 3225 else
3226 goto writeback;
e99f0507
AP		 3227 break;
3228 case 0x35: /* sysexit */
3fb1b5db 3229 rc = emulate_sysexit(ctxt, ops);
e54cfa97
TY		 3230 if (rc != X86EMUL_CONTINUE)
3231 goto done;
4668f050
AP		 3232 else
3233 goto writeback;
e99f0507 3234 break;
6aa8b732 3235 case 0x40 ... 0x4f: /* cmov */
e4e03ded 3236 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 3237 if (!test_cc(c->b, ctxt->eflags))
3238 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3239 break;
b2833e3c 3240 case 0x80 ... 0x8f: /* jnz rel, etc*/
018a98db 3241 if (test_cc(c->b, ctxt->eflags))
b2833e3c 3242 jmp_rel(c, c->src.val);
018a98db
AK		 3243 c->dst.type = OP_NONE;
3244 break;
0934ac9d 3245 case 0xa0: /* push fs */
79168fd1 3246 emulate_push_sreg(ctxt, ops, VCPU_SREG_FS);
0934ac9d
MG		 3247 break;
3248 case 0xa1: /* pop fs */
3249 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
1b30eaa8 3250 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 3251 goto done;
3252 break;
7de75248
NK		 3253 case 0xa3:
3254 bt: /* bt */
e4f8e039 3255 c->dst.type = OP_NONE;
e4e03ded
LV		 3256 /* only subword offset */
3257 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3258 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248 3259 break;
9bf8ea42
GT		 3260 case 0xa4: /* shld imm8, r, r/m */
3261 case 0xa5: /* shld cl, r, r/m */
3262 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
3263 break;
0934ac9d 3264 case 0xa8: /* push gs */
79168fd1 3265 emulate_push_sreg(ctxt, ops, VCPU_SREG_GS);
0934ac9d
MG		 3266 break;
3267 case 0xa9: /* pop gs */
3268 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
1b30eaa8 3269 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 3270 goto done;
3271 break;
7de75248
NK		 3272 case 0xab:
3273 bts: /* bts */
e4e03ded
LV		 3274 /* only subword offset */
3275 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3276 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 3277 break;
9bf8ea42
GT		 3278 case 0xac: /* shrd imm8, r, r/m */
3279 case 0xad: /* shrd cl, r, r/m */
3280 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
3281 break;
2a7c5b8b
GC		 3282 case 0xae: /* clflush */
3283 break;
6aa8b732
AK		 3284 case 0xb0 ... 0xb1: /* cmpxchg */
3285 /*
3286 * Save real source value, then compare EAX against
3287 * destination.
3288 */
e4e03ded
LV		 3289 c->src.orig_val = c->src.val;
3290 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 3291 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
3292 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 3293 /* Success: write back to memory. */
e4e03ded 3294 c->dst.val = c->src.orig_val;
6aa8b732
AK		 3295 } else {
3296 /* Failure: write the value we saw to EAX. */
e4e03ded
LV		 3297 c->dst.type = OP_REG;
3298 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 3299 }
3300 break;
6aa8b732
AK		 3301 case 0xb3:
3302 btr: /* btr */
e4e03ded
LV		 3303 /* only subword offset */
3304 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3305 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 3306 break;
6aa8b732 3307 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 3308 c->dst.bytes = c->op_bytes;
3309 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
3310 : (u16) c->src.val;
6aa8b732 3311 break;
6aa8b732 3312 case 0xba: /* Grp8 */
e4e03ded 3313 switch (c->modrm_reg & 3) {
6aa8b732
AK		 3314 case 0:
3315 goto bt;
3316 case 1:
3317 goto bts;
3318 case 2:
3319 goto btr;
3320 case 3:
3321 goto btc;
3322 }
3323 break;
7de75248
NK		 3324 case 0xbb:
3325 btc: /* btc */
e4e03ded
LV		 3326 /* only subword offset */
3327 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3328 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 3329 break;
6aa8b732 3330 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 3331 c->dst.bytes = c->op_bytes;
3332 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
3333 (s16) c->src.val;
6aa8b732 3334 break;
a012e65a 3335 case 0xc3: /* movnti */
e4e03ded
LV		 3336 c->dst.bytes = c->op_bytes;
3337 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
3338 (u64) c->src.val;
a012e65a 3339 break;
6aa8b732 3340 case 0xc7: /* Grp9 (cmpxchg8b) */
69f55cb1 3341 rc = emulate_grp9(ctxt, ops);
1b30eaa8 3342 if (rc != X86EMUL_CONTINUE)
8cdbd2c9
LV		 3343 goto done;
3344 break;
91269b8f
AK		 3345 default:
3346 goto cannot_emulate;
6aa8b732
AK		 3347 }
3348 goto writeback;
3349
3350cannot_emulate:
e4e03ded 3351 DPRINTF("Cannot emulate %02x\n", c->b);
6aa8b732
AK		 3352 return -1;
3353}
Linux 6.x block layer and io_uring tree(s)