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KVM: x86: Open code kvm_set_hflags
[linux-2.6-block.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
56e82318 25#include <asm/kvm_emulate.h>
b7d491e7 26#include <linux/stringify.h>
3db176d5 27#include <asm/debugreg.h>
1a29b5b7 28#include <asm/nospec-branch.h>
6aa8b732 29
3eeb3288 30#include "x86.h"
38ba30ba 31#include "tss.h"
d1cd3ce9 32#include "mmu.h"
2d7921c4 33#include "pmu.h"
e99f0507 34
a9945549
AK		 35/*
36 * Operand types
37 */
b1ea50b2
AK		 38#define OpNone 0ull
39#define OpImplicit 1ull /* No generic decode */
40#define OpReg 2ull /* Register */
41#define OpMem 3ull /* Memory */
42#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
43#define OpDI 5ull /* ES:DI/EDI/RDI */
44#define OpMem64 6ull /* Memory, 64-bit */
45#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
46#define OpDX 8ull /* DX register */
4dd6a57d
AK		 47#define OpCL 9ull /* CL register (for shifts) */
48#define OpImmByte 10ull /* 8-bit sign extended immediate */
49#define OpOne 11ull /* Implied 1 */
5e2c6883 50#define OpImm 12ull /* Sign extended up to 32-bit immediate */
0fe59128
AK		 51#define OpMem16 13ull /* Memory operand (16-bit). */
52#define OpMem32 14ull /* Memory operand (32-bit). */
53#define OpImmU 15ull /* Immediate operand, zero extended */
54#define OpSI 16ull /* SI/ESI/RSI */
55#define OpImmFAddr 17ull /* Immediate far address */
56#define OpMemFAddr 18ull /* Far address in memory */
57#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 58#define OpES 20ull /* ES */
59#define OpCS 21ull /* CS */
60#define OpSS 22ull /* SS */
61#define OpDS 23ull /* DS */
62#define OpFS 24ull /* FS */
63#define OpGS 25ull /* GS */
28867cee 64#define OpMem8 26ull /* 8-bit zero extended memory operand */
5e2c6883 65#define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
7fa57952 66#define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */
820207c8
AK		 67#define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */
68#define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */
0fe59128
AK		 69
70#define OpBits 5 /* Width of operand field */
b1ea50b2 71#define OpMask ((1ull << OpBits) - 1)
a9945549 72
6aa8b732
AK		 73/*
74 * Opcode effective-address decode tables.
75 * Note that we only emulate instructions that have at least one memory
76 * operand (excluding implicit stack references). We assume that stack
77 * references and instruction fetches will never occur in special memory
78 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
79 * not be handled.
80 */
81
82/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 83#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 84/* Destination operand type. */
a9945549
AK		 85#define DstShift 1
86#define ImplicitOps (OpImplicit << DstShift)
87#define DstReg (OpReg << DstShift)
88#define DstMem (OpMem << DstShift)
89#define DstAcc (OpAcc << DstShift)
90#define DstDI (OpDI << DstShift)
91#define DstMem64 (OpMem64 << DstShift)
16bebefe 92#define DstMem16 (OpMem16 << DstShift)
a9945549
AK		 93#define DstImmUByte (OpImmUByte << DstShift)
94#define DstDX (OpDX << DstShift)
820207c8 95#define DstAccLo (OpAccLo << DstShift)
a9945549 96#define DstMask (OpMask << DstShift)
6aa8b732 97/* Source operand type. */
0fe59128
AK		 98#define SrcShift 6
99#define SrcNone (OpNone << SrcShift)
100#define SrcReg (OpReg << SrcShift)
101#define SrcMem (OpMem << SrcShift)
102#define SrcMem16 (OpMem16 << SrcShift)
103#define SrcMem32 (OpMem32 << SrcShift)
104#define SrcImm (OpImm << SrcShift)
105#define SrcImmByte (OpImmByte << SrcShift)
106#define SrcOne (OpOne << SrcShift)
107#define SrcImmUByte (OpImmUByte << SrcShift)
108#define SrcImmU (OpImmU << SrcShift)
109#define SrcSI (OpSI << SrcShift)
7fa57952 110#define SrcXLat (OpXLat << SrcShift)
0fe59128
AK		 111#define SrcImmFAddr (OpImmFAddr << SrcShift)
112#define SrcMemFAddr (OpMemFAddr << SrcShift)
113#define SrcAcc (OpAcc << SrcShift)
114#define SrcImmU16 (OpImmU16 << SrcShift)
5e2c6883 115#define SrcImm64 (OpImm64 << SrcShift)
0fe59128 116#define SrcDX (OpDX << SrcShift)
28867cee 117#define SrcMem8 (OpMem8 << SrcShift)
820207c8 118#define SrcAccHi (OpAccHi << SrcShift)
0fe59128 119#define SrcMask (OpMask << SrcShift)
221192bd
MT		 120#define BitOp (1<<11)
121#define MemAbs (1<<12) /* Memory operand is absolute displacement */
122#define String (1<<13) /* String instruction (rep capable) */
123#define Stack (1<<14) /* Stack instruction (push/pop) */
124#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
125#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
126#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
127#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
128#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
045a282c 129#define Escape (5<<15) /* Escape to coprocessor instruction */
39f062ff 130#define InstrDual (6<<15) /* Alternate instruction decoding of mod == 3 */
2276b511 131#define ModeDual (7<<15) /* Different instruction for 32/64 bit */
221192bd 132#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 133/* Generic ModRM decode. */
134#define ModRM (1<<19)
135/* Destination is only written; never read. */
136#define Mov (1<<20)
d8769fed 137/* Misc flags */
8ea7d6ae 138#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
b51e974f 139#define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */
5a506b12 140#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 141#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 142#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 143#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 144#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 145#define No64 (1<<28)
d5ae7ce8 146#define PageTable (1 << 29) /* instruction used to write page table */
0b789eee 147#define NotImpl (1 << 30) /* instruction is not implemented */
0dc8d10f 148/* Source 2 operand type */
0b789eee 149#define Src2Shift (31)
4dd6a57d 150#define Src2None (OpNone << Src2Shift)
ab2c5ce6 151#define Src2Mem (OpMem << Src2Shift)
4dd6a57d
AK		 152#define Src2CL (OpCL << Src2Shift)
153#define Src2ImmByte (OpImmByte << Src2Shift)
154#define Src2One (OpOne << Src2Shift)
155#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 156#define Src2ES (OpES << Src2Shift)
157#define Src2CS (OpCS << Src2Shift)
158#define Src2SS (OpSS << Src2Shift)
159#define Src2DS (OpDS << Src2Shift)
160#define Src2FS (OpFS << Src2Shift)
161#define Src2GS (OpGS << Src2Shift)
4dd6a57d 162#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 163#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
48520187 164#define AlignMask ((u64)7 << 41)
1c11b376 165#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
48520187
RK		 166#define Unaligned ((u64)2 << 41) /* Explicitly unaligned (e.g. MOVDQU) */
167#define Avx ((u64)3 << 41) /* Advanced Vector Extensions */
168#define Aligned16 ((u64)4 << 41) /* Aligned to 16 byte boundary (e.g. FXSAVE) */
e28bbd44 169#define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
b6744dc3 170#define NoWrite ((u64)1 << 45) /* No writeback */
fb32b1ed 171#define SrcWrite ((u64)1 << 46) /* Write back src operand */
9b88ae99 172#define NoMod ((u64)1 << 47) /* Mod field is ignored */
d40a6898
PB		 173#define Intercept ((u64)1 << 48) /* Has valid intercept field */
174#define CheckPerm ((u64)1 << 49) /* Has valid check_perm field */
68efa764 175#define PrivUD ((u64)1 << 51) /* #UD instead of #GP on CPL > 0 */
58b7075d 176#define NearBranch ((u64)1 << 52) /* Near branches */
ed9aad21 177#define No16 ((u64)1 << 53) /* No 16 bit operand */
ab708099 178#define IncSP ((u64)1 << 54) /* SP is incremented before ModRM calc */
0f89b207 179#define TwoMemOp ((u64)1 << 55) /* Instruction has two memory operand */
6aa8b732 180
820207c8 181#define DstXacc (DstAccLo | SrcAccHi | SrcWrite)
6aa8b732 182
d0e53325
AK		 183#define X2(x...) x, x
184#define X3(x...) X2(x), x
185#define X4(x...) X2(x), X2(x)
186#define X5(x...) X4(x), x
187#define X6(x...) X4(x), X2(x)
188#define X7(x...) X4(x), X3(x)
189#define X8(x...) X4(x), X4(x)
190#define X16(x...) X8(x), X8(x)
83babbca 191
e28bbd44
AK		 192#define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
193#define FASTOP_SIZE 8
194
195/*
196 * fastop functions have a special calling convention:
197 *
017da7b6
AK		 198 * dst: rax (in/out)
199 * src: rdx (in/out)
e28bbd44
AK		 200 * src2: rcx (in)
201 * flags: rflags (in/out)
b8c0b6ae 202 * ex: rsi (in:fastop pointer, out:zero if exception)
e28bbd44
AK		 203 *
204 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
205 * different operand sizes can be reached by calculation, rather than a jump
206 * table (which would be bigger than the code).
207 *
208 * fastop functions are declared as taking a never-defined fastop parameter,
209 * so they can't be called from C directly.
210 */
211
212struct fastop;
213
d65b1dee 214struct opcode {
b1ea50b2
AK		 215 u64 flags : 56;
216 u64 intercept : 8;
120df890 217 union {
ef65c889 218 int (*execute)(struct x86_emulate_ctxt *ctxt);
fd0a0d82
MK		 219 const struct opcode *group;
220 const struct group_dual *gdual;
221 const struct gprefix *gprefix;
045a282c 222 const struct escape *esc;
39f062ff 223 const struct instr_dual *idual;
2276b511 224 const struct mode_dual *mdual;
e28bbd44 225 void (*fastop)(struct fastop *fake);
120df890 226 } u;
d09beabd 227 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 228};
229
230struct group_dual {
231 struct opcode mod012[8];
232 struct opcode mod3[8];
d65b1dee
AK		 233};
234
0d7cdee8
AK		 235struct gprefix {
236 struct opcode pfx_no;
237 struct opcode pfx_66;
238 struct opcode pfx_f2;
239 struct opcode pfx_f3;
240};
241
045a282c
GN		 242struct escape {
243 struct opcode op[8];
244 struct opcode high[64];
245};
246
39f062ff
NA		 247struct instr_dual {
248 struct opcode mod012;
249 struct opcode mod3;
250};
251
2276b511
NA		 252struct mode_dual {
253 struct opcode mode32;
254 struct opcode mode64;
255};
256
62bd430e 257#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
62bd430e 258
3dc4bc4f
NA		 259enum x86_transfer_type {
260 X86_TRANSFER_NONE,
261 X86_TRANSFER_CALL_JMP,
262 X86_TRANSFER_RET,
263 X86_TRANSFER_TASK_SWITCH,
264};
265
dd856efa
AK		 266static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
267{
268 if (!(ctxt->regs_valid & (1 << nr))) {
269 ctxt->regs_valid |= 1 << nr;
270 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
271 }
272 return ctxt->_regs[nr];
273}
274
275static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
276{
277 ctxt->regs_valid |= 1 << nr;
278 ctxt->regs_dirty |= 1 << nr;
279 return &ctxt->_regs[nr];
280}
281
282static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
283{
284 reg_read(ctxt, nr);
285 return reg_write(ctxt, nr);
286}
287
288static void writeback_registers(struct x86_emulate_ctxt *ctxt)
289{
290 unsigned reg;
291
292 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
293 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
294}
295
296static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
297{
298 ctxt->regs_dirty = 0;
299 ctxt->regs_valid = 0;
300}
301
6aa8b732
AK		 302/*
303 * These EFLAGS bits are restored from saved value during emulation, and
304 * any changes are written back to the saved value after emulation.
305 */
0efb0440
NA		 306#define EFLAGS_MASK (X86_EFLAGS_OF|X86_EFLAGS_SF|X86_EFLAGS_ZF|X86_EFLAGS_AF|\
307 X86_EFLAGS_PF|X86_EFLAGS_CF)
6aa8b732 308
dda96d8f
AK		 309#ifdef CONFIG_X86_64
310#define ON64(x) x
311#else
312#define ON64(x)
313#endif
314
4d758349
AK		 315static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));
316
1482a082
JP		 317#define FOP_FUNC(name) \
318 ".align " __stringify(FASTOP_SIZE) " \n\t" \
319 ".type " name ", @function \n\t" \
320 name ":\n\t"
321
b7d491e7
AK		 322#define FOP_RET "ret \n\t"
323
324#define FOP_START(op) \
325 extern void em_##op(struct fastop *fake); \
326 asm(".pushsection .text, \"ax\" \n\t" \
327 ".global em_" #op " \n\t" \
1482a082 328 FOP_FUNC("em_" #op)
b7d491e7
AK		 329
330#define FOP_END \
331 ".popsection")
332
1482a082
JP		 333#define FOPNOP() \
334 FOP_FUNC(__stringify(__UNIQUE_ID(nop))) \
335 FOP_RET
0bdea068 336
b7d491e7 337#define FOP1E(op, dst) \
1482a082
JP		 338 FOP_FUNC(#op "_" #dst) \
339 "10: " #op " %" #dst " \n\t" FOP_RET
b8c0b6ae
AK		 340
341#define FOP1EEX(op, dst) \
342 FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception)
b7d491e7
AK		 343
344#define FASTOP1(op) \
345 FOP_START(op) \
346 FOP1E(op##b, al) \
347 FOP1E(op##w, ax) \
348 FOP1E(op##l, eax) \
349 ON64(FOP1E(op##q, rax)) \
350 FOP_END
351
b9fa409b
AK		 352/* 1-operand, using src2 (for MUL/DIV r/m) */
353#define FASTOP1SRC2(op, name) \
354 FOP_START(name) \
355 FOP1E(op, cl) \
356 FOP1E(op, cx) \
357 FOP1E(op, ecx) \
358 ON64(FOP1E(op, rcx)) \
359 FOP_END
360
b8c0b6ae
AK		 361/* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */
362#define FASTOP1SRC2EX(op, name) \
363 FOP_START(name) \
364 FOP1EEX(op, cl) \
365 FOP1EEX(op, cx) \
366 FOP1EEX(op, ecx) \
367 ON64(FOP1EEX(op, rcx)) \
368 FOP_END
369
f7857f35 370#define FOP2E(op, dst, src) \
1482a082
JP		 371 FOP_FUNC(#op "_" #dst "_" #src) \
372 #op " %" #src ", %" #dst " \n\t" FOP_RET
f7857f35
AK		 373
374#define FASTOP2(op) \
375 FOP_START(op) \
017da7b6
AK		 376 FOP2E(op##b, al, dl) \
377 FOP2E(op##w, ax, dx) \
378 FOP2E(op##l, eax, edx) \
379 ON64(FOP2E(op##q, rax, rdx)) \
f7857f35
AK		 380 FOP_END
381
11c363ba
AK		 382/* 2 operand, word only */
383#define FASTOP2W(op) \
384 FOP_START(op) \
385 FOPNOP() \
017da7b6
AK		 386 FOP2E(op##w, ax, dx) \
387 FOP2E(op##l, eax, edx) \
388 ON64(FOP2E(op##q, rax, rdx)) \
11c363ba
AK		 389 FOP_END
390
007a3b54
AK		 391/* 2 operand, src is CL */
392#define FASTOP2CL(op) \
393 FOP_START(op) \
394 FOP2E(op##b, al, cl) \
395 FOP2E(op##w, ax, cl) \
396 FOP2E(op##l, eax, cl) \
397 ON64(FOP2E(op##q, rax, cl)) \
398 FOP_END
399
5aca3722
NA		 400/* 2 operand, src and dest are reversed */
401#define FASTOP2R(op, name) \
402 FOP_START(name) \
403 FOP2E(op##b, dl, al) \
404 FOP2E(op##w, dx, ax) \
405 FOP2E(op##l, edx, eax) \
406 ON64(FOP2E(op##q, rdx, rax)) \
407 FOP_END
408
0bdea068 409#define FOP3E(op, dst, src, src2) \
1482a082
JP		 410 FOP_FUNC(#op "_" #dst "_" #src "_" #src2) \
411 #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET
0bdea068
AK		 412
413/* 3-operand, word-only, src2=cl */
414#define FASTOP3WCL(op) \
415 FOP_START(op) \
416 FOPNOP() \
017da7b6
AK		 417 FOP3E(op##w, ax, dx, cl) \
418 FOP3E(op##l, eax, edx, cl) \
419 ON64(FOP3E(op##q, rax, rdx, cl)) \
0bdea068
AK		 420 FOP_END
421
9ae9feba 422/* Special case for SETcc - 1 instruction per cc */
1482a082
JP		 423#define FOP_SETCC(op) \
424 ".align 4 \n\t" \
425 ".type " #op ", @function \n\t" \
426 #op ": \n\t" \
427 #op " %al \n\t" \
428 FOP_RET
9ae9feba 429
f26e6016
JP		 430asm(".pushsection .fixup, \"ax\"\n"
431 ".global kvm_fastop_exception \n"
432 "kvm_fastop_exception: xor %esi, %esi; ret\n"
433 ".popsection");
b8c0b6ae 434
9ae9feba
AK		 435FOP_START(setcc)
436FOP_SETCC(seto)
437FOP_SETCC(setno)
438FOP_SETCC(setc)
439FOP_SETCC(setnc)
440FOP_SETCC(setz)
441FOP_SETCC(setnz)
442FOP_SETCC(setbe)
443FOP_SETCC(setnbe)
444FOP_SETCC(sets)
445FOP_SETCC(setns)
446FOP_SETCC(setp)
447FOP_SETCC(setnp)
448FOP_SETCC(setl)
449FOP_SETCC(setnl)
450FOP_SETCC(setle)
451FOP_SETCC(setnle)
452FOP_END;
453
326f578f
PB		 454FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET
455FOP_END;
456
aabba3c6
RK		 457/*
458 * XXX: inoutclob user must know where the argument is being expanded.
e9666d10 459 * Relying on CONFIG_CC_HAS_ASM_GOTO would allow us to remove _fault.
aabba3c6
RK		 460 */
461#define asm_safe(insn, inoutclob...) \
462({ \
463 int _fault = 0; \
464 \
465 asm volatile("1:" insn "\n" \
466 "2:\n" \
467 ".pushsection .fixup, \"ax\"\n" \
468 "3: movl $1, %[_fault]\n" \
469 " jmp 2b\n" \
470 ".popsection\n" \
471 _ASM_EXTABLE(1b, 3b) \
472 : [_fault] "+qm"(_fault) inoutclob ); \
473 \
474 _fault ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE; \
475})
476
8a76d7f2
JR		 477static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
478 enum x86_intercept intercept,
479 enum x86_intercept_stage stage)
480{
481 struct x86_instruction_info info = {
482 .intercept = intercept,
9dac77fa
AK		 483 .rep_prefix = ctxt->rep_prefix,
484 .modrm_mod = ctxt->modrm_mod,
485 .modrm_reg = ctxt->modrm_reg,
486 .modrm_rm = ctxt->modrm_rm,
487 .src_val = ctxt->src.val64,
6cbc5f5a 488 .dst_val = ctxt->dst.val64,
9dac77fa
AK		 489 .src_bytes = ctxt->src.bytes,
490 .dst_bytes = ctxt->dst.bytes,
491 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 492 .next_rip = ctxt->eip,
493 };
494
2953538e 495 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 496}
497
f47cfa31
AK		 498static void assign_masked(ulong *dest, ulong src, ulong mask)
499{
500 *dest = (*dest & ~mask) | (src & mask);
501}
502
6fd8e127
NA		 503static void assign_register(unsigned long *reg, u64 val, int bytes)
504{
505 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
506 switch (bytes) {
507 case 1:
508 *(u8 *)reg = (u8)val;
509 break;
510 case 2:
511 *(u16 *)reg = (u16)val;
512 break;
513 case 4:
514 *reg = (u32)val;
515 break; /* 64b: zero-extend */
516 case 8:
517 *reg = val;
518 break;
519 }
520}
521
9dac77fa 522static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 523{
9dac77fa 524 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 525}
526
f47cfa31
AK		 527static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
528{
529 u16 sel;
530 struct desc_struct ss;
531
532 if (ctxt->mode == X86EMUL_MODE_PROT64)
533 return ~0UL;
534 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
535 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
536}
537
612e89f0
AK		 538static int stack_size(struct x86_emulate_ctxt *ctxt)
539{
540 return (__fls(stack_mask(ctxt)) + 1) >> 3;
541}
542
6aa8b732 543/* Access/update address held in a register, based on addressing mode. */
e4706772 544static inline unsigned long
9dac77fa 545address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 546{
9dac77fa 547 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 548 return reg;
549 else
9dac77fa 550 return reg & ad_mask(ctxt);
e4706772
HH		 551}
552
553static inline unsigned long
01485a22 554register_address(struct x86_emulate_ctxt *ctxt, int reg)
e4706772 555{
01485a22 556 return address_mask(ctxt, reg_read(ctxt, reg));
e4706772
HH		 557}
558
5ad105e5
AK		 559static void masked_increment(ulong *reg, ulong mask, int inc)
560{
561 assign_masked(reg, *reg + inc, mask);
562}
563
7a957275 564static inline void
01485a22 565register_address_increment(struct x86_emulate_ctxt *ctxt, int reg, int inc)
7a957275 566{
ee122a71 567 ulong *preg = reg_rmw(ctxt, reg);
5ad105e5 568
ee122a71 569 assign_register(preg, *preg + inc, ctxt->ad_bytes);
5ad105e5
AK		 570}
571
572static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
573{
dd856efa 574 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
7a957275 575}
6aa8b732 576
56697687
AK		 577static u32 desc_limit_scaled(struct desc_struct *desc)
578{
579 u32 limit = get_desc_limit(desc);
580
581 return desc->g ? (limit << 12) | 0xfff : limit;
582}
583
7b105ca2 584static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 585{
586 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
587 return 0;
588
7b105ca2 589 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 590}
591
35d3d4a1
AK		 592static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
593 u32 error, bool valid)
54b8486f 594{
e0ad0b47 595 WARN_ON(vec > 0x1f);
da9cb575
AK		 596 ctxt->exception.vector = vec;
597 ctxt->exception.error_code = error;
598 ctxt->exception.error_code_valid = valid;
35d3d4a1 599 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 600}
601
3b88e41a
JR		 602static int emulate_db(struct x86_emulate_ctxt *ctxt)
603{
604 return emulate_exception(ctxt, DB_VECTOR, 0, false);
605}
606
35d3d4a1 607static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 608{
35d3d4a1 609 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 610}
611
618ff15d
AK		 612static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
613{
614 return emulate_exception(ctxt, SS_VECTOR, err, true);
615}
616
35d3d4a1 617static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 618{
35d3d4a1 619 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 620}
621
35d3d4a1 622static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 623{
35d3d4a1 624 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 625}
626
34d1f490
AK		 627static int emulate_de(struct x86_emulate_ctxt *ctxt)
628{
35d3d4a1 629 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 630}
631
1253791d
AK		 632static int emulate_nm(struct x86_emulate_ctxt *ctxt)
633{
634 return emulate_exception(ctxt, NM_VECTOR, 0, false);
635}
636
1aa36616
AK		 637static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
638{
639 u16 selector;
640 struct desc_struct desc;
641
642 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
643 return selector;
644}
645
646static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
647 unsigned seg)
648{
649 u16 dummy;
650 u32 base3;
651 struct desc_struct desc;
652
653 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
654 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
655}
656
1c11b376
AK		 657/*
658 * x86 defines three classes of vector instructions: explicitly
659 * aligned, explicitly unaligned, and the rest, which change behaviour
660 * depending on whether they're AVX encoded or not.
661 *
662 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
d3fe959f
RK		 663 * subject to the same check. FXSAVE and FXRSTOR are checked here too as their
664 * 512 bytes of data must be aligned to a 16 byte boundary.
1c11b376 665 */
d3fe959f 666static unsigned insn_alignment(struct x86_emulate_ctxt *ctxt, unsigned size)
1c11b376 667{
48520187 668 u64 alignment = ctxt->d & AlignMask;
1c11b376 669
1c11b376 670 if (likely(size < 16))
d3fe959f 671 return 1;
1c11b376 672
48520187
RK		 673 switch (alignment) {
674 case Unaligned:
675 case Avx:
d3fe959f 676 return 1;
48520187 677 case Aligned16:
d3fe959f 678 return 16;
48520187
RK		 679 case Aligned:
680 default:
d3fe959f 681 return size;
48520187 682 }
1c11b376
AK		 683}
684
d09155d2
PB		 685static __always_inline int __linearize(struct x86_emulate_ctxt *ctxt,
686 struct segmented_address addr,
687 unsigned *max_size, unsigned size,
688 bool write, bool fetch,
d50eaa18 689 enum x86emul_mode mode, ulong *linear)
52fd8b44 690{
618ff15d
AK		 691 struct desc_struct desc;
692 bool usable;
52fd8b44 693 ulong la;
618ff15d 694 u32 lim;
1aa36616 695 u16 sel;
fd8cb433 696 u8 va_bits;
52fd8b44 697
7b105ca2 698 la = seg_base(ctxt, addr.seg) + addr.ea;
fd56e154 699 *max_size = 0;
d50eaa18 700 switch (mode) {
618ff15d 701 case X86EMUL_MODE_PROT64:
0c1d77f4 702 *linear = la;
fd8cb433
YZ		 703 va_bits = ctxt_virt_addr_bits(ctxt);
704 if (get_canonical(la, va_bits) != la)
abc7d8a4 705 goto bad;
fd56e154 706
fd8cb433 707 *max_size = min_t(u64, ~0u, (1ull << va_bits) - la);
fd56e154
PB		 708 if (size > *max_size)
709 goto bad;
618ff15d
AK		 710 break;
711 default:
0c1d77f4 712 *linear = la = (u32)la;
1aa36616
AK		 713 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
714 addr.seg);
618ff15d
AK		 715 if (!usable)
716 goto bad;
58b7825b
GN		 717 /* code segment in protected mode or read-only data segment */
718 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
719 || !(desc.type & 2)) && write)
618ff15d
AK		 720 goto bad;
721 /* unreadable code segment */
3d9b938e 722 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 723 goto bad;
724 lim = desc_limit_scaled(&desc);
997b0412 725 if (!(desc.type & 8) && (desc.type & 4)) {
fc058680 726 /* expand-down segment */
fd56e154 727 if (addr.ea <= lim)
618ff15d
AK		 728 goto bad;
729 lim = desc.d ? 0xffffffff : 0xffff;
618ff15d 730 }
997b0412
PB		 731 if (addr.ea > lim)
732 goto bad;
bac15531
NA		 733 if (lim == 0xffffffff)
734 *max_size = ~0u;
735 else {
736 *max_size = (u64)lim + 1 - addr.ea;
737 if (size > *max_size)
738 goto bad;
739 }
618ff15d
AK		 740 break;
741 }
d3fe959f 742 if (la & (insn_alignment(ctxt, size) - 1))
1c11b376 743 return emulate_gp(ctxt, 0);
52fd8b44 744 return X86EMUL_CONTINUE;
618ff15d
AK		 745bad:
746 if (addr.seg == VCPU_SREG_SS)
3606189f 747 return emulate_ss(ctxt, 0);
618ff15d 748 else
3606189f 749 return emulate_gp(ctxt, 0);
52fd8b44
AK		 750}
751
3d9b938e
NE		 752static int linearize(struct x86_emulate_ctxt *ctxt,
753 struct segmented_address addr,
754 unsigned size, bool write,
755 ulong *linear)
756{
fd56e154 757 unsigned max_size;
d50eaa18
NA		 758 return __linearize(ctxt, addr, &max_size, size, write, false,
759 ctxt->mode, linear);
3d9b938e
NE		 760}
761
d50eaa18
NA		 762static inline int assign_eip(struct x86_emulate_ctxt *ctxt, ulong dst,
763 enum x86emul_mode mode)
764{
765 ulong linear;
766 int rc;
767 unsigned max_size;
768 struct segmented_address addr = { .seg = VCPU_SREG_CS,
769 .ea = dst };
770
771 if (ctxt->op_bytes != sizeof(unsigned long))
772 addr.ea = dst & ((1UL << (ctxt->op_bytes << 3)) - 1);
773 rc = __linearize(ctxt, addr, &max_size, 1, false, true, mode, &linear);
774 if (rc == X86EMUL_CONTINUE)
775 ctxt->_eip = addr.ea;
776 return rc;
777}
778
779static inline int assign_eip_near(struct x86_emulate_ctxt *ctxt, ulong dst)
780{
781 return assign_eip(ctxt, dst, ctxt->mode);
3d9b938e
NE		 782}
783
d50eaa18
NA		 784static int assign_eip_far(struct x86_emulate_ctxt *ctxt, ulong dst,
785 const struct desc_struct *cs_desc)
786{
787 enum x86emul_mode mode = ctxt->mode;
82268083 788 int rc;
d50eaa18
NA		 789
790#ifdef CONFIG_X86_64
82268083
NA		 791 if (ctxt->mode >= X86EMUL_MODE_PROT16) {
792 if (cs_desc->l) {
793 u64 efer = 0;
d50eaa18 794
82268083
NA		 795 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
796 if (efer & EFER_LMA)
797 mode = X86EMUL_MODE_PROT64;
798 } else
799 mode = X86EMUL_MODE_PROT32; /* temporary value */
d50eaa18
NA		 800 }
801#endif
802 if (mode == X86EMUL_MODE_PROT16 || mode == X86EMUL_MODE_PROT32)
803 mode = cs_desc->d ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
82268083
NA		 804 rc = assign_eip(ctxt, dst, mode);
805 if (rc == X86EMUL_CONTINUE)
806 ctxt->mode = mode;
807 return rc;
d50eaa18
NA		 808}
809
810static inline int jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
811{
812 return assign_eip_near(ctxt, ctxt->_eip + rel);
813}
3d9b938e 814
79367a65
PB		 815static int linear_read_system(struct x86_emulate_ctxt *ctxt, ulong linear,
816 void *data, unsigned size)
817{
3c9fa24c 818 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception, true);
79367a65
PB		 819}
820
821static int linear_write_system(struct x86_emulate_ctxt *ctxt,
822 ulong linear, void *data,
823 unsigned int size)
824{
3c9fa24c 825 return ctxt->ops->write_std(ctxt, linear, data, size, &ctxt->exception, true);
79367a65
PB		 826}
827
3ca3ac4d
AK		 828static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
829 struct segmented_address addr,
830 void *data,
831 unsigned size)
832{
9fa088f4
AK		 833 int rc;
834 ulong linear;
835
83b8795a 836 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 837 if (rc != X86EMUL_CONTINUE)
838 return rc;
3c9fa24c 839 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception, false);
3ca3ac4d
AK		 840}
841
129a72a0
SR		 842static int segmented_write_std(struct x86_emulate_ctxt *ctxt,
843 struct segmented_address addr,
844 void *data,
845 unsigned int size)
846{
847 int rc;
848 ulong linear;
849
850 rc = linearize(ctxt, addr, size, true, &linear);
851 if (rc != X86EMUL_CONTINUE)
852 return rc;
3c9fa24c 853 return ctxt->ops->write_std(ctxt, linear, data, size, &ctxt->exception, false);
129a72a0
SR		 854}
855
807941b1 856/*
285ca9e9 857 * Prefetch the remaining bytes of the instruction without crossing page
807941b1
TY		 858 * boundary if they are not in fetch_cache yet.
859 */
9506d57d 860static int __do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, int op_size)
62266869 861{
62266869 862 int rc;
fd56e154 863 unsigned size, max_size;
285ca9e9 864 unsigned long linear;
17052f16 865 int cur_size = ctxt->fetch.end - ctxt->fetch.data;
285ca9e9 866 struct segmented_address addr = { .seg = VCPU_SREG_CS,
17052f16
PB		 867 .ea = ctxt->eip + cur_size };
868
fd56e154
PB		 869 /*
870 * We do not know exactly how many bytes will be needed, and
871 * __linearize is expensive, so fetch as much as possible. We
872 * just have to avoid going beyond the 15 byte limit, the end
873 * of the segment, or the end of the page.
874 *
875 * __linearize is called with size 0 so that it does not do any
876 * boundary check itself. Instead, we use max_size to check
877 * against op_size.
878 */
d50eaa18
NA		 879 rc = __linearize(ctxt, addr, &max_size, 0, false, true, ctxt->mode,
880 &linear);
719d5a9b
PB		 881 if (unlikely(rc != X86EMUL_CONTINUE))
882 return rc;
883
fd56e154 884 size = min_t(unsigned, 15UL ^ cur_size, max_size);
719d5a9b 885 size = min_t(unsigned, size, PAGE_SIZE - offset_in_page(linear));
5cfc7e0f
PB		 886
887 /*
888 * One instruction can only straddle two pages,
889 * and one has been loaded at the beginning of
890 * x86_decode_insn. So, if not enough bytes
891 * still, we must have hit the 15-byte boundary.
892 */
893 if (unlikely(size < op_size))
fd56e154
PB		 894 return emulate_gp(ctxt, 0);
895
17052f16 896 rc = ctxt->ops->fetch(ctxt, linear, ctxt->fetch.end,
285ca9e9
PB		 897 size, &ctxt->exception);
898 if (unlikely(rc != X86EMUL_CONTINUE))
899 return rc;
17052f16 900 ctxt->fetch.end += size;
3e2815e9 901 return X86EMUL_CONTINUE;
62266869
AK		 902}
903
9506d57d
PB		 904static __always_inline int do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt,
905 unsigned size)
62266869 906{
08da44ae
NA		 907 unsigned done_size = ctxt->fetch.end - ctxt->fetch.ptr;
908
909 if (unlikely(done_size < size))
910 return __do_insn_fetch_bytes(ctxt, size - done_size);
9506d57d
PB		 911 else
912 return X86EMUL_CONTINUE;
62266869
AK		 913}
914
67cbc90d 915/* Fetch next part of the instruction being emulated. */
e85a1085 916#define insn_fetch(_type, _ctxt) \
9506d57d 917({ _type _x; \
9506d57d
PB		 918 \
919 rc = do_insn_fetch_bytes(_ctxt, sizeof(_type)); \
67cbc90d
TY		 920 if (rc != X86EMUL_CONTINUE) \
921 goto done; \
9506d57d 922 ctxt->_eip += sizeof(_type); \
8616abc2 923 memcpy(&_x, ctxt->fetch.ptr, sizeof(_type)); \
17052f16 924 ctxt->fetch.ptr += sizeof(_type); \
9506d57d 925 _x; \
67cbc90d
TY		 926})
927
807941b1 928#define insn_fetch_arr(_arr, _size, _ctxt) \
9506d57d 929({ \
9506d57d 930 rc = do_insn_fetch_bytes(_ctxt, _size); \
67cbc90d
TY		 931 if (rc != X86EMUL_CONTINUE) \
932 goto done; \
9506d57d 933 ctxt->_eip += (_size); \
17052f16
PB		 934 memcpy(_arr, ctxt->fetch.ptr, _size); \
935 ctxt->fetch.ptr += (_size); \
67cbc90d
TY		 936})
937
1e3c5cb0
RR		 938/*
939 * Given the 'reg' portion of a ModRM byte, and a register block, return a
940 * pointer into the block that addresses the relevant register.
941 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
942 */
dd856efa 943static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
aa9ac1a6 944 int byteop)
6aa8b732
AK		 945{
946 void *p;
aa9ac1a6 947 int highbyte_regs = (ctxt->rex_prefix == 0) && byteop;
6aa8b732 948
6aa8b732 949 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
dd856efa
AK		 950 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
951 else
952 p = reg_rmw(ctxt, modrm_reg);
6aa8b732
AK		 953 return p;
954}
955
956static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 957 struct segmented_address addr,
6aa8b732
AK		 958 u16 *size, unsigned long *address, int op_bytes)
959{
960 int rc;
961
962 if (op_bytes == 2)
963 op_bytes = 3;
964 *address = 0;
3ca3ac4d 965 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 966 if (rc != X86EMUL_CONTINUE)
6aa8b732 967 return rc;
30b31ab6 968 addr.ea += 2;
3ca3ac4d 969 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 970 return rc;
971}
972
34b77652
AK		 973FASTOP2(add);
974FASTOP2(or);
975FASTOP2(adc);
976FASTOP2(sbb);
977FASTOP2(and);
978FASTOP2(sub);
979FASTOP2(xor);
980FASTOP2(cmp);
981FASTOP2(test);
982
b9fa409b
AK		 983FASTOP1SRC2(mul, mul_ex);
984FASTOP1SRC2(imul, imul_ex);
b8c0b6ae
AK		 985FASTOP1SRC2EX(div, div_ex);
986FASTOP1SRC2EX(idiv, idiv_ex);
b9fa409b 987
34b77652
AK		 988FASTOP3WCL(shld);
989FASTOP3WCL(shrd);
990
991FASTOP2W(imul);
992
993FASTOP1(not);
994FASTOP1(neg);
995FASTOP1(inc);
996FASTOP1(dec);
997
998FASTOP2CL(rol);
999FASTOP2CL(ror);
1000FASTOP2CL(rcl);
1001FASTOP2CL(rcr);
1002FASTOP2CL(shl);
1003FASTOP2CL(shr);
1004FASTOP2CL(sar);
1005
1006FASTOP2W(bsf);
1007FASTOP2W(bsr);
1008FASTOP2W(bt);
1009FASTOP2W(bts);
1010FASTOP2W(btr);
1011FASTOP2W(btc);
1012
e47a5f5f
AK		 1013FASTOP2(xadd);
1014
5aca3722
NA		 1015FASTOP2R(cmp, cmp_r);
1016
900efe20
NA		 1017static int em_bsf_c(struct x86_emulate_ctxt *ctxt)
1018{
1019 /* If src is zero, do not writeback, but update flags */
1020 if (ctxt->src.val == 0)
1021 ctxt->dst.type = OP_NONE;
1022 return fastop(ctxt, em_bsf);
1023}
1024
1025static int em_bsr_c(struct x86_emulate_ctxt *ctxt)
1026{
1027 /* If src is zero, do not writeback, but update flags */
1028 if (ctxt->src.val == 0)
1029 ctxt->dst.type = OP_NONE;
1030 return fastop(ctxt, em_bsr);
1031}
1032
cb7390fe 1033static __always_inline u8 test_cc(unsigned int condition, unsigned long flags)
bbe9abbd 1034{
9ae9feba
AK		 1035 u8 rc;
1036 void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
bbe9abbd 1037
9ae9feba 1038 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
1a29b5b7
PZ		 1039 asm("push %[flags]; popf; " CALL_NOSPEC
1040 : "=a"(rc) : [thunk_target]"r"(fop), [flags]"r"(flags));
9ae9feba 1041 return rc;
bbe9abbd
NK		 1042}
1043
91ff3cb4
AK		 1044static void fetch_register_operand(struct operand *op)
1045{
1046 switch (op->bytes) {
1047 case 1:
1048 op->val = *(u8 *)op->addr.reg;
1049 break;
1050 case 2:
1051 op->val = *(u16 *)op->addr.reg;
1052 break;
1053 case 4:
1054 op->val = *(u32 *)op->addr.reg;
1055 break;
1056 case 8:
1057 op->val = *(u64 *)op->addr.reg;
1058 break;
1059 }
1060}
1061
1253791d
AK		 1062static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
1063{
1253791d 1064 switch (reg) {
89a87c67
MK		 1065 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
1066 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
1067 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
1068 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
1069 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
1070 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
1071 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
1072 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
1253791d 1073#ifdef CONFIG_X86_64
89a87c67
MK		 1074 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
1075 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
1076 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
1077 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
1078 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
1079 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
1080 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
1081 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
1253791d
AK		 1082#endif
1083 default: BUG();
1084 }
1253791d
AK		 1085}
1086
1087static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
1088 int reg)
1089{
1253791d 1090 switch (reg) {
89a87c67
MK		 1091 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
1092 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
1093 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
1094 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
1095 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
1096 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
1097 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
1098 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
1253791d 1099#ifdef CONFIG_X86_64
89a87c67
MK		 1100 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
1101 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
1102 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
1103 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
1104 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
1105 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
1106 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
1107 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
1253791d
AK		 1108#endif
1109 default: BUG();
1110 }
1253791d
AK		 1111}
1112
cbe2c9d3
AK		 1113static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1114{
cbe2c9d3
AK		 1115 switch (reg) {
1116 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
1117 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
1118 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
1119 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
1120 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
1121 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
1122 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
1123 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
1124 default: BUG();
1125 }
cbe2c9d3
AK		 1126}
1127
1128static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1129{
cbe2c9d3
AK		 1130 switch (reg) {
1131 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
1132 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
1133 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
1134 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
1135 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
1136 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
1137 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
1138 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
1139 default: BUG();
1140 }
cbe2c9d3
AK		 1141}
1142
045a282c
GN		 1143static int em_fninit(struct x86_emulate_ctxt *ctxt)
1144{
1145 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1146 return emulate_nm(ctxt);
1147
045a282c 1148 asm volatile("fninit");
045a282c
GN		 1149 return X86EMUL_CONTINUE;
1150}
1151
1152static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
1153{
1154 u16 fcw;
1155
1156 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1157 return emulate_nm(ctxt);
1158
045a282c 1159 asm volatile("fnstcw %0": "+m"(fcw));
045a282c 1160
045a282c
GN		 1161 ctxt->dst.val = fcw;
1162
1163 return X86EMUL_CONTINUE;
1164}
1165
1166static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
1167{
1168 u16 fsw;
1169
1170 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1171 return emulate_nm(ctxt);
1172
045a282c 1173 asm volatile("fnstsw %0": "+m"(fsw));
045a282c 1174
045a282c
GN		 1175 ctxt->dst.val = fsw;
1176
1177 return X86EMUL_CONTINUE;
1178}
1179
1253791d 1180static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 1181 struct operand *op)
3c118e24 1182{
9dac77fa 1183 unsigned reg = ctxt->modrm_reg;
33615aa9 1184
9dac77fa
AK		 1185 if (!(ctxt->d & ModRM))
1186 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 1187
9dac77fa 1188 if (ctxt->d & Sse) {
1253791d
AK		 1189 op->type = OP_XMM;
1190 op->bytes = 16;
1191 op->addr.xmm = reg;
1192 read_sse_reg(ctxt, &op->vec_val, reg);
1193 return;
1194 }
cbe2c9d3
AK		 1195 if (ctxt->d & Mmx) {
1196 reg &= 7;
1197 op->type = OP_MM;
1198 op->bytes = 8;
1199 op->addr.mm = reg;
1200 return;
1201 }
1253791d 1202
3c118e24 1203 op->type = OP_REG;
6d4d85ec
GN		 1204 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1205 op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp);
1206
91ff3cb4 1207 fetch_register_operand(op);
3c118e24
AK		 1208 op->orig_val = op->val;
1209}
1210
a6e3407b
AK		 1211static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1212{
1213 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1214 ctxt->modrm_seg = VCPU_SREG_SS;
1215}
1216
1c73ef66 1217static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1218 struct operand *op)
1c73ef66 1219{
1c73ef66 1220 u8 sib;
02357bdc 1221 int index_reg, base_reg, scale;
3e2815e9 1222 int rc = X86EMUL_CONTINUE;
2dbd0dd7 1223 ulong modrm_ea = 0;
1c73ef66 1224
02357bdc
BD		 1225 ctxt->modrm_reg = ((ctxt->rex_prefix << 1) & 8); /* REX.R */
1226 index_reg = (ctxt->rex_prefix << 2) & 8; /* REX.X */
1227 base_reg = (ctxt->rex_prefix << 3) & 8; /* REX.B */
1c73ef66 1228
02357bdc 1229 ctxt->modrm_mod = (ctxt->modrm & 0xc0) >> 6;
9dac77fa 1230 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
02357bdc 1231 ctxt->modrm_rm = base_reg | (ctxt->modrm & 0x07);
9dac77fa 1232 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 1233
9b88ae99 1234 if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) {
2dbd0dd7 1235 op->type = OP_REG;
9dac77fa 1236 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
8acb4207 1237 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm,
aa9ac1a6 1238 ctxt->d & ByteOp);
9dac77fa 1239 if (ctxt->d & Sse) {
1253791d
AK		 1240 op->type = OP_XMM;
1241 op->bytes = 16;
9dac77fa
AK		 1242 op->addr.xmm = ctxt->modrm_rm;
1243 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 1244 return rc;
1245 }
cbe2c9d3
AK		 1246 if (ctxt->d & Mmx) {
1247 op->type = OP_MM;
1248 op->bytes = 8;
bdc90722 1249 op->addr.mm = ctxt->modrm_rm & 7;
cbe2c9d3
AK		 1250 return rc;
1251 }
2dbd0dd7 1252 fetch_register_operand(op);
1c73ef66
AK		 1253 return rc;
1254 }
1255
2dbd0dd7
AK		 1256 op->type = OP_MEM;
1257
9dac77fa 1258 if (ctxt->ad_bytes == 2) {
dd856efa
AK		 1259 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1260 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1261 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1262 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1c73ef66
AK		 1263
1264 /* 16-bit ModR/M decode. */
9dac77fa 1265 switch (ctxt->modrm_mod) {
1c73ef66 1266 case 0:
9dac77fa 1267 if (ctxt->modrm_rm == 6)
e85a1085 1268 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1269 break;
1270 case 1:
e85a1085 1271 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1272 break;
1273 case 2:
e85a1085 1274 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1275 break;
1276 }
9dac77fa 1277 switch (ctxt->modrm_rm) {
1c73ef66 1278 case 0:
2dbd0dd7 1279 modrm_ea += bx + si;
1c73ef66
AK		 1280 break;
1281 case 1:
2dbd0dd7 1282 modrm_ea += bx + di;
1c73ef66
AK		 1283 break;
1284 case 2:
2dbd0dd7 1285 modrm_ea += bp + si;
1c73ef66
AK		 1286 break;
1287 case 3:
2dbd0dd7 1288 modrm_ea += bp + di;
1c73ef66
AK		 1289 break;
1290 case 4:
2dbd0dd7 1291 modrm_ea += si;
1c73ef66
AK		 1292 break;
1293 case 5:
2dbd0dd7 1294 modrm_ea += di;
1c73ef66
AK		 1295 break;
1296 case 6:
9dac77fa 1297 if (ctxt->modrm_mod != 0)
2dbd0dd7 1298 modrm_ea += bp;
1c73ef66
AK		 1299 break;
1300 case 7:
2dbd0dd7 1301 modrm_ea += bx;
1c73ef66
AK		 1302 break;
1303 }
9dac77fa
AK		 1304 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1305 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1306 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1307 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1308 } else {
1309 /* 32/64-bit ModR/M decode. */
9dac77fa 1310 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1311 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1312 index_reg |= (sib >> 3) & 7;
1313 base_reg |= sib & 7;
1314 scale = sib >> 6;
1315
9dac77fa 1316 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1317 modrm_ea += insn_fetch(s32, ctxt);
a6e3407b 1318 else {
dd856efa 1319 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b 1320 adjust_modrm_seg(ctxt, base_reg);
ab708099
NA		 1321 /* Increment ESP on POP [ESP] */
1322 if ((ctxt->d & IncSP) &&
1323 base_reg == VCPU_REGS_RSP)
1324 modrm_ea += ctxt->op_bytes;
a6e3407b 1325 }
dc71d0f1 1326 if (index_reg != 4)
dd856efa 1327 modrm_ea += reg_read(ctxt, index_reg) << scale;
9dac77fa 1328 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
5b38ab87 1329 modrm_ea += insn_fetch(s32, ctxt);
84411d85 1330 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1331 ctxt->rip_relative = 1;
a6e3407b
AK		 1332 } else {
1333 base_reg = ctxt->modrm_rm;
dd856efa 1334 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1335 adjust_modrm_seg(ctxt, base_reg);
1336 }
9dac77fa 1337 switch (ctxt->modrm_mod) {
1c73ef66 1338 case 1:
e85a1085 1339 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1340 break;
1341 case 2:
e85a1085 1342 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1343 break;
1344 }
1345 }
90de84f5 1346 op->addr.mem.ea = modrm_ea;
41061cdb
BD		 1347 if (ctxt->ad_bytes != 8)
1348 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
1349
1c73ef66
AK		 1350done:
1351 return rc;
1352}
1353
1354static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1355 struct operand *op)
1c73ef66 1356{
3e2815e9 1357 int rc = X86EMUL_CONTINUE;
1c73ef66 1358
2dbd0dd7 1359 op->type = OP_MEM;
9dac77fa 1360 switch (ctxt->ad_bytes) {
1c73ef66 1361 case 2:
e85a1085 1362 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1363 break;
1364 case 4:
e85a1085 1365 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1366 break;
1367 case 8:
e85a1085 1368 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1369 break;
1370 }
1371done:
1372 return rc;
1373}
1374
9dac77fa 1375static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1376{
7129eeca 1377 long sv = 0, mask;
35c843c4 1378
9dac77fa 1379 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
7dec5603 1380 mask = ~((long)ctxt->dst.bytes * 8 - 1);
35c843c4 1381
9dac77fa
AK		 1382 if (ctxt->src.bytes == 2)
1383 sv = (s16)ctxt->src.val & (s16)mask;
1384 else if (ctxt->src.bytes == 4)
1385 sv = (s32)ctxt->src.val & (s32)mask;
7dec5603
NA		 1386 else
1387 sv = (s64)ctxt->src.val & (s64)mask;
35c843c4 1388
1c1c35ae
NA		 1389 ctxt->dst.addr.mem.ea = address_mask(ctxt,
1390 ctxt->dst.addr.mem.ea + (sv >> 3));
35c843c4 1391 }
ba7ff2b7
WY		 1392
1393 /* only subword offset */
9dac77fa 1394 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1395}
1396
dde7e6d1 1397static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1398 unsigned long addr, void *dest, unsigned size)
6aa8b732 1399{
dde7e6d1 1400 int rc;
9dac77fa 1401 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1402
f23b070e
XG		 1403 if (mc->pos < mc->end)
1404 goto read_cached;
6aa8b732 1405
f23b070e
XG		 1406 WARN_ON((mc->end + size) >= sizeof(mc->data));
1407
1408 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1409 &ctxt->exception);
1410 if (rc != X86EMUL_CONTINUE)
1411 return rc;
1412
1413 mc->end += size;
1414
1415read_cached:
1416 memcpy(dest, mc->data + mc->pos, size);
1417 mc->pos += size;
dde7e6d1
AK		 1418 return X86EMUL_CONTINUE;
1419}
6aa8b732 1420
3ca3ac4d
AK		 1421static int segmented_read(struct x86_emulate_ctxt *ctxt,
1422 struct segmented_address addr,
1423 void *data,
1424 unsigned size)
1425{
9fa088f4
AK		 1426 int rc;
1427 ulong linear;
1428
83b8795a 1429 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1430 if (rc != X86EMUL_CONTINUE)
1431 return rc;
7b105ca2 1432 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1433}
1434
1435static int segmented_write(struct x86_emulate_ctxt *ctxt,
1436 struct segmented_address addr,
1437 const void *data,
1438 unsigned size)
1439{
9fa088f4
AK		 1440 int rc;
1441 ulong linear;
1442
83b8795a 1443 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1444 if (rc != X86EMUL_CONTINUE)
1445 return rc;
0f65dd70
AK		 1446 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1447 &ctxt->exception);
3ca3ac4d
AK		 1448}
1449
1450static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1451 struct segmented_address addr,
1452 const void *orig_data, const void *data,
1453 unsigned size)
1454{
9fa088f4
AK		 1455 int rc;
1456 ulong linear;
1457
83b8795a 1458 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1459 if (rc != X86EMUL_CONTINUE)
1460 return rc;
0f65dd70
AK		 1461 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1462 size, &ctxt->exception);
3ca3ac4d
AK		 1463}
1464
dde7e6d1 1465static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1466 unsigned int size, unsigned short port,
1467 void *dest)
1468{
9dac77fa 1469 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1470
dde7e6d1 1471 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1472 unsigned int in_page, n;
9dac77fa 1473 unsigned int count = ctxt->rep_prefix ?
dd856efa 1474 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
0efb0440 1475 in_page = (ctxt->eflags & X86_EFLAGS_DF) ?
dd856efa
AK		 1476 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1477 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
b55a8144 1478 n = min3(in_page, (unsigned int)sizeof(rc->data) / size, count);
dde7e6d1
AK		 1479 if (n == 0)
1480 n = 1;
1481 rc->pos = rc->end = 0;
7b105ca2 1482 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1483 return 0;
1484 rc->end = n * size;
6aa8b732
AK		 1485 }
1486
e6e39f04 1487 if (ctxt->rep_prefix && (ctxt->d & String) &&
0efb0440 1488 !(ctxt->eflags & X86_EFLAGS_DF)) {
b3356bf0
GN		 1489 ctxt->dst.data = rc->data + rc->pos;
1490 ctxt->dst.type = OP_MEM_STR;
1491 ctxt->dst.count = (rc->end - rc->pos) / size;
1492 rc->pos = rc->end;
1493 } else {
1494 memcpy(dest, rc->data + rc->pos, size);
1495 rc->pos += size;
1496 }
dde7e6d1
AK		 1497 return 1;
1498}
6aa8b732 1499
7f3d35fd
KW		 1500static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1501 u16 index, struct desc_struct *desc)
1502{
1503 struct desc_ptr dt;
1504 ulong addr;
1505
1506 ctxt->ops->get_idt(ctxt, &dt);
1507
1508 if (dt.size < index * 8 + 7)
1509 return emulate_gp(ctxt, index << 3 | 0x2);
1510
1511 addr = dt.address + index * 8;
0e96f31e 1512 return linear_read_system(ctxt, addr, desc, sizeof(*desc));
7f3d35fd
KW		 1513}
1514
dde7e6d1 1515static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1516 u16 selector, struct desc_ptr *dt)
1517{
0225fb50 1518 const struct x86_emulate_ops *ops = ctxt->ops;
2eedcac8 1519 u32 base3 = 0;
7b105ca2 1520
dde7e6d1
AK		 1521 if (selector & 1 << 2) {
1522 struct desc_struct desc;
1aa36616
AK		 1523 u16 sel;
1524
0e96f31e 1525 memset(dt, 0, sizeof(*dt));
2eedcac8
NA		 1526 if (!ops->get_segment(ctxt, &sel, &desc, &base3,
1527 VCPU_SREG_LDTR))
dde7e6d1 1528 return;
e09d082c 1529
dde7e6d1 1530 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
2eedcac8 1531 dt->address = get_desc_base(&desc) | ((u64)base3 << 32);
dde7e6d1 1532 } else
4bff1e86 1533 ops->get_gdt(ctxt, dt);
dde7e6d1 1534}
120df890 1535
edccda7c
NA		 1536static int get_descriptor_ptr(struct x86_emulate_ctxt *ctxt,
1537 u16 selector, ulong *desc_addr_p)
dde7e6d1
AK		 1538{
1539 struct desc_ptr dt;
1540 u16 index = selector >> 3;
dde7e6d1 1541 ulong addr;
120df890 1542
7b105ca2 1543 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1544
35d3d4a1
AK		 1545 if (dt.size < index * 8 + 7)
1546 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1547
edccda7c
NA		 1548 addr = dt.address + index * 8;
1549
1550#ifdef CONFIG_X86_64
1551 if (addr >> 32 != 0) {
1552 u64 efer = 0;
1553
1554 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
1555 if (!(efer & EFER_LMA))
1556 addr &= (u32)-1;
1557 }
1558#endif
1559
1560 *desc_addr_p = addr;
1561 return X86EMUL_CONTINUE;
1562}
1563
1564/* allowed just for 8 bytes segments */
1565static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1566 u16 selector, struct desc_struct *desc,
1567 ulong *desc_addr_p)
1568{
1569 int rc;
1570
1571 rc = get_descriptor_ptr(ctxt, selector, desc_addr_p);
1572 if (rc != X86EMUL_CONTINUE)
1573 return rc;
1574
79367a65 1575 return linear_read_system(ctxt, *desc_addr_p, desc, sizeof(*desc));
dde7e6d1 1576}
ef65c889 1577
dde7e6d1
AK		 1578/* allowed just for 8 bytes segments */
1579static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1580 u16 selector, struct desc_struct *desc)
1581{
edccda7c 1582 int rc;
dde7e6d1 1583 ulong addr;
6aa8b732 1584
edccda7c
NA		 1585 rc = get_descriptor_ptr(ctxt, selector, &addr);
1586 if (rc != X86EMUL_CONTINUE)
1587 return rc;
6aa8b732 1588
0e96f31e 1589 return linear_write_system(ctxt, addr, desc, sizeof(*desc));
dde7e6d1 1590}
c7e75a3d 1591
2356aaeb 1592static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
d1442d85 1593 u16 selector, int seg, u8 cpl,
3dc4bc4f 1594 enum x86_transfer_type transfer,
d1442d85 1595 struct desc_struct *desc)
dde7e6d1 1596{
869be99c 1597 struct desc_struct seg_desc, old_desc;
2356aaeb 1598 u8 dpl, rpl;
dde7e6d1
AK		 1599 unsigned err_vec = GP_VECTOR;
1600 u32 err_code = 0;
1601 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
e919464b 1602 ulong desc_addr;
dde7e6d1 1603 int ret;
03ebebeb 1604 u16 dummy;
e37a75a1 1605 u32 base3 = 0;
69f55cb1 1606
0e96f31e 1607 memset(&seg_desc, 0, sizeof(seg_desc));
69f55cb1 1608
f8da94e9
KW		 1609 if (ctxt->mode == X86EMUL_MODE_REAL) {
1610 /* set real mode segment descriptor (keep limit etc. for
1611 * unreal mode) */
03ebebeb 1612 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
dde7e6d1 1613 set_desc_base(&seg_desc, selector << 4);
dde7e6d1 1614 goto load;
f8da94e9
KW		 1615 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
1616 /* VM86 needs a clean new segment descriptor */
1617 set_desc_base(&seg_desc, selector << 4);
1618 set_desc_limit(&seg_desc, 0xffff);
1619 seg_desc.type = 3;
1620 seg_desc.p = 1;
1621 seg_desc.s = 1;
1622 seg_desc.dpl = 3;
1623 goto load;
dde7e6d1
AK		 1624 }
1625
79d5b4c3 1626 rpl = selector & 3;
79d5b4c3 1627
dde7e6d1
AK		 1628 /* TR should be in GDT only */
1629 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1630 goto exception;
1631
33ab9110
PB		 1632 /* NULL selector is not valid for TR, CS and (except for long mode) SS */
1633 if (null_selector) {
1634 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_TR)
1635 goto exception;
1636
1637 if (seg == VCPU_SREG_SS) {
1638 if (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl)
1639 goto exception;
1640
1641 /*
1642 * ctxt->ops->set_segment expects the CPL to be in
1643 * SS.DPL, so fake an expand-up 32-bit data segment.
1644 */
1645 seg_desc.type = 3;
1646 seg_desc.p = 1;
1647 seg_desc.s = 1;
1648 seg_desc.dpl = cpl;
1649 seg_desc.d = 1;
1650 seg_desc.g = 1;
1651 }
1652
1653 /* Skip all following checks */
dde7e6d1 1654 goto load;
33ab9110 1655 }
dde7e6d1 1656
e919464b 1657 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
dde7e6d1
AK		 1658 if (ret != X86EMUL_CONTINUE)
1659 return ret;
1660
1661 err_code = selector & 0xfffc;
3dc4bc4f
NA		 1662 err_vec = (transfer == X86_TRANSFER_TASK_SWITCH) ? TS_VECTOR :
1663 GP_VECTOR;
dde7e6d1 1664
fc058680 1665 /* can't load system descriptor into segment selector */
3dc4bc4f
NA		 1666 if (seg <= VCPU_SREG_GS && !seg_desc.s) {
1667 if (transfer == X86_TRANSFER_CALL_JMP)
1668 return X86EMUL_UNHANDLEABLE;
dde7e6d1 1669 goto exception;
3dc4bc4f 1670 }
dde7e6d1
AK		 1671
1672 if (!seg_desc.p) {
1673 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1674 goto exception;
1675 }
1676
dde7e6d1 1677 dpl = seg_desc.dpl;
dde7e6d1
AK		 1678
1679 switch (seg) {
1680 case VCPU_SREG_SS:
1681 /*
1682 * segment is not a writable data segment or segment
1683 * selector's RPL != CPL or segment selector's RPL != CPL
1684 */
1685 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1686 goto exception;
6aa8b732 1687 break;
dde7e6d1
AK		 1688 case VCPU_SREG_CS:
1689 if (!(seg_desc.type & 8))
1690 goto exception;
1691
1692 if (seg_desc.type & 4) {
1693 /* conforming */
1694 if (dpl > cpl)
1695 goto exception;
1696 } else {
1697 /* nonconforming */
1698 if (rpl > cpl || dpl != cpl)
1699 goto exception;
1700 }
040c8dc8
NA		 1701 /* in long-mode d/b must be clear if l is set */
1702 if (seg_desc.d && seg_desc.l) {
1703 u64 efer = 0;
1704
1705 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
1706 if (efer & EFER_LMA)
1707 goto exception;
1708 }
1709
dde7e6d1
AK		 1710 /* CS(RPL) <- CPL */
1711 selector = (selector & 0xfffc) | cpl;
6aa8b732 1712 break;
dde7e6d1
AK		 1713 case VCPU_SREG_TR:
1714 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1715 goto exception;
869be99c
AK		 1716 old_desc = seg_desc;
1717 seg_desc.type |= 2; /* busy */
1718 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1719 sizeof(seg_desc), &ctxt->exception);
1720 if (ret != X86EMUL_CONTINUE)
1721 return ret;
dde7e6d1
AK		 1722 break;
1723 case VCPU_SREG_LDTR:
1724 if (seg_desc.s || seg_desc.type != 2)
1725 goto exception;
1726 break;
1727 default: /* DS, ES, FS, or GS */
4e62417b 1728 /*
dde7e6d1
AK		 1729 * segment is not a data or readable code segment or
1730 * ((segment is a data or nonconforming code segment)
1731 * and (both RPL and CPL > DPL))
4e62417b 1732 */
dde7e6d1
AK		 1733 if ((seg_desc.type & 0xa) == 0x8 ||
1734 (((seg_desc.type & 0xc) != 0xc) &&
1735 (rpl > dpl && cpl > dpl)))
1736 goto exception;
6aa8b732 1737 break;
dde7e6d1
AK		 1738 }
1739
1740 if (seg_desc.s) {
1741 /* mark segment as accessed */
e2cefa74
NA		 1742 if (!(seg_desc.type & 1)) {
1743 seg_desc.type |= 1;
1744 ret = write_segment_descriptor(ctxt, selector,
1745 &seg_desc);
1746 if (ret != X86EMUL_CONTINUE)
1747 return ret;
1748 }
e37a75a1 1749 } else if (ctxt->mode == X86EMUL_MODE_PROT64) {
79367a65 1750 ret = linear_read_system(ctxt, desc_addr+8, &base3, sizeof(base3));
e37a75a1
NA		 1751 if (ret != X86EMUL_CONTINUE)
1752 return ret;
fd8cb433
YZ		 1753 if (emul_is_noncanonical_address(get_desc_base(&seg_desc) |
1754 ((u64)base3 << 32), ctxt))
9a9abf6b 1755 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1756 }
1757load:
e37a75a1 1758 ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg);
d1442d85
NA		 1759 if (desc)
1760 *desc = seg_desc;
dde7e6d1
AK		 1761 return X86EMUL_CONTINUE;
1762exception:
592f0858 1763 return emulate_exception(ctxt, err_vec, err_code, true);
dde7e6d1
AK		 1764}
1765
2356aaeb
PB		 1766static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1767 u16 selector, int seg)
1768{
1769 u8 cpl = ctxt->ops->cpl(ctxt);
33ab9110
PB		 1770
1771 /*
1772 * None of MOV, POP and LSS can load a NULL selector in CPL=3, but
1773 * they can load it at CPL<3 (Intel's manual says only LSS can,
1774 * but it's wrong).
1775 *
1776 * However, the Intel manual says that putting IST=1/DPL=3 in
1777 * an interrupt gate will result in SS=3 (the AMD manual instead
1778 * says it doesn't), so allow SS=3 in __load_segment_descriptor
1779 * and only forbid it here.
1780 */
1781 if (seg == VCPU_SREG_SS && selector == 3 &&
1782 ctxt->mode == X86EMUL_MODE_PROT64)
1783 return emulate_exception(ctxt, GP_VECTOR, 0, true);
1784
3dc4bc4f
NA		 1785 return __load_segment_descriptor(ctxt, selector, seg, cpl,
1786 X86_TRANSFER_NONE, NULL);
2356aaeb
PB		 1787}
1788
31be40b3
WY		 1789static void write_register_operand(struct operand *op)
1790{
6fd8e127 1791 return assign_register(op->addr.reg, op->val, op->bytes);
31be40b3
WY		 1792}
1793
fb32b1ed 1794static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
dde7e6d1 1795{
fb32b1ed 1796 switch (op->type) {
dde7e6d1 1797 case OP_REG:
fb32b1ed 1798 write_register_operand(op);
6aa8b732 1799 break;
dde7e6d1 1800 case OP_MEM:
9dac77fa 1801 if (ctxt->lock_prefix)
f5f87dfb
PB		 1802 return segmented_cmpxchg(ctxt,
1803 op->addr.mem,
1804 &op->orig_val,
1805 &op->val,
1806 op->bytes);
1807 else
1808 return segmented_write(ctxt,
fb32b1ed 1809 op->addr.mem,
fb32b1ed
AK		 1810 &op->val,
1811 op->bytes);
a682e354 1812 break;
b3356bf0 1813 case OP_MEM_STR:
f5f87dfb
PB		 1814 return segmented_write(ctxt,
1815 op->addr.mem,
1816 op->data,
1817 op->bytes * op->count);
b3356bf0 1818 break;
1253791d 1819 case OP_XMM:
fb32b1ed 1820 write_sse_reg(ctxt, &op->vec_val, op->addr.xmm);
1253791d 1821 break;
cbe2c9d3 1822 case OP_MM:
fb32b1ed 1823 write_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
cbe2c9d3 1824 break;
dde7e6d1
AK		 1825 case OP_NONE:
1826 /* no writeback */
414e6277 1827 break;
dde7e6d1 1828 default:
414e6277 1829 break;
6aa8b732 1830 }
dde7e6d1
AK		 1831 return X86EMUL_CONTINUE;
1832}
6aa8b732 1833
51ddff50 1834static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
dde7e6d1 1835{
4179bb02 1836 struct segmented_address addr;
0dc8d10f 1837
5ad105e5 1838 rsp_increment(ctxt, -bytes);
dd856efa 1839 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
4179bb02
TY		 1840 addr.seg = VCPU_SREG_SS;
1841
51ddff50
AK		 1842 return segmented_write(ctxt, addr, data, bytes);
1843}
1844
1845static int em_push(struct x86_emulate_ctxt *ctxt)
1846{
4179bb02 1847 /* Disable writeback. */
9dac77fa 1848 ctxt->dst.type = OP_NONE;
51ddff50 1849 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1850}
69f55cb1 1851
dde7e6d1 1852static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1853 void *dest, int len)
1854{
dde7e6d1 1855 int rc;
90de84f5 1856 struct segmented_address addr;
8b4caf66 1857
dd856efa 1858 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
90de84f5 1859 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1860 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1861 if (rc != X86EMUL_CONTINUE)
1862 return rc;
1863
5ad105e5 1864 rsp_increment(ctxt, len);
dde7e6d1 1865 return rc;
8b4caf66
LV		 1866}
1867
c54fe504
TY		 1868static int em_pop(struct x86_emulate_ctxt *ctxt)
1869{
9dac77fa 1870 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1871}
1872
dde7e6d1 1873static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1874 void *dest, int len)
9de41573
GN		 1875{
1876 int rc;
dde7e6d1 1877 unsigned long val, change_mask;
0efb0440 1878 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> X86_EFLAGS_IOPL_BIT;
7b105ca2 1879 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1880
3b9be3bf 1881 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1882 if (rc != X86EMUL_CONTINUE)
1883 return rc;
9de41573 1884
0efb0440
NA		 1885 change_mask = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
1886 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF |
1887 X86_EFLAGS_TF | X86_EFLAGS_DF | X86_EFLAGS_NT |
1888 X86_EFLAGS_AC | X86_EFLAGS_ID;
9de41573 1889
dde7e6d1
AK		 1890 switch(ctxt->mode) {
1891 case X86EMUL_MODE_PROT64:
1892 case X86EMUL_MODE_PROT32:
1893 case X86EMUL_MODE_PROT16:
1894 if (cpl == 0)
0efb0440 1895 change_mask |= X86_EFLAGS_IOPL;
dde7e6d1 1896 if (cpl <= iopl)
0efb0440 1897 change_mask |= X86_EFLAGS_IF;
dde7e6d1
AK		 1898 break;
1899 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1900 if (iopl < 3)
1901 return emulate_gp(ctxt, 0);
0efb0440 1902 change_mask |= X86_EFLAGS_IF;
dde7e6d1
AK		 1903 break;
1904 default: /* real mode */
0efb0440 1905 change_mask |= (X86_EFLAGS_IOPL | X86_EFLAGS_IF);
dde7e6d1 1906 break;
9de41573 1907 }
dde7e6d1
AK		 1908
1909 *(unsigned long *)dest =
1910 (ctxt->eflags & ~change_mask) | (val & change_mask);
1911
1912 return rc;
9de41573
GN		 1913}
1914
62aaa2f0
TY		 1915static int em_popf(struct x86_emulate_ctxt *ctxt)
1916{
9dac77fa
AK		 1917 ctxt->dst.type = OP_REG;
1918 ctxt->dst.addr.reg = &ctxt->eflags;
1919 ctxt->dst.bytes = ctxt->op_bytes;
1920 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1921}
1922
612e89f0
AK		 1923static int em_enter(struct x86_emulate_ctxt *ctxt)
1924{
1925 int rc;
1926 unsigned frame_size = ctxt->src.val;
1927 unsigned nesting_level = ctxt->src2.val & 31;
dd856efa 1928 ulong rbp;
612e89f0
AK		 1929
1930 if (nesting_level)
1931 return X86EMUL_UNHANDLEABLE;
1932
dd856efa
AK		 1933 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1934 rc = push(ctxt, &rbp, stack_size(ctxt));
612e89f0
AK		 1935 if (rc != X86EMUL_CONTINUE)
1936 return rc;
dd856efa 1937 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
612e89f0 1938 stack_mask(ctxt));
dd856efa
AK		 1939 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1940 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
612e89f0
AK		 1941 stack_mask(ctxt));
1942 return X86EMUL_CONTINUE;
1943}
1944
f47cfa31
AK		 1945static int em_leave(struct x86_emulate_ctxt *ctxt)
1946{
dd856efa 1947 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
f47cfa31 1948 stack_mask(ctxt));
dd856efa 1949 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
f47cfa31
AK		 1950}
1951
1cd196ea 1952static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1953{
1cd196ea
AK		 1954 int seg = ctxt->src2.val;
1955
9dac77fa 1956 ctxt->src.val = get_segment_selector(ctxt, seg);
0fcc207c
NA		 1957 if (ctxt->op_bytes == 4) {
1958 rsp_increment(ctxt, -2);
1959 ctxt->op_bytes = 2;
1960 }
7b262e90 1961
4487b3b4 1962 return em_push(ctxt);
7b262e90
GN		 1963}
1964
1cd196ea 1965static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1966{
1cd196ea 1967 int seg = ctxt->src2.val;
dde7e6d1
AK		 1968 unsigned long selector;
1969 int rc;
38ba30ba 1970
3313bc4e 1971 rc = emulate_pop(ctxt, &selector, 2);
dde7e6d1
AK		 1972 if (rc != X86EMUL_CONTINUE)
1973 return rc;
1974
a5457e7b
PB		 1975 if (ctxt->modrm_reg == VCPU_SREG_SS)
1976 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3313bc4e
NA		 1977 if (ctxt->op_bytes > 2)
1978 rsp_increment(ctxt, ctxt->op_bytes - 2);
a5457e7b 1979
7b105ca2 1980 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1981 return rc;
38ba30ba
GN		 1982}
1983
b96a7fad 1984static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1985{
dd856efa 1986 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
dde7e6d1
AK		 1987 int rc = X86EMUL_CONTINUE;
1988 int reg = VCPU_REGS_RAX;
38ba30ba 1989
dde7e6d1
AK		 1990 while (reg <= VCPU_REGS_RDI) {
1991 (reg == VCPU_REGS_RSP) ?
dd856efa 1992 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
38ba30ba 1993
4487b3b4 1994 rc = em_push(ctxt);
dde7e6d1
AK		 1995 if (rc != X86EMUL_CONTINUE)
1996 return rc;
38ba30ba 1997
dde7e6d1 1998 ++reg;
38ba30ba 1999 }
38ba30ba 2000
dde7e6d1 2001 return rc;
38ba30ba
GN		 2002}
2003
62aaa2f0
TY		 2004static int em_pushf(struct x86_emulate_ctxt *ctxt)
2005{
0efb0440 2006 ctxt->src.val = (unsigned long)ctxt->eflags & ~X86_EFLAGS_VM;
62aaa2f0
TY		 2007 return em_push(ctxt);
2008}
2009
b96a7fad 2010static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 2011{
dde7e6d1
AK		 2012 int rc = X86EMUL_CONTINUE;
2013 int reg = VCPU_REGS_RDI;
6fd8e127 2014 u32 val;
38ba30ba 2015
dde7e6d1
AK		 2016 while (reg >= VCPU_REGS_RAX) {
2017 if (reg == VCPU_REGS_RSP) {
5ad105e5 2018 rsp_increment(ctxt, ctxt->op_bytes);
dde7e6d1
AK		 2019 --reg;
2020 }
38ba30ba 2021
6fd8e127 2022 rc = emulate_pop(ctxt, &val, ctxt->op_bytes);
dde7e6d1
AK		 2023 if (rc != X86EMUL_CONTINUE)
2024 break;
6fd8e127 2025 assign_register(reg_rmw(ctxt, reg), val, ctxt->op_bytes);
dde7e6d1 2026 --reg;
38ba30ba 2027 }
dde7e6d1 2028 return rc;
38ba30ba
GN		 2029}
2030
dd856efa 2031static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 2032{
0225fb50 2033 const struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 2034 int rc;
6e154e56
MG		 2035 struct desc_ptr dt;
2036 gva_t cs_addr;
2037 gva_t eip_addr;
2038 u16 cs, eip;
6e154e56
MG		 2039
2040 /* TODO: Add limit checks */
9dac77fa 2041 ctxt->src.val = ctxt->eflags;
4487b3b4 2042 rc = em_push(ctxt);
5c56e1cf
AK		 2043 if (rc != X86EMUL_CONTINUE)
2044 return rc;
6e154e56 2045
0efb0440 2046 ctxt->eflags &= ~(X86_EFLAGS_IF | X86_EFLAGS_TF | X86_EFLAGS_AC);
6e154e56 2047
9dac77fa 2048 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 2049 rc = em_push(ctxt);
5c56e1cf
AK		 2050 if (rc != X86EMUL_CONTINUE)
2051 return rc;
6e154e56 2052
9dac77fa 2053 ctxt->src.val = ctxt->_eip;
4487b3b4 2054 rc = em_push(ctxt);
5c56e1cf
AK		 2055 if (rc != X86EMUL_CONTINUE)
2056 return rc;
2057
4bff1e86 2058 ops->get_idt(ctxt, &dt);
6e154e56
MG		 2059
2060 eip_addr = dt.address + (irq << 2);
2061 cs_addr = dt.address + (irq << 2) + 2;
2062
79367a65 2063 rc = linear_read_system(ctxt, cs_addr, &cs, 2);
6e154e56
MG		 2064 if (rc != X86EMUL_CONTINUE)
2065 return rc;
2066
79367a65 2067 rc = linear_read_system(ctxt, eip_addr, &eip, 2);
6e154e56
MG		 2068 if (rc != X86EMUL_CONTINUE)
2069 return rc;
2070
7b105ca2 2071 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 2072 if (rc != X86EMUL_CONTINUE)
2073 return rc;
2074
9dac77fa 2075 ctxt->_eip = eip;
6e154e56
MG		 2076
2077 return rc;
2078}
2079
dd856efa
AK		 2080int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
2081{
2082 int rc;
2083
2084 invalidate_registers(ctxt);
2085 rc = __emulate_int_real(ctxt, irq);
2086 if (rc == X86EMUL_CONTINUE)
2087 writeback_registers(ctxt);
2088 return rc;
2089}
2090
7b105ca2 2091static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 2092{
2093 switch(ctxt->mode) {
2094 case X86EMUL_MODE_REAL:
dd856efa 2095 return __emulate_int_real(ctxt, irq);
6e154e56
MG		 2096 case X86EMUL_MODE_VM86:
2097 case X86EMUL_MODE_PROT16:
2098 case X86EMUL_MODE_PROT32:
2099 case X86EMUL_MODE_PROT64:
2100 default:
2101 /* Protected mode interrupts unimplemented yet */
2102 return X86EMUL_UNHANDLEABLE;
2103 }
2104}
2105
7b105ca2 2106static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 2107{
dde7e6d1
AK		 2108 int rc = X86EMUL_CONTINUE;
2109 unsigned long temp_eip = 0;
2110 unsigned long temp_eflags = 0;
2111 unsigned long cs = 0;
0efb0440
NA		 2112 unsigned long mask = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
2113 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_TF |
2114 X86_EFLAGS_IF | X86_EFLAGS_DF | X86_EFLAGS_OF |
2115 X86_EFLAGS_IOPL | X86_EFLAGS_NT | X86_EFLAGS_RF |
2116 X86_EFLAGS_AC | X86_EFLAGS_ID |
35fd68a3 2117 X86_EFLAGS_FIXED;
0efb0440
NA		 2118 unsigned long vm86_mask = X86_EFLAGS_VM | X86_EFLAGS_VIF |
2119 X86_EFLAGS_VIP;
38ba30ba 2120
dde7e6d1 2121 /* TODO: Add stack limit check */
38ba30ba 2122
9dac77fa 2123 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 2124
dde7e6d1
AK		 2125 if (rc != X86EMUL_CONTINUE)
2126 return rc;
38ba30ba 2127
35d3d4a1
AK		 2128 if (temp_eip & ~0xffff)
2129 return emulate_gp(ctxt, 0);
38ba30ba 2130
9dac77fa 2131 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 2132
dde7e6d1
AK		 2133 if (rc != X86EMUL_CONTINUE)
2134 return rc;
38ba30ba 2135
9dac77fa 2136 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 2137
dde7e6d1
AK		 2138 if (rc != X86EMUL_CONTINUE)
2139 return rc;
38ba30ba 2140
7b105ca2 2141 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 2142
dde7e6d1
AK		 2143 if (rc != X86EMUL_CONTINUE)
2144 return rc;
38ba30ba 2145
9dac77fa 2146 ctxt->_eip = temp_eip;
38ba30ba 2147
9dac77fa 2148 if (ctxt->op_bytes == 4)
dde7e6d1 2149 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 2150 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 2151 ctxt->eflags &= ~0xffff;
2152 ctxt->eflags |= temp_eflags;
38ba30ba 2153 }
dde7e6d1
AK		 2154
2155 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
35fd68a3 2156 ctxt->eflags |= X86_EFLAGS_FIXED;
801806d9 2157 ctxt->ops->set_nmi_mask(ctxt, false);
dde7e6d1
AK		 2158
2159 return rc;
38ba30ba
GN		 2160}
2161
e01991e7 2162static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 2163{
dde7e6d1
AK		 2164 switch(ctxt->mode) {
2165 case X86EMUL_MODE_REAL:
7b105ca2 2166 return emulate_iret_real(ctxt);
dde7e6d1
AK		 2167 case X86EMUL_MODE_VM86:
2168 case X86EMUL_MODE_PROT16:
2169 case X86EMUL_MODE_PROT32:
2170 case X86EMUL_MODE_PROT64:
c37eda13 2171 default:
dde7e6d1
AK		 2172 /* iret from protected mode unimplemented yet */
2173 return X86EMUL_UNHANDLEABLE;
c37eda13 2174 }
c37eda13
WY		 2175}
2176
d2f62766
TY		 2177static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
2178{
d2f62766 2179 int rc;
2117d539
RK		 2180 unsigned short sel;
2181 struct desc_struct new_desc;
d1442d85
NA		 2182 u8 cpl = ctxt->ops->cpl(ctxt);
2183
9dac77fa 2184 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 2185
3dc4bc4f
NA		 2186 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl,
2187 X86_TRANSFER_CALL_JMP,
d1442d85 2188 &new_desc);
d2f62766
TY		 2189 if (rc != X86EMUL_CONTINUE)
2190 return rc;
2191
d50eaa18 2192 rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc);
2117d539
RK		 2193 /* Error handling is not implemented. */
2194 if (rc != X86EMUL_CONTINUE)
2195 return X86EMUL_UNHANDLEABLE;
2196
d1442d85 2197 return rc;
d2f62766
TY		 2198}
2199
f7784046 2200static int em_jmp_abs(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2201{
f7784046
NA		 2202 return assign_eip_near(ctxt, ctxt->src.val);
2203}
8cdbd2c9 2204
f7784046
NA		 2205static int em_call_near_abs(struct x86_emulate_ctxt *ctxt)
2206{
2207 int rc;
2208 long int old_eip;
2209
2210 old_eip = ctxt->_eip;
2211 rc = assign_eip_near(ctxt, ctxt->src.val);
2212 if (rc != X86EMUL_CONTINUE)
2213 return rc;
2214 ctxt->src.val = old_eip;
2215 rc = em_push(ctxt);
4179bb02 2216 return rc;
8cdbd2c9
LV		 2217}
2218
e0dac408 2219static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2220{
9dac77fa 2221 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 2222
aaa05f24
NA		 2223 if (ctxt->dst.bytes == 16)
2224 return X86EMUL_UNHANDLEABLE;
2225
dd856efa
AK		 2226 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
2227 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
2228 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
2229 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
0efb0440 2230 ctxt->eflags &= ~X86_EFLAGS_ZF;
8cdbd2c9 2231 } else {
dd856efa
AK		 2232 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2233 (u32) reg_read(ctxt, VCPU_REGS_RBX);
8cdbd2c9 2234
0efb0440 2235 ctxt->eflags |= X86_EFLAGS_ZF;
8cdbd2c9 2236 }
1b30eaa8 2237 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2238}
2239
ebda02c2
TY		 2240static int em_ret(struct x86_emulate_ctxt *ctxt)
2241{
234f3ce4
NA		 2242 int rc;
2243 unsigned long eip;
2244
2245 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
2246 if (rc != X86EMUL_CONTINUE)
2247 return rc;
2248
2249 return assign_eip_near(ctxt, eip);
ebda02c2
TY		 2250}
2251
e01991e7 2252static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 2253{
a77ab5ea 2254 int rc;
d1442d85 2255 unsigned long eip, cs;
9e8919ae 2256 int cpl = ctxt->ops->cpl(ctxt);
2117d539 2257 struct desc_struct new_desc;
a77ab5ea 2258
d1442d85 2259 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
1b30eaa8 2260 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2261 return rc;
9dac77fa 2262 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 2263 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2264 return rc;
9e8919ae
NA		 2265 /* Outer-privilege level return is not implemented */
2266 if (ctxt->mode >= X86EMUL_MODE_PROT16 && (cs & 3) > cpl)
2267 return X86EMUL_UNHANDLEABLE;
3dc4bc4f
NA		 2268 rc = __load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS, cpl,
2269 X86_TRANSFER_RET,
d1442d85
NA		 2270 &new_desc);
2271 if (rc != X86EMUL_CONTINUE)
2272 return rc;
d50eaa18 2273 rc = assign_eip_far(ctxt, eip, &new_desc);
2117d539
RK		 2274 /* Error handling is not implemented. */
2275 if (rc != X86EMUL_CONTINUE)
2276 return X86EMUL_UNHANDLEABLE;
2277
a77ab5ea
AK		 2278 return rc;
2279}
2280
3261107e
BR		 2281static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt)
2282{
2283 int rc;
2284
2285 rc = em_ret_far(ctxt);
2286 if (rc != X86EMUL_CONTINUE)
2287 return rc;
2288 rsp_increment(ctxt, ctxt->src.val);
2289 return X86EMUL_CONTINUE;
2290}
2291
e940b5c2
TY		 2292static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2293{
2294 /* Save real source value, then compare EAX against destination. */
37c564f2
NA		 2295 ctxt->dst.orig_val = ctxt->dst.val;
2296 ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX);
e940b5c2 2297 ctxt->src.orig_val = ctxt->src.val;
37c564f2 2298 ctxt->src.val = ctxt->dst.orig_val;
158de57f 2299 fastop(ctxt, em_cmp);
e940b5c2 2300
0efb0440 2301 if (ctxt->eflags & X86_EFLAGS_ZF) {
2fcf5c8a
NA		 2302 /* Success: write back to memory; no update of EAX */
2303 ctxt->src.type = OP_NONE;
e940b5c2
TY		 2304 ctxt->dst.val = ctxt->src.orig_val;
2305 } else {
2306 /* Failure: write the value we saw to EAX. */
2fcf5c8a
NA		 2307 ctxt->src.type = OP_REG;
2308 ctxt->src.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
2309 ctxt->src.val = ctxt->dst.orig_val;
2310 /* Create write-cycle to dest by writing the same value */
37c564f2 2311 ctxt->dst.val = ctxt->dst.orig_val;
e940b5c2
TY		 2312 }
2313 return X86EMUL_CONTINUE;
2314}
2315
d4b4325f 2316static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 2317{
d4b4325f 2318 int seg = ctxt->src2.val;
09b5f4d3
WY		 2319 unsigned short sel;
2320 int rc;
2321
9dac77fa 2322 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 2323
7b105ca2 2324 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 2325 if (rc != X86EMUL_CONTINUE)
2326 return rc;
2327
9dac77fa 2328 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 2329 return rc;
2330}
2331
660a5d51
PB		 2332static int emulator_has_longmode(struct x86_emulate_ctxt *ctxt)
2333{
2334 u32 eax, ebx, ecx, edx;
2335
2336 eax = 0x80000001;
2337 ecx = 0;
e911eb3b 2338 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, false);
660a5d51
PB		 2339 return edx & bit(X86_FEATURE_LM);
2340}
2341
660a5d51
PB		 2342static void rsm_set_desc_flags(struct desc_struct *desc, u32 flags)
2343{
2344 desc->g = (flags >> 23) & 1;
2345 desc->d = (flags >> 22) & 1;
2346 desc->l = (flags >> 21) & 1;
2347 desc->avl = (flags >> 20) & 1;
2348 desc->p = (flags >> 15) & 1;
2349 desc->dpl = (flags >> 13) & 3;
2350 desc->s = (flags >> 12) & 1;
2351 desc->type = (flags >> 8) & 15;
2352}
2353
ed19321f
SC		 2354static int rsm_load_seg_32(struct x86_emulate_ctxt *ctxt, const char *smstate,
2355 int n)
660a5d51
PB		 2356{
2357 struct desc_struct desc;
2358 int offset;
2359 u16 selector;
2360
ed19321f 2361 selector = GET_SMSTATE(u32, smstate, 0x7fa8 + n * 4);
660a5d51
PB		 2362
2363 if (n < 3)
2364 offset = 0x7f84 + n * 12;
2365 else
2366 offset = 0x7f2c + (n - 3) * 12;
2367
ed19321f
SC		 2368 set_desc_base(&desc, GET_SMSTATE(u32, smstate, offset + 8));
2369 set_desc_limit(&desc, GET_SMSTATE(u32, smstate, offset + 4));
2370 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smstate, offset));
660a5d51
PB		 2371 ctxt->ops->set_segment(ctxt, selector, &desc, 0, n);
2372 return X86EMUL_CONTINUE;
2373}
2374
ed19321f
SC		 2375static int rsm_load_seg_64(struct x86_emulate_ctxt *ctxt, const char *smstate,
2376 int n)
660a5d51
PB		 2377{
2378 struct desc_struct desc;
2379 int offset;
2380 u16 selector;
2381 u32 base3;
2382
2383 offset = 0x7e00 + n * 16;
2384
ed19321f
SC		 2385 selector = GET_SMSTATE(u16, smstate, offset);
2386 rsm_set_desc_flags(&desc, GET_SMSTATE(u16, smstate, offset + 2) << 8);
2387 set_desc_limit(&desc, GET_SMSTATE(u32, smstate, offset + 4));
2388 set_desc_base(&desc, GET_SMSTATE(u32, smstate, offset + 8));
2389 base3 = GET_SMSTATE(u32, smstate, offset + 12);
660a5d51
PB		 2390
2391 ctxt->ops->set_segment(ctxt, selector, &desc, base3, n);
2392 return X86EMUL_CONTINUE;
2393}
2394
2395static int rsm_enter_protected_mode(struct x86_emulate_ctxt *ctxt,
fae1a3e7 2396 u64 cr0, u64 cr3, u64 cr4)
660a5d51
PB		 2397{
2398 int bad;
fae1a3e7
PB		 2399 u64 pcid;
2400
2401 /* In order to later set CR4.PCIDE, CR3[11:0] must be zero. */
2402 pcid = 0;
2403 if (cr4 & X86_CR4_PCIDE) {
2404 pcid = cr3 & 0xfff;
2405 cr3 &= ~0xfff;
2406 }
2407
2408 bad = ctxt->ops->set_cr(ctxt, 3, cr3);
2409 if (bad)
2410 return X86EMUL_UNHANDLEABLE;
660a5d51
PB		 2411
2412 /*
2413 * First enable PAE, long mode needs it before CR0.PG = 1 is set.
2414 * Then enable protected mode. However, PCID cannot be enabled
2415 * if EFER.LMA=0, so set it separately.
2416 */
2417 bad = ctxt->ops->set_cr(ctxt, 4, cr4 & ~X86_CR4_PCIDE);
2418 if (bad)
2419 return X86EMUL_UNHANDLEABLE;
2420
2421 bad = ctxt->ops->set_cr(ctxt, 0, cr0);
2422 if (bad)
2423 return X86EMUL_UNHANDLEABLE;
2424
2425 if (cr4 & X86_CR4_PCIDE) {
2426 bad = ctxt->ops->set_cr(ctxt, 4, cr4);
2427 if (bad)
2428 return X86EMUL_UNHANDLEABLE;
fae1a3e7
PB		 2429 if (pcid) {
2430 bad = ctxt->ops->set_cr(ctxt, 3, cr3 | pcid);
2431 if (bad)
2432 return X86EMUL_UNHANDLEABLE;
2433 }
2434
660a5d51
PB		 2435 }
2436
2437 return X86EMUL_CONTINUE;
2438}
2439
ed19321f
SC		 2440static int rsm_load_state_32(struct x86_emulate_ctxt *ctxt,
2441 const char *smstate)
660a5d51
PB		 2442{
2443 struct desc_struct desc;
2444 struct desc_ptr dt;
2445 u16 selector;
fae1a3e7 2446 u32 val, cr0, cr3, cr4;
660a5d51
PB		 2447 int i;
2448
ed19321f
SC		 2449 cr0 = GET_SMSTATE(u32, smstate, 0x7ffc);
2450 cr3 = GET_SMSTATE(u32, smstate, 0x7ff8);
2451 ctxt->eflags = GET_SMSTATE(u32, smstate, 0x7ff4) | X86_EFLAGS_FIXED;
2452 ctxt->_eip = GET_SMSTATE(u32, smstate, 0x7ff0);
660a5d51
PB		 2453
2454 for (i = 0; i < 8; i++)
ed19321f 2455 *reg_write(ctxt, i) = GET_SMSTATE(u32, smstate, 0x7fd0 + i * 4);
660a5d51 2456
ed19321f 2457 val = GET_SMSTATE(u32, smstate, 0x7fcc);
660a5d51 2458 ctxt->ops->set_dr(ctxt, 6, (val & DR6_VOLATILE) | DR6_FIXED_1);
ed19321f 2459 val = GET_SMSTATE(u32, smstate, 0x7fc8);
660a5d51
PB		 2460 ctxt->ops->set_dr(ctxt, 7, (val & DR7_VOLATILE) | DR7_FIXED_1);
2461
ed19321f
SC		 2462 selector = GET_SMSTATE(u32, smstate, 0x7fc4);
2463 set_desc_base(&desc, GET_SMSTATE(u32, smstate, 0x7f64));
2464 set_desc_limit(&desc, GET_SMSTATE(u32, smstate, 0x7f60));
2465 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smstate, 0x7f5c));
660a5d51
PB		 2466 ctxt->ops->set_segment(ctxt, selector, &desc, 0, VCPU_SREG_TR);
2467
ed19321f
SC		 2468 selector = GET_SMSTATE(u32, smstate, 0x7fc0);
2469 set_desc_base(&desc, GET_SMSTATE(u32, smstate, 0x7f80));
2470 set_desc_limit(&desc, GET_SMSTATE(u32, smstate, 0x7f7c));
2471 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smstate, 0x7f78));
660a5d51
PB		 2472 ctxt->ops->set_segment(ctxt, selector, &desc, 0, VCPU_SREG_LDTR);
2473
ed19321f
SC		 2474 dt.address = GET_SMSTATE(u32, smstate, 0x7f74);
2475 dt.size = GET_SMSTATE(u32, smstate, 0x7f70);
660a5d51
PB		 2476 ctxt->ops->set_gdt(ctxt, &dt);
2477
ed19321f
SC		 2478 dt.address = GET_SMSTATE(u32, smstate, 0x7f58);
2479 dt.size = GET_SMSTATE(u32, smstate, 0x7f54);
660a5d51
PB		 2480 ctxt->ops->set_idt(ctxt, &dt);
2481
2482 for (i = 0; i < 6; i++) {
ed19321f 2483 int r = rsm_load_seg_32(ctxt, smstate, i);
660a5d51
PB		 2484 if (r != X86EMUL_CONTINUE)
2485 return r;
2486 }
2487
ed19321f 2488 cr4 = GET_SMSTATE(u32, smstate, 0x7f14);
660a5d51 2489
ed19321f 2490 ctxt->ops->set_smbase(ctxt, GET_SMSTATE(u32, smstate, 0x7ef8));
660a5d51 2491
fae1a3e7 2492 return rsm_enter_protected_mode(ctxt, cr0, cr3, cr4);
660a5d51
PB		 2493}
2494
ed19321f
SC		 2495static int rsm_load_state_64(struct x86_emulate_ctxt *ctxt,
2496 const char *smstate)
660a5d51
PB		 2497{
2498 struct desc_struct desc;
2499 struct desc_ptr dt;
fae1a3e7 2500 u64 val, cr0, cr3, cr4;
660a5d51
PB		 2501 u32 base3;
2502 u16 selector;
b10d92a5 2503 int i, r;
660a5d51
PB		 2504
2505 for (i = 0; i < 16; i++)
ed19321f 2506 *reg_write(ctxt, i) = GET_SMSTATE(u64, smstate, 0x7ff8 - i * 8);
660a5d51 2507
ed19321f
SC		 2508 ctxt->_eip = GET_SMSTATE(u64, smstate, 0x7f78);
2509 ctxt->eflags = GET_SMSTATE(u32, smstate, 0x7f70) | X86_EFLAGS_FIXED;
660a5d51 2510
ed19321f 2511 val = GET_SMSTATE(u32, smstate, 0x7f68);
660a5d51 2512 ctxt->ops->set_dr(ctxt, 6, (val & DR6_VOLATILE) | DR6_FIXED_1);
ed19321f 2513 val = GET_SMSTATE(u32, smstate, 0x7f60);
660a5d51
PB		 2514 ctxt->ops->set_dr(ctxt, 7, (val & DR7_VOLATILE) | DR7_FIXED_1);
2515
ed19321f
SC		 2516 cr0 = GET_SMSTATE(u64, smstate, 0x7f58);
2517 cr3 = GET_SMSTATE(u64, smstate, 0x7f50);
2518 cr4 = GET_SMSTATE(u64, smstate, 0x7f48);
2519 ctxt->ops->set_smbase(ctxt, GET_SMSTATE(u32, smstate, 0x7f00));
2520 val = GET_SMSTATE(u64, smstate, 0x7ed0);
660a5d51
PB		 2521 ctxt->ops->set_msr(ctxt, MSR_EFER, val & ~EFER_LMA);
2522
ed19321f
SC		 2523 selector = GET_SMSTATE(u32, smstate, 0x7e90);
2524 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smstate, 0x7e92) << 8);
2525 set_desc_limit(&desc, GET_SMSTATE(u32, smstate, 0x7e94));
2526 set_desc_base(&desc, GET_SMSTATE(u32, smstate, 0x7e98));
2527 base3 = GET_SMSTATE(u32, smstate, 0x7e9c);
660a5d51
PB		 2528 ctxt->ops->set_segment(ctxt, selector, &desc, base3, VCPU_SREG_TR);
2529
ed19321f
SC		 2530 dt.size = GET_SMSTATE(u32, smstate, 0x7e84);
2531 dt.address = GET_SMSTATE(u64, smstate, 0x7e88);
660a5d51
PB		 2532 ctxt->ops->set_idt(ctxt, &dt);
2533
ed19321f
SC		 2534 selector = GET_SMSTATE(u32, smstate, 0x7e70);
2535 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smstate, 0x7e72) << 8);
2536 set_desc_limit(&desc, GET_SMSTATE(u32, smstate, 0x7e74));
2537 set_desc_base(&desc, GET_SMSTATE(u32, smstate, 0x7e78));
2538 base3 = GET_SMSTATE(u32, smstate, 0x7e7c);
660a5d51
PB		 2539 ctxt->ops->set_segment(ctxt, selector, &desc, base3, VCPU_SREG_LDTR);
2540
ed19321f
SC		 2541 dt.size = GET_SMSTATE(u32, smstate, 0x7e64);
2542 dt.address = GET_SMSTATE(u64, smstate, 0x7e68);
660a5d51
PB		 2543 ctxt->ops->set_gdt(ctxt, &dt);
2544
fae1a3e7 2545 r = rsm_enter_protected_mode(ctxt, cr0, cr3, cr4);
b10d92a5
PB		 2546 if (r != X86EMUL_CONTINUE)
2547 return r;
2548
660a5d51 2549 for (i = 0; i < 6; i++) {
ed19321f 2550 r = rsm_load_seg_64(ctxt, smstate, i);
660a5d51
PB		 2551 if (r != X86EMUL_CONTINUE)
2552 return r;
2553 }
2554
b10d92a5 2555 return X86EMUL_CONTINUE;
660a5d51
PB		 2556}
2557
64d60670
PB		 2558static int em_rsm(struct x86_emulate_ctxt *ctxt)
2559{
660a5d51 2560 unsigned long cr0, cr4, efer;
ed19321f 2561 char buf[512];
660a5d51
PB		 2562 u64 smbase;
2563 int ret;
2564
6ed071f0 2565 if ((ctxt->ops->get_hflags(ctxt) & X86EMUL_SMM_MASK) == 0)
64d60670
PB		 2566 return emulate_ud(ctxt);
2567
ed19321f
SC		 2568 smbase = ctxt->ops->get_smbase(ctxt);
2569
2570 ret = ctxt->ops->read_phys(ctxt, smbase + 0xfe00, buf, sizeof(buf));
2571 if (ret != X86EMUL_CONTINUE)
2572 return X86EMUL_UNHANDLEABLE;
2573
660a5d51
PB		 2574 /*
2575 * Get back to real mode, to prepare a safe state in which to load
89651a3d
PB		 2576 * CR0/CR3/CR4/EFER. It's all a bit more complicated if the vCPU
2577 * supports long mode.
660a5d51 2578 */
89651a3d
PB		 2579 cr4 = ctxt->ops->get_cr(ctxt, 4);
2580 if (emulator_has_longmode(ctxt)) {
2581 struct desc_struct cs_desc;
2582
2583 /* Zero CR4.PCIDE before CR0.PG. */
2584 if (cr4 & X86_CR4_PCIDE) {
2585 ctxt->ops->set_cr(ctxt, 4, cr4 & ~X86_CR4_PCIDE);
2586 cr4 &= ~X86_CR4_PCIDE;
2587 }
2588
2589 /* A 32-bit code segment is required to clear EFER.LMA. */
2590 memset(&cs_desc, 0, sizeof(cs_desc));
2591 cs_desc.type = 0xb;
2592 cs_desc.s = cs_desc.g = cs_desc.p = 1;
2593 ctxt->ops->set_segment(ctxt, 0, &cs_desc, 0, VCPU_SREG_CS);
2594 }
2595
2596 /* For the 64-bit case, this will clear EFER.LMA. */
660a5d51
PB		 2597 cr0 = ctxt->ops->get_cr(ctxt, 0);
2598 if (cr0 & X86_CR0_PE)
2599 ctxt->ops->set_cr(ctxt, 0, cr0 & ~(X86_CR0_PG | X86_CR0_PE));
89651a3d
PB		 2600
2601 /* Now clear CR4.PAE (which must be done before clearing EFER.LME). */
660a5d51
PB		 2602 if (cr4 & X86_CR4_PAE)
2603 ctxt->ops->set_cr(ctxt, 4, cr4 & ~X86_CR4_PAE);
89651a3d
PB		 2604
2605 /* And finally go back to 32-bit mode. */
660a5d51
PB		 2606 efer = 0;
2607 ctxt->ops->set_msr(ctxt, MSR_EFER, efer);
2608
0234bf88
LP		 2609 /*
2610 * Give pre_leave_smm() a chance to make ISA-specific changes to the
2611 * vCPU state (e.g. enter guest mode) before loading state from the SMM
2612 * state-save area.
2613 */
ed19321f 2614 if (ctxt->ops->pre_leave_smm(ctxt, buf))
0234bf88
LP		 2615 return X86EMUL_UNHANDLEABLE;
2616
660a5d51 2617 if (emulator_has_longmode(ctxt))
ed19321f 2618 ret = rsm_load_state_64(ctxt, buf);
660a5d51 2619 else
ed19321f 2620 ret = rsm_load_state_32(ctxt, buf);
660a5d51
PB		 2621
2622 if (ret != X86EMUL_CONTINUE) {
2623 /* FIXME: should triple fault */
2624 return X86EMUL_UNHANDLEABLE;
2625 }
2626
6ed071f0 2627 if ((ctxt->ops->get_hflags(ctxt) & X86EMUL_SMM_INSIDE_NMI_MASK) == 0)
660a5d51
PB		 2628 ctxt->ops->set_nmi_mask(ctxt, false);
2629
6ed071f0
LP		 2630 ctxt->ops->set_hflags(ctxt, ctxt->ops->get_hflags(ctxt) &
2631 ~(X86EMUL_SMM_INSIDE_NMI_MASK | X86EMUL_SMM_MASK));
c5833c7a
SC		 2632
2633 ctxt->ops->post_leave_smm(ctxt);
2634
660a5d51 2635 return X86EMUL_CONTINUE;
64d60670
PB		 2636}
2637
7b105ca2 2638static void
e66bb2cc 2639setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 2640 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 2641{
e66bb2cc 2642 cs->l = 0; /* will be adjusted later */
79168fd1 2643 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 2644 cs->g = 1; /* 4kb granularity */
79168fd1 2645 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2646 cs->type = 0x0b; /* Read, Execute, Accessed */
2647 cs->s = 1;
2648 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 2649 cs->p = 1;
2650 cs->d = 1;
99245b50 2651 cs->avl = 0;
e66bb2cc 2652
79168fd1
GN		 2653 set_desc_base(ss, 0); /* flat segment */
2654 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2655 ss->g = 1; /* 4kb granularity */
2656 ss->s = 1;
2657 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2658 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2659 ss->dpl = 0;
79168fd1 2660 ss->p = 1;
99245b50
GN		 2661 ss->l = 0;
2662 ss->avl = 0;
e66bb2cc
AP		 2663}
2664
1a18a69b
AK		 2665static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2666{
2667 u32 eax, ebx, ecx, edx;
2668
2669 eax = ecx = 0;
e911eb3b 2670 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, false);
0017f93a 2671 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1a18a69b
AK		 2672 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2673 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2674}
2675
c2226fc9
SB		 2676static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2677{
0225fb50 2678 const struct x86_emulate_ops *ops = ctxt->ops;
c2226fc9
SB		 2679 u32 eax, ebx, ecx, edx;
2680
2681 /*
2682 * syscall should always be enabled in longmode - so only become
2683 * vendor specific (cpuid) if other modes are active...
2684 */
2685 if (ctxt->mode == X86EMUL_MODE_PROT64)
2686 return true;
2687
2688 eax = 0x00000000;
2689 ecx = 0x00000000;
e911eb3b 2690 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, false);
0017f93a
AK		 2691 /*
2692 * Intel ("GenuineIntel")
2693 * remark: Intel CPUs only support "syscall" in 64bit
2694 * longmode. Also an 64bit guest with a
2695 * 32bit compat-app running will #UD !! While this
2696 * behaviour can be fixed (by emulating) into AMD
2697 * response - CPUs of AMD can't behave like Intel.
2698 */
2699 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2700 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2701 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2702 return false;
2703
2704 /* AMD ("AuthenticAMD") */
2705 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2706 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2707 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2708 return true;
2709
2710 /* AMD ("AMDisbetter!") */
2711 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2712 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2713 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2714 return true;
c2226fc9 2715
b8f4abb6
PW		 2716 /* Hygon ("HygonGenuine") */
2717 if (ebx == X86EMUL_CPUID_VENDOR_HygonGenuine_ebx &&
2718 ecx == X86EMUL_CPUID_VENDOR_HygonGenuine_ecx &&
2719 edx == X86EMUL_CPUID_VENDOR_HygonGenuine_edx)
2720 return true;
2721
2722 /*
2723 * default: (not Intel, not AMD, not Hygon), apply Intel's
2724 * stricter rules...
2725 */
c2226fc9
SB		 2726 return false;
2727}
2728
e01991e7 2729static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2730{
0225fb50 2731 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2732 struct desc_struct cs, ss;
e66bb2cc 2733 u64 msr_data;
79168fd1 2734 u16 cs_sel, ss_sel;
c2ad2bb3 2735 u64 efer = 0;
e66bb2cc
AP		 2736
2737 /* syscall is not available in real mode */
2e901c4c 2738 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2739 ctxt->mode == X86EMUL_MODE_VM86)
2740 return emulate_ud(ctxt);
e66bb2cc 2741
c2226fc9
SB		 2742 if (!(em_syscall_is_enabled(ctxt)))
2743 return emulate_ud(ctxt);
2744
c2ad2bb3 2745 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2746 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2747
c2226fc9
SB		 2748 if (!(efer & EFER_SCE))
2749 return emulate_ud(ctxt);
2750
717746e3 2751 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2752 msr_data >>= 32;
79168fd1
GN		 2753 cs_sel = (u16)(msr_data & 0xfffc);
2754 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2755
c2ad2bb3 2756 if (efer & EFER_LMA) {
79168fd1 2757 cs.d = 0;
e66bb2cc
AP		 2758 cs.l = 1;
2759 }
1aa36616
AK		 2760 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2761 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2762
dd856efa 2763 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
c2ad2bb3 2764 if (efer & EFER_LMA) {
e66bb2cc 2765#ifdef CONFIG_X86_64
6c6cb69b 2766 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags;
e66bb2cc 2767
717746e3 2768 ops->get_msr(ctxt,
3fb1b5db
GN		 2769 ctxt->mode == X86EMUL_MODE_PROT64 ?
2770 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2771 ctxt->_eip = msr_data;
e66bb2cc 2772
717746e3 2773 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
6c6cb69b 2774 ctxt->eflags &= ~msr_data;
35fd68a3 2775 ctxt->eflags |= X86_EFLAGS_FIXED;
e66bb2cc
AP		 2776#endif
2777 } else {
2778 /* legacy mode */
717746e3 2779 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2780 ctxt->_eip = (u32)msr_data;
e66bb2cc 2781
0efb0440 2782 ctxt->eflags &= ~(X86_EFLAGS_VM | X86_EFLAGS_IF);
e66bb2cc
AP		 2783 }
2784
c8401dda 2785 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
e54cfa97 2786 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2787}
2788
e01991e7 2789static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2790{
0225fb50 2791 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2792 struct desc_struct cs, ss;
8c604352 2793 u64 msr_data;
79168fd1 2794 u16 cs_sel, ss_sel;
c2ad2bb3 2795 u64 efer = 0;
8c604352 2796
7b105ca2 2797 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2798 /* inject #GP if in real mode */
35d3d4a1
AK		 2799 if (ctxt->mode == X86EMUL_MODE_REAL)
2800 return emulate_gp(ctxt, 0);
8c604352 2801
1a18a69b
AK		 2802 /*
2803 * Not recognized on AMD in compat mode (but is recognized in legacy
2804 * mode).
2805 */
f3747379 2806 if ((ctxt->mode != X86EMUL_MODE_PROT64) && (efer & EFER_LMA)
1a18a69b
AK		 2807 && !vendor_intel(ctxt))
2808 return emulate_ud(ctxt);
2809
b2c9d43e 2810 /* sysenter/sysexit have not been tested in 64bit mode. */
35d3d4a1 2811 if (ctxt->mode == X86EMUL_MODE_PROT64)
b2c9d43e 2812 return X86EMUL_UNHANDLEABLE;
8c604352 2813
7b105ca2 2814 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2815
717746e3 2816 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
f3747379
NA		 2817 if ((msr_data & 0xfffc) == 0x0)
2818 return emulate_gp(ctxt, 0);
8c604352 2819
0efb0440 2820 ctxt->eflags &= ~(X86_EFLAGS_VM | X86_EFLAGS_IF);
b32a9918 2821 cs_sel = (u16)msr_data & ~SEGMENT_RPL_MASK;
79168fd1 2822 ss_sel = cs_sel + 8;
f3747379 2823 if (efer & EFER_LMA) {
79168fd1 2824 cs.d = 0;
8c604352
AP		 2825 cs.l = 1;
2826 }
2827
1aa36616
AK		 2828 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2829 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2830
717746e3 2831 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
f3747379 2832 ctxt->_eip = (efer & EFER_LMA) ? msr_data : (u32)msr_data;
8c604352 2833
717746e3 2834 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
f3747379
NA		 2835 *reg_write(ctxt, VCPU_REGS_RSP) = (efer & EFER_LMA) ? msr_data :
2836 (u32)msr_data;
8c604352 2837
e54cfa97 2838 return X86EMUL_CONTINUE;
8c604352
AP		 2839}
2840
e01991e7 2841static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2842{
0225fb50 2843 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2844 struct desc_struct cs, ss;
234f3ce4 2845 u64 msr_data, rcx, rdx;
4668f050 2846 int usermode;
1249b96e 2847 u16 cs_sel = 0, ss_sel = 0;
4668f050 2848
a0044755
GN		 2849 /* inject #GP if in real mode or Virtual 8086 mode */
2850 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2851 ctxt->mode == X86EMUL_MODE_VM86)
2852 return emulate_gp(ctxt, 0);
4668f050 2853
7b105ca2 2854 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2855
9dac77fa 2856 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2857 usermode = X86EMUL_MODE_PROT64;
2858 else
2859 usermode = X86EMUL_MODE_PROT32;
2860
234f3ce4
NA		 2861 rcx = reg_read(ctxt, VCPU_REGS_RCX);
2862 rdx = reg_read(ctxt, VCPU_REGS_RDX);
2863
4668f050
AP		 2864 cs.dpl = 3;
2865 ss.dpl = 3;
717746e3 2866 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2867 switch (usermode) {
2868 case X86EMUL_MODE_PROT32:
79168fd1 2869 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2870 if ((msr_data & 0xfffc) == 0x0)
2871 return emulate_gp(ctxt, 0);
79168fd1 2872 ss_sel = (u16)(msr_data + 24);
bf0b682c
NA		 2873 rcx = (u32)rcx;
2874 rdx = (u32)rdx;
4668f050
AP		 2875 break;
2876 case X86EMUL_MODE_PROT64:
79168fd1 2877 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2878 if (msr_data == 0x0)
2879 return emulate_gp(ctxt, 0);
79168fd1
GN		 2880 ss_sel = cs_sel + 8;
2881 cs.d = 0;
4668f050 2882 cs.l = 1;
fd8cb433
YZ		 2883 if (emul_is_noncanonical_address(rcx, ctxt) ||
2884 emul_is_noncanonical_address(rdx, ctxt))
234f3ce4 2885 return emulate_gp(ctxt, 0);
4668f050
AP		 2886 break;
2887 }
b32a9918
NA		 2888 cs_sel |= SEGMENT_RPL_MASK;
2889 ss_sel |= SEGMENT_RPL_MASK;
4668f050 2890
1aa36616
AK		 2891 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2892 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2893
234f3ce4
NA		 2894 ctxt->_eip = rdx;
2895 *reg_write(ctxt, VCPU_REGS_RSP) = rcx;
4668f050 2896
e54cfa97 2897 return X86EMUL_CONTINUE;
4668f050
AP		 2898}
2899
7b105ca2 2900static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2901{
2902 int iopl;
2903 if (ctxt->mode == X86EMUL_MODE_REAL)
2904 return false;
2905 if (ctxt->mode == X86EMUL_MODE_VM86)
2906 return true;
0efb0440 2907 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> X86_EFLAGS_IOPL_BIT;
7b105ca2 2908 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2909}
2910
9a29d449
LA		 2911#define VMWARE_PORT_VMPORT (0x5658)
2912#define VMWARE_PORT_VMRPC (0x5659)
2913
f850e2e6 2914static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2915 u16 port, u16 len)
2916{
0225fb50 2917 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2918 struct desc_struct tr_seg;
5601d05b 2919 u32 base3;
f850e2e6 2920 int r;
1aa36616 2921 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2922 unsigned mask = (1 << len) - 1;
5601d05b 2923 unsigned long base;
f850e2e6 2924
9a29d449
LA		 2925 /*
2926 * VMware allows access to these ports even if denied
2927 * by TSS I/O permission bitmap. Mimic behavior.
2928 */
2929 if (enable_vmware_backdoor &&
2930 ((port == VMWARE_PORT_VMPORT) || (port == VMWARE_PORT_VMRPC)))
2931 return true;
2932
1aa36616 2933 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2934 if (!tr_seg.p)
f850e2e6 2935 return false;
79168fd1 2936 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2937 return false;
5601d05b
GN		 2938 base = get_desc_base(&tr_seg);
2939#ifdef CONFIG_X86_64
2940 base |= ((u64)base3) << 32;
2941#endif
3c9fa24c 2942 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL, true);
f850e2e6
GN		 2943 if (r != X86EMUL_CONTINUE)
2944 return false;
79168fd1 2945 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2946 return false;
3c9fa24c 2947 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL, true);
f850e2e6
GN		 2948 if (r != X86EMUL_CONTINUE)
2949 return false;
2950 if ((perm >> bit_idx) & mask)
2951 return false;
2952 return true;
2953}
2954
2955static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2956 u16 port, u16 len)
2957{
4fc40f07
GN		 2958 if (ctxt->perm_ok)
2959 return true;
2960
7b105ca2
TY		 2961 if (emulator_bad_iopl(ctxt))
2962 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2963 return false;
4fc40f07
GN		 2964
2965 ctxt->perm_ok = true;
2966
f850e2e6
GN		 2967 return true;
2968}
2969
428e3d08
NA		 2970static void string_registers_quirk(struct x86_emulate_ctxt *ctxt)
2971{
2972 /*
2973 * Intel CPUs mask the counter and pointers in quite strange
2974 * manner when ECX is zero due to REP-string optimizations.
2975 */
2976#ifdef CONFIG_X86_64
2977 if (ctxt->ad_bytes != 4 || !vendor_intel(ctxt))
2978 return;
2979
2980 *reg_write(ctxt, VCPU_REGS_RCX) = 0;
2981
2982 switch (ctxt->b) {
2983 case 0xa4: /* movsb */
2984 case 0xa5: /* movsd/w */
2985 *reg_rmw(ctxt, VCPU_REGS_RSI) &= (u32)-1;
2986 /* fall through */
2987 case 0xaa: /* stosb */
2988 case 0xab: /* stosd/w */
2989 *reg_rmw(ctxt, VCPU_REGS_RDI) &= (u32)-1;
2990 }
2991#endif
2992}
2993
38ba30ba 2994static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2995 struct tss_segment_16 *tss)
2996{
9dac77fa 2997 tss->ip = ctxt->_eip;
38ba30ba 2998 tss->flag = ctxt->eflags;
dd856efa
AK		 2999 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
3000 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
3001 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
3002 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
3003 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
3004 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
3005 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
3006 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 3007
1aa36616
AK		 3008 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
3009 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
3010 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
3011 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
3012 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 3013}
3014
3015static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 3016 struct tss_segment_16 *tss)
3017{
38ba30ba 3018 int ret;
2356aaeb 3019 u8 cpl;
38ba30ba 3020
9dac77fa 3021 ctxt->_eip = tss->ip;
38ba30ba 3022 ctxt->eflags = tss->flag | 2;
dd856efa
AK		 3023 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
3024 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
3025 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
3026 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
3027 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
3028 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
3029 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
3030 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
38ba30ba
GN		 3031
3032 /*
3033 * SDM says that segment selectors are loaded before segment
3034 * descriptors
3035 */
1aa36616
AK		 3036 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
3037 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
3038 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
3039 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
3040 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba 3041
2356aaeb
PB		 3042 cpl = tss->cs & 3;
3043
38ba30ba 3044 /*
fc058680 3045 * Now load segment descriptors. If fault happens at this stage
38ba30ba
GN		 3046 * it is handled in a context of new task
3047 */
d1442d85 3048 ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl,
3dc4bc4f 3049 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3050 if (ret != X86EMUL_CONTINUE)
3051 return ret;
d1442d85 3052 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
3dc4bc4f 3053 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3054 if (ret != X86EMUL_CONTINUE)
3055 return ret;
d1442d85 3056 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
3dc4bc4f 3057 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3058 if (ret != X86EMUL_CONTINUE)
3059 return ret;
d1442d85 3060 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
3dc4bc4f 3061 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3062 if (ret != X86EMUL_CONTINUE)
3063 return ret;
d1442d85 3064 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
3dc4bc4f 3065 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3066 if (ret != X86EMUL_CONTINUE)
3067 return ret;
3068
3069 return X86EMUL_CONTINUE;
3070}
3071
3072static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 3073 u16 tss_selector, u16 old_tss_sel,
3074 ulong old_tss_base, struct desc_struct *new_desc)
3075{
3076 struct tss_segment_16 tss_seg;
3077 int ret;
bcc55cba 3078 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 3079
0e96f31e 3080 ret = linear_read_system(ctxt, old_tss_base, &tss_seg, sizeof(tss_seg));
db297e3d 3081 if (ret != X86EMUL_CONTINUE)
38ba30ba 3082 return ret;
38ba30ba 3083
7b105ca2 3084 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 3085
0e96f31e 3086 ret = linear_write_system(ctxt, old_tss_base, &tss_seg, sizeof(tss_seg));
db297e3d 3087 if (ret != X86EMUL_CONTINUE)
38ba30ba 3088 return ret;
38ba30ba 3089
0e96f31e 3090 ret = linear_read_system(ctxt, new_tss_base, &tss_seg, sizeof(tss_seg));
db297e3d 3091 if (ret != X86EMUL_CONTINUE)
38ba30ba 3092 return ret;
38ba30ba
GN		 3093
3094 if (old_tss_sel != 0xffff) {
3095 tss_seg.prev_task_link = old_tss_sel;
3096
79367a65
PB		 3097 ret = linear_write_system(ctxt, new_tss_base,
3098 &tss_seg.prev_task_link,
0e96f31e 3099 sizeof(tss_seg.prev_task_link));
db297e3d 3100 if (ret != X86EMUL_CONTINUE)
38ba30ba 3101 return ret;
38ba30ba
GN		 3102 }
3103
7b105ca2 3104 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 3105}
3106
3107static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 3108 struct tss_segment_32 *tss)
3109{
5c7411e2 3110 /* CR3 and ldt selector are not saved intentionally */
9dac77fa 3111 tss->eip = ctxt->_eip;
38ba30ba 3112 tss->eflags = ctxt->eflags;
dd856efa
AK		 3113 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
3114 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
3115 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
3116 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
3117 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
3118 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
3119 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
3120 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 3121
1aa36616
AK		 3122 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
3123 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
3124 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
3125 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
3126 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
3127 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
38ba30ba
GN		 3128}
3129
3130static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 3131 struct tss_segment_32 *tss)
3132{
38ba30ba 3133 int ret;
2356aaeb 3134 u8 cpl;
38ba30ba 3135
7b105ca2 3136 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 3137 return emulate_gp(ctxt, 0);
9dac77fa 3138 ctxt->_eip = tss->eip;
38ba30ba 3139 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 3140
3141 /* General purpose registers */
dd856efa
AK		 3142 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
3143 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
3144 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
3145 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
3146 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
3147 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
3148 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
3149 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
38ba30ba
GN		 3150
3151 /*
3152 * SDM says that segment selectors are loaded before segment
2356aaeb
PB		 3153 * descriptors. This is important because CPL checks will
3154 * use CS.RPL.
38ba30ba 3155 */
1aa36616
AK		 3156 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
3157 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
3158 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
3159 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
3160 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
3161 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
3162 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 3163
4cee4798
KW		 3164 /*
3165 * If we're switching between Protected Mode and VM86, we need to make
3166 * sure to update the mode before loading the segment descriptors so
3167 * that the selectors are interpreted correctly.
4cee4798 3168 */
2356aaeb 3169 if (ctxt->eflags & X86_EFLAGS_VM) {
4cee4798 3170 ctxt->mode = X86EMUL_MODE_VM86;
2356aaeb
PB		 3171 cpl = 3;
3172 } else {
4cee4798 3173 ctxt->mode = X86EMUL_MODE_PROT32;
2356aaeb
PB		 3174 cpl = tss->cs & 3;
3175 }
4cee4798 3176
38ba30ba
GN		 3177 /*
3178 * Now load segment descriptors. If fault happenes at this stage
3179 * it is handled in a context of new task
3180 */
d1442d85 3181 ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR,
3dc4bc4f 3182 cpl, X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3183 if (ret != X86EMUL_CONTINUE)
3184 return ret;
d1442d85 3185 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
3dc4bc4f 3186 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3187 if (ret != X86EMUL_CONTINUE)
3188 return ret;
d1442d85 3189 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
3dc4bc4f 3190 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3191 if (ret != X86EMUL_CONTINUE)
3192 return ret;
d1442d85 3193 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
3dc4bc4f 3194 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3195 if (ret != X86EMUL_CONTINUE)
3196 return ret;
d1442d85 3197 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
3dc4bc4f 3198 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3199 if (ret != X86EMUL_CONTINUE)
3200 return ret;
d1442d85 3201 ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl,
3dc4bc4f 3202 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3203 if (ret != X86EMUL_CONTINUE)
3204 return ret;
d1442d85 3205 ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl,
3dc4bc4f 3206 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba 3207
2f729b10 3208 return ret;
38ba30ba
GN		 3209}
3210
3211static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 3212 u16 tss_selector, u16 old_tss_sel,
3213 ulong old_tss_base, struct desc_struct *new_desc)
3214{
3215 struct tss_segment_32 tss_seg;
3216 int ret;
bcc55cba 3217 u32 new_tss_base = get_desc_base(new_desc);
5c7411e2
NA		 3218 u32 eip_offset = offsetof(struct tss_segment_32, eip);
3219 u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector);
38ba30ba 3220
0e96f31e 3221 ret = linear_read_system(ctxt, old_tss_base, &tss_seg, sizeof(tss_seg));
db297e3d 3222 if (ret != X86EMUL_CONTINUE)
38ba30ba 3223 return ret;
38ba30ba 3224
7b105ca2 3225 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 3226
5c7411e2 3227 /* Only GP registers and segment selectors are saved */
79367a65
PB		 3228 ret = linear_write_system(ctxt, old_tss_base + eip_offset, &tss_seg.eip,
3229 ldt_sel_offset - eip_offset);
db297e3d 3230 if (ret != X86EMUL_CONTINUE)
38ba30ba 3231 return ret;
38ba30ba 3232
0e96f31e 3233 ret = linear_read_system(ctxt, new_tss_base, &tss_seg, sizeof(tss_seg));
db297e3d 3234 if (ret != X86EMUL_CONTINUE)
38ba30ba 3235 return ret;
38ba30ba
GN		 3236
3237 if (old_tss_sel != 0xffff) {
3238 tss_seg.prev_task_link = old_tss_sel;
3239
79367a65
PB		 3240 ret = linear_write_system(ctxt, new_tss_base,
3241 &tss_seg.prev_task_link,
0e96f31e 3242 sizeof(tss_seg.prev_task_link));
db297e3d 3243 if (ret != X86EMUL_CONTINUE)
38ba30ba 3244 return ret;
38ba30ba
GN		 3245 }
3246
7b105ca2 3247 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 3248}
3249
3250static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 3251 u16 tss_selector, int idt_index, int reason,
e269fb21 3252 bool has_error_code, u32 error_code)
38ba30ba 3253{
0225fb50 3254 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 3255 struct desc_struct curr_tss_desc, next_tss_desc;
3256 int ret;
1aa36616 3257 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 3258 ulong old_tss_base =
4bff1e86 3259 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 3260 u32 desc_limit;
3db176d5 3261 ulong desc_addr, dr7;
38ba30ba
GN		 3262
3263 /* FIXME: old_tss_base == ~0 ? */
3264
e919464b 3265 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
38ba30ba
GN		 3266 if (ret != X86EMUL_CONTINUE)
3267 return ret;
e919464b 3268 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
38ba30ba
GN		 3269 if (ret != X86EMUL_CONTINUE)
3270 return ret;
3271
3272 /* FIXME: check that next_tss_desc is tss */
3273
7f3d35fd
KW		 3274 /*
3275 * Check privileges. The three cases are task switch caused by...
3276 *
3277 * 1. jmp/call/int to task gate: Check against DPL of the task gate
3278 * 2. Exception/IRQ/iret: No check is performed
2c2ca2d1
NA		 3279 * 3. jmp/call to TSS/task-gate: No check is performed since the
3280 * hardware checks it before exiting.
7f3d35fd
KW		 3281 */
3282 if (reason == TASK_SWITCH_GATE) {
3283 if (idt_index != -1) {
3284 /* Software interrupts */
3285 struct desc_struct task_gate_desc;
3286 int dpl;
3287
3288 ret = read_interrupt_descriptor(ctxt, idt_index,
3289 &task_gate_desc);
3290 if (ret != X86EMUL_CONTINUE)
3291 return ret;
3292
3293 dpl = task_gate_desc.dpl;
3294 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
3295 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
3296 }
38ba30ba
GN		 3297 }
3298
ceffb459
GN		 3299 desc_limit = desc_limit_scaled(&next_tss_desc);
3300 if (!next_tss_desc.p ||
3301 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
3302 desc_limit < 0x2b)) {
592f0858 3303 return emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 3304 }
3305
3306 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3307 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 3308 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 3309 }
3310
3311 if (reason == TASK_SWITCH_IRET)
3312 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
3313
3314 /* set back link to prev task only if NT bit is set in eflags
fc058680 3315 note that old_tss_sel is not used after this point */
38ba30ba
GN		 3316 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
3317 old_tss_sel = 0xffff;
3318
3319 if (next_tss_desc.type & 8)
7b105ca2 3320 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 3321 old_tss_base, &next_tss_desc);
3322 else
7b105ca2 3323 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 3324 old_tss_base, &next_tss_desc);
0760d448
JK		 3325 if (ret != X86EMUL_CONTINUE)
3326 return ret;
38ba30ba
GN		 3327
3328 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
3329 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
3330
3331 if (reason != TASK_SWITCH_IRET) {
3332 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 3333 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 3334 }
3335
717746e3 3336 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 3337 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 3338
e269fb21 3339 if (has_error_code) {
9dac77fa
AK		 3340 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
3341 ctxt->lock_prefix = 0;
3342 ctxt->src.val = (unsigned long) error_code;
4487b3b4 3343 ret = em_push(ctxt);
e269fb21
JK		 3344 }
3345
3db176d5
NA		 3346 ops->get_dr(ctxt, 7, &dr7);
3347 ops->set_dr(ctxt, 7, dr7 & ~(DR_LOCAL_ENABLE_MASK | DR_LOCAL_SLOWDOWN));
3348
38ba30ba
GN		 3349 return ret;
3350}
3351
3352int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 3353 u16 tss_selector, int idt_index, int reason,
e269fb21 3354 bool has_error_code, u32 error_code)
38ba30ba 3355{
38ba30ba
GN		 3356 int rc;
3357
dd856efa 3358 invalidate_registers(ctxt);
9dac77fa
AK		 3359 ctxt->_eip = ctxt->eip;
3360 ctxt->dst.type = OP_NONE;
38ba30ba 3361
7f3d35fd 3362 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 3363 has_error_code, error_code);
38ba30ba 3364
dd856efa 3365 if (rc == X86EMUL_CONTINUE) {
9dac77fa 3366 ctxt->eip = ctxt->_eip;
dd856efa
AK		 3367 writeback_registers(ctxt);
3368 }
38ba30ba 3369
a0c0ab2f 3370 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 3371}
3372
f3bd64c6
GN		 3373static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
3374 struct operand *op)
a682e354 3375{
0efb0440 3376 int df = (ctxt->eflags & X86_EFLAGS_DF) ? -op->count : op->count;
a682e354 3377
01485a22
PB		 3378 register_address_increment(ctxt, reg, df * op->bytes);
3379 op->addr.mem.ea = register_address(ctxt, reg);
a682e354
GN		 3380}
3381
7af04fc0
AK		 3382static int em_das(struct x86_emulate_ctxt *ctxt)
3383{
7af04fc0
AK		 3384 u8 al, old_al;
3385 bool af, cf, old_cf;
3386
3387 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 3388 al = ctxt->dst.val;
7af04fc0
AK		 3389
3390 old_al = al;
3391 old_cf = cf;
3392 cf = false;
3393 af = ctxt->eflags & X86_EFLAGS_AF;
3394 if ((al & 0x0f) > 9 || af) {
3395 al -= 6;
3396 cf = old_cf | (al >= 250);
3397 af = true;
3398 } else {
3399 af = false;
3400 }
3401 if (old_al > 0x99 || old_cf) {
3402 al -= 0x60;
3403 cf = true;
3404 }
3405
9dac77fa 3406 ctxt->dst.val = al;
7af04fc0 3407 /* Set PF, ZF, SF */
9dac77fa
AK		 3408 ctxt->src.type = OP_IMM;
3409 ctxt->src.val = 0;
3410 ctxt->src.bytes = 1;
158de57f 3411 fastop(ctxt, em_or);
7af04fc0
AK		 3412 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
3413 if (cf)
3414 ctxt->eflags |= X86_EFLAGS_CF;
3415 if (af)
3416 ctxt->eflags |= X86_EFLAGS_AF;
3417 return X86EMUL_CONTINUE;
3418}
3419
a035d5c6
PB		 3420static int em_aam(struct x86_emulate_ctxt *ctxt)
3421{
3422 u8 al, ah;
3423
3424 if (ctxt->src.val == 0)
3425 return emulate_de(ctxt);
3426
3427 al = ctxt->dst.val & 0xff;
3428 ah = al / ctxt->src.val;
3429 al %= ctxt->src.val;
3430
3431 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);
3432
3433 /* Set PF, ZF, SF */
3434 ctxt->src.type = OP_IMM;
3435 ctxt->src.val = 0;
3436 ctxt->src.bytes = 1;
3437 fastop(ctxt, em_or);
3438
3439 return X86EMUL_CONTINUE;
3440}
3441
7f662273
GN		 3442static int em_aad(struct x86_emulate_ctxt *ctxt)
3443{
3444 u8 al = ctxt->dst.val & 0xff;
3445 u8 ah = (ctxt->dst.val >> 8) & 0xff;
3446
3447 al = (al + (ah * ctxt->src.val)) & 0xff;
3448
3449 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
3450
f583c29b
GN		 3451 /* Set PF, ZF, SF */
3452 ctxt->src.type = OP_IMM;
3453 ctxt->src.val = 0;
3454 ctxt->src.bytes = 1;
3455 fastop(ctxt, em_or);
7f662273
GN		 3456
3457 return X86EMUL_CONTINUE;
3458}
3459
d4ddafcd
TY		 3460static int em_call(struct x86_emulate_ctxt *ctxt)
3461{
234f3ce4 3462 int rc;
d4ddafcd
TY		 3463 long rel = ctxt->src.val;
3464
3465 ctxt->src.val = (unsigned long)ctxt->_eip;
234f3ce4
NA		 3466 rc = jmp_rel(ctxt, rel);
3467 if (rc != X86EMUL_CONTINUE)
3468 return rc;
d4ddafcd
TY		 3469 return em_push(ctxt);
3470}
3471
0ef753b8
AK		 3472static int em_call_far(struct x86_emulate_ctxt *ctxt)
3473{
0ef753b8
AK		 3474 u16 sel, old_cs;
3475 ulong old_eip;
3476 int rc;
d1442d85
NA		 3477 struct desc_struct old_desc, new_desc;
3478 const struct x86_emulate_ops *ops = ctxt->ops;
3479 int cpl = ctxt->ops->cpl(ctxt);
82268083 3480 enum x86emul_mode prev_mode = ctxt->mode;
0ef753b8 3481
9dac77fa 3482 old_eip = ctxt->_eip;
d1442d85 3483 ops->get_segment(ctxt, &old_cs, &old_desc, NULL, VCPU_SREG_CS);
0ef753b8 3484
9dac77fa 3485 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
3dc4bc4f
NA		 3486 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl,
3487 X86_TRANSFER_CALL_JMP, &new_desc);
d1442d85 3488 if (rc != X86EMUL_CONTINUE)
80976dbb 3489 return rc;
0ef753b8 3490
d50eaa18 3491 rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc);
d1442d85
NA		 3492 if (rc != X86EMUL_CONTINUE)
3493 goto fail;
0ef753b8 3494
9dac77fa 3495 ctxt->src.val = old_cs;
4487b3b4 3496 rc = em_push(ctxt);
0ef753b8 3497 if (rc != X86EMUL_CONTINUE)
d1442d85 3498 goto fail;
0ef753b8 3499
9dac77fa 3500 ctxt->src.val = old_eip;
d1442d85
NA		 3501 rc = em_push(ctxt);
3502 /* If we failed, we tainted the memory, but the very least we should
3503 restore cs */
82268083
NA		 3504 if (rc != X86EMUL_CONTINUE) {
3505 pr_warn_once("faulting far call emulation tainted memory\n");
d1442d85 3506 goto fail;
82268083 3507 }
d1442d85
NA		 3508 return rc;
3509fail:
3510 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
82268083 3511 ctxt->mode = prev_mode;
d1442d85
NA		 3512 return rc;
3513
0ef753b8
AK		 3514}
3515
40ece7c7
AK		 3516static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
3517{
40ece7c7 3518 int rc;
234f3ce4 3519 unsigned long eip;
40ece7c7 3520
234f3ce4
NA		 3521 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
3522 if (rc != X86EMUL_CONTINUE)
3523 return rc;
3524 rc = assign_eip_near(ctxt, eip);
40ece7c7
AK		 3525 if (rc != X86EMUL_CONTINUE)
3526 return rc;
5ad105e5 3527 rsp_increment(ctxt, ctxt->src.val);
40ece7c7
AK		 3528 return X86EMUL_CONTINUE;
3529}
3530
e4f973ae
TY		 3531static int em_xchg(struct x86_emulate_ctxt *ctxt)
3532{
e4f973ae 3533 /* Write back the register source. */
9dac77fa
AK		 3534 ctxt->src.val = ctxt->dst.val;
3535 write_register_operand(&ctxt->src);
e4f973ae
TY		 3536
3537 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 3538 ctxt->dst.val = ctxt->src.orig_val;
3539 ctxt->lock_prefix = 1;
e4f973ae
TY		 3540 return X86EMUL_CONTINUE;
3541}
3542
5c82aa29
AK		 3543static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
3544{
9dac77fa 3545 ctxt->dst.val = ctxt->src2.val;
4d758349 3546 return fastop(ctxt, em_imul);
5c82aa29
AK		 3547}
3548
61429142
AK		 3549static int em_cwd(struct x86_emulate_ctxt *ctxt)
3550{
9dac77fa
AK		 3551 ctxt->dst.type = OP_REG;
3552 ctxt->dst.bytes = ctxt->src.bytes;
dd856efa 3553 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
9dac77fa 3554 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 3555
3556 return X86EMUL_CONTINUE;
3557}
3558
fb6d4d34
PB		 3559static int em_rdpid(struct x86_emulate_ctxt *ctxt)
3560{
3561 u64 tsc_aux = 0;
3562
3563 if (ctxt->ops->get_msr(ctxt, MSR_TSC_AUX, &tsc_aux))
3564 return emulate_gp(ctxt, 0);
3565 ctxt->dst.val = tsc_aux;
3566 return X86EMUL_CONTINUE;
3567}
3568
48bb5d3c
AK		 3569static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
3570{
48bb5d3c
AK		 3571 u64 tsc = 0;
3572
717746e3 3573 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
dd856efa
AK		 3574 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
3575 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
48bb5d3c
AK		 3576 return X86EMUL_CONTINUE;
3577}
3578
222d21aa
AK		 3579static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
3580{
3581 u64 pmc;
3582
dd856efa 3583 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
222d21aa 3584 return emulate_gp(ctxt, 0);
dd856efa
AK		 3585 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
3586 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
222d21aa
AK		 3587 return X86EMUL_CONTINUE;
3588}
3589
b9eac5f4
AK		 3590static int em_mov(struct x86_emulate_ctxt *ctxt)
3591{
54cfdb3e 3592 memcpy(ctxt->dst.valptr, ctxt->src.valptr, sizeof(ctxt->src.valptr));
b9eac5f4
AK		 3593 return X86EMUL_CONTINUE;
3594}
3595
84cffe49
BP		 3596#define FFL(x) bit(X86_FEATURE_##x)
3597
3598static int em_movbe(struct x86_emulate_ctxt *ctxt)
3599{
3600 u32 ebx, ecx, edx, eax = 1;
3601 u16 tmp;
3602
3603 /*
3604 * Check MOVBE is set in the guest-visible CPUID leaf.
3605 */
e911eb3b 3606 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, false);
84cffe49
BP		 3607 if (!(ecx & FFL(MOVBE)))
3608 return emulate_ud(ctxt);
3609
3610 switch (ctxt->op_bytes) {
3611 case 2:
3612 /*
3613 * From MOVBE definition: "...When the operand size is 16 bits,
3614 * the upper word of the destination register remains unchanged
3615 * ..."
3616 *
3617 * Both casting ->valptr and ->val to u16 breaks strict aliasing
3618 * rules so we have to do the operation almost per hand.
3619 */
3620 tmp = (u16)ctxt->src.val;
3621 ctxt->dst.val &= ~0xffffUL;
3622 ctxt->dst.val |= (unsigned long)swab16(tmp);
3623 break;
3624 case 4:
3625 ctxt->dst.val = swab32((u32)ctxt->src.val);
3626 break;
3627 case 8:
3628 ctxt->dst.val = swab64(ctxt->src.val);
3629 break;
3630 default:
592f0858 3631 BUG();
84cffe49
BP		 3632 }
3633 return X86EMUL_CONTINUE;
3634}
3635
bc00f8d2
TY		 3636static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3637{
3638 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
3639 return emulate_gp(ctxt, 0);
3640
3641 /* Disable writeback. */
3642 ctxt->dst.type = OP_NONE;
3643 return X86EMUL_CONTINUE;
3644}
3645
3646static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3647{
3648 unsigned long val;
3649
3650 if (ctxt->mode == X86EMUL_MODE_PROT64)
3651 val = ctxt->src.val & ~0ULL;
3652 else
3653 val = ctxt->src.val & ~0U;
3654
3655 /* #UD condition is already handled. */
3656 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3657 return emulate_gp(ctxt, 0);
3658
3659 /* Disable writeback. */
3660 ctxt->dst.type = OP_NONE;
3661 return X86EMUL_CONTINUE;
3662}
3663
e1e210b0
TY		 3664static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3665{
3666 u64 msr_data;
3667
dd856efa
AK		 3668 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3669 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3670 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
e1e210b0
TY		 3671 return emulate_gp(ctxt, 0);
3672
3673 return X86EMUL_CONTINUE;
3674}
3675
3676static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3677{
3678 u64 msr_data;
3679
dd856efa 3680 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
e1e210b0
TY		 3681 return emulate_gp(ctxt, 0);
3682
dd856efa
AK		 3683 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3684 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
e1e210b0
TY		 3685 return X86EMUL_CONTINUE;
3686}
3687
dd307d01 3688static int em_store_sreg(struct x86_emulate_ctxt *ctxt, int segment)
1bd5f469 3689{
dd307d01
PB		 3690 if (segment > VCPU_SREG_GS &&
3691 (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_UMIP) &&
3692 ctxt->ops->cpl(ctxt) > 0)
3693 return emulate_gp(ctxt, 0);
1bd5f469 3694
dd307d01 3695 ctxt->dst.val = get_segment_selector(ctxt, segment);
b5bbf10e
NA		 3696 if (ctxt->dst.bytes == 4 && ctxt->dst.type == OP_MEM)
3697 ctxt->dst.bytes = 2;
1bd5f469
TY		 3698 return X86EMUL_CONTINUE;
3699}
3700
dd307d01
PB		 3701static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3702{
3703 if (ctxt->modrm_reg > VCPU_SREG_GS)
3704 return emulate_ud(ctxt);
3705
3706 return em_store_sreg(ctxt, ctxt->modrm_reg);
3707}
3708
1bd5f469
TY		 3709static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3710{
9dac77fa 3711 u16 sel = ctxt->src.val;
1bd5f469 3712
9dac77fa 3713 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3714 return emulate_ud(ctxt);
3715
9dac77fa 3716 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 3717 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3718
3719 /* Disable writeback. */
9dac77fa
AK		 3720 ctxt->dst.type = OP_NONE;
3721 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 3722}
3723
dd307d01
PB		 3724static int em_sldt(struct x86_emulate_ctxt *ctxt)
3725{
3726 return em_store_sreg(ctxt, VCPU_SREG_LDTR);
3727}
3728
a14e579f
AK		 3729static int em_lldt(struct x86_emulate_ctxt *ctxt)
3730{
3731 u16 sel = ctxt->src.val;
3732
3733 /* Disable writeback. */
3734 ctxt->dst.type = OP_NONE;
3735 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3736}
3737
dd307d01
PB		 3738static int em_str(struct x86_emulate_ctxt *ctxt)
3739{
3740 return em_store_sreg(ctxt, VCPU_SREG_TR);
3741}
3742
80890006
AK		 3743static int em_ltr(struct x86_emulate_ctxt *ctxt)
3744{
3745 u16 sel = ctxt->src.val;
3746
3747 /* Disable writeback. */
3748 ctxt->dst.type = OP_NONE;
3749 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3750}
3751
38503911
AK		 3752static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3753{
9fa088f4
AK		 3754 int rc;
3755 ulong linear;
3756
9dac77fa 3757 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 3758 if (rc == X86EMUL_CONTINUE)
3cb16fe7 3759 ctxt->ops->invlpg(ctxt, linear);
38503911 3760 /* Disable writeback. */
9dac77fa 3761 ctxt->dst.type = OP_NONE;
38503911
AK		 3762 return X86EMUL_CONTINUE;
3763}
3764
2d04a05b
AK		 3765static int em_clts(struct x86_emulate_ctxt *ctxt)
3766{
3767 ulong cr0;
3768
3769 cr0 = ctxt->ops->get_cr(ctxt, 0);
3770 cr0 &= ~X86_CR0_TS;
3771 ctxt->ops->set_cr(ctxt, 0, cr0);
3772 return X86EMUL_CONTINUE;
3773}
3774
b34a8051 3775static int em_hypercall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3776{
0f54a321 3777 int rc = ctxt->ops->fix_hypercall(ctxt);
26d05cc7 3778
26d05cc7
AK		 3779 if (rc != X86EMUL_CONTINUE)
3780 return rc;
3781
3782 /* Let the processor re-execute the fixed hypercall */
9dac77fa 3783 ctxt->_eip = ctxt->eip;
26d05cc7 3784 /* Disable writeback. */
9dac77fa 3785 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3786 return X86EMUL_CONTINUE;
3787}
3788
96051572
AK		 3789static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3790 void (*get)(struct x86_emulate_ctxt *ctxt,
3791 struct desc_ptr *ptr))
3792{
3793 struct desc_ptr desc_ptr;
3794
ae3e61e1
PB		 3795 if ((ctxt->ops->get_cr(ctxt, 4) & X86_CR4_UMIP) &&
3796 ctxt->ops->cpl(ctxt) > 0)
3797 return emulate_gp(ctxt, 0);
3798
96051572
AK		 3799 if (ctxt->mode == X86EMUL_MODE_PROT64)
3800 ctxt->op_bytes = 8;
3801 get(ctxt, &desc_ptr);
3802 if (ctxt->op_bytes == 2) {
3803 ctxt->op_bytes = 4;
3804 desc_ptr.address &= 0x00ffffff;
3805 }
3806 /* Disable writeback. */
3807 ctxt->dst.type = OP_NONE;
129a72a0
SR		 3808 return segmented_write_std(ctxt, ctxt->dst.addr.mem,
3809 &desc_ptr, 2 + ctxt->op_bytes);
96051572
AK		 3810}
3811
3812static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3813{
3814 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3815}
3816
3817static int em_sidt(struct x86_emulate_ctxt *ctxt)
3818{
3819 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3820}
3821
5b7f6a1e 3822static int em_lgdt_lidt(struct x86_emulate_ctxt *ctxt, bool lgdt)
26d05cc7 3823{
26d05cc7
AK		 3824 struct desc_ptr desc_ptr;
3825 int rc;
3826
510425ff
AK		 3827 if (ctxt->mode == X86EMUL_MODE_PROT64)
3828 ctxt->op_bytes = 8;
9dac77fa 3829 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3830 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3831 ctxt->op_bytes);
26d05cc7
AK		 3832 if (rc != X86EMUL_CONTINUE)
3833 return rc;
9a9abf6b 3834 if (ctxt->mode == X86EMUL_MODE_PROT64 &&
fd8cb433 3835 emul_is_noncanonical_address(desc_ptr.address, ctxt))
9a9abf6b 3836 return emulate_gp(ctxt, 0);
5b7f6a1e
NA		 3837 if (lgdt)
3838 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3839 else
3840 ctxt->ops->set_idt(ctxt, &desc_ptr);
26d05cc7 3841 /* Disable writeback. */
9dac77fa 3842 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3843 return X86EMUL_CONTINUE;
3844}
3845
5b7f6a1e
NA		 3846static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3847{
3848 return em_lgdt_lidt(ctxt, true);
3849}
3850
26d05cc7
AK		 3851static int em_lidt(struct x86_emulate_ctxt *ctxt)
3852{
5b7f6a1e 3853 return em_lgdt_lidt(ctxt, false);
26d05cc7
AK		 3854}
3855
3856static int em_smsw(struct x86_emulate_ctxt *ctxt)
3857{
ae3e61e1
PB		 3858 if ((ctxt->ops->get_cr(ctxt, 4) & X86_CR4_UMIP) &&
3859 ctxt->ops->cpl(ctxt) > 0)
3860 return emulate_gp(ctxt, 0);
3861
32e94d06
NA		 3862 if (ctxt->dst.type == OP_MEM)
3863 ctxt->dst.bytes = 2;
9dac77fa 3864 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3865 return X86EMUL_CONTINUE;
3866}
3867
3868static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3869{
26d05cc7 3870 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3871 | (ctxt->src.val & 0x0f));
3872 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3873 return X86EMUL_CONTINUE;
3874}
3875
d06e03ad
TY		 3876static int em_loop(struct x86_emulate_ctxt *ctxt)
3877{
234f3ce4
NA		 3878 int rc = X86EMUL_CONTINUE;
3879
01485a22 3880 register_address_increment(ctxt, VCPU_REGS_RCX, -1);
dd856efa 3881 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
9dac77fa 3882 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
234f3ce4 3883 rc = jmp_rel(ctxt, ctxt->src.val);
d06e03ad 3884
234f3ce4 3885 return rc;
d06e03ad
TY		 3886}
3887
3888static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3889{
234f3ce4
NA		 3890 int rc = X86EMUL_CONTINUE;
3891
dd856efa 3892 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
234f3ce4 3893 rc = jmp_rel(ctxt, ctxt->src.val);
d06e03ad 3894
234f3ce4 3895 return rc;
d06e03ad
TY		 3896}
3897
d7841a4b
TY		 3898static int em_in(struct x86_emulate_ctxt *ctxt)
3899{
3900 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3901 &ctxt->dst.val))
3902 return X86EMUL_IO_NEEDED;
3903
3904 return X86EMUL_CONTINUE;
3905}
3906
3907static int em_out(struct x86_emulate_ctxt *ctxt)
3908{
3909 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3910 &ctxt->src.val, 1);
3911 /* Disable writeback. */
3912 ctxt->dst.type = OP_NONE;
3913 return X86EMUL_CONTINUE;
3914}
3915
f411e6cd
TY		 3916static int em_cli(struct x86_emulate_ctxt *ctxt)
3917{
3918 if (emulator_bad_iopl(ctxt))
3919 return emulate_gp(ctxt, 0);
3920
3921 ctxt->eflags &= ~X86_EFLAGS_IF;
3922 return X86EMUL_CONTINUE;
3923}
3924
3925static int em_sti(struct x86_emulate_ctxt *ctxt)
3926{
3927 if (emulator_bad_iopl(ctxt))
3928 return emulate_gp(ctxt, 0);
3929
3930 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3931 ctxt->eflags |= X86_EFLAGS_IF;
3932 return X86EMUL_CONTINUE;
3933}
3934
6d6eede4
AK		 3935static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3936{
3937 u32 eax, ebx, ecx, edx;
db2336a8
KH		 3938 u64 msr = 0;
3939
3940 ctxt->ops->get_msr(ctxt, MSR_MISC_FEATURES_ENABLES, &msr);
3941 if (msr & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
3942 ctxt->ops->cpl(ctxt)) {
3943 return emulate_gp(ctxt, 0);
3944 }
6d6eede4 3945
dd856efa
AK		 3946 eax = reg_read(ctxt, VCPU_REGS_RAX);
3947 ecx = reg_read(ctxt, VCPU_REGS_RCX);
e911eb3b 3948 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, true);
dd856efa
AK		 3949 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3950 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3951 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3952 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
6d6eede4
AK		 3953 return X86EMUL_CONTINUE;
3954}
3955
98f73630
PB		 3956static int em_sahf(struct x86_emulate_ctxt *ctxt)
3957{
3958 u32 flags;
3959
0efb0440
NA		 3960 flags = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
3961 X86_EFLAGS_SF;
98f73630
PB		 3962 flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8;
3963
3964 ctxt->eflags &= ~0xffUL;
3965 ctxt->eflags |= flags | X86_EFLAGS_FIXED;
3966 return X86EMUL_CONTINUE;
3967}
3968
2dd7caa0
AK		 3969static int em_lahf(struct x86_emulate_ctxt *ctxt)
3970{
dd856efa
AK		 3971 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3972 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
2dd7caa0
AK		 3973 return X86EMUL_CONTINUE;
3974}
3975
9299836e
AK		 3976static int em_bswap(struct x86_emulate_ctxt *ctxt)
3977{
3978 switch (ctxt->op_bytes) {
3979#ifdef CONFIG_X86_64
3980 case 8:
3981 asm("bswap %0" : "+r"(ctxt->dst.val));
3982 break;
3983#endif
3984 default:
3985 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3986 break;
3987 }
3988 return X86EMUL_CONTINUE;
3989}
3990
13e457e0
NA		 3991static int em_clflush(struct x86_emulate_ctxt *ctxt)
3992{
3993 /* emulating clflush regardless of cpuid */
3994 return X86EMUL_CONTINUE;
3995}
3996
2276b511
NA		 3997static int em_movsxd(struct x86_emulate_ctxt *ctxt)
3998{
3999 ctxt->dst.val = (s32) ctxt->src.val;
4000 return X86EMUL_CONTINUE;
4001}
4002
283c95d0
RK		 4003static int check_fxsr(struct x86_emulate_ctxt *ctxt)
4004{
4005 u32 eax = 1, ebx, ecx = 0, edx;
4006
e911eb3b 4007 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, false);
283c95d0
RK		 4008 if (!(edx & FFL(FXSR)))
4009 return emulate_ud(ctxt);
4010
4011 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
4012 return emulate_nm(ctxt);
4013
4014 /*
4015 * Don't emulate a case that should never be hit, instead of working
4016 * around a lack of fxsave64/fxrstor64 on old compilers.
4017 */
4018 if (ctxt->mode >= X86EMUL_MODE_PROT64)
4019 return X86EMUL_UNHANDLEABLE;
4020
4021 return X86EMUL_CONTINUE;
4022}
4023
9d643f63
ND		 4024/*
4025 * Hardware doesn't save and restore XMM 0-7 without CR4.OSFXSR, but does save
4026 * and restore MXCSR.
4027 */
4028static size_t __fxstate_size(int nregs)
4029{
4030 return offsetof(struct fxregs_state, xmm_space[0]) + nregs * 16;
4031}
4032
4033static inline size_t fxstate_size(struct x86_emulate_ctxt *ctxt)
4034{
4035 bool cr4_osfxsr;
4036 if (ctxt->mode == X86EMUL_MODE_PROT64)
4037 return __fxstate_size(16);
4038
4039 cr4_osfxsr = ctxt->ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR;
4040 return __fxstate_size(cr4_osfxsr ? 8 : 0);
4041}
4042
283c95d0
RK		 4043/*
4044 * FXSAVE and FXRSTOR have 4 different formats depending on execution mode,
4045 * 1) 16 bit mode
4046 * 2) 32 bit mode
4047 * - like (1), but FIP and FDP (foo) are only 16 bit. At least Intel CPUs
4048 * preserve whole 32 bit values, though, so (1) and (2) are the same wrt.
4049 * save and restore
4050 * 3) 64-bit mode with REX.W prefix
4051 * - like (2), but XMM 8-15 are being saved and restored
4052 * 4) 64-bit mode without REX.W prefix
4053 * - like (3), but FIP and FDP are 64 bit
4054 *
4055 * Emulation uses (3) for (1) and (2) and preserves XMM 8-15 to reach the
4056 * desired result. (4) is not emulated.
4057 *
4058 * Note: Guest and host CPUID.(EAX=07H,ECX=0H):EBX[bit 13] (deprecate FPU CS
4059 * and FPU DS) should match.
4060 */
4061static int em_fxsave(struct x86_emulate_ctxt *ctxt)
4062{
4063 struct fxregs_state fx_state;
283c95d0
RK		 4064 int rc;
4065
4066 rc = check_fxsr(ctxt);
4067 if (rc != X86EMUL_CONTINUE)
4068 return rc;
4069
283c95d0
RK		 4070 rc = asm_safe("fxsave %[fx]", , [fx] "+m"(fx_state));
4071
283c95d0
RK		 4072 if (rc != X86EMUL_CONTINUE)
4073 return rc;
4074
9d643f63
ND		 4075 return segmented_write_std(ctxt, ctxt->memop.addr.mem, &fx_state,
4076 fxstate_size(ctxt));
283c95d0
RK		 4077}
4078
4d772cb8
DH		 4079/*
4080 * FXRSTOR might restore XMM registers not provided by the guest. Fill
4081 * in the host registers (via FXSAVE) instead, so they won't be modified.
4082 * (preemption has to stay disabled until FXRSTOR).
4083 *
4084 * Use noinline to keep the stack for other functions called by callers small.
4085 */
4086static noinline int fxregs_fixup(struct fxregs_state *fx_state,
4087 const size_t used_size)
4088{
4089 struct fxregs_state fx_tmp;
4090 int rc;
4091
4092 rc = asm_safe("fxsave %[fx]", , [fx] "+m"(fx_tmp));
4093 memcpy((void *)fx_state + used_size, (void *)&fx_tmp + used_size,
4094 __fxstate_size(16) - used_size);
4095
4096 return rc;
4097}
4098
283c95d0
RK		 4099static int em_fxrstor(struct x86_emulate_ctxt *ctxt)
4100{
4101 struct fxregs_state fx_state;
4102 int rc;
9d643f63 4103 size_t size;
283c95d0
RK		 4104
4105 rc = check_fxsr(ctxt);
4106 if (rc != X86EMUL_CONTINUE)
4107 return rc;
4108
4d772cb8
DH		 4109 size = fxstate_size(ctxt);
4110 rc = segmented_read_std(ctxt, ctxt->memop.addr.mem, &fx_state, size);
4111 if (rc != X86EMUL_CONTINUE)
4112 return rc;
4113
9d643f63 4114 if (size < __fxstate_size(16)) {
4d772cb8 4115 rc = fxregs_fixup(&fx_state, size);
9d643f63
ND		 4116 if (rc != X86EMUL_CONTINUE)
4117 goto out;
4118 }
283c95d0 4119
9d643f63
ND		 4120 if (fx_state.mxcsr >> 16) {
4121 rc = emulate_gp(ctxt, 0);
4122 goto out;
4123 }
283c95d0
RK		 4124
4125 if (rc == X86EMUL_CONTINUE)
4126 rc = asm_safe("fxrstor %[fx]", : [fx] "m"(fx_state));
4127
9d643f63 4128out:
283c95d0
RK		 4129 return rc;
4130}
4131
cfec82cb
JR		 4132static bool valid_cr(int nr)
4133{
4134 switch (nr) {
4135 case 0:
4136 case 2 ... 4:
4137 case 8:
4138 return true;
4139 default:
4140 return false;
4141 }
4142}
4143
4144static int check_cr_read(struct x86_emulate_ctxt *ctxt)
4145{
9dac77fa 4146 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 4147 return emulate_ud(ctxt);
4148
4149 return X86EMUL_CONTINUE;
4150}
4151
4152static int check_cr_write(struct x86_emulate_ctxt *ctxt)
4153{
9dac77fa
AK		 4154 u64 new_val = ctxt->src.val64;
4155 int cr = ctxt->modrm_reg;
c2ad2bb3 4156 u64 efer = 0;
cfec82cb
JR		 4157
4158 static u64 cr_reserved_bits[] = {
4159 0xffffffff00000000ULL,
4160 0, 0, 0, /* CR3 checked later */
4161 CR4_RESERVED_BITS,
4162 0, 0, 0,
4163 CR8_RESERVED_BITS,
4164 };
4165
4166 if (!valid_cr(cr))
4167 return emulate_ud(ctxt);
4168
4169 if (new_val & cr_reserved_bits[cr])
4170 return emulate_gp(ctxt, 0);
4171
4172 switch (cr) {
4173 case 0: {
c2ad2bb3 4174 u64 cr4;
cfec82cb
JR		 4175 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
4176 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
4177 return emulate_gp(ctxt, 0);
4178
717746e3
AK		 4179 cr4 = ctxt->ops->get_cr(ctxt, 4);
4180 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 4181
4182 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
4183 !(cr4 & X86_CR4_PAE))
4184 return emulate_gp(ctxt, 0);
4185
4186 break;
4187 }
4188 case 3: {
4189 u64 rsvd = 0;
4190
c2ad2bb3 4191 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
d1cd3ce9
YZ		 4192 if (efer & EFER_LMA) {
4193 u64 maxphyaddr;
d6500149 4194 u32 eax, ebx, ecx, edx;
d1cd3ce9 4195
d6500149
YZ		 4196 eax = 0x80000008;
4197 ecx = 0;
4198 if (ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx,
4199 &edx, false))
d1cd3ce9
YZ		 4200 maxphyaddr = eax & 0xff;
4201 else
4202 maxphyaddr = 36;
a780a3ea
WL		 4203 rsvd = rsvd_bits(maxphyaddr, 63);
4204 if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PCIDE)
208320ba 4205 rsvd &= ~X86_CR3_PCID_NOFLUSH;
d1cd3ce9 4206 }
cfec82cb
JR		 4207
4208 if (new_val & rsvd)
4209 return emulate_gp(ctxt, 0);
4210
4211 break;
4212 }
4213 case 4: {
717746e3 4214 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 4215
4216 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
4217 return emulate_gp(ctxt, 0);
4218
4219 break;
4220 }
4221 }
4222
4223 return X86EMUL_CONTINUE;
4224}
4225
3b88e41a
JR		 4226static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
4227{
4228 unsigned long dr7;
4229
717746e3 4230 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 4231
4232 /* Check if DR7.Global_Enable is set */
4233 return dr7 & (1 << 13);
4234}
4235
4236static int check_dr_read(struct x86_emulate_ctxt *ctxt)
4237{
9dac77fa 4238 int dr = ctxt->modrm_reg;
3b88e41a
JR		 4239 u64 cr4;
4240
4241 if (dr > 7)
4242 return emulate_ud(ctxt);
4243
717746e3 4244 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 4245 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
4246 return emulate_ud(ctxt);
4247
6d2a0526
NA		 4248 if (check_dr7_gd(ctxt)) {
4249 ulong dr6;
4250
4251 ctxt->ops->get_dr(ctxt, 6, &dr6);
4252 dr6 &= ~15;
4253 dr6 |= DR6_BD | DR6_RTM;
4254 ctxt->ops->set_dr(ctxt, 6, dr6);
3b88e41a 4255 return emulate_db(ctxt);
6d2a0526 4256 }
3b88e41a
JR		 4257
4258 return X86EMUL_CONTINUE;
4259}
4260
4261static int check_dr_write(struct x86_emulate_ctxt *ctxt)
4262{
9dac77fa
AK		 4263 u64 new_val = ctxt->src.val64;
4264 int dr = ctxt->modrm_reg;
3b88e41a
JR		 4265
4266 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
4267 return emulate_gp(ctxt, 0);
4268
4269 return check_dr_read(ctxt);
4270}
4271
01de8b09
JR		 4272static int check_svme(struct x86_emulate_ctxt *ctxt)
4273{
92ceb767 4274 u64 efer = 0;
01de8b09 4275
717746e3 4276 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 4277
4278 if (!(efer & EFER_SVME))
4279 return emulate_ud(ctxt);
4280
4281 return X86EMUL_CONTINUE;
4282}
4283
4284static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
4285{
dd856efa 4286 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
01de8b09
JR		 4287
4288 /* Valid physical address? */
d4224449 4289 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 4290 return emulate_gp(ctxt, 0);
4291
4292 return check_svme(ctxt);
4293}
4294
d7eb8203
JR		 4295static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
4296{
717746e3 4297 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 4298
717746e3 4299 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 4300 return emulate_ud(ctxt);
4301
4302 return X86EMUL_CONTINUE;
4303}
4304
8061252e
JR		 4305static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
4306{
717746e3 4307 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
dd856efa 4308 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
8061252e 4309
2d7921c4
AM		 4310 /*
4311 * VMware allows access to these Pseduo-PMCs even when read via RDPMC
4312 * in Ring3 when CR4.PCE=0.
4313 */
4314 if (enable_vmware_backdoor && is_vmware_backdoor_pmc(rcx))
4315 return X86EMUL_CONTINUE;
4316
717746e3 4317 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
67f4d428 4318 ctxt->ops->check_pmc(ctxt, rcx))
8061252e
JR		 4319 return emulate_gp(ctxt, 0);
4320
4321 return X86EMUL_CONTINUE;
4322}
4323
f6511935
JR		 4324static int check_perm_in(struct x86_emulate_ctxt *ctxt)
4325{
9dac77fa
AK		 4326 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
4327 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 4328 return emulate_gp(ctxt, 0);
4329
4330 return X86EMUL_CONTINUE;
4331}
4332
4333static int check_perm_out(struct x86_emulate_ctxt *ctxt)
4334{
9dac77fa
AK		 4335 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
4336 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 4337 return emulate_gp(ctxt, 0);
4338
4339 return X86EMUL_CONTINUE;
4340}
4341
73fba5f4 4342#define D(_y) { .flags = (_y) }
d40a6898
PB		 4343#define DI(_y, _i) { .flags = (_y)|Intercept, .intercept = x86_intercept_##_i }
4344#define DIP(_y, _i, _p) { .flags = (_y)|Intercept|CheckPerm, \
4345 .intercept = x86_intercept_##_i, .check_perm = (_p) }
0b789eee 4346#define N D(NotImpl)
01de8b09 4347#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 4348#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
4349#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
39f062ff 4350#define ID(_f, _i) { .flags = ((_f) | InstrDual | ModRM), .u.idual = (_i) }
2276b511 4351#define MD(_f, _m) { .flags = ((_f) | ModeDual), .u.mdual = (_m) }
045a282c 4352#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
73fba5f4 4353#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
e28bbd44 4354#define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
c4f035c6 4355#define II(_f, _e, _i) \
d40a6898 4356 { .flags = (_f)|Intercept, .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd 4357#define IIP(_f, _e, _i, _p) \
d40a6898
PB		 4358 { .flags = (_f)|Intercept|CheckPerm, .u.execute = (_e), \
4359 .intercept = x86_intercept_##_i, .check_perm = (_p) }
aa97bb48 4360#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 4361
8d8f4e9f 4362#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 4363#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 4364#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
f7857f35 4365#define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e)
d7841a4b
TY		 4366#define I2bvIP(_f, _e, _i, _p) \
4367 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 4368
fb864fbc
AK		 4369#define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \
4370 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
4371 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 4372
0f54a321
NA		 4373static const struct opcode group7_rm0[] = {
4374 N,
b34a8051 4375 I(SrcNone | Priv | EmulateOnUD, em_hypercall),
0f54a321
NA		 4376 N, N, N, N, N, N,
4377};
4378
fd0a0d82 4379static const struct opcode group7_rm1[] = {
1c2545be
TY		 4380 DI(SrcNone | Priv, monitor),
4381 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 4382 N, N, N, N, N, N,
4383};
4384
fd0a0d82 4385static const struct opcode group7_rm3[] = {
1c2545be 4386 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
b34a8051 4387 II(SrcNone | Prot | EmulateOnUD, em_hypercall, vmmcall),
1c2545be
TY		 4388 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
4389 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
4390 DIP(SrcNone | Prot | Priv, stgi, check_svme),
4391 DIP(SrcNone | Prot | Priv, clgi, check_svme),
4392 DIP(SrcNone | Prot | Priv, skinit, check_svme),
4393 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 4394};
6230f7fc 4395
fd0a0d82 4396static const struct opcode group7_rm7[] = {
d7eb8203 4397 N,
1c2545be 4398 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 4399 N, N, N, N, N, N,
4400};
d67fc27a 4401
fd0a0d82 4402static const struct opcode group1[] = {
fb864fbc
AK		 4403 F(Lock, em_add),
4404 F(Lock | PageTable, em_or),
4405 F(Lock, em_adc),
4406 F(Lock, em_sbb),
4407 F(Lock | PageTable, em_and),
4408 F(Lock, em_sub),
4409 F(Lock, em_xor),
4410 F(NoWrite, em_cmp),
73fba5f4
AK		 4411};
4412
fd0a0d82 4413static const struct opcode group1A[] = {
0f89b207 4414 I(DstMem | SrcNone | Mov | Stack | IncSP | TwoMemOp, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 4415};
4416
007a3b54
AK		 4417static const struct opcode group2[] = {
4418 F(DstMem | ModRM, em_rol),
4419 F(DstMem | ModRM, em_ror),
4420 F(DstMem | ModRM, em_rcl),
4421 F(DstMem | ModRM, em_rcr),
4422 F(DstMem | ModRM, em_shl),
4423 F(DstMem | ModRM, em_shr),
4424 F(DstMem | ModRM, em_shl),
4425 F(DstMem | ModRM, em_sar),
4426};
4427
fd0a0d82 4428static const struct opcode group3[] = {
fb864fbc
AK		 4429 F(DstMem | SrcImm | NoWrite, em_test),
4430 F(DstMem | SrcImm | NoWrite, em_test),
45a1467d
AK		 4431 F(DstMem | SrcNone | Lock, em_not),
4432 F(DstMem | SrcNone | Lock, em_neg),
b9fa409b
AK		 4433 F(DstXacc | Src2Mem, em_mul_ex),
4434 F(DstXacc | Src2Mem, em_imul_ex),
b8c0b6ae
AK		 4435 F(DstXacc | Src2Mem, em_div_ex),
4436 F(DstXacc | Src2Mem, em_idiv_ex),
73fba5f4
AK		 4437};
4438
fd0a0d82 4439static const struct opcode group4[] = {
95413dc4
AK		 4440 F(ByteOp | DstMem | SrcNone | Lock, em_inc),
4441 F(ByteOp | DstMem | SrcNone | Lock, em_dec),
73fba5f4
AK		 4442 N, N, N, N, N, N,
4443};
4444
fd0a0d82 4445static const struct opcode group5[] = {
95413dc4
AK		 4446 F(DstMem | SrcNone | Lock, em_inc),
4447 F(DstMem | SrcNone | Lock, em_dec),
58b7075d 4448 I(SrcMem | NearBranch, em_call_near_abs),
acac6f89 4449 I(SrcMemFAddr | ImplicitOps, em_call_far),
58b7075d 4450 I(SrcMem | NearBranch, em_jmp_abs),
f7784046 4451 I(SrcMemFAddr | ImplicitOps, em_jmp_far),
0f89b207 4452 I(SrcMem | Stack | TwoMemOp, em_push), D(Undefined),
73fba5f4
AK		 4453};
4454
fd0a0d82 4455static const struct opcode group6[] = {
dd307d01
PB		 4456 II(Prot | DstMem, em_sldt, sldt),
4457 II(Prot | DstMem, em_str, str),
a14e579f 4458 II(Prot | Priv | SrcMem16, em_lldt, lldt),
80890006 4459 II(Prot | Priv | SrcMem16, em_ltr, ltr),
dee6bb70
JR		 4460 N, N, N, N,
4461};
4462
fd0a0d82 4463static const struct group_dual group7 = { {
606b1c3e
NA		 4464 II(Mov | DstMem, em_sgdt, sgdt),
4465 II(Mov | DstMem, em_sidt, sidt),
1c2545be
TY		 4466 II(SrcMem | Priv, em_lgdt, lgdt),
4467 II(SrcMem | Priv, em_lidt, lidt),
4468 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
4469 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
4470 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 4471}, {
0f54a321 4472 EXT(0, group7_rm0),
5ef39c71 4473 EXT(0, group7_rm1),
01de8b09 4474 N, EXT(0, group7_rm3),
1c2545be
TY		 4475 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
4476 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
4477 EXT(0, group7_rm7),
73fba5f4
AK		 4478} };
4479
fd0a0d82 4480static const struct opcode group8[] = {
73fba5f4 4481 N, N, N, N,
11c363ba
AK		 4482 F(DstMem | SrcImmByte | NoWrite, em_bt),
4483 F(DstMem | SrcImmByte | Lock | PageTable, em_bts),
4484 F(DstMem | SrcImmByte | Lock, em_btr),
4485 F(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 4486};
4487
fb6d4d34
PB		 4488/*
4489 * The "memory" destination is actually always a register, since we come
4490 * from the register case of group9.
4491 */
4492static const struct gprefix pfx_0f_c7_7 = {
4493 N, N, N, II(DstMem | ModRM | Op3264 | EmulateOnUD, em_rdpid, rdtscp),
4494};
4495
4496
fd0a0d82 4497static const struct group_dual group9 = { {
1c2545be 4498 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4 4499}, {
fb6d4d34
PB		 4500 N, N, N, N, N, N, N,
4501 GP(0, &pfx_0f_c7_7),
73fba5f4
AK		 4502} };
4503
fd0a0d82 4504static const struct opcode group11[] = {
1c2545be 4505 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 4506 X7(D(Undefined)),
a4d4a7c1
AK		 4507};
4508
13e457e0 4509static const struct gprefix pfx_0f_ae_7 = {
3f6f1480 4510 I(SrcMem | ByteOp, em_clflush), N, N, N,
13e457e0
NA		 4511};
4512
4513static const struct group_dual group15 = { {
283c95d0
RK		 4514 I(ModRM | Aligned16, em_fxsave),
4515 I(ModRM | Aligned16, em_fxrstor),
4516 N, N, N, N, N, GP(0, &pfx_0f_ae_7),
13e457e0
NA		 4517}, {
4518 N, N, N, N, N, N, N, N,
4519} };
4520
fd0a0d82 4521static const struct gprefix pfx_0f_6f_0f_7f = {
e5971755 4522 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 4523};
4524
39f062ff
NA		 4525static const struct instr_dual instr_dual_0f_2b = {
4526 I(0, em_mov), N
4527};
4528
d5b77069 4529static const struct gprefix pfx_0f_2b = {
39f062ff 4530 ID(0, &instr_dual_0f_2b), ID(0, &instr_dual_0f_2b), N, N,
3e114eb4
AK		 4531};
4532
29916968
SF		 4533static const struct gprefix pfx_0f_10_0f_11 = {
4534 I(Unaligned, em_mov), I(Unaligned, em_mov), N, N,
4535};
4536
27ce8258 4537static const struct gprefix pfx_0f_28_0f_29 = {
6fec27d8 4538 I(Aligned, em_mov), I(Aligned, em_mov), N, N,
27ce8258
IM		 4539};
4540
0a37027e
AW		 4541static const struct gprefix pfx_0f_e7 = {
4542 N, I(Sse, em_mov), N, N,
4543};
4544
045a282c 4545static const struct escape escape_d9 = { {
16bebefe 4546 N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstcw),
045a282c
GN		 4547}, {
4548 /* 0xC0 - 0xC7 */
4549 N, N, N, N, N, N, N, N,
4550 /* 0xC8 - 0xCF */
4551 N, N, N, N, N, N, N, N,
4552 /* 0xD0 - 0xC7 */
4553 N, N, N, N, N, N, N, N,
4554 /* 0xD8 - 0xDF */
4555 N, N, N, N, N, N, N, N,
4556 /* 0xE0 - 0xE7 */
4557 N, N, N, N, N, N, N, N,
4558 /* 0xE8 - 0xEF */
4559 N, N, N, N, N, N, N, N,
4560 /* 0xF0 - 0xF7 */
4561 N, N, N, N, N, N, N, N,
4562 /* 0xF8 - 0xFF */
4563 N, N, N, N, N, N, N, N,
4564} };
4565
4566static const struct escape escape_db = { {
4567 N, N, N, N, N, N, N, N,
4568}, {
4569 /* 0xC0 - 0xC7 */
4570 N, N, N, N, N, N, N, N,
4571 /* 0xC8 - 0xCF */
4572 N, N, N, N, N, N, N, N,
4573 /* 0xD0 - 0xC7 */
4574 N, N, N, N, N, N, N, N,
4575 /* 0xD8 - 0xDF */
4576 N, N, N, N, N, N, N, N,
4577 /* 0xE0 - 0xE7 */
4578 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
4579 /* 0xE8 - 0xEF */
4580 N, N, N, N, N, N, N, N,
4581 /* 0xF0 - 0xF7 */
4582 N, N, N, N, N, N, N, N,
4583 /* 0xF8 - 0xFF */
4584 N, N, N, N, N, N, N, N,
4585} };
4586
4587static const struct escape escape_dd = { {
16bebefe 4588 N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstsw),
045a282c
GN		 4589}, {
4590 /* 0xC0 - 0xC7 */
4591 N, N, N, N, N, N, N, N,
4592 /* 0xC8 - 0xCF */
4593 N, N, N, N, N, N, N, N,
4594 /* 0xD0 - 0xC7 */
4595 N, N, N, N, N, N, N, N,
4596 /* 0xD8 - 0xDF */
4597 N, N, N, N, N, N, N, N,
4598 /* 0xE0 - 0xE7 */
4599 N, N, N, N, N, N, N, N,
4600 /* 0xE8 - 0xEF */
4601 N, N, N, N, N, N, N, N,
4602 /* 0xF0 - 0xF7 */
4603 N, N, N, N, N, N, N, N,
4604 /* 0xF8 - 0xFF */
4605 N, N, N, N, N, N, N, N,
4606} };
4607
39f062ff
NA		 4608static const struct instr_dual instr_dual_0f_c3 = {
4609 I(DstMem | SrcReg | ModRM | No16 | Mov, em_mov), N
4610};
4611
2276b511
NA		 4612static const struct mode_dual mode_dual_63 = {
4613 N, I(DstReg | SrcMem32 | ModRM | Mov, em_movsxd)
4614};
4615
fd0a0d82 4616static const struct opcode opcode_table[256] = {
73fba5f4 4617 /* 0x00 - 0x07 */
fb864fbc 4618 F6ALU(Lock, em_add),
1cd196ea
AK		 4619 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
4620 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 4621 /* 0x08 - 0x0F */
fb864fbc 4622 F6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 4623 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
4624 N,
73fba5f4 4625 /* 0x10 - 0x17 */
fb864fbc 4626 F6ALU(Lock, em_adc),
1cd196ea
AK		 4627 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
4628 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 4629 /* 0x18 - 0x1F */
fb864fbc 4630 F6ALU(Lock, em_sbb),
1cd196ea
AK		 4631 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
4632 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 4633 /* 0x20 - 0x27 */
fb864fbc 4634 F6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 4635 /* 0x28 - 0x2F */
fb864fbc 4636 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 4637 /* 0x30 - 0x37 */
fb864fbc 4638 F6ALU(Lock, em_xor), N, N,
73fba5f4 4639 /* 0x38 - 0x3F */
fb864fbc 4640 F6ALU(NoWrite, em_cmp), N, N,
73fba5f4 4641 /* 0x40 - 0x4F */
95413dc4 4642 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
73fba5f4 4643 /* 0x50 - 0x57 */
63540382 4644 X8(I(SrcReg | Stack, em_push)),
73fba5f4 4645 /* 0x58 - 0x5F */
c54fe504 4646 X8(I(DstReg | Stack, em_pop)),
73fba5f4 4647 /* 0x60 - 0x67 */
b96a7fad
TY		 4648 I(ImplicitOps | Stack | No64, em_pusha),
4649 I(ImplicitOps | Stack | No64, em_popa),
2276b511 4650 N, MD(ModRM, &mode_dual_63),
73fba5f4
AK		 4651 N, N, N, N,
4652 /* 0x68 - 0x6F */
d46164db
AK		 4653 I(SrcImm | Mov | Stack, em_push),
4654 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 4655 I(SrcImmByte | Mov | Stack, em_push),
4656 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
b3356bf0 4657 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
2b5e97e1 4658 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4 4659 /* 0x70 - 0x7F */
58b7075d 4660 X16(D(SrcImmByte | NearBranch)),
73fba5f4 4661 /* 0x80 - 0x87 */
1c2545be
TY		 4662 G(ByteOp | DstMem | SrcImm, group1),
4663 G(DstMem | SrcImm, group1),
4664 G(ByteOp | DstMem | SrcImm | No64, group1),
4665 G(DstMem | SrcImmByte, group1),
fb864fbc 4666 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
d5ae7ce8 4667 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 4668 /* 0x88 - 0x8F */
d5ae7ce8 4669 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 4670 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 4671 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 4672 D(ModRM | SrcMem | NoAccess | DstReg),
4673 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
4674 G(0, group1A),
73fba5f4 4675 /* 0x90 - 0x97 */
bf608f88 4676 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 4677 /* 0x98 - 0x9F */
61429142 4678 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 4679 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0 4680 II(ImplicitOps | Stack, em_pushf, pushf),
98f73630
PB		 4681 II(ImplicitOps | Stack, em_popf, popf),
4682 I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf),
73fba5f4 4683 /* 0xA0 - 0xA7 */
b9eac5f4 4684 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 4685 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
0f89b207
TL		 4686 I2bv(SrcSI | DstDI | Mov | String | TwoMemOp, em_mov),
4687 F2bv(SrcSI | DstDI | String | NoWrite | TwoMemOp, em_cmp_r),
73fba5f4 4688 /* 0xA8 - 0xAF */
fb864fbc 4689 F2bv(DstAcc | SrcImm | NoWrite, em_test),
b9eac5f4
AK		 4690 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
4691 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
5aca3722 4692 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp_r),
73fba5f4 4693 /* 0xB0 - 0xB7 */
b9eac5f4 4694 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 4695 /* 0xB8 - 0xBF */
5e2c6883 4696 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
73fba5f4 4697 /* 0xC0 - 0xC7 */
007a3b54 4698 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
58b7075d
NA		 4699 I(ImplicitOps | NearBranch | SrcImmU16, em_ret_near_imm),
4700 I(ImplicitOps | NearBranch, em_ret),
d4b4325f
AK		 4701 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
4702 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 4703 G(ByteOp, group11), G(0, group11),
73fba5f4 4704 /* 0xC8 - 0xCF */
612e89f0 4705 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
16794aaa
NA		 4706 I(ImplicitOps | SrcImmU16, em_ret_far_imm),
4707 I(ImplicitOps, em_ret_far),
3c6e276f 4708 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 4709 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 4710 /* 0xD0 - 0xD7 */
007a3b54
AK		 4711 G(Src2One | ByteOp, group2), G(Src2One, group2),
4712 G(Src2CL | ByteOp, group2), G(Src2CL, group2),
a035d5c6 4713 I(DstAcc | SrcImmUByte | No64, em_aam),
326f578f
PB		 4714 I(DstAcc | SrcImmUByte | No64, em_aad),
4715 F(DstAcc | ByteOp | No64, em_salc),
7fa57952 4716 I(DstAcc | SrcXLat | ByteOp, em_mov),
73fba5f4 4717 /* 0xD8 - 0xDF */
045a282c 4718 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
73fba5f4 4719 /* 0xE0 - 0xE7 */
58b7075d
NA		 4720 X3(I(SrcImmByte | NearBranch, em_loop)),
4721 I(SrcImmByte | NearBranch, em_jcxz),
d7841a4b
TY		 4722 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
4723 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 4724 /* 0xE8 - 0xEF */
58b7075d
NA		 4725 I(SrcImm | NearBranch, em_call), D(SrcImm | ImplicitOps | NearBranch),
4726 I(SrcImmFAddr | No64, em_jmp_far),
4727 D(SrcImmByte | ImplicitOps | NearBranch),
d7841a4b
TY		 4728 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
4729 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 4730 /* 0xF0 - 0xF7 */
bf608f88 4731 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 4732 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
4733 G(ByteOp, group3), G(0, group3),
73fba5f4 4734 /* 0xF8 - 0xFF */
f411e6cd
TY		 4735 D(ImplicitOps), D(ImplicitOps),
4736 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 4737 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
4738};
4739
fd0a0d82 4740static const struct opcode twobyte_table[256] = {
73fba5f4 4741 /* 0x00 - 0x0F */
dee6bb70 4742 G(0, group6), GD(0, &group7), N, N,
b51e974f 4743 N, I(ImplicitOps | EmulateOnUD, em_syscall),
db5b0762 4744 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 4745 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
3f6f1480 4746 N, D(ImplicitOps | ModRM | SrcMem | NoAccess), N, N,
73fba5f4 4747 /* 0x10 - 0x1F */
29916968
SF		 4748 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_10_0f_11),
4749 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_10_0f_11),
4750 N, N, N, N, N, N,
3f6f1480
NA		 4751 D(ImplicitOps | ModRM | SrcMem | NoAccess),
4752 N, N, N, N, N, N, D(ImplicitOps | ModRM | SrcMem | NoAccess),
73fba5f4 4753 /* 0x20 - 0x2F */
9b88ae99
NA		 4754 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_read),
4755 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read),
4756 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write,
4757 check_cr_write),
4758 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write,
4759 check_dr_write),
73fba5f4 4760 N, N, N, N,
27ce8258
IM		 4761 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29),
4762 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29),
d5b77069 4763 N, GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_2b),
3e114eb4 4764 N, N, N, N,
73fba5f4 4765 /* 0x30 - 0x3F */
e1e210b0 4766 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 4767 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 4768 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 4769 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
b51e974f
BP		 4770 I(ImplicitOps | EmulateOnUD, em_sysenter),
4771 I(ImplicitOps | Priv | EmulateOnUD, em_sysexit),
d867162c 4772 N, N,
73fba5f4
AK		 4773 N, N, N, N, N, N, N, N,
4774 /* 0x40 - 0x4F */
140bad89 4775 X16(D(DstReg | SrcMem | ModRM)),
73fba5f4
AK		 4776 /* 0x50 - 0x5F */
4777 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4778 /* 0x60 - 0x6F */
aa97bb48
AK		 4779 N, N, N, N,
4780 N, N, N, N,
4781 N, N, N, N,
4782 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 4783 /* 0x70 - 0x7F */
aa97bb48
AK		 4784 N, N, N, N,
4785 N, N, N, N,
4786 N, N, N, N,
4787 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 4788 /* 0x80 - 0x8F */
58b7075d 4789 X16(D(SrcImm | NearBranch)),
73fba5f4 4790 /* 0x90 - 0x9F */
ee45b58e 4791 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 4792 /* 0xA0 - 0xA7 */
1cd196ea 4793 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
11c363ba
AK		 4794 II(ImplicitOps, em_cpuid, cpuid),
4795 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
0bdea068
AK		 4796 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
4797 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
73fba5f4 4798 /* 0xA8 - 0xAF */
1cd196ea 4799 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
89651a3d 4800 II(EmulateOnUD | ImplicitOps, em_rsm, rsm),
11c363ba 4801 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
0bdea068
AK		 4802 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
4803 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
13e457e0 4804 GD(0, &group15), F(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 4805 /* 0xB0 - 0xB7 */
2fcf5c8a 4806 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable | SrcWrite, em_cmpxchg),
d4b4325f 4807 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
11c363ba 4808 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 4809 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
4810 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 4811 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 4812 /* 0xB8 - 0xBF */
4813 N, N,
ce7faab2 4814 G(BitOp, group8),
11c363ba 4815 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
900efe20
NA		 4816 I(DstReg | SrcMem | ModRM, em_bsf_c),
4817 I(DstReg | SrcMem | ModRM, em_bsr_c),
2adb5ad9 4818 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
9299836e 4819 /* 0xC0 - 0xC7 */
e47a5f5f 4820 F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd),
39f062ff 4821 N, ID(0, &instr_dual_0f_c3),
73fba5f4 4822 N, N, N, GD(0, &group9),
9299836e
AK		 4823 /* 0xC8 - 0xCF */
4824 X8(I(DstReg, em_bswap)),
73fba5f4
AK		 4825 /* 0xD0 - 0xDF */
4826 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4827 /* 0xE0 - 0xEF */
0a37027e
AW		 4828 N, N, N, N, N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_e7),
4829 N, N, N, N, N, N, N, N,
73fba5f4
AK		 4830 /* 0xF0 - 0xFF */
4831 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
4832};
4833
39f062ff
NA		 4834static const struct instr_dual instr_dual_0f_38_f0 = {
4835 I(DstReg | SrcMem | Mov, em_movbe), N
4836};
4837
4838static const struct instr_dual instr_dual_0f_38_f1 = {
4839 I(DstMem | SrcReg | Mov, em_movbe), N
4840};
4841
0bc5eedb 4842static const struct gprefix three_byte_0f_38_f0 = {
39f062ff 4843 ID(0, &instr_dual_0f_38_f0), N, N, N
0bc5eedb
BP		 4844};
4845
4846static const struct gprefix three_byte_0f_38_f1 = {
39f062ff 4847 ID(0, &instr_dual_0f_38_f1), N, N, N
0bc5eedb
BP		 4848};
4849
4850/*
4851 * Insns below are selected by the prefix which indexed by the third opcode
4852 * byte.
4853 */
4854static const struct opcode opcode_map_0f_38[256] = {
4855 /* 0x00 - 0x7f */
4856 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
84cffe49
BP		 4857 /* 0x80 - 0xef */
4858 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
4859 /* 0xf0 - 0xf1 */
53bb4f78
NA		 4860 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f0),
4861 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f1),
84cffe49
BP		 4862 /* 0xf2 - 0xff */
4863 N, N, X4(N), X8(N)
0bc5eedb
BP		 4864};
4865
73fba5f4
AK		 4866#undef D
4867#undef N
4868#undef G
4869#undef GD
4870#undef I
aa97bb48 4871#undef GP
01de8b09 4872#undef EXT
2276b511 4873#undef MD
2b42fce6 4874#undef ID
73fba5f4 4875
8d8f4e9f 4876#undef D2bv
f6511935 4877#undef D2bvIP
8d8f4e9f 4878#undef I2bv
d7841a4b 4879#undef I2bvIP
d67fc27a 4880#undef I6ALU
8d8f4e9f 4881
9dac77fa 4882static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 4883{
4884 unsigned size;
4885
9dac77fa 4886 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 4887 if (size == 8)
4888 size = 4;
4889 return size;
4890}
4891
4892static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
4893 unsigned size, bool sign_extension)
4894{
39f21ee5
AK		 4895 int rc = X86EMUL_CONTINUE;
4896
4897 op->type = OP_IMM;
4898 op->bytes = size;
9dac77fa 4899 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 4900 /* NB. Immediates are sign-extended as necessary. */
4901 switch (op->bytes) {
4902 case 1:
e85a1085 4903 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 4904 break;
4905 case 2:
e85a1085 4906 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 4907 break;
4908 case 4:
e85a1085 4909 op->val = insn_fetch(s32, ctxt);
39f21ee5 4910 break;
5e2c6883
NA		 4911 case 8:
4912 op->val = insn_fetch(s64, ctxt);
4913 break;
39f21ee5
AK		 4914 }
4915 if (!sign_extension) {
4916 switch (op->bytes) {
4917 case 1:
4918 op->val &= 0xff;
4919 break;
4920 case 2:
4921 op->val &= 0xffff;
4922 break;
4923 case 4:
4924 op->val &= 0xffffffff;
4925 break;
4926 }
4927 }
4928done:
4929 return rc;
4930}
4931
a9945549
AK		 4932static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
4933 unsigned d)
4934{
4935 int rc = X86EMUL_CONTINUE;
4936
4937 switch (d) {
4938 case OpReg:
2adb5ad9 4939 decode_register_operand(ctxt, op);
a9945549
AK		 4940 break;
4941 case OpImmUByte:
608aabe3 4942 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 4943 break;
4944 case OpMem:
41ddf978 4945 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 4946 mem_common:
4947 *op = ctxt->memop;
4948 ctxt->memopp = op;
96888977 4949 if (ctxt->d & BitOp)
a9945549
AK		 4950 fetch_bit_operand(ctxt);
4951 op->orig_val = op->val;
4952 break;
41ddf978 4953 case OpMem64:
aaa05f24 4954 ctxt->memop.bytes = (ctxt->op_bytes == 8) ? 16 : 8;
41ddf978 4955 goto mem_common;
a9945549
AK		 4956 case OpAcc:
4957 op->type = OP_REG;
4958 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 4959 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
a9945549
AK		 4960 fetch_register_operand(op);
4961 op->orig_val = op->val;
4962 break;
820207c8
AK		 4963 case OpAccLo:
4964 op->type = OP_REG;
4965 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes;
4966 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4967 fetch_register_operand(op);
4968 op->orig_val = op->val;
4969 break;
4970 case OpAccHi:
4971 if (ctxt->d & ByteOp) {
4972 op->type = OP_NONE;
4973 break;
4974 }
4975 op->type = OP_REG;
4976 op->bytes = ctxt->op_bytes;
4977 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4978 fetch_register_operand(op);
4979 op->orig_val = op->val;
4980 break;
a9945549
AK		 4981 case OpDI:
4982 op->type = OP_MEM;
4983 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4984 op->addr.mem.ea =
01485a22 4985 register_address(ctxt, VCPU_REGS_RDI);
a9945549
AK		 4986 op->addr.mem.seg = VCPU_SREG_ES;
4987 op->val = 0;
b3356bf0 4988 op->count = 1;
a9945549
AK		 4989 break;
4990 case OpDX:
4991 op->type = OP_REG;
4992 op->bytes = 2;
dd856efa 4993 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
a9945549
AK		 4994 fetch_register_operand(op);
4995 break;
4dd6a57d 4996 case OpCL:
d29b9d7e 4997 op->type = OP_IMM;
4dd6a57d 4998 op->bytes = 1;
dd856efa 4999 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4dd6a57d
AK		 5000 break;
5001 case OpImmByte:
5002 rc = decode_imm(ctxt, op, 1, true);
5003 break;
5004 case OpOne:
d29b9d7e 5005 op->type = OP_IMM;
4dd6a57d
AK		 5006 op->bytes = 1;
5007 op->val = 1;
5008 break;
5009 case OpImm:
5010 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
5011 break;
5e2c6883
NA		 5012 case OpImm64:
5013 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
5014 break;
28867cee
AK		 5015 case OpMem8:
5016 ctxt->memop.bytes = 1;
660696d1 5017 if (ctxt->memop.type == OP_REG) {
aa9ac1a6
GN		 5018 ctxt->memop.addr.reg = decode_register(ctxt,
5019 ctxt->modrm_rm, true);
660696d1
GN		 5020 fetch_register_operand(&ctxt->memop);
5021 }
28867cee 5022 goto mem_common;
0fe59128
AK		 5023 case OpMem16:
5024 ctxt->memop.bytes = 2;
5025 goto mem_common;
5026 case OpMem32:
5027 ctxt->memop.bytes = 4;
5028 goto mem_common;
5029 case OpImmU16:
5030 rc = decode_imm(ctxt, op, 2, false);
5031 break;
5032 case OpImmU:
5033 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
5034 break;
5035 case OpSI:
5036 op->type = OP_MEM;
5037 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
5038 op->addr.mem.ea =
01485a22 5039 register_address(ctxt, VCPU_REGS_RSI);
573e80fe 5040 op->addr.mem.seg = ctxt->seg_override;
0fe59128 5041 op->val = 0;
b3356bf0 5042 op->count = 1;
0fe59128 5043 break;
7fa57952
PB		 5044 case OpXLat:
5045 op->type = OP_MEM;
5046 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
5047 op->addr.mem.ea =
01485a22 5048 address_mask(ctxt,
7fa57952
PB		 5049 reg_read(ctxt, VCPU_REGS_RBX) +
5050 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
573e80fe 5051 op->addr.mem.seg = ctxt->seg_override;
7fa57952
PB		 5052 op->val = 0;
5053 break;
0fe59128
AK		 5054 case OpImmFAddr:
5055 op->type = OP_IMM;
5056 op->addr.mem.ea = ctxt->_eip;
5057 op->bytes = ctxt->op_bytes + 2;
5058 insn_fetch_arr(op->valptr, op->bytes, ctxt);
5059 break;
5060 case OpMemFAddr:
5061 ctxt->memop.bytes = ctxt->op_bytes + 2;
5062 goto mem_common;
c191a7a0 5063 case OpES:
d29b9d7e 5064 op->type = OP_IMM;
c191a7a0
AK		 5065 op->val = VCPU_SREG_ES;
5066 break;
5067 case OpCS:
d29b9d7e 5068 op->type = OP_IMM;
c191a7a0
AK		 5069 op->val = VCPU_SREG_CS;
5070 break;
5071 case OpSS:
d29b9d7e 5072 op->type = OP_IMM;
c191a7a0
AK		 5073 op->val = VCPU_SREG_SS;
5074 break;
5075 case OpDS:
d29b9d7e 5076 op->type = OP_IMM;
c191a7a0
AK		 5077 op->val = VCPU_SREG_DS;
5078 break;
5079 case OpFS:
d29b9d7e 5080 op->type = OP_IMM;
c191a7a0
AK		 5081 op->val = VCPU_SREG_FS;
5082 break;
5083 case OpGS:
d29b9d7e 5084 op->type = OP_IMM;
c191a7a0
AK		 5085 op->val = VCPU_SREG_GS;
5086 break;
a9945549
AK		 5087 case OpImplicit:
5088 /* Special instructions do their own operand decoding. */
5089 default:
5090 op->type = OP_NONE; /* Disable writeback. */
5091 break;
5092 }
5093
5094done:
5095 return rc;
5096}
5097
ef5d75cc 5098int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 5099{
dde7e6d1
AK		 5100 int rc = X86EMUL_CONTINUE;
5101 int mode = ctxt->mode;
46561646 5102 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 5103 bool op_prefix = false;
573e80fe 5104 bool has_seg_override = false;
46561646 5105 struct opcode opcode;
3853be26
WL		 5106 u16 dummy;
5107 struct desc_struct desc;
dde7e6d1 5108
f09ed83e
AK		 5109 ctxt->memop.type = OP_NONE;
5110 ctxt->memopp = NULL;
9dac77fa 5111 ctxt->_eip = ctxt->eip;
17052f16
PB		 5112 ctxt->fetch.ptr = ctxt->fetch.data;
5113 ctxt->fetch.end = ctxt->fetch.data + insn_len;
1ce19dc1 5114 ctxt->opcode_len = 1;
dc25e89e 5115 if (insn_len > 0)
9dac77fa 5116 memcpy(ctxt->fetch.data, insn, insn_len);
285ca9e9 5117 else {
9506d57d 5118 rc = __do_insn_fetch_bytes(ctxt, 1);
285ca9e9
PB		 5119 if (rc != X86EMUL_CONTINUE)
5120 return rc;
5121 }
dde7e6d1
AK		 5122
5123 switch (mode) {
5124 case X86EMUL_MODE_REAL:
5125 case X86EMUL_MODE_VM86:
3853be26
WL		 5126 def_op_bytes = def_ad_bytes = 2;
5127 ctxt->ops->get_segment(ctxt, &dummy, &desc, NULL, VCPU_SREG_CS);
5128 if (desc.d)
5129 def_op_bytes = def_ad_bytes = 4;
5130 break;
dde7e6d1
AK		 5131 case X86EMUL_MODE_PROT16:
5132 def_op_bytes = def_ad_bytes = 2;
5133 break;
5134 case X86EMUL_MODE_PROT32:
5135 def_op_bytes = def_ad_bytes = 4;
5136 break;
5137#ifdef CONFIG_X86_64
5138 case X86EMUL_MODE_PROT64:
5139 def_op_bytes = 4;
5140 def_ad_bytes = 8;
5141 break;
5142#endif
5143 default:
1d2887e2 5144 return EMULATION_FAILED;
dde7e6d1
AK		 5145 }
5146
9dac77fa
AK		 5147 ctxt->op_bytes = def_op_bytes;
5148 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 5149
5150 /* Legacy prefixes. */
5151 for (;;) {
e85a1085 5152 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 5153 case 0x66: /* operand-size override */
0d7cdee8 5154 op_prefix = true;
dde7e6d1 5155 /* switch between 2/4 bytes */
9dac77fa 5156 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 5157 break;
5158 case 0x67: /* address-size override */
5159 if (mode == X86EMUL_MODE_PROT64)
5160 /* switch between 4/8 bytes */
9dac77fa 5161 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 5162 else
5163 /* switch between 2/4 bytes */
9dac77fa 5164 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 5165 break;
5166 case 0x26: /* ES override */
5167 case 0x2e: /* CS override */
5168 case 0x36: /* SS override */
5169 case 0x3e: /* DS override */
573e80fe
BD		 5170 has_seg_override = true;
5171 ctxt->seg_override = (ctxt->b >> 3) & 3;
dde7e6d1
AK		 5172 break;
5173 case 0x64: /* FS override */
5174 case 0x65: /* GS override */
573e80fe
BD		 5175 has_seg_override = true;
5176 ctxt->seg_override = ctxt->b & 7;
dde7e6d1
AK		 5177 break;
5178 case 0x40 ... 0x4f: /* REX */
5179 if (mode != X86EMUL_MODE_PROT64)
5180 goto done_prefixes;
9dac77fa 5181 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 5182 continue;
5183 case 0xf0: /* LOCK */
9dac77fa 5184 ctxt->lock_prefix = 1;
dde7e6d1
AK		 5185 break;
5186 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 5187 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 5188 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 5189 break;
5190 default:
5191 goto done_prefixes;
5192 }
5193
5194 /* Any legacy prefix after a REX prefix nullifies its effect. */
5195
9dac77fa 5196 ctxt->rex_prefix = 0;
dde7e6d1
AK		 5197 }
5198
5199done_prefixes:
5200
5201 /* REX prefix. */
9dac77fa
AK		 5202 if (ctxt->rex_prefix & 8)
5203 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 5204
5205 /* Opcode byte(s). */
9dac77fa 5206 opcode = opcode_table[ctxt->b];
d3ad6243 5207 /* Two-byte opcode? */
9dac77fa 5208 if (ctxt->b == 0x0f) {
1ce19dc1 5209 ctxt->opcode_len = 2;
e85a1085 5210 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 5211 opcode = twobyte_table[ctxt->b];
0bc5eedb
BP		 5212
5213 /* 0F_38 opcode map */
5214 if (ctxt->b == 0x38) {
5215 ctxt->opcode_len = 3;
5216 ctxt->b = insn_fetch(u8, ctxt);
5217 opcode = opcode_map_0f_38[ctxt->b];
5218 }
dde7e6d1 5219 }
9dac77fa 5220 ctxt->d = opcode.flags;
dde7e6d1 5221
9f4260e7
TY		 5222 if (ctxt->d & ModRM)
5223 ctxt->modrm = insn_fetch(u8, ctxt);
5224
7fe864dc
NA		 5225 /* vex-prefix instructions are not implemented */
5226 if (ctxt->opcode_len == 1 && (ctxt->b == 0xc5 || ctxt->b == 0xc4) &&
d14cb5df 5227 (mode == X86EMUL_MODE_PROT64 || (ctxt->modrm & 0xc0) == 0xc0)) {
7fe864dc
NA		 5228 ctxt->d = NotImpl;
5229 }
5230
9dac77fa
AK		 5231 while (ctxt->d & GroupMask) {
5232 switch (ctxt->d & GroupMask) {
46561646 5233 case Group:
9dac77fa 5234 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 5235 opcode = opcode.u.group[goffset];
5236 break;
5237 case GroupDual:
9dac77fa
AK		 5238 goffset = (ctxt->modrm >> 3) & 7;
5239 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 5240 opcode = opcode.u.gdual->mod3[goffset];
5241 else
5242 opcode = opcode.u.gdual->mod012[goffset];
5243 break;
5244 case RMExt:
9dac77fa 5245 goffset = ctxt->modrm & 7;
01de8b09 5246 opcode = opcode.u.group[goffset];
46561646
AK		 5247 break;
5248 case Prefix:
9dac77fa 5249 if (ctxt->rep_prefix && op_prefix)
1d2887e2 5250 return EMULATION_FAILED;
9dac77fa 5251 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 5252 switch (simd_prefix) {
5253 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
5254 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
5255 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
5256 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
5257 }
5258 break;
045a282c
GN		 5259 case Escape:
5260 if (ctxt->modrm > 0xbf)
5261 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
5262 else
5263 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
5264 break;
39f062ff
NA		 5265 case InstrDual:
5266 if ((ctxt->modrm >> 6) == 3)
5267 opcode = opcode.u.idual->mod3;
5268 else
5269 opcode = opcode.u.idual->mod012;
5270 break;
2276b511
NA		 5271 case ModeDual:
5272 if (ctxt->mode == X86EMUL_MODE_PROT64)
5273 opcode = opcode.u.mdual->mode64;
5274 else
5275 opcode = opcode.u.mdual->mode32;
5276 break;
46561646 5277 default:
1d2887e2 5278 return EMULATION_FAILED;
0d7cdee8 5279 }
46561646 5280
b1ea50b2 5281 ctxt->d &= ~(u64)GroupMask;
9dac77fa 5282 ctxt->d |= opcode.flags;
0d7cdee8
AK		 5283 }
5284
e24186e0
PB		 5285 /* Unrecognised? */
5286 if (ctxt->d == 0)
5287 return EMULATION_FAILED;
5288
9dac77fa 5289 ctxt->execute = opcode.u.execute;
dde7e6d1 5290
3a6095a0
NA		 5291 if (unlikely(ctxt->ud) && likely(!(ctxt->d & EmulateOnUD)))
5292 return EMULATION_FAILED;
5293
d40a6898 5294 if (unlikely(ctxt->d &
ed9aad21
NA		 5295 (NotImpl|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm|NearBranch|
5296 No16))) {
d40a6898
PB		 5297 /*
5298 * These are copied unconditionally here, and checked unconditionally
5299 * in x86_emulate_insn.
5300 */
5301 ctxt->check_perm = opcode.check_perm;
5302 ctxt->intercept = opcode.intercept;
dde7e6d1 5303
d40a6898
PB		 5304 if (ctxt->d & NotImpl)
5305 return EMULATION_FAILED;
d867162c 5306
58b7075d
NA		 5307 if (mode == X86EMUL_MODE_PROT64) {
5308 if (ctxt->op_bytes == 4 && (ctxt->d & Stack))
5309 ctxt->op_bytes = 8;
5310 else if (ctxt->d & NearBranch)
5311 ctxt->op_bytes = 8;
5312 }
7f9b4b75 5313
d40a6898
PB		 5314 if (ctxt->d & Op3264) {
5315 if (mode == X86EMUL_MODE_PROT64)
5316 ctxt->op_bytes = 8;
5317 else
5318 ctxt->op_bytes = 4;
5319 }
5320
ed9aad21
NA		 5321 if ((ctxt->d & No16) && ctxt->op_bytes == 2)
5322 ctxt->op_bytes = 4;
5323
d40a6898
PB		 5324 if (ctxt->d & Sse)
5325 ctxt->op_bytes = 16;
5326 else if (ctxt->d & Mmx)
5327 ctxt->op_bytes = 8;
5328 }
1253791d 5329
dde7e6d1 5330 /* ModRM and SIB bytes. */
9dac77fa 5331 if (ctxt->d & ModRM) {
f09ed83e 5332 rc = decode_modrm(ctxt, &ctxt->memop);
573e80fe
BD		 5333 if (!has_seg_override) {
5334 has_seg_override = true;
5335 ctxt->seg_override = ctxt->modrm_seg;
5336 }
9dac77fa 5337 } else if (ctxt->d & MemAbs)
f09ed83e 5338 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 5339 if (rc != X86EMUL_CONTINUE)
5340 goto done;
5341
573e80fe
BD		 5342 if (!has_seg_override)
5343 ctxt->seg_override = VCPU_SREG_DS;
dde7e6d1 5344
573e80fe 5345 ctxt->memop.addr.mem.seg = ctxt->seg_override;
dde7e6d1 5346
dde7e6d1
AK		 5347 /*
5348 * Decode and fetch the source operand: register, memory
5349 * or immediate.
5350 */
0fe59128 5351 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 5352 if (rc != X86EMUL_CONTINUE)
5353 goto done;
5354
dde7e6d1
AK		 5355 /*
5356 * Decode and fetch the second source operand: register, memory
5357 * or immediate.
5358 */
4dd6a57d 5359 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 5360 if (rc != X86EMUL_CONTINUE)
5361 goto done;
5362
dde7e6d1 5363 /* Decode and fetch the destination operand: register or memory. */
a9945549 5364 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1 5365
d9092f52 5366 if (ctxt->rip_relative && likely(ctxt->memopp))
1c1c35ae
NA		 5367 ctxt->memopp->addr.mem.ea = address_mask(ctxt,
5368 ctxt->memopp->addr.mem.ea + ctxt->_eip);
cb16c348 5369
a430c916 5370done:
1d2887e2 5371 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 5372}
5373
1cb3f3ae
XG		 5374bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
5375{
5376 return ctxt->d & PageTable;
5377}
5378
3e2f65d5
GN		 5379static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
5380{
3e2f65d5
GN		 5381 /* The second termination condition only applies for REPE
5382 * and REPNE. Test if the repeat string operation prefix is
5383 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
5384 * corresponding termination condition according to:
5385 * - if REPE/REPZ and ZF = 0 then done
5386 * - if REPNE/REPNZ and ZF = 1 then done
5387 */
9dac77fa
AK		 5388 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
5389 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
5390 && (((ctxt->rep_prefix == REPE_PREFIX) &&
0efb0440 5391 ((ctxt->eflags & X86_EFLAGS_ZF) == 0))
9dac77fa 5392 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
0efb0440 5393 ((ctxt->eflags & X86_EFLAGS_ZF) == X86_EFLAGS_ZF))))
3e2f65d5
GN		 5394 return true;
5395
5396 return false;
5397}
5398
cbe2c9d3
AK		 5399static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
5400{
aabba3c6 5401 int rc;
cbe2c9d3 5402
aabba3c6 5403 rc = asm_safe("fwait");
cbe2c9d3 5404
aabba3c6 5405 if (unlikely(rc != X86EMUL_CONTINUE))
cbe2c9d3
AK		 5406 return emulate_exception(ctxt, MF_VECTOR, 0, false);
5407
5408 return X86EMUL_CONTINUE;
5409}
5410
5411static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
5412 struct operand *op)
5413{
5414 if (op->type == OP_MM)
5415 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
5416}
5417
e28bbd44
AK		 5418static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
5419{
5420 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
4548f63e 5421
b9fa409b
AK		 5422 if (!(ctxt->d & ByteOp))
5423 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
4548f63e 5424
1a29b5b7 5425 asm("push %[flags]; popf; " CALL_NOSPEC " ; pushf; pop %[flags]\n"
b8c0b6ae 5426 : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags),
1a29b5b7 5427 [thunk_target]"+S"(fop), ASM_CALL_CONSTRAINT
b8c0b6ae 5428 : "c"(ctxt->src2.val));
4548f63e 5429
e28bbd44 5430 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
b8c0b6ae
AK		 5431 if (!fop) /* exception is returned in fop variable */
5432 return emulate_de(ctxt);
e28bbd44
AK		 5433 return X86EMUL_CONTINUE;
5434}
dd856efa 5435
1498507a
BD		 5436void init_decode_cache(struct x86_emulate_ctxt *ctxt)
5437{
573e80fe
BD		 5438 memset(&ctxt->rip_relative, 0,
5439 (void *)&ctxt->modrm - (void *)&ctxt->rip_relative);
1498507a 5440
1498507a
BD		 5441 ctxt->io_read.pos = 0;
5442 ctxt->io_read.end = 0;
1498507a
BD		 5443 ctxt->mem_read.end = 0;
5444}
5445
7b105ca2 5446int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 5447{
0225fb50 5448 const struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 5449 int rc = X86EMUL_CONTINUE;
9dac77fa 5450 int saved_dst_type = ctxt->dst.type;
6ed071f0 5451 unsigned emul_flags;
8b4caf66 5452
9dac77fa 5453 ctxt->mem_read.pos = 0;
310b5d30 5454
e24186e0
PB		 5455 /* LOCK prefix is allowed only with some instructions */
5456 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 5457 rc = emulate_ud(ctxt);
1161624f
GN		 5458 goto done;
5459 }
5460
e24186e0 5461 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 5462 rc = emulate_ud(ctxt);
d380a5e4
GN		 5463 goto done;
5464 }
5465
6ed071f0 5466 emul_flags = ctxt->ops->get_hflags(ctxt);
d40a6898
PB		 5467 if (unlikely(ctxt->d &
5468 (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) {
5469 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
5470 (ctxt->d & Undefined)) {
5471 rc = emulate_ud(ctxt);
5472 goto done;
5473 }
1253791d 5474
d40a6898
PB		 5475 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
5476 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
5477 rc = emulate_ud(ctxt);
cbe2c9d3 5478 goto done;
d40a6898 5479 }
cbe2c9d3 5480
d40a6898
PB		 5481 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
5482 rc = emulate_nm(ctxt);
c4f035c6 5483 goto done;
d40a6898 5484 }
c4f035c6 5485
d40a6898
PB		 5486 if (ctxt->d & Mmx) {
5487 rc = flush_pending_x87_faults(ctxt);
5488 if (rc != X86EMUL_CONTINUE)
5489 goto done;
5490 /*
5491 * Now that we know the fpu is exception safe, we can fetch
5492 * operands from it.
5493 */
5494 fetch_possible_mmx_operand(ctxt, &ctxt->src);
5495 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
5496 if (!(ctxt->d & Mov))
5497 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
5498 }
e92805ac 5499
6ed071f0 5500 if (unlikely(emul_flags & X86EMUL_GUEST_MASK) && ctxt->intercept) {
d40a6898
PB		 5501 rc = emulator_check_intercept(ctxt, ctxt->intercept,
5502 X86_ICPT_PRE_EXCEPT);
5503 if (rc != X86EMUL_CONTINUE)
5504 goto done;
5505 }
8ea7d6ae 5506
64a38292
NA		 5507 /* Instruction can only be executed in protected mode */
5508 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
5509 rc = emulate_ud(ctxt);
5510 goto done;
5511 }
5512
d40a6898
PB		 5513 /* Privileged instruction can be executed only in CPL=0 */
5514 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
68efa764
NA		 5515 if (ctxt->d & PrivUD)
5516 rc = emulate_ud(ctxt);
5517 else
5518 rc = emulate_gp(ctxt, 0);
d09beabd 5519 goto done;
d40a6898 5520 }
d09beabd 5521
d40a6898 5522 /* Do instruction specific permission checks */
685bbf4a 5523 if (ctxt->d & CheckPerm) {
d40a6898
PB		 5524 rc = ctxt->check_perm(ctxt);
5525 if (rc != X86EMUL_CONTINUE)
5526 goto done;
5527 }
5528
6ed071f0 5529 if (unlikely(emul_flags & X86EMUL_GUEST_MASK) && (ctxt->d & Intercept)) {
d40a6898
PB		 5530 rc = emulator_check_intercept(ctxt, ctxt->intercept,
5531 X86_ICPT_POST_EXCEPT);
5532 if (rc != X86EMUL_CONTINUE)
5533 goto done;
5534 }
5535
5536 if (ctxt->rep_prefix && (ctxt->d & String)) {
5537 /* All REP prefixes have the same first termination condition */
5538 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
428e3d08 5539 string_registers_quirk(ctxt);
d40a6898 5540 ctxt->eip = ctxt->_eip;
0efb0440 5541 ctxt->eflags &= ~X86_EFLAGS_RF;
d40a6898
PB		 5542 goto done;
5543 }
b9fa9d6b 5544 }
b9fa9d6b
AK		 5545 }
5546
9dac77fa
AK		 5547 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
5548 rc = segmented_read(ctxt, ctxt->src.addr.mem,
5549 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 5550 if (rc != X86EMUL_CONTINUE)
8b4caf66 5551 goto done;
9dac77fa 5552 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 5553 }
5554
9dac77fa
AK		 5555 if (ctxt->src2.type == OP_MEM) {
5556 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
5557 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 5558 if (rc != X86EMUL_CONTINUE)
5559 goto done;
5560 }
5561
9dac77fa 5562 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 5563 goto special_insn;
5564
5565
9dac77fa 5566 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 5567 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 5568 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
5569 &ctxt->dst.val, ctxt->dst.bytes);
c205fb7d 5570 if (rc != X86EMUL_CONTINUE) {
d44e1212
PB		 5571 if (!(ctxt->d & NoWrite) &&
5572 rc == X86EMUL_PROPAGATE_FAULT &&
c205fb7d
NA		 5573 ctxt->exception.vector == PF_VECTOR)
5574 ctxt->exception.error_code |= PFERR_WRITE_MASK;
69f55cb1 5575 goto done;
c205fb7d 5576 }
038e51de 5577 }
4ff6f8e6
PB		 5578 /* Copy full 64-bit value for CMPXCHG8B. */
5579 ctxt->dst.orig_val64 = ctxt->dst.val64;
038e51de 5580
018a98db
AK		 5581special_insn:
5582
6ed071f0 5583 if (unlikely(emul_flags & X86EMUL_GUEST_MASK) && (ctxt->d & Intercept)) {
9dac77fa 5584 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 5585 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 5586 if (rc != X86EMUL_CONTINUE)
5587 goto done;
5588 }
5589
b9a1ecb9 5590 if (ctxt->rep_prefix && (ctxt->d & String))
0efb0440 5591 ctxt->eflags |= X86_EFLAGS_RF;
b9a1ecb9 5592 else
0efb0440 5593 ctxt->eflags &= ~X86_EFLAGS_RF;
4467c3f1 5594
9dac77fa 5595 if (ctxt->execute) {
e28bbd44
AK		 5596 if (ctxt->d & Fastop) {
5597 void (*fop)(struct fastop *) = (void *)ctxt->execute;
5598 rc = fastop(ctxt, fop);
5599 if (rc != X86EMUL_CONTINUE)
5600 goto done;
5601 goto writeback;
5602 }
9dac77fa 5603 rc = ctxt->execute(ctxt);
ef65c889
AK		 5604 if (rc != X86EMUL_CONTINUE)
5605 goto done;
5606 goto writeback;
5607 }
5608
1ce19dc1 5609 if (ctxt->opcode_len == 2)
6aa8b732 5610 goto twobyte_insn;
0bc5eedb
BP		 5611 else if (ctxt->opcode_len == 3)
5612 goto threebyte_insn;
6aa8b732 5613
9dac77fa 5614 switch (ctxt->b) {
b2833e3c 5615 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa 5616 if (test_cc(ctxt->b, ctxt->eflags))
234f3ce4 5617 rc = jmp_rel(ctxt, ctxt->src.val);
018a98db 5618 break;
7e0b54b1 5619 case 0x8d: /* lea r16/r32, m */
9dac77fa 5620 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 5621 break;
3d9e77df 5622 case 0x90 ... 0x97: /* nop / xchg reg, rax */
dd856efa 5623 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
a825f5cc
NA		 5624 ctxt->dst.type = OP_NONE;
5625 else
5626 rc = em_xchg(ctxt);
e4f973ae 5627 break;
e8b6fa70 5628 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 5629 switch (ctxt->op_bytes) {
5630 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
5631 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
5632 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 5633 }
5634 break;
6e154e56 5635 case 0xcc: /* int3 */
5c5df76b
TY		 5636 rc = emulate_int(ctxt, 3);
5637 break;
6e154e56 5638 case 0xcd: /* int n */
9dac77fa 5639 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 5640 break;
5641 case 0xce: /* into */
0efb0440 5642 if (ctxt->eflags & X86_EFLAGS_OF)
5c5df76b 5643 rc = emulate_int(ctxt, 4);
6e154e56 5644 break;
1a52e051 5645 case 0xe9: /* jmp rel */
db5b0762 5646 case 0xeb: /* jmp rel short */
234f3ce4 5647 rc = jmp_rel(ctxt, ctxt->src.val);
9dac77fa 5648 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 5649 break;
111de5d6 5650 case 0xf4: /* hlt */
6c3287f7 5651 ctxt->ops->halt(ctxt);
19fdfa0d 5652 break;
111de5d6
AK		 5653 case 0xf5: /* cmc */
5654 /* complement carry flag from eflags reg */
0efb0440 5655 ctxt->eflags ^= X86_EFLAGS_CF;
111de5d6
AK		 5656 break;
5657 case 0xf8: /* clc */
0efb0440 5658 ctxt->eflags &= ~X86_EFLAGS_CF;
111de5d6 5659 break;
8744aa9a 5660 case 0xf9: /* stc */
0efb0440 5661 ctxt->eflags |= X86_EFLAGS_CF;
8744aa9a 5662 break;
fb4616f4 5663 case 0xfc: /* cld */
0efb0440 5664 ctxt->eflags &= ~X86_EFLAGS_DF;
fb4616f4
MG		 5665 break;
5666 case 0xfd: /* std */
0efb0440 5667 ctxt->eflags |= X86_EFLAGS_DF;
fb4616f4 5668 break;
91269b8f
AK		 5669 default:
5670 goto cannot_emulate;
6aa8b732 5671 }
018a98db 5672
7d9ddaed
AK		 5673 if (rc != X86EMUL_CONTINUE)
5674 goto done;
5675
018a98db 5676writeback:
fb32b1ed
AK		 5677 if (ctxt->d & SrcWrite) {
5678 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR);
5679 rc = writeback(ctxt, &ctxt->src);
5680 if (rc != X86EMUL_CONTINUE)
5681 goto done;
5682 }
ee212297
NA		 5683 if (!(ctxt->d & NoWrite)) {
5684 rc = writeback(ctxt, &ctxt->dst);
5685 if (rc != X86EMUL_CONTINUE)
5686 goto done;
5687 }
018a98db 5688
5cd21917
GN		 5689 /*
5690 * restore dst type in case the decoding will be reused
5691 * (happens for string instruction )
5692 */
9dac77fa 5693 ctxt->dst.type = saved_dst_type;
5cd21917 5694
9dac77fa 5695 if ((ctxt->d & SrcMask) == SrcSI)
f3bd64c6 5696 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
a682e354 5697
9dac77fa 5698 if ((ctxt->d & DstMask) == DstDI)
f3bd64c6 5699 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
d9271123 5700
9dac77fa 5701 if (ctxt->rep_prefix && (ctxt->d & String)) {
b3356bf0 5702 unsigned int count;
9dac77fa 5703 struct read_cache *r = &ctxt->io_read;
b3356bf0
GN		 5704 if ((ctxt->d & SrcMask) == SrcSI)
5705 count = ctxt->src.count;
5706 else
5707 count = ctxt->dst.count;
01485a22 5708 register_address_increment(ctxt, VCPU_REGS_RCX, -count);
3e2f65d5 5709
d2ddd1c4
GN		 5710 if (!string_insn_completed(ctxt)) {
5711 /*
5712 * Re-enter guest when pio read ahead buffer is empty
5713 * or, if it is not used, after each 1024 iteration.
5714 */
dd856efa 5715 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
d2ddd1c4
GN		 5716 (r->end == 0 || r->end != r->pos)) {
5717 /*
5718 * Reset read cache. Usually happens before
5719 * decode, but since instruction is restarted
5720 * we have to do it here.
5721 */
9dac77fa 5722 ctxt->mem_read.end = 0;
dd856efa 5723 writeback_registers(ctxt);
d2ddd1c4
GN		 5724 return EMULATION_RESTART;
5725 }
5726 goto done; /* skip rip writeback */
0fa6ccbd 5727 }
0efb0440 5728 ctxt->eflags &= ~X86_EFLAGS_RF;
5cd21917 5729 }
d2ddd1c4 5730
9dac77fa 5731 ctxt->eip = ctxt->_eip;
018a98db
AK		 5732
5733done:
e0ad0b47
PB		 5734 if (rc == X86EMUL_PROPAGATE_FAULT) {
5735 WARN_ON(ctxt->exception.vector > 0x1f);
da9cb575 5736 ctxt->have_exception = true;
e0ad0b47 5737 }
775fde86
JR		 5738 if (rc == X86EMUL_INTERCEPTED)
5739 return EMULATION_INTERCEPTED;
5740
dd856efa
AK		 5741 if (rc == X86EMUL_CONTINUE)
5742 writeback_registers(ctxt);
5743
d2ddd1c4 5744 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 5745
5746twobyte_insn:
9dac77fa 5747 switch (ctxt->b) {
018a98db 5748 case 0x09: /* wbinvd */
cfb22375 5749 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 5750 break;
5751 case 0x08: /* invd */
018a98db
AK		 5752 case 0x0d: /* GrpP (prefetch) */
5753 case 0x18: /* Grp16 (prefetch/nop) */
103f98ea 5754 case 0x1f: /* nop */
018a98db
AK		 5755 break;
5756 case 0x20: /* mov cr, reg */
9dac77fa 5757 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 5758 break;
6aa8b732 5759 case 0x21: /* mov from dr to reg */
9dac77fa 5760 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 5761 break;
6aa8b732 5762 case 0x40 ... 0x4f: /* cmov */
140bad89
NA		 5763 if (test_cc(ctxt->b, ctxt->eflags))
5764 ctxt->dst.val = ctxt->src.val;
b91aa14d 5765 else if (ctxt->op_bytes != 4)
9dac77fa 5766 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 5767 break;
b2833e3c 5768 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa 5769 if (test_cc(ctxt->b, ctxt->eflags))
234f3ce4 5770 rc = jmp_rel(ctxt, ctxt->src.val);
018a98db 5771 break;
ee45b58e 5772 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 5773 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 5774 break;
6aa8b732 5775 case 0xb6 ... 0xb7: /* movzx */
9dac77fa 5776 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 5777 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
9dac77fa 5778 : (u16) ctxt->src.val;
6aa8b732 5779 break;
6aa8b732 5780 case 0xbe ... 0xbf: /* movsx */
9dac77fa 5781 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 5782 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
9dac77fa 5783 (s16) ctxt->src.val;
6aa8b732 5784 break;
91269b8f
AK		 5785 default:
5786 goto cannot_emulate;
6aa8b732 5787 }
7d9ddaed 5788
0bc5eedb
BP		 5789threebyte_insn:
5790
7d9ddaed
AK		 5791 if (rc != X86EMUL_CONTINUE)
5792 goto done;
5793
6aa8b732
AK		 5794 goto writeback;
5795
5796cannot_emulate:
a0c0ab2f 5797 return EMULATION_FAILED;
6aa8b732 5798}
dd856efa
AK		 5799
5800void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
5801{
5802 invalidate_registers(ctxt);
5803}
5804
5805void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
5806{
5807 writeback_registers(ctxt);
5808}
0f89b207
TL		 5809
5810bool emulator_can_use_gpa(struct x86_emulate_ctxt *ctxt)
5811{
5812 if (ctxt->rep_prefix && (ctxt->d & String))
5813 return false;
5814
5815 if (ctxt->d & TwoMemOp)
5816 return false;
5817
5818 return true;
5819}
Linux 6.x block layer and io_uring tree(s)