Commit | Line | Data |
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20c8ccb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
00b27a3e AK |
2 | /* |
3 | * Kernel-based Virtual Machine driver for Linux | |
4 | * cpuid support routines | |
5 | * | |
6 | * derived from arch/x86/kvm/x86.c | |
7 | * | |
8 | * Copyright 2011 Red Hat, Inc. and/or its affiliates. | |
9 | * Copyright IBM Corporation, 2008 | |
00b27a3e | 10 | */ |
8d20bd63 | 11 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
00b27a3e AK |
12 | |
13 | #include <linux/kvm_host.h> | |
9717efbe | 14 | #include "linux/lockdep.h" |
1767e931 | 15 | #include <linux/export.h> |
bb5a798a JK |
16 | #include <linux/vmalloc.h> |
17 | #include <linux/uaccess.h> | |
3905f9ad IM |
18 | #include <linux/sched/stat.h> |
19 | ||
4504b5c9 | 20 | #include <asm/processor.h> |
00b27a3e | 21 | #include <asm/user.h> |
669ebabb | 22 | #include <asm/fpu/xstate.h> |
72add915 | 23 | #include <asm/sgx.h> |
b66370db | 24 | #include <asm/cpuid.h> |
00b27a3e AK |
25 | #include "cpuid.h" |
26 | #include "lapic.h" | |
27 | #include "mmu.h" | |
28 | #include "trace.h" | |
474a5bb9 | 29 | #include "pmu.h" |
f422f853 | 30 | #include "xen.h" |
00b27a3e | 31 | |
66a6950f SC |
32 | /* |
33 | * Unlike "struct cpuinfo_x86.x86_capability", kvm_cpu_caps doesn't need to be | |
34 | * aligned to sizeof(unsigned long) because it's not accessed via bitops. | |
35 | */ | |
4e66c0cb | 36 | u32 kvm_cpu_caps[NR_KVM_CPU_CAPS] __read_mostly; |
66a6950f SC |
37 | EXPORT_SYMBOL_GPL(kvm_cpu_caps); |
38 | ||
be50b206 | 39 | u32 xstate_required_size(u64 xstate_bv, bool compacted) |
4344ee98 PB |
40 | { |
41 | int feature_bit = 0; | |
42 | u32 ret = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; | |
43 | ||
d91cab78 | 44 | xstate_bv &= XFEATURE_MASK_EXTEND; |
4344ee98 PB |
45 | while (xstate_bv) { |
46 | if (xstate_bv & 0x1) { | |
412a3c41 | 47 | u32 eax, ebx, ecx, edx, offset; |
4344ee98 | 48 | cpuid_count(0xD, feature_bit, &eax, &ebx, &ecx, &edx); |
cc04b6a2 JL |
49 | /* ECX[1]: 64B alignment in compacted form */ |
50 | if (compacted) | |
51 | offset = (ecx & 0x2) ? ALIGN(ret, 64) : ret; | |
52 | else | |
53 | offset = ebx; | |
412a3c41 | 54 | ret = max(ret, offset + eax); |
4344ee98 PB |
55 | } |
56 | ||
57 | xstate_bv >>= 1; | |
58 | feature_bit++; | |
59 | } | |
60 | ||
61 | return ret; | |
62 | } | |
63 | ||
87382003 | 64 | #define F feature_bit |
c4690d01 SC |
65 | |
66 | /* Scattered Flag - For features that are scattered by cpufeatures.h. */ | |
67 | #define SF(name) \ | |
68 | ({ \ | |
69 | BUILD_BUG_ON(X86_FEATURE_##name >= MAX_CPU_FEATURES); \ | |
70 | (boot_cpu_has(X86_FEATURE_##name) ? F(name) : 0); \ | |
71 | }) | |
5c404cab | 72 | |
277ad7d5 SC |
73 | /* |
74 | * Magic value used by KVM when querying userspace-provided CPUID entries and | |
75 | * doesn't care about the CPIUD index because the index of the function in | |
76 | * question is not significant. Note, this magic value must have at least one | |
77 | * bit set in bits[63:32] and must be consumed as a u64 by cpuid_entry2_find() | |
78 | * to avoid false positives when processing guest CPUID input. | |
79 | */ | |
80 | #define KVM_CPUID_INDEX_NOT_SIGNIFICANT -1ull | |
b73a5432 | 81 | |
f69858fc | 82 | static inline struct kvm_cpuid_entry2 *cpuid_entry2_find( |
277ad7d5 | 83 | struct kvm_cpuid_entry2 *entries, int nent, u32 function, u64 index) |
f69858fc VK |
84 | { |
85 | struct kvm_cpuid_entry2 *e; | |
86 | int i; | |
87 | ||
9717efbe SC |
88 | /* |
89 | * KVM has a semi-arbitrary rule that querying the guest's CPUID model | |
90 | * with IRQs disabled is disallowed. The CPUID model can legitimately | |
91 | * have over one hundred entries, i.e. the lookup is slow, and IRQs are | |
92 | * typically disabled in KVM only when KVM is in a performance critical | |
93 | * path, e.g. the core VM-Enter/VM-Exit run loop. Nothing will break | |
94 | * if this rule is violated, this assertion is purely to flag potential | |
95 | * performance issues. If this fires, consider moving the lookup out | |
96 | * of the hotpath, e.g. by caching information during CPUID updates. | |
97 | */ | |
98 | lockdep_assert_irqs_enabled(); | |
99 | ||
f69858fc VK |
100 | for (i = 0; i < nent; i++) { |
101 | e = &entries[i]; | |
102 | ||
277ad7d5 SC |
103 | if (e->function != function) |
104 | continue; | |
105 | ||
106 | /* | |
107 | * If the index isn't significant, use the first entry with a | |
54aa699e | 108 | * matching function. It's userspace's responsibility to not |
277ad7d5 SC |
109 | * provide "duplicate" entries in all cases. |
110 | */ | |
111 | if (!(e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) || e->index == index) | |
112 | return e; | |
113 | ||
114 | ||
115 | /* | |
116 | * Similarly, use the first matching entry if KVM is doing a | |
117 | * lookup (as opposed to emulating CPUID) for a function that's | |
118 | * architecturally defined as not having a significant index. | |
119 | */ | |
120 | if (index == KVM_CPUID_INDEX_NOT_SIGNIFICANT) { | |
121 | /* | |
122 | * Direct lookups from KVM should not diverge from what | |
123 | * KVM defines internally (the architectural behavior). | |
124 | */ | |
125 | WARN_ON_ONCE(cpuid_function_is_indexed(function)); | |
f69858fc | 126 | return e; |
277ad7d5 | 127 | } |
f69858fc VK |
128 | } |
129 | ||
130 | return NULL; | |
131 | } | |
132 | ||
5ab2f45b JL |
133 | static int kvm_check_cpuid(struct kvm_vcpu *vcpu, |
134 | struct kvm_cpuid_entry2 *entries, | |
135 | int nent) | |
a76733a9 XL |
136 | { |
137 | struct kvm_cpuid_entry2 *best; | |
5ab2f45b | 138 | u64 xfeatures; |
a76733a9 XL |
139 | |
140 | /* | |
141 | * The existing code assumes virtual address is 48-bit or 57-bit in the | |
142 | * canonical address checks; exit if it is ever changed. | |
143 | */ | |
277ad7d5 SC |
144 | best = cpuid_entry2_find(entries, nent, 0x80000008, |
145 | KVM_CPUID_INDEX_NOT_SIGNIFICANT); | |
a76733a9 XL |
146 | if (best) { |
147 | int vaddr_bits = (best->eax & 0xff00) >> 8; | |
148 | ||
149 | if (vaddr_bits != 48 && vaddr_bits != 57 && vaddr_bits != 0) | |
150 | return -EINVAL; | |
151 | } | |
152 | ||
5ab2f45b JL |
153 | /* |
154 | * Exposing dynamic xfeatures to the guest requires additional | |
155 | * enabling in the FPU, e.g. to expand the guest XSAVE state size. | |
156 | */ | |
157 | best = cpuid_entry2_find(entries, nent, 0xd, 0); | |
158 | if (!best) | |
159 | return 0; | |
160 | ||
161 | xfeatures = best->eax | ((u64)best->edx << 32); | |
162 | xfeatures &= XFEATURE_MASK_USER_DYNAMIC; | |
163 | if (!xfeatures) | |
164 | return 0; | |
165 | ||
166 | return fpu_enable_guest_xfd_features(&vcpu->arch.guest_fpu, xfeatures); | |
a76733a9 XL |
167 | } |
168 | ||
c6617c61 VK |
169 | /* Check whether the supplied CPUID data is equal to what is already set for the vCPU. */ |
170 | static int kvm_cpuid_check_equal(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *e2, | |
171 | int nent) | |
172 | { | |
173 | struct kvm_cpuid_entry2 *orig; | |
174 | int i; | |
175 | ||
176 | if (nent != vcpu->arch.cpuid_nent) | |
177 | return -EINVAL; | |
178 | ||
179 | for (i = 0; i < nent; i++) { | |
180 | orig = &vcpu->arch.cpuid_entries[i]; | |
181 | if (e2[i].function != orig->function || | |
182 | e2[i].index != orig->index || | |
033a3ea5 | 183 | e2[i].flags != orig->flags || |
c6617c61 VK |
184 | e2[i].eax != orig->eax || e2[i].ebx != orig->ebx || |
185 | e2[i].ecx != orig->ecx || e2[i].edx != orig->edx) | |
186 | return -EINVAL; | |
187 | } | |
188 | ||
189 | return 0; | |
190 | } | |
191 | ||
92e82cf6 VK |
192 | static struct kvm_hypervisor_cpuid __kvm_get_hypervisor_cpuid(struct kvm_cpuid_entry2 *entries, |
193 | int nent, const char *sig) | |
01b4f510 | 194 | { |
48639df8 | 195 | struct kvm_hypervisor_cpuid cpuid = {}; |
760849b1 | 196 | struct kvm_cpuid_entry2 *entry; |
48639df8 | 197 | u32 base; |
760849b1 | 198 | |
48639df8 | 199 | for_each_possible_hypervisor_cpuid_base(base) { |
92e82cf6 | 200 | entry = cpuid_entry2_find(entries, nent, base, KVM_CPUID_INDEX_NOT_SIGNIFICANT); |
760849b1 PD |
201 | |
202 | if (entry) { | |
203 | u32 signature[3]; | |
204 | ||
205 | signature[0] = entry->ebx; | |
206 | signature[1] = entry->ecx; | |
207 | signature[2] = entry->edx; | |
208 | ||
48639df8 PD |
209 | if (!memcmp(signature, sig, sizeof(signature))) { |
210 | cpuid.base = base; | |
211 | cpuid.limit = entry->eax; | |
760849b1 PD |
212 | break; |
213 | } | |
214 | } | |
215 | } | |
48639df8 PD |
216 | |
217 | return cpuid; | |
760849b1 PD |
218 | } |
219 | ||
92e82cf6 VK |
220 | static struct kvm_hypervisor_cpuid kvm_get_hypervisor_cpuid(struct kvm_vcpu *vcpu, |
221 | const char *sig) | |
222 | { | |
223 | return __kvm_get_hypervisor_cpuid(vcpu->arch.cpuid_entries, | |
224 | vcpu->arch.cpuid_nent, sig); | |
225 | } | |
226 | ||
4736d85f VK |
227 | static struct kvm_cpuid_entry2 *__kvm_find_kvm_cpuid_features(struct kvm_cpuid_entry2 *entries, |
228 | int nent, u32 kvm_cpuid_base) | |
760849b1 | 229 | { |
4736d85f | 230 | return cpuid_entry2_find(entries, nent, kvm_cpuid_base | KVM_CPUID_FEATURES, |
277ad7d5 | 231 | KVM_CPUID_INDEX_NOT_SIGNIFICANT); |
ee3a5f9e VK |
232 | } |
233 | ||
234 | static struct kvm_cpuid_entry2 *kvm_find_kvm_cpuid_features(struct kvm_vcpu *vcpu) | |
235 | { | |
4736d85f VK |
236 | u32 base = vcpu->arch.kvm_cpuid.base; |
237 | ||
238 | if (!base) | |
239 | return NULL; | |
240 | ||
241 | return __kvm_find_kvm_cpuid_features(vcpu->arch.cpuid_entries, | |
242 | vcpu->arch.cpuid_nent, base); | |
760849b1 | 243 | } |
01b4f510 | 244 | |
760849b1 PD |
245 | void kvm_update_pv_runtime(struct kvm_vcpu *vcpu) |
246 | { | |
247 | struct kvm_cpuid_entry2 *best = kvm_find_kvm_cpuid_features(vcpu); | |
01b4f510 OU |
248 | |
249 | /* | |
250 | * save the feature bitmap to avoid cpuid lookup for every PV | |
251 | * operation | |
252 | */ | |
253 | if (best) | |
254 | vcpu->arch.pv_cpuid.features = best->eax; | |
255 | } | |
256 | ||
5c89be1d VK |
257 | /* |
258 | * Calculate guest's supported XCR0 taking into account guest CPUID data and | |
938c8745 | 259 | * KVM's supported XCR0 (comprised of host's XCR0 and KVM_SUPPORTED_XCR0). |
5c89be1d VK |
260 | */ |
261 | static u64 cpuid_get_supported_xcr0(struct kvm_cpuid_entry2 *entries, int nent) | |
262 | { | |
263 | struct kvm_cpuid_entry2 *best; | |
264 | ||
265 | best = cpuid_entry2_find(entries, nent, 0xd, 0); | |
266 | if (!best) | |
267 | return 0; | |
268 | ||
938c8745 | 269 | return (best->eax | ((u64)best->edx << 32)) & kvm_caps.supported_xcr0; |
5c89be1d VK |
270 | } |
271 | ||
ee3a5f9e VK |
272 | static void __kvm_update_cpuid_runtime(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *entries, |
273 | int nent) | |
00b27a3e AK |
274 | { |
275 | struct kvm_cpuid_entry2 *best; | |
4736d85f | 276 | struct kvm_hypervisor_cpuid kvm_cpuid; |
00b27a3e | 277 | |
277ad7d5 | 278 | best = cpuid_entry2_find(entries, nent, 1, KVM_CPUID_INDEX_NOT_SIGNIFICANT); |
0d3b2ba1 XL |
279 | if (best) { |
280 | /* Update OSXSAVE bit */ | |
281 | if (boot_cpu_has(X86_FEATURE_XSAVE)) | |
282 | cpuid_entry_change(best, X86_FEATURE_OSXSAVE, | |
607475cf | 283 | kvm_is_cr4_bit_set(vcpu, X86_CR4_OSXSAVE)); |
00b27a3e | 284 | |
0d3b2ba1 | 285 | cpuid_entry_change(best, X86_FEATURE_APIC, |
b32666b1 | 286 | vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE); |
0d3b2ba1 | 287 | } |
c7dd15b3 | 288 | |
ee3a5f9e | 289 | best = cpuid_entry2_find(entries, nent, 7, 0); |
b32666b1 SC |
290 | if (best && boot_cpu_has(X86_FEATURE_PKU) && best->function == 0x7) |
291 | cpuid_entry_change(best, X86_FEATURE_OSPKE, | |
607475cf | 292 | kvm_is_cr4_bit_set(vcpu, X86_CR4_PKE)); |
b9baba86 | 293 | |
ee3a5f9e | 294 | best = cpuid_entry2_find(entries, nent, 0xD, 0); |
aedbaf4f | 295 | if (best) |
a71936ab | 296 | best->ebx = xstate_required_size(vcpu->arch.xcr0, false); |
d7876f1b | 297 | |
ee3a5f9e | 298 | best = cpuid_entry2_find(entries, nent, 0xD, 1); |
4c61534a SC |
299 | if (best && (cpuid_entry_has(best, X86_FEATURE_XSAVES) || |
300 | cpuid_entry_has(best, X86_FEATURE_XSAVEC))) | |
412a3c41 PB |
301 | best->ebx = xstate_required_size(vcpu->arch.xcr0, true); |
302 | ||
4736d85f VK |
303 | kvm_cpuid = __kvm_get_hypervisor_cpuid(entries, nent, KVM_SIGNATURE); |
304 | if (kvm_cpuid.base) { | |
305 | best = __kvm_find_kvm_cpuid_features(entries, nent, kvm_cpuid.base); | |
306 | if (kvm_hlt_in_guest(vcpu->kvm) && best) | |
307 | best->eax &= ~(1 << KVM_FEATURE_PV_UNHALT); | |
308 | } | |
caa057a2 | 309 | |
511a8556 | 310 | if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT)) { |
277ad7d5 | 311 | best = cpuid_entry2_find(entries, nent, 0x1, KVM_CPUID_INDEX_NOT_SIGNIFICANT); |
b32666b1 SC |
312 | if (best) |
313 | cpuid_entry_change(best, X86_FEATURE_MWAIT, | |
314 | vcpu->arch.ia32_misc_enable_msr & | |
315 | MSR_IA32_MISC_ENABLE_MWAIT); | |
511a8556 | 316 | } |
aedbaf4f | 317 | } |
ee3a5f9e VK |
318 | |
319 | void kvm_update_cpuid_runtime(struct kvm_vcpu *vcpu) | |
320 | { | |
321 | __kvm_update_cpuid_runtime(vcpu, vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent); | |
322 | } | |
2259c17f | 323 | EXPORT_SYMBOL_GPL(kvm_update_cpuid_runtime); |
aedbaf4f | 324 | |
3be29eb7 SC |
325 | static bool kvm_cpuid_has_hyperv(struct kvm_cpuid_entry2 *entries, int nent) |
326 | { | |
b4f69df0 | 327 | #ifdef CONFIG_KVM_HYPERV |
3be29eb7 SC |
328 | struct kvm_cpuid_entry2 *entry; |
329 | ||
330 | entry = cpuid_entry2_find(entries, nent, HYPERV_CPUID_INTERFACE, | |
331 | KVM_CPUID_INDEX_NOT_SIGNIFICANT); | |
332 | return entry && entry->eax == HYPERV_CPUID_SIGNATURE_EAX; | |
b4f69df0 VK |
333 | #else |
334 | return false; | |
335 | #endif | |
3be29eb7 SC |
336 | } |
337 | ||
346ce359 | 338 | static void kvm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu) |
aedbaf4f XL |
339 | { |
340 | struct kvm_lapic *apic = vcpu->arch.apic; | |
341 | struct kvm_cpuid_entry2 *best; | |
ccf31d6e | 342 | bool allow_gbpages; |
aedbaf4f | 343 | |
42764413 SC |
344 | BUILD_BUG_ON(KVM_NR_GOVERNED_FEATURES > KVM_MAX_NR_GOVERNED_FEATURES); |
345 | bitmap_zero(vcpu->arch.governed_features.enabled, | |
346 | KVM_MAX_NR_GOVERNED_FEATURES); | |
347 | ||
ccf31d6e SC |
348 | /* |
349 | * If TDP is enabled, let the guest use GBPAGES if they're supported in | |
350 | * hardware. The hardware page walker doesn't let KVM disable GBPAGES, | |
351 | * i.e. won't treat them as reserved, and KVM doesn't redo the GVA->GPA | |
352 | * walk for performance and complexity reasons. Not to mention KVM | |
353 | * _can't_ solve the problem because GVA->GPA walks aren't visible to | |
354 | * KVM once a TDP translation is installed. Mimic hardware behavior so | |
355 | * that KVM's is at least consistent, i.e. doesn't randomly inject #PF. | |
356 | * If TDP is disabled, honor *only* guest CPUID as KVM has full control | |
357 | * and can install smaller shadow pages if the host lacks 1GiB support. | |
358 | */ | |
359 | allow_gbpages = tdp_enabled ? boot_cpu_has(X86_FEATURE_GBPAGES) : | |
360 | guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES); | |
361 | if (allow_gbpages) | |
362 | kvm_governed_feature_set(vcpu, X86_FEATURE_GBPAGES); | |
aedbaf4f | 363 | |
277ad7d5 | 364 | best = kvm_find_cpuid_entry(vcpu, 1); |
aedbaf4f XL |
365 | if (best && apic) { |
366 | if (cpuid_entry_has(best, X86_FEATURE_TSC_DEADLINE_TIMER)) | |
367 | apic->lapic_timer.timer_mode_mask = 3 << 17; | |
368 | else | |
369 | apic->lapic_timer.timer_mode_mask = 1 << 17; | |
370 | ||
371 | kvm_apic_set_version(vcpu); | |
372 | } | |
373 | ||
ee519b3a | 374 | vcpu->arch.guest_supported_xcr0 = |
5c89be1d | 375 | cpuid_get_supported_xcr0(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent); |
72add915 | 376 | |
01b4f510 OU |
377 | kvm_update_pv_runtime(vcpu); |
378 | ||
fd706c9b | 379 | vcpu->arch.is_amd_compatible = guest_cpuid_is_amd_or_hygon(vcpu); |
5a4f55cd | 380 | vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); |
a8ac864a | 381 | vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu); |
5a4f55cd | 382 | |
c6702c9d | 383 | kvm_pmu_refresh(vcpu); |
b899c132 KS |
384 | vcpu->arch.cr4_guest_rsvd_bits = |
385 | __cr4_reserved_bits(guest_cpuid_has, vcpu); | |
c44d9b34 | 386 | |
3be29eb7 SC |
387 | kvm_hv_set_cpuid(vcpu, kvm_cpuid_has_hyperv(vcpu->arch.cpuid_entries, |
388 | vcpu->arch.cpuid_nent)); | |
8f014550 | 389 | |
c44d9b34 | 390 | /* Invoke the vendor callback only after the above state is updated. */ |
b3646477 | 391 | static_call(kvm_x86_vcpu_after_set_cpuid)(vcpu); |
5b7f575c SC |
392 | |
393 | /* | |
49c6f875 SC |
394 | * Except for the MMU, which needs to do its thing any vendor specific |
395 | * adjustments to the reserved GPA bits. | |
5b7f575c | 396 | */ |
49c6f875 | 397 | kvm_mmu_after_set_cpuid(vcpu); |
00b27a3e AK |
398 | } |
399 | ||
5a4f55cd EK |
400 | int cpuid_query_maxphyaddr(struct kvm_vcpu *vcpu) |
401 | { | |
402 | struct kvm_cpuid_entry2 *best; | |
403 | ||
277ad7d5 | 404 | best = kvm_find_cpuid_entry(vcpu, 0x80000000); |
5a4f55cd EK |
405 | if (!best || best->eax < 0x80000008) |
406 | goto not_found; | |
277ad7d5 | 407 | best = kvm_find_cpuid_entry(vcpu, 0x80000008); |
5a4f55cd EK |
408 | if (best) |
409 | return best->eax & 0xff; | |
410 | not_found: | |
411 | return 36; | |
412 | } | |
5a4f55cd | 413 | |
a8ac864a SC |
414 | /* |
415 | * This "raw" version returns the reserved GPA bits without any adjustments for | |
416 | * encryption technologies that usurp bits. The raw mask should be used if and | |
417 | * only if hardware does _not_ strip the usurped bits, e.g. in virtual MTRRs. | |
418 | */ | |
419 | u64 kvm_vcpu_reserved_gpa_bits_raw(struct kvm_vcpu *vcpu) | |
420 | { | |
421 | return rsvd_bits(cpuid_maxphyaddr(vcpu), 63); | |
422 | } | |
423 | ||
8b44b174 SC |
424 | static int kvm_set_cpuid(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *e2, |
425 | int nent) | |
426 | { | |
5ab2f45b | 427 | int r; |
8b44b174 | 428 | |
ee3a5f9e VK |
429 | __kvm_update_cpuid_runtime(vcpu, e2, nent); |
430 | ||
c6617c61 VK |
431 | /* |
432 | * KVM does not correctly handle changing guest CPUID after KVM_RUN, as | |
433 | * MAXPHYADDR, GBPAGES support, AMD reserved bit behavior, etc.. aren't | |
434 | * tracked in kvm_mmu_page_role. As a result, KVM may miss guest page | |
435 | * faults due to reusing SPs/SPTEs. In practice no sane VMM mucks with | |
436 | * the core vCPU model on the fly. It would've been better to forbid any | |
437 | * KVM_SET_CPUID{,2} calls after KVM_RUN altogether but unfortunately | |
438 | * some VMMs (e.g. QEMU) reuse vCPU fds for CPU hotplug/unplug and do | |
439 | * KVM_SET_CPUID{,2} again. To support this legacy behavior, check | |
440 | * whether the supplied CPUID data is equal to what's already set. | |
441 | */ | |
fb3146b4 | 442 | if (kvm_vcpu_has_run(vcpu)) { |
811f95ff SC |
443 | r = kvm_cpuid_check_equal(vcpu, e2, nent); |
444 | if (r) | |
445 | return r; | |
446 | ||
447 | kvfree(e2); | |
448 | return 0; | |
449 | } | |
c6617c61 | 450 | |
b4f69df0 | 451 | #ifdef CONFIG_KVM_HYPERV |
3be29eb7 SC |
452 | if (kvm_cpuid_has_hyperv(e2, nent)) { |
453 | r = kvm_hv_vcpu_init(vcpu); | |
454 | if (r) | |
455 | return r; | |
456 | } | |
b4f69df0 | 457 | #endif |
3be29eb7 | 458 | |
5ab2f45b JL |
459 | r = kvm_check_cpuid(vcpu, e2, nent); |
460 | if (r) | |
461 | return r; | |
8b44b174 | 462 | |
5ab2f45b JL |
463 | kvfree(vcpu->arch.cpuid_entries); |
464 | vcpu->arch.cpuid_entries = e2; | |
465 | vcpu->arch.cpuid_nent = nent; | |
8b44b174 | 466 | |
48639df8 | 467 | vcpu->arch.kvm_cpuid = kvm_get_hypervisor_cpuid(vcpu, KVM_SIGNATURE); |
ee11ab6b | 468 | #ifdef CONFIG_KVM_XEN |
f422f853 | 469 | vcpu->arch.xen.cpuid = kvm_get_hypervisor_cpuid(vcpu, XEN_SIGNATURE); |
ee11ab6b | 470 | #endif |
5ab2f45b | 471 | kvm_vcpu_after_set_cpuid(vcpu); |
8b44b174 | 472 | |
5ab2f45b | 473 | return 0; |
8b44b174 SC |
474 | } |
475 | ||
00b27a3e AK |
476 | /* when an old userspace process fills a new kernel module */ |
477 | int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu, | |
478 | struct kvm_cpuid *cpuid, | |
479 | struct kvm_cpuid_entry __user *entries) | |
480 | { | |
481 | int r, i; | |
255cbecf VK |
482 | struct kvm_cpuid_entry *e = NULL; |
483 | struct kvm_cpuid_entry2 *e2 = NULL; | |
00b27a3e | 484 | |
00b27a3e | 485 | if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) |
255cbecf VK |
486 | return -E2BIG; |
487 | ||
83676e92 | 488 | if (cpuid->nent) { |
573cc0e5 | 489 | e = vmemdup_array_user(entries, cpuid->nent, sizeof(*e)); |
255cbecf VK |
490 | if (IS_ERR(e)) |
491 | return PTR_ERR(e); | |
492 | ||
493 | e2 = kvmalloc_array(cpuid->nent, sizeof(*e2), GFP_KERNEL_ACCOUNT); | |
494 | if (!e2) { | |
495 | r = -ENOMEM; | |
496 | goto out_free_cpuid; | |
7ec28e26 | 497 | } |
83676e92 | 498 | } |
00b27a3e | 499 | for (i = 0; i < cpuid->nent; i++) { |
255cbecf VK |
500 | e2[i].function = e[i].function; |
501 | e2[i].eax = e[i].eax; | |
502 | e2[i].ebx = e[i].ebx; | |
503 | e2[i].ecx = e[i].ecx; | |
504 | e2[i].edx = e[i].edx; | |
505 | e2[i].index = 0; | |
506 | e2[i].flags = 0; | |
507 | e2[i].padding[0] = 0; | |
508 | e2[i].padding[1] = 0; | |
509 | e2[i].padding[2] = 0; | |
00b27a3e | 510 | } |
255cbecf | 511 | |
8b44b174 SC |
512 | r = kvm_set_cpuid(vcpu, e2, cpuid->nent); |
513 | if (r) | |
255cbecf | 514 | kvfree(e2); |
00b27a3e | 515 | |
255cbecf VK |
516 | out_free_cpuid: |
517 | kvfree(e); | |
518 | ||
00b27a3e AK |
519 | return r; |
520 | } | |
521 | ||
522 | int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu, | |
523 | struct kvm_cpuid2 *cpuid, | |
524 | struct kvm_cpuid_entry2 __user *entries) | |
525 | { | |
255cbecf | 526 | struct kvm_cpuid_entry2 *e2 = NULL; |
00b27a3e AK |
527 | int r; |
528 | ||
00b27a3e | 529 | if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) |
255cbecf VK |
530 | return -E2BIG; |
531 | ||
532 | if (cpuid->nent) { | |
573cc0e5 | 533 | e2 = vmemdup_array_user(entries, cpuid->nent, sizeof(*e2)); |
255cbecf VK |
534 | if (IS_ERR(e2)) |
535 | return PTR_ERR(e2); | |
536 | } | |
537 | ||
8b44b174 SC |
538 | r = kvm_set_cpuid(vcpu, e2, cpuid->nent); |
539 | if (r) | |
255cbecf | 540 | kvfree(e2); |
255cbecf | 541 | |
8b44b174 | 542 | return r; |
00b27a3e AK |
543 | } |
544 | ||
545 | int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu, | |
546 | struct kvm_cpuid2 *cpuid, | |
547 | struct kvm_cpuid_entry2 __user *entries) | |
548 | { | |
00b27a3e | 549 | if (cpuid->nent < vcpu->arch.cpuid_nent) |
ab322c43 SC |
550 | return -E2BIG; |
551 | ||
181f4948 | 552 | if (copy_to_user(entries, vcpu->arch.cpuid_entries, |
00b27a3e | 553 | vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2))) |
ab322c43 | 554 | return -EFAULT; |
00b27a3e | 555 | |
00b27a3e | 556 | cpuid->nent = vcpu->arch.cpuid_nent; |
ab322c43 | 557 | return 0; |
00b27a3e AK |
558 | } |
559 | ||
4e66c0cb | 560 | /* Mask kvm_cpu_caps for @leaf with the raw CPUID capabilities of this CPU. */ |
462f8dde | 561 | static __always_inline void __kvm_cpu_cap_mask(unsigned int leaf) |
66a6950f | 562 | { |
d8577a4c SC |
563 | const struct cpuid_reg cpuid = x86_feature_cpuid(leaf * 32); |
564 | struct kvm_cpuid_entry2 entry; | |
565 | ||
66a6950f | 566 | reverse_cpuid_check(leaf); |
d8577a4c SC |
567 | |
568 | cpuid_count(cpuid.function, cpuid.index, | |
569 | &entry.eax, &entry.ebx, &entry.ecx, &entry.edx); | |
570 | ||
855c7e9b | 571 | kvm_cpu_caps[leaf] &= *__cpuid_entry_get_reg(&entry, cpuid.reg); |
66a6950f SC |
572 | } |
573 | ||
462f8dde | 574 | static __always_inline |
047c7229 | 575 | void kvm_cpu_cap_init_kvm_defined(enum kvm_only_cpuid_leafs leaf, u32 mask) |
4e66c0cb | 576 | { |
047c7229 | 577 | /* Use kvm_cpu_cap_mask for leafs that aren't KVM-only. */ |
4e66c0cb SC |
578 | BUILD_BUG_ON(leaf < NCAPINTS); |
579 | ||
580 | kvm_cpu_caps[leaf] = mask; | |
581 | ||
582 | __kvm_cpu_cap_mask(leaf); | |
583 | } | |
584 | ||
585 | static __always_inline void kvm_cpu_cap_mask(enum cpuid_leafs leaf, u32 mask) | |
586 | { | |
047c7229 | 587 | /* Use kvm_cpu_cap_init_kvm_defined for KVM-only leafs. */ |
4e66c0cb SC |
588 | BUILD_BUG_ON(leaf >= NCAPINTS); |
589 | ||
590 | kvm_cpu_caps[leaf] &= mask; | |
591 | ||
592 | __kvm_cpu_cap_mask(leaf); | |
593 | } | |
594 | ||
66a6950f SC |
595 | void kvm_set_cpu_caps(void) |
596 | { | |
66a6950f SC |
597 | #ifdef CONFIG_X86_64 |
598 | unsigned int f_gbpages = F(GBPAGES); | |
599 | unsigned int f_lm = F(LM); | |
690a757d | 600 | unsigned int f_xfd = F(XFD); |
66a6950f SC |
601 | #else |
602 | unsigned int f_gbpages = 0; | |
603 | unsigned int f_lm = 0; | |
690a757d | 604 | unsigned int f_xfd = 0; |
66a6950f | 605 | #endif |
4e66c0cb | 606 | memset(kvm_cpu_caps, 0, sizeof(kvm_cpu_caps)); |
66a6950f | 607 | |
4e66c0cb | 608 | BUILD_BUG_ON(sizeof(kvm_cpu_caps) - (NKVMCAPINTS * sizeof(*kvm_cpu_caps)) > |
66a6950f SC |
609 | sizeof(boot_cpu_data.x86_capability)); |
610 | ||
611 | memcpy(&kvm_cpu_caps, &boot_cpu_data.x86_capability, | |
4e66c0cb | 612 | sizeof(kvm_cpu_caps) - (NKVMCAPINTS * sizeof(*kvm_cpu_caps))); |
66a6950f SC |
613 | |
614 | kvm_cpu_cap_mask(CPUID_1_ECX, | |
615 | /* | |
616 | * NOTE: MONITOR (and MWAIT) are emulated as NOP, but *not* | |
617 | * advertised to guests via CPUID! | |
618 | */ | |
619 | F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ | | |
620 | 0 /* DS-CPL, VMX, SMX, EST */ | | |
621 | 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ | | |
27461da3 | 622 | F(FMA) | F(CX16) | 0 /* xTPR Update */ | F(PDCM) | |
66a6950f SC |
623 | F(PCID) | 0 /* Reserved, DCA */ | F(XMM4_1) | |
624 | F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) | | |
625 | 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) | | |
626 | F(F16C) | F(RDRAND) | |
627 | ); | |
93c380e7 SC |
628 | /* KVM emulates x2apic in software irrespective of host support. */ |
629 | kvm_cpu_cap_set(X86_FEATURE_X2APIC); | |
66a6950f SC |
630 | |
631 | kvm_cpu_cap_mask(CPUID_1_EDX, | |
632 | F(FPU) | F(VME) | F(DE) | F(PSE) | | |
633 | F(TSC) | F(MSR) | F(PAE) | F(MCE) | | |
634 | F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) | | |
635 | F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | | |
636 | F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLUSH) | | |
637 | 0 /* Reserved, DS, ACPI */ | F(MMX) | | |
638 | F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) | | |
639 | 0 /* HTT, TM, Reserved, PBE */ | |
640 | ); | |
641 | ||
642 | kvm_cpu_cap_mask(CPUID_7_0_EBX, | |
e3bcfda0 JM |
643 | F(FSGSBASE) | F(SGX) | F(BMI1) | F(HLE) | F(AVX2) | |
644 | F(FDP_EXCPTN_ONLY) | F(SMEP) | F(BMI2) | F(ERMS) | F(INVPCID) | | |
645 | F(RTM) | F(ZERO_FCS_FDS) | 0 /*MPX*/ | F(AVX512F) | | |
646 | F(AVX512DQ) | F(RDSEED) | F(ADX) | F(SMAP) | F(AVX512IFMA) | | |
647 | F(CLFLUSHOPT) | F(CLWB) | 0 /*INTEL_PT*/ | F(AVX512PF) | | |
648 | F(AVX512ER) | F(AVX512CD) | F(SHA_NI) | F(AVX512BW) | | |
649 | F(AVX512VL)); | |
66a6950f SC |
650 | |
651 | kvm_cpu_cap_mask(CPUID_7_ECX, | |
fa44b82e | 652 | F(AVX512VBMI) | F(LA57) | F(PKU) | 0 /*OSPKE*/ | F(RDPID) | |
66a6950f SC |
653 | F(AVX512_VPOPCNTDQ) | F(UMIP) | F(AVX512_VBMI2) | F(GFNI) | |
654 | F(VAES) | F(VPCLMULQDQ) | F(AVX512_VNNI) | F(AVX512_BITALG) | | |
72add915 | 655 | F(CLDEMOTE) | F(MOVDIRI) | F(MOVDIR64B) | 0 /*WAITPKG*/ | |
76ea438b | 656 | F(SGX_LC) | F(BUS_LOCK_DETECT) |
66a6950f SC |
657 | ); |
658 | /* Set LA57 based on hardware capability. */ | |
659 | if (cpuid_ecx(7) & F(LA57)) | |
660 | kvm_cpu_cap_set(X86_FEATURE_LA57); | |
661 | ||
fa44b82e BM |
662 | /* |
663 | * PKU not yet implemented for shadow paging and requires OSPKE | |
664 | * to be set on the host. Clear it if that is not the case | |
665 | */ | |
666 | if (!tdp_enabled || !boot_cpu_has(X86_FEATURE_OSPKE)) | |
667 | kvm_cpu_cap_clear(X86_FEATURE_PKU); | |
668 | ||
66a6950f SC |
669 | kvm_cpu_cap_mask(CPUID_7_EDX, |
670 | F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) | | |
671 | F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) | | |
43bd9ef4 | 672 | F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) | |
690a757d | 673 | F(SERIALIZE) | F(TSXLDTRK) | F(AVX512_FP16) | |
45cf86f2 | 674 | F(AMX_TILE) | F(AMX_INT8) | F(AMX_BF16) | F(FLUSH_L1D) |
66a6950f SC |
675 | ); |
676 | ||
93c380e7 SC |
677 | /* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */ |
678 | kvm_cpu_cap_set(X86_FEATURE_TSC_ADJUST); | |
679 | kvm_cpu_cap_set(X86_FEATURE_ARCH_CAPABILITIES); | |
680 | ||
681 | if (boot_cpu_has(X86_FEATURE_IBPB) && boot_cpu_has(X86_FEATURE_IBRS)) | |
682 | kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL); | |
683 | if (boot_cpu_has(X86_FEATURE_STIBP)) | |
684 | kvm_cpu_cap_set(X86_FEATURE_INTEL_STIBP); | |
685 | if (boot_cpu_has(X86_FEATURE_AMD_SSBD)) | |
686 | kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD); | |
687 | ||
66a6950f | 688 | kvm_cpu_cap_mask(CPUID_7_1_EAX, |
2a4209d6 JM |
689 | F(AVX_VNNI) | F(AVX512_BF16) | F(CMPCCXADD) | |
690 | F(FZRM) | F(FSRS) | F(FSRC) | | |
703d794c | 691 | F(AMX_FP16) | F(AVX_IFMA) | F(LAM) |
66a6950f SC |
692 | ); |
693 | ||
24d74b9f | 694 | kvm_cpu_cap_init_kvm_defined(CPUID_7_1_EDX, |
99b66854 TS |
695 | F(AVX_VNNI_INT8) | F(AVX_NE_CONVERT) | F(PREFETCHITI) | |
696 | F(AMX_COMPLEX) | |
66a6950f SC |
697 | ); |
698 | ||
eefe5e66 JM |
699 | kvm_cpu_cap_init_kvm_defined(CPUID_7_2_EDX, |
700 | F(INTEL_PSFD) | F(IPRED_CTRL) | F(RRSBA_CTRL) | F(DDPD_U) | | |
701 | F(BHI_CTRL) | F(MCDT_NO) | |
702 | ); | |
703 | ||
66a6950f | 704 | kvm_cpu_cap_mask(CPUID_D_1_EAX, |
690a757d | 705 | F(XSAVEOPT) | F(XSAVEC) | F(XGETBV1) | F(XSAVES) | f_xfd |
66a6950f SC |
706 | ); |
707 | ||
047c7229 | 708 | kvm_cpu_cap_init_kvm_defined(CPUID_12_EAX, |
16a7fe37 | 709 | SF(SGX1) | SF(SGX2) | SF(SGX_EDECCSSA) |
72add915 SC |
710 | ); |
711 | ||
66a6950f SC |
712 | kvm_cpu_cap_mask(CPUID_8000_0001_ECX, |
713 | F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ | | |
714 | F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) | | |
715 | F(3DNOWPREFETCH) | F(OSVW) | 0 /* IBS */ | F(XOP) | | |
716 | 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM) | | |
b1d66dad | 717 | F(TOPOEXT) | 0 /* PERFCTR_CORE */ |
66a6950f SC |
718 | ); |
719 | ||
720 | kvm_cpu_cap_mask(CPUID_8000_0001_EDX, | |
721 | F(FPU) | F(VME) | F(DE) | F(PSE) | | |
722 | F(TSC) | F(MSR) | F(PAE) | F(MCE) | | |
723 | F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) | | |
724 | F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | | |
725 | F(PAT) | F(PSE36) | 0 /* Reserved */ | | |
1383279c | 726 | F(NX) | 0 /* Reserved */ | F(MMXEXT) | F(MMX) | |
66a6950f SC |
727 | F(FXSR) | F(FXSR_OPT) | f_gbpages | F(RDTSCP) | |
728 | 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW) | |
729 | ); | |
730 | ||
731 | if (!tdp_enabled && IS_ENABLED(CONFIG_X86_64)) | |
732 | kvm_cpu_cap_set(X86_FEATURE_GBPAGES); | |
733 | ||
0fcf86f0 VK |
734 | kvm_cpu_cap_init_kvm_defined(CPUID_8000_0007_EDX, |
735 | SF(CONSTANT_TSC) | |
736 | ); | |
737 | ||
66a6950f SC |
738 | kvm_cpu_cap_mask(CPUID_8000_0008_EBX, |
739 | F(CLZERO) | F(XSAVEERPTR) | | |
740 | F(WBNOINVD) | F(AMD_IBPB) | F(AMD_IBRS) | F(AMD_SSBD) | F(VIRT_SSBD) | | |
b73a5432 | 741 | F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_STIBP_ALWAYS_ON) | |
3d8f61bf | 742 | F(AMD_PSFD) |
66a6950f SC |
743 | ); |
744 | ||
93c380e7 SC |
745 | /* |
746 | * AMD has separate bits for each SPEC_CTRL bit. | |
747 | * arch/x86/kernel/cpu/bugs.c is kind enough to | |
748 | * record that in cpufeatures so use them. | |
749 | */ | |
750 | if (boot_cpu_has(X86_FEATURE_IBPB)) | |
751 | kvm_cpu_cap_set(X86_FEATURE_AMD_IBPB); | |
752 | if (boot_cpu_has(X86_FEATURE_IBRS)) | |
753 | kvm_cpu_cap_set(X86_FEATURE_AMD_IBRS); | |
754 | if (boot_cpu_has(X86_FEATURE_STIBP)) | |
755 | kvm_cpu_cap_set(X86_FEATURE_AMD_STIBP); | |
756 | if (boot_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD)) | |
757 | kvm_cpu_cap_set(X86_FEATURE_AMD_SSBD); | |
758 | if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
759 | kvm_cpu_cap_set(X86_FEATURE_AMD_SSB_NO); | |
760 | /* | |
761 | * The preference is to use SPEC CTRL MSR instead of the | |
762 | * VIRT_SPEC MSR. | |
763 | */ | |
764 | if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) && | |
765 | !boot_cpu_has(X86_FEATURE_AMD_SSBD)) | |
766 | kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD); | |
767 | ||
9b58b985 SC |
768 | /* |
769 | * Hide all SVM features by default, SVM will set the cap bits for | |
770 | * features it emulates and/or exposes for L1. | |
771 | */ | |
772 | kvm_cpu_cap_mask(CPUID_8000_000A_EDX, 0); | |
773 | ||
d9db0fd6 PB |
774 | kvm_cpu_cap_mask(CPUID_8000_001F_EAX, |
775 | 0 /* SME */ | F(SEV) | 0 /* VM_PAGE_FLUSH */ | F(SEV_ES) | | |
776 | F(SME_COHERENT)); | |
777 | ||
c35ac8c4 | 778 | kvm_cpu_cap_mask(CPUID_8000_0021_EAX, |
84168ae7 | 779 | F(NO_NESTED_DATA_BP) | F(LFENCE_RDTSC) | 0 /* SmmPgCfgLock */ | |
329369ca JM |
780 | F(NULL_SEL_CLR_BASE) | F(AUTOIBRS) | 0 /* PrefetchCtlMsr */ | |
781 | F(WRMSR_XX_BASE_NS) | |
c35ac8c4 | 782 | ); |
84168ae7 | 783 | |
e47d8608 | 784 | kvm_cpu_cap_check_and_set(X86_FEATURE_SBPB); |
6f0f23ef JP |
785 | kvm_cpu_cap_check_and_set(X86_FEATURE_IBPB_BRTYPE); |
786 | kvm_cpu_cap_check_and_set(X86_FEATURE_SRSO_NO); | |
1b5277c0 | 787 | |
94cdeebd LX |
788 | kvm_cpu_cap_init_kvm_defined(CPUID_8000_0022_EAX, |
789 | F(PERFMON_V2) | |
790 | ); | |
791 | ||
84168ae7 KP |
792 | /* |
793 | * Synthesize "LFENCE is serializing" into the AMD-defined entry in | |
794 | * KVM's supported CPUID if the feature is reported as supported by the | |
795 | * kernel. LFENCE_RDTSC was a Linux-defined synthetic feature long | |
796 | * before AMD joined the bandwagon, e.g. LFENCE is serializing on most | |
797 | * CPUs that support SSE2. On CPUs that don't support AMD's leaf, | |
798 | * kvm_cpu_cap_mask() will unfortunately drop the flag due to ANDing | |
799 | * the mask with the raw host CPUID, and reporting support in AMD's | |
800 | * leaf can make it easier for userspace to detect the feature. | |
801 | */ | |
c35ac8c4 | 802 | if (cpu_feature_enabled(X86_FEATURE_LFENCE_RDTSC)) |
84168ae7 | 803 | kvm_cpu_cap_set(X86_FEATURE_LFENCE_RDTSC); |
c35ac8c4 | 804 | if (!static_cpu_has_bug(X86_BUG_NULL_SEG)) |
5b909d4a | 805 | kvm_cpu_cap_set(X86_FEATURE_NULL_SEL_CLR_BASE); |
faabfcb1 | 806 | kvm_cpu_cap_set(X86_FEATURE_NO_SMM_CTL_MSR); |
c35ac8c4 | 807 | |
66a6950f SC |
808 | kvm_cpu_cap_mask(CPUID_C000_0001_EDX, |
809 | F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) | | |
810 | F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) | | |
811 | F(PMM) | F(PMM_EN) | |
812 | ); | |
78bba966 SC |
813 | |
814 | /* | |
815 | * Hide RDTSCP and RDPID if either feature is reported as supported but | |
816 | * probing MSR_TSC_AUX failed. This is purely a sanity check and | |
817 | * should never happen, but the guest will likely crash if RDTSCP or | |
818 | * RDPID is misreported, and KVM has botched MSR_TSC_AUX emulation in | |
819 | * the past. For example, the sanity check may fire if this instance of | |
820 | * KVM is running as L1 on top of an older, broken KVM. | |
821 | */ | |
822 | if (WARN_ON((kvm_cpu_cap_has(X86_FEATURE_RDTSCP) || | |
823 | kvm_cpu_cap_has(X86_FEATURE_RDPID)) && | |
824 | !kvm_is_supported_user_return_msr(MSR_TSC_AUX))) { | |
825 | kvm_cpu_cap_clear(X86_FEATURE_RDTSCP); | |
826 | kvm_cpu_cap_clear(X86_FEATURE_RDPID); | |
827 | } | |
66a6950f SC |
828 | } |
829 | EXPORT_SYMBOL_GPL(kvm_set_cpu_caps); | |
830 | ||
e53c95e8 SC |
831 | struct kvm_cpuid_array { |
832 | struct kvm_cpuid_entry2 *entries; | |
65b18914 | 833 | int maxnent; |
e53c95e8 SC |
834 | int nent; |
835 | }; | |
836 | ||
45e966fc PB |
837 | static struct kvm_cpuid_entry2 *get_next_cpuid(struct kvm_cpuid_array *array) |
838 | { | |
839 | if (array->nent >= array->maxnent) | |
840 | return NULL; | |
841 | ||
842 | return &array->entries[array->nent++]; | |
843 | } | |
844 | ||
e53c95e8 | 845 | static struct kvm_cpuid_entry2 *do_host_cpuid(struct kvm_cpuid_array *array, |
aa10a7dc | 846 | u32 function, u32 index) |
00b27a3e | 847 | { |
45e966fc | 848 | struct kvm_cpuid_entry2 *entry = get_next_cpuid(array); |
e53c95e8 | 849 | |
45e966fc | 850 | if (!entry) |
aa10a7dc | 851 | return NULL; |
e53c95e8 | 852 | |
2746a6b7 | 853 | memset(entry, 0, sizeof(*entry)); |
00b27a3e AK |
854 | entry->function = function; |
855 | entry->index = index; | |
2746a6b7 PB |
856 | switch (function & 0xC0000000) { |
857 | case 0x40000000: | |
858 | /* Hypervisor leaves are always synthesized by __do_cpuid_func. */ | |
859 | return entry; | |
860 | ||
f144c49e PB |
861 | case 0x80000000: |
862 | /* | |
863 | * 0x80000021 is sometimes synthesized by __do_cpuid_func, which | |
864 | * would result in out-of-bounds calls to do_host_cpuid. | |
865 | */ | |
866 | { | |
867 | static int max_cpuid_80000000; | |
868 | if (!READ_ONCE(max_cpuid_80000000)) | |
869 | WRITE_ONCE(max_cpuid_80000000, cpuid_eax(0x80000000)); | |
870 | if (function > READ_ONCE(max_cpuid_80000000)) | |
871 | return entry; | |
872 | } | |
07ea4ab1 | 873 | break; |
f144c49e | 874 | |
2746a6b7 PB |
875 | default: |
876 | break; | |
877 | } | |
ab8bcf64 | 878 | |
00b27a3e AK |
879 | cpuid_count(entry->function, entry->index, |
880 | &entry->eax, &entry->ebx, &entry->ecx, &entry->edx); | |
d9aadaf6 | 881 | |
b66370db | 882 | if (cpuid_function_is_indexed(function)) |
d9aadaf6 | 883 | entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; |
aa10a7dc SC |
884 | |
885 | return entry; | |
00b27a3e AK |
886 | } |
887 | ||
e53c95e8 | 888 | static int __do_cpuid_func_emulated(struct kvm_cpuid_array *array, u32 func) |
9c15bb1d | 889 | { |
7c7f9548 SC |
890 | struct kvm_cpuid_entry2 *entry; |
891 | ||
892 | if (array->nent >= array->maxnent) | |
893 | return -E2BIG; | |
e53c95e8 | 894 | |
7c7f9548 | 895 | entry = &array->entries[array->nent]; |
ab8bcf64 PB |
896 | entry->function = func; |
897 | entry->index = 0; | |
898 | entry->flags = 0; | |
899 | ||
84cffe49 BP |
900 | switch (func) { |
901 | case 0: | |
fb6d4d34 | 902 | entry->eax = 7; |
e53c95e8 | 903 | ++array->nent; |
84cffe49 BP |
904 | break; |
905 | case 1: | |
906 | entry->ecx = F(MOVBE); | |
e53c95e8 | 907 | ++array->nent; |
84cffe49 | 908 | break; |
fb6d4d34 PB |
909 | case 7: |
910 | entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
ab8bcf64 | 911 | entry->eax = 0; |
85d00112 SC |
912 | if (kvm_cpu_cap_has(X86_FEATURE_RDTSCP)) |
913 | entry->ecx = F(RDPID); | |
e53c95e8 | 914 | ++array->nent; |
551912d2 | 915 | break; |
84cffe49 BP |
916 | default: |
917 | break; | |
918 | } | |
919 | ||
9c15bb1d BP |
920 | return 0; |
921 | } | |
922 | ||
e53c95e8 | 923 | static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) |
00b27a3e | 924 | { |
e53c95e8 | 925 | struct kvm_cpuid_entry2 *entry; |
74fa0bc7 | 926 | int r, i, max_idx; |
00b27a3e | 927 | |
00b27a3e AK |
928 | /* all calls to cpuid_count() should be made on the same cpu */ |
929 | get_cpu(); | |
831bf664 SL |
930 | |
931 | r = -E2BIG; | |
932 | ||
e53c95e8 | 933 | entry = do_host_cpuid(array, function, 0); |
7c7f9548 | 934 | if (!entry) |
831bf664 SL |
935 | goto out; |
936 | ||
00b27a3e AK |
937 | switch (function) { |
938 | case 0: | |
a87f2d3a LX |
939 | /* Limited to the highest leaf implemented in KVM. */ |
940 | entry->eax = min(entry->eax, 0x1fU); | |
00b27a3e AK |
941 | break; |
942 | case 1: | |
bd791999 SC |
943 | cpuid_entry_override(entry, CPUID_1_EDX); |
944 | cpuid_entry_override(entry, CPUID_1_ECX); | |
00b27a3e | 945 | break; |
74fa0bc7 | 946 | case 2: |
c571a144 SC |
947 | /* |
948 | * On ancient CPUs, function 2 entries are STATEFUL. That is, | |
949 | * CPUID(function=2, index=0) may return different results each | |
950 | * time, with the least-significant byte in EAX enumerating the | |
951 | * number of times software should do CPUID(2, 0). | |
952 | * | |
7ff6c035 SC |
953 | * Modern CPUs, i.e. every CPU KVM has *ever* run on are less |
954 | * idiotic. Intel's SDM states that EAX & 0xff "will always | |
955 | * return 01H. Software should ignore this value and not | |
c571a144 SC |
956 | * interpret it as an informational descriptor", while AMD's |
957 | * APM states that CPUID(2) is reserved. | |
7ff6c035 SC |
958 | * |
959 | * WARN if a frankenstein CPU that supports virtualization and | |
960 | * a stateful CPUID.0x2 is encountered. | |
c571a144 | 961 | */ |
7ff6c035 | 962 | WARN_ON_ONCE((entry->eax & 0xff) > 1); |
00b27a3e | 963 | break; |
32a243df JM |
964 | /* functions 4 and 0x8000001d have additional index. */ |
965 | case 4: | |
c8629039 SC |
966 | case 0x8000001d: |
967 | /* | |
968 | * Read entries until the cache type in the previous entry is | |
969 | * zero, i.e. indicates an invalid entry. | |
970 | */ | |
e53c95e8 SC |
971 | for (i = 1; entry->eax & 0x1f; ++i) { |
972 | entry = do_host_cpuid(array, function, i); | |
973 | if (!entry) | |
0fc62671 | 974 | goto out; |
00b27a3e AK |
975 | } |
976 | break; | |
e453aa0f JK |
977 | case 6: /* Thermal management */ |
978 | entry->eax = 0x4; /* allow ARAT */ | |
979 | entry->ebx = 0; | |
980 | entry->ecx = 0; | |
981 | entry->edx = 0; | |
982 | break; | |
54d360d4 | 983 | /* function 7 has additional index. */ |
74fa0bc7 | 984 | case 7: |
eefe5e66 | 985 | max_idx = entry->eax = min(entry->eax, 2u); |
bd791999 SC |
986 | cpuid_entry_override(entry, CPUID_7_0_EBX); |
987 | cpuid_entry_override(entry, CPUID_7_ECX); | |
988 | cpuid_entry_override(entry, CPUID_7_EDX); | |
09f628a0 | 989 | |
eefe5e66 JM |
990 | /* KVM only supports up to 0x7.2, capped above via min(). */ |
991 | if (max_idx >= 1) { | |
bcf600ca | 992 | entry = do_host_cpuid(array, function, 1); |
e53c95e8 | 993 | if (!entry) |
54d360d4 PB |
994 | goto out; |
995 | ||
bd791999 | 996 | cpuid_entry_override(entry, CPUID_7_1_EAX); |
24d74b9f | 997 | cpuid_entry_override(entry, CPUID_7_1_EDX); |
09f628a0 SC |
998 | entry->ebx = 0; |
999 | entry->ecx = 0; | |
54d360d4 | 1000 | } |
eefe5e66 JM |
1001 | if (max_idx >= 2) { |
1002 | entry = do_host_cpuid(array, function, 2); | |
1003 | if (!entry) | |
1004 | goto out; | |
1005 | ||
1006 | cpuid_entry_override(entry, CPUID_7_2_EDX); | |
1007 | entry->ecx = 0; | |
1008 | entry->ebx = 0; | |
1009 | entry->eax = 0; | |
1010 | } | |
00b27a3e | 1011 | break; |
a6c06ed1 | 1012 | case 0xa: { /* Architectural Performance Monitoring */ |
a6c06ed1 GN |
1013 | union cpuid10_eax eax; |
1014 | union cpuid10_edx edx; | |
1015 | ||
6593039d | 1016 | if (!enable_pmu || !static_cpu_has(X86_FEATURE_ARCH_PERFMON)) { |
5a1bde46 SD |
1017 | entry->eax = entry->ebx = entry->ecx = entry->edx = 0; |
1018 | break; | |
1019 | } | |
1020 | ||
968635ab LX |
1021 | eax.split.version_id = kvm_pmu_cap.version; |
1022 | eax.split.num_counters = kvm_pmu_cap.num_counters_gp; | |
1023 | eax.split.bit_width = kvm_pmu_cap.bit_width_gp; | |
1024 | eax.split.mask_length = kvm_pmu_cap.events_mask_len; | |
1025 | edx.split.num_counters_fixed = kvm_pmu_cap.num_counters_fixed; | |
1026 | edx.split.bit_width_fixed = kvm_pmu_cap.bit_width_fixed; | |
a6c06ed1 | 1027 | |
968635ab | 1028 | if (kvm_pmu_cap.version) |
7234c362 | 1029 | edx.split.anythread_deprecated = 1; |
cadbaa03 SE |
1030 | edx.split.reserved1 = 0; |
1031 | edx.split.reserved2 = 0; | |
a6c06ed1 GN |
1032 | |
1033 | entry->eax = eax.full; | |
968635ab | 1034 | entry->ebx = kvm_pmu_cap.events_mask; |
a6c06ed1 GN |
1035 | entry->ecx = 0; |
1036 | entry->edx = edx.full; | |
1037 | break; | |
1038 | } | |
a87f2d3a | 1039 | case 0x1f: |
74fa0bc7 | 1040 | case 0xb: |
a1a640b8 | 1041 | /* |
45e966fc PB |
1042 | * No topology; a valid topology is indicated by the presence |
1043 | * of subleaf 1. | |
a1a640b8 | 1044 | */ |
45e966fc | 1045 | entry->eax = entry->ebx = entry->ecx = 0; |
00b27a3e | 1046 | break; |
445ecdf7 | 1047 | case 0xd: { |
6be3ae45 | 1048 | u64 permitted_xcr0 = kvm_get_filtered_xcr0(); |
938c8745 | 1049 | u64 permitted_xss = kvm_caps.supported_xss; |
445ecdf7 | 1050 | |
1ffce092 LX |
1051 | entry->eax &= permitted_xcr0; |
1052 | entry->ebx = xstate_required_size(permitted_xcr0, false); | |
e08e8336 | 1053 | entry->ecx = entry->ebx; |
1ffce092 LX |
1054 | entry->edx &= permitted_xcr0 >> 32; |
1055 | if (!permitted_xcr0) | |
b65d6e17 PB |
1056 | break; |
1057 | ||
e53c95e8 SC |
1058 | entry = do_host_cpuid(array, function, 1); |
1059 | if (!entry) | |
3dc4a9cf SC |
1060 | goto out; |
1061 | ||
bd791999 | 1062 | cpuid_entry_override(entry, CPUID_D_1_EAX); |
e53c95e8 | 1063 | if (entry->eax & (F(XSAVES)|F(XSAVEC))) |
1ffce092 | 1064 | entry->ebx = xstate_required_size(permitted_xcr0 | permitted_xss, |
408e9a31 PB |
1065 | true); |
1066 | else { | |
1ffce092 | 1067 | WARN_ON_ONCE(permitted_xss != 0); |
e53c95e8 | 1068 | entry->ebx = 0; |
408e9a31 | 1069 | } |
1ffce092 LX |
1070 | entry->ecx &= permitted_xss; |
1071 | entry->edx &= permitted_xss >> 32; | |
3dc4a9cf | 1072 | |
0eee8f9d | 1073 | for (i = 2; i < 64; ++i) { |
408e9a31 | 1074 | bool s_state; |
1ffce092 | 1075 | if (permitted_xcr0 & BIT_ULL(i)) |
408e9a31 | 1076 | s_state = false; |
1ffce092 | 1077 | else if (permitted_xss & BIT_ULL(i)) |
408e9a31 PB |
1078 | s_state = true; |
1079 | else | |
1893c941 | 1080 | continue; |
3dc4a9cf | 1081 | |
0eee8f9d | 1082 | entry = do_host_cpuid(array, function, i); |
e53c95e8 | 1083 | if (!entry) |
831bf664 SL |
1084 | goto out; |
1085 | ||
91001d40 | 1086 | /* |
cfc48181 | 1087 | * The supported check above should have filtered out |
408e9a31 | 1088 | * invalid sub-leafs. Only valid sub-leafs should |
91001d40 | 1089 | * reach this point, and they should have a non-zero |
408e9a31 | 1090 | * save state size. Furthermore, check whether the |
1ffce092 | 1091 | * processor agrees with permitted_xcr0/permitted_xss |
408e9a31 | 1092 | * on whether this is an XCR0- or IA32_XSS-managed area. |
91001d40 | 1093 | */ |
408e9a31 | 1094 | if (WARN_ON_ONCE(!entry->eax || (entry->ecx & 0x1) != s_state)) { |
e53c95e8 | 1095 | --array->nent; |
3dc4a9cf | 1096 | continue; |
8b2fc445 | 1097 | } |
e9737468 LX |
1098 | |
1099 | if (!kvm_cpu_cap_has(X86_FEATURE_XFD)) | |
1100 | entry->ecx &= ~BIT_ULL(2); | |
e53c95e8 | 1101 | entry->edx = 0; |
00b27a3e AK |
1102 | } |
1103 | break; | |
445ecdf7 | 1104 | } |
72add915 SC |
1105 | case 0x12: |
1106 | /* Intel SGX */ | |
1107 | if (!kvm_cpu_cap_has(X86_FEATURE_SGX)) { | |
1108 | entry->eax = entry->ebx = entry->ecx = entry->edx = 0; | |
1109 | break; | |
1110 | } | |
1111 | ||
1112 | /* | |
1113 | * Index 0: Sub-features, MISCSELECT (a.k.a extended features) | |
1114 | * and max enclave sizes. The SGX sub-features and MISCSELECT | |
1115 | * are restricted by kernel and KVM capabilities (like most | |
1116 | * feature flags), while enclave size is unrestricted. | |
1117 | */ | |
1118 | cpuid_entry_override(entry, CPUID_12_EAX); | |
1119 | entry->ebx &= SGX_MISC_EXINFO; | |
1120 | ||
1121 | entry = do_host_cpuid(array, function, 1); | |
1122 | if (!entry) | |
1123 | goto out; | |
1124 | ||
1125 | /* | |
1126 | * Index 1: SECS.ATTRIBUTES. ATTRIBUTES are restricted a la | |
1127 | * feature flags. Advertise all supported flags, including | |
1128 | * privileged attributes that require explicit opt-in from | |
1129 | * userspace. ATTRIBUTES.XFRM is not adjusted as userspace is | |
1130 | * expected to derive it from supported XCR0. | |
1131 | */ | |
370839c2 | 1132 | entry->eax &= SGX_ATTR_PRIV_MASK | SGX_ATTR_UNPRIV_MASK; |
72add915 SC |
1133 | entry->ebx &= 0; |
1134 | break; | |
86f5201d | 1135 | /* Intel PT */ |
74fa0bc7 | 1136 | case 0x14: |
dd69cc25 | 1137 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) { |
7392079c | 1138 | entry->eax = entry->ebx = entry->ecx = entry->edx = 0; |
86f5201d | 1139 | break; |
7392079c | 1140 | } |
86f5201d | 1141 | |
74fa0bc7 | 1142 | for (i = 1, max_idx = entry->eax; i <= max_idx; ++i) { |
e53c95e8 | 1143 | if (!do_host_cpuid(array, function, i)) |
86f5201d | 1144 | goto out; |
86f5201d CP |
1145 | } |
1146 | break; | |
690a757d JL |
1147 | /* Intel AMX TILE */ |
1148 | case 0x1d: | |
1149 | if (!kvm_cpu_cap_has(X86_FEATURE_AMX_TILE)) { | |
1150 | entry->eax = entry->ebx = entry->ecx = entry->edx = 0; | |
1151 | break; | |
1152 | } | |
1153 | ||
1154 | for (i = 1, max_idx = entry->eax; i <= max_idx; ++i) { | |
1155 | if (!do_host_cpuid(array, function, i)) | |
1156 | goto out; | |
1157 | } | |
1158 | break; | |
1159 | case 0x1e: /* TMUL information */ | |
1160 | if (!kvm_cpu_cap_has(X86_FEATURE_AMX_TILE)) { | |
1161 | entry->eax = entry->ebx = entry->ecx = entry->edx = 0; | |
1162 | break; | |
1163 | } | |
1164 | break; | |
00b27a3e | 1165 | case KVM_CPUID_SIGNATURE: { |
760849b1 | 1166 | const u32 *sigptr = (const u32 *)KVM_SIGNATURE; |
57c22e5f | 1167 | entry->eax = KVM_CPUID_FEATURES; |
00b27a3e AK |
1168 | entry->ebx = sigptr[0]; |
1169 | entry->ecx = sigptr[1]; | |
1170 | entry->edx = sigptr[2]; | |
1171 | break; | |
1172 | } | |
1173 | case KVM_CPUID_FEATURES: | |
1174 | entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) | | |
1175 | (1 << KVM_FEATURE_NOP_IO_DELAY) | | |
1176 | (1 << KVM_FEATURE_CLOCKSOURCE2) | | |
1177 | (1 << KVM_FEATURE_ASYNC_PF) | | |
ae7a2a3f | 1178 | (1 << KVM_FEATURE_PV_EOI) | |
6aef266c | 1179 | (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT) | |
f38a7b75 | 1180 | (1 << KVM_FEATURE_PV_UNHALT) | |
fe2a3027 | 1181 | (1 << KVM_FEATURE_PV_TLB_FLUSH) | |
4180bf1b | 1182 | (1 << KVM_FEATURE_ASYNC_PF_VMEXIT) | |
2d5ba19b | 1183 | (1 << KVM_FEATURE_PV_SEND_IPI) | |
32b72ecc | 1184 | (1 << KVM_FEATURE_POLL_CONTROL) | |
72de5fa4 VK |
1185 | (1 << KVM_FEATURE_PV_SCHED_YIELD) | |
1186 | (1 << KVM_FEATURE_ASYNC_PF_INT); | |
00b27a3e AK |
1187 | |
1188 | if (sched_info_on()) | |
1189 | entry->eax |= (1 << KVM_FEATURE_STEAL_TIME); | |
1190 | ||
1191 | entry->ebx = 0; | |
1192 | entry->ecx = 0; | |
1193 | entry->edx = 0; | |
1194 | break; | |
1195 | case 0x80000000: | |
94cdeebd | 1196 | entry->eax = min(entry->eax, 0x80000022); |
f144c49e | 1197 | /* |
f751d8ea PB |
1198 | * Serializing LFENCE is reported in a multitude of ways, and |
1199 | * NullSegClearsBase is not reported in CPUID on Zen2; help | |
1200 | * userspace by providing the CPUID leaf ourselves. | |
1201 | * | |
1202 | * However, only do it if the host has CPUID leaf 0x8000001d. | |
1203 | * QEMU thinks that it can query the host blindly for that | |
1204 | * CPUID leaf if KVM reports that it supports 0x8000001d or | |
1205 | * above. The processor merrily returns values from the | |
1206 | * highest Intel leaf which QEMU tries to use as the guest's | |
1207 | * 0x8000001d. Even worse, this can result in an infinite | |
1208 | * loop if said highest leaf has no subleaves indexed by ECX. | |
f144c49e | 1209 | */ |
f751d8ea PB |
1210 | if (entry->eax >= 0x8000001d && |
1211 | (static_cpu_has(X86_FEATURE_LFENCE_RDTSC) | |
1212 | || !static_cpu_has_bug(X86_BUG_NULL_SEG))) | |
f144c49e | 1213 | entry->eax = max(entry->eax, 0x80000021); |
00b27a3e AK |
1214 | break; |
1215 | case 0x80000001: | |
0469e56a | 1216 | entry->ebx &= ~GENMASK(27, 16); |
bd791999 SC |
1217 | cpuid_entry_override(entry, CPUID_8000_0001_EDX); |
1218 | cpuid_entry_override(entry, CPUID_8000_0001_ECX); | |
00b27a3e | 1219 | break; |
af8e2ccf TI |
1220 | case 0x80000005: |
1221 | /* Pass host L1 cache and TLB info. */ | |
1222 | break; | |
43d05de2 | 1223 | case 0x80000006: |
eeb69eab JM |
1224 | /* Drop reserved bits, pass host L2 cache and TLB info. */ |
1225 | entry->edx &= ~GENMASK(17, 16); | |
43d05de2 | 1226 | break; |
e4c9a5a1 | 1227 | case 0x80000007: /* Advanced power management */ |
0fcf86f0 VK |
1228 | cpuid_entry_override(entry, CPUID_8000_0007_EDX); |
1229 | ||
e4c9a5a1 MT |
1230 | /* mask against host */ |
1231 | entry->edx &= boot_cpu_data.x86_power; | |
1232 | entry->eax = entry->ebx = entry->ecx = 0; | |
1233 | break; | |
00b27a3e AK |
1234 | case 0x80000008: { |
1235 | unsigned g_phys_as = (entry->eax >> 16) & 0xff; | |
1236 | unsigned virt_as = max((entry->eax >> 8) & 0xff, 48U); | |
1237 | unsigned phys_as = entry->eax & 0xff; | |
1238 | ||
4bf48e3c | 1239 | /* |
e39f00f6 SC |
1240 | * If TDP (NPT) is disabled use the adjusted host MAXPHYADDR as |
1241 | * the guest operates in the same PA space as the host, i.e. | |
1242 | * reductions in MAXPHYADDR for memory encryption affect shadow | |
1243 | * paging, too. | |
1244 | * | |
1245 | * If TDP is enabled but an explicit guest MAXPHYADDR is not | |
1246 | * provided, use the raw bare metal MAXPHYADDR as reductions to | |
1247 | * the HPAs do not affect GPAs. | |
4bf48e3c | 1248 | */ |
e39f00f6 SC |
1249 | if (!tdp_enabled) |
1250 | g_phys_as = boot_cpu_data.x86_phys_bits; | |
1251 | else if (!g_phys_as) | |
00b27a3e | 1252 | g_phys_as = phys_as; |
4bf48e3c | 1253 | |
00b27a3e | 1254 | entry->eax = g_phys_as | (virt_as << 8); |
7030d853 | 1255 | entry->ecx &= ~(GENMASK(31, 16) | GENMASK(11, 8)); |
15d45071 | 1256 | entry->edx = 0; |
bd791999 | 1257 | cpuid_entry_override(entry, CPUID_8000_0008_EBX); |
00b27a3e AK |
1258 | break; |
1259 | } | |
25703874 SC |
1260 | case 0x8000000A: |
1261 | if (!kvm_cpu_cap_has(X86_FEATURE_SVM)) { | |
1262 | entry->eax = entry->ebx = entry->ecx = entry->edx = 0; | |
1263 | break; | |
1264 | } | |
1265 | entry->eax = 1; /* SVM revision 1 */ | |
1266 | entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper | |
1267 | ASID emulation to nested SVM */ | |
1268 | entry->ecx = 0; /* Reserved */ | |
1269 | cpuid_entry_override(entry, CPUID_8000_000A_EDX); | |
1270 | break; | |
00b27a3e AK |
1271 | case 0x80000019: |
1272 | entry->ecx = entry->edx = 0; | |
1273 | break; | |
1274 | case 0x8000001a: | |
079f6889 JM |
1275 | entry->eax &= GENMASK(2, 0); |
1276 | entry->ebx = entry->ecx = entry->edx = 0; | |
1277 | break; | |
382409b4 | 1278 | case 0x8000001e: |
45e966fc PB |
1279 | /* Do not return host topology information. */ |
1280 | entry->eax = entry->ebx = entry->ecx = 0; | |
1281 | entry->edx = 0; /* reserved */ | |
00b27a3e | 1282 | break; |
c1de0f25 | 1283 | case 0x8000001F: |
e39f00f6 | 1284 | if (!kvm_cpu_cap_has(X86_FEATURE_SEV)) { |
c1de0f25 | 1285 | entry->eax = entry->ebx = entry->ecx = entry->edx = 0; |
e39f00f6 | 1286 | } else { |
d9db0fd6 | 1287 | cpuid_entry_override(entry, CPUID_8000_001F_EAX); |
86c4f0d5 JM |
1288 | /* Clear NumVMPL since KVM does not support VMPL. */ |
1289 | entry->ebx &= ~GENMASK(31, 12); | |
e39f00f6 SC |
1290 | /* |
1291 | * Enumerate '0' for "PA bits reduction", the adjusted | |
1292 | * MAXPHYADDR is enumerated directly (see 0x80000008). | |
1293 | */ | |
1294 | entry->ebx &= ~GENMASK(11, 6); | |
1295 | } | |
c1de0f25 | 1296 | break; |
58b3d12c PB |
1297 | case 0x80000020: |
1298 | entry->eax = entry->ebx = entry->ecx = entry->edx = 0; | |
1299 | break; | |
1300 | case 0x80000021: | |
1301 | entry->ebx = entry->ecx = entry->edx = 0; | |
c35ac8c4 | 1302 | cpuid_entry_override(entry, CPUID_8000_0021_EAX); |
58b3d12c | 1303 | break; |
94cdeebd LX |
1304 | /* AMD Extended Performance Monitoring and Debug */ |
1305 | case 0x80000022: { | |
1306 | union cpuid_0x80000022_ebx ebx; | |
1307 | ||
1308 | entry->ecx = entry->edx = 0; | |
1309 | if (!enable_pmu || !kvm_cpu_cap_has(X86_FEATURE_PERFMON_V2)) { | |
1310 | entry->eax = entry->ebx; | |
1311 | break; | |
1312 | } | |
1313 | ||
1314 | cpuid_entry_override(entry, CPUID_8000_0022_EAX); | |
1315 | ||
1316 | if (kvm_cpu_cap_has(X86_FEATURE_PERFMON_V2)) | |
1317 | ebx.split.num_core_pmc = kvm_pmu_cap.num_counters_gp; | |
1318 | else if (kvm_cpu_cap_has(X86_FEATURE_PERFCTR_CORE)) | |
1319 | ebx.split.num_core_pmc = AMD64_NUM_COUNTERS_CORE; | |
1320 | else | |
1321 | ebx.split.num_core_pmc = AMD64_NUM_COUNTERS; | |
1322 | ||
1323 | entry->ebx = ebx.full; | |
1324 | break; | |
1325 | } | |
00b27a3e AK |
1326 | /*Add support for Centaur's CPUID instruction*/ |
1327 | case 0xC0000000: | |
1328 | /*Just support up to 0xC0000004 now*/ | |
1329 | entry->eax = min(entry->eax, 0xC0000004); | |
1330 | break; | |
1331 | case 0xC0000001: | |
bd791999 | 1332 | cpuid_entry_override(entry, CPUID_C000_0001_EDX); |
00b27a3e AK |
1333 | break; |
1334 | case 3: /* Processor serial number */ | |
1335 | case 5: /* MONITOR/MWAIT */ | |
00b27a3e AK |
1336 | case 0xC0000002: |
1337 | case 0xC0000003: | |
1338 | case 0xC0000004: | |
1339 | default: | |
1340 | entry->eax = entry->ebx = entry->ecx = entry->edx = 0; | |
1341 | break; | |
1342 | } | |
1343 | ||
831bf664 SL |
1344 | r = 0; |
1345 | ||
1346 | out: | |
00b27a3e | 1347 | put_cpu(); |
831bf664 SL |
1348 | |
1349 | return r; | |
00b27a3e AK |
1350 | } |
1351 | ||
e53c95e8 SC |
1352 | static int do_cpuid_func(struct kvm_cpuid_array *array, u32 func, |
1353 | unsigned int type) | |
9c15bb1d BP |
1354 | { |
1355 | if (type == KVM_GET_EMULATED_CPUID) | |
e53c95e8 | 1356 | return __do_cpuid_func_emulated(array, func); |
9c15bb1d | 1357 | |
e53c95e8 | 1358 | return __do_cpuid_func(array, func); |
9c15bb1d BP |
1359 | } |
1360 | ||
8b86079c | 1361 | #define CENTAUR_CPUID_SIGNATURE 0xC0000000 |
831bf664 | 1362 | |
e53c95e8 SC |
1363 | static int get_cpuid_func(struct kvm_cpuid_array *array, u32 func, |
1364 | unsigned int type) | |
619a17f1 SC |
1365 | { |
1366 | u32 limit; | |
1367 | int r; | |
1368 | ||
8b86079c SC |
1369 | if (func == CENTAUR_CPUID_SIGNATURE && |
1370 | boot_cpu_data.x86_vendor != X86_VENDOR_CENTAUR) | |
1371 | return 0; | |
1372 | ||
e53c95e8 | 1373 | r = do_cpuid_func(array, func, type); |
619a17f1 SC |
1374 | if (r) |
1375 | return r; | |
1376 | ||
e53c95e8 | 1377 | limit = array->entries[array->nent - 1].eax; |
619a17f1 | 1378 | for (func = func + 1; func <= limit; ++func) { |
e53c95e8 | 1379 | r = do_cpuid_func(array, func, type); |
619a17f1 SC |
1380 | if (r) |
1381 | break; | |
1382 | } | |
1383 | ||
1384 | return r; | |
1385 | } | |
1386 | ||
9c15bb1d BP |
1387 | static bool sanity_check_entries(struct kvm_cpuid_entry2 __user *entries, |
1388 | __u32 num_entries, unsigned int ioctl_type) | |
1389 | { | |
1390 | int i; | |
1b2ca422 | 1391 | __u32 pad[3]; |
9c15bb1d BP |
1392 | |
1393 | if (ioctl_type != KVM_GET_EMULATED_CPUID) | |
1394 | return false; | |
1395 | ||
1396 | /* | |
1397 | * We want to make sure that ->padding is being passed clean from | |
1398 | * userspace in case we want to use it for something in the future. | |
1399 | * | |
1400 | * Sadly, this wasn't enforced for KVM_GET_SUPPORTED_CPUID and so we | |
1401 | * have to give ourselves satisfied only with the emulated side. /me | |
1402 | * sheds a tear. | |
1403 | */ | |
1404 | for (i = 0; i < num_entries; i++) { | |
1b2ca422 BP |
1405 | if (copy_from_user(pad, entries[i].padding, sizeof(pad))) |
1406 | return true; | |
1407 | ||
1408 | if (pad[0] || pad[1] || pad[2]) | |
9c15bb1d BP |
1409 | return true; |
1410 | } | |
1411 | return false; | |
1412 | } | |
1413 | ||
1414 | int kvm_dev_ioctl_get_cpuid(struct kvm_cpuid2 *cpuid, | |
1415 | struct kvm_cpuid_entry2 __user *entries, | |
1416 | unsigned int type) | |
00b27a3e | 1417 | { |
8b86079c SC |
1418 | static const u32 funcs[] = { |
1419 | 0, 0x80000000, CENTAUR_CPUID_SIGNATURE, KVM_CPUID_SIGNATURE, | |
831bf664 | 1420 | }; |
00b27a3e | 1421 | |
e53c95e8 SC |
1422 | struct kvm_cpuid_array array = { |
1423 | .nent = 0, | |
e53c95e8 SC |
1424 | }; |
1425 | int r, i; | |
d5a661d1 | 1426 | |
00b27a3e | 1427 | if (cpuid->nent < 1) |
d5a661d1 | 1428 | return -E2BIG; |
00b27a3e AK |
1429 | if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) |
1430 | cpuid->nent = KVM_MAX_CPUID_ENTRIES; | |
9c15bb1d BP |
1431 | |
1432 | if (sanity_check_entries(entries, cpuid->nent, type)) | |
1433 | return -EINVAL; | |
1434 | ||
8670866b | 1435 | array.entries = kvcalloc(cpuid->nent, sizeof(struct kvm_cpuid_entry2), GFP_KERNEL); |
e53c95e8 | 1436 | if (!array.entries) |
d5a661d1 | 1437 | return -ENOMEM; |
00b27a3e | 1438 | |
65b18914 XL |
1439 | array.maxnent = cpuid->nent; |
1440 | ||
8b86079c | 1441 | for (i = 0; i < ARRAY_SIZE(funcs); i++) { |
e53c95e8 | 1442 | r = get_cpuid_func(&array, funcs[i], type); |
831bf664 | 1443 | if (r) |
00b27a3e AK |
1444 | goto out_free; |
1445 | } | |
e53c95e8 | 1446 | cpuid->nent = array.nent; |
00b27a3e | 1447 | |
e53c95e8 SC |
1448 | if (copy_to_user(entries, array.entries, |
1449 | array.nent * sizeof(struct kvm_cpuid_entry2))) | |
d5a661d1 | 1450 | r = -EFAULT; |
00b27a3e AK |
1451 | |
1452 | out_free: | |
c9b8fecd | 1453 | kvfree(array.entries); |
00b27a3e AK |
1454 | return r; |
1455 | } | |
1456 | ||
277ad7d5 SC |
1457 | struct kvm_cpuid_entry2 *kvm_find_cpuid_entry_index(struct kvm_vcpu *vcpu, |
1458 | u32 function, u32 index) | |
00b27a3e | 1459 | { |
f69858fc VK |
1460 | return cpuid_entry2_find(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent, |
1461 | function, index); | |
00b27a3e | 1462 | } |
277ad7d5 SC |
1463 | EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry_index); |
1464 | ||
1465 | struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu, | |
1466 | u32 function) | |
1467 | { | |
1468 | return cpuid_entry2_find(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent, | |
1469 | function, KVM_CPUID_INDEX_NOT_SIGNIFICANT); | |
1470 | } | |
00b27a3e AK |
1471 | EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry); |
1472 | ||
00b27a3e | 1473 | /* |
8d892311 SC |
1474 | * Intel CPUID semantics treats any query for an out-of-range leaf as if the |
1475 | * highest basic leaf (i.e. CPUID.0H:EAX) were requested. AMD CPUID semantics | |
1476 | * returns all zeroes for any undefined leaf, whether or not the leaf is in | |
1477 | * range. Centaur/VIA follows Intel semantics. | |
1478 | * | |
1479 | * A leaf is considered out-of-range if its function is higher than the maximum | |
1480 | * supported leaf of its associated class or if its associated class does not | |
1481 | * exist. | |
1482 | * | |
1483 | * There are three primary classes to be considered, with their respective | |
1484 | * ranges described as "<base> - <top>[,<base2> - <top2>] inclusive. A primary | |
1485 | * class exists if a guest CPUID entry for its <base> leaf exists. For a given | |
1486 | * class, CPUID.<base>.EAX contains the max supported leaf for the class. | |
1487 | * | |
1488 | * - Basic: 0x00000000 - 0x3fffffff, 0x50000000 - 0x7fffffff | |
1489 | * - Hypervisor: 0x40000000 - 0x4fffffff | |
1490 | * - Extended: 0x80000000 - 0xbfffffff | |
1491 | * - Centaur: 0xc0000000 - 0xcfffffff | |
1492 | * | |
1493 | * The Hypervisor class is further subdivided into sub-classes that each act as | |
d9f6e12f | 1494 | * their own independent class associated with a 0x100 byte range. E.g. if Qemu |
8d892311 SC |
1495 | * is advertising support for both HyperV and KVM, the resulting Hypervisor |
1496 | * CPUID sub-classes are: | |
1497 | * | |
1498 | * - HyperV: 0x40000000 - 0x400000ff | |
1499 | * - KVM: 0x40000100 - 0x400001ff | |
00b27a3e | 1500 | */ |
09c7431e SC |
1501 | static struct kvm_cpuid_entry2 * |
1502 | get_out_of_range_cpuid_entry(struct kvm_vcpu *vcpu, u32 *fn_ptr, u32 index) | |
00b27a3e | 1503 | { |
8d892311 | 1504 | struct kvm_cpuid_entry2 *basic, *class; |
09c7431e | 1505 | u32 function = *fn_ptr; |
8d892311 | 1506 | |
277ad7d5 | 1507 | basic = kvm_find_cpuid_entry(vcpu, 0); |
8d892311 | 1508 | if (!basic) |
09c7431e SC |
1509 | return NULL; |
1510 | ||
1511 | if (is_guest_vendor_amd(basic->ebx, basic->ecx, basic->edx) || | |
1512 | is_guest_vendor_hygon(basic->ebx, basic->ecx, basic->edx)) | |
1513 | return NULL; | |
8d892311 SC |
1514 | |
1515 | if (function >= 0x40000000 && function <= 0x4fffffff) | |
277ad7d5 | 1516 | class = kvm_find_cpuid_entry(vcpu, function & 0xffffff00); |
8d892311 | 1517 | else if (function >= 0xc0000000) |
277ad7d5 | 1518 | class = kvm_find_cpuid_entry(vcpu, 0xc0000000); |
8d892311 | 1519 | else |
277ad7d5 | 1520 | class = kvm_find_cpuid_entry(vcpu, function & 0x80000000); |
43561123 | 1521 | |
09c7431e SC |
1522 | if (class && function <= class->eax) |
1523 | return NULL; | |
1524 | ||
1525 | /* | |
1526 | * Leaf specific adjustments are also applied when redirecting to the | |
1527 | * max basic entry, e.g. if the max basic leaf is 0xb but there is no | |
1528 | * entry for CPUID.0xb.index (see below), then the output value for EDX | |
1529 | * needs to be pulled from CPUID.0xb.1. | |
1530 | */ | |
1531 | *fn_ptr = basic->eax; | |
1532 | ||
1533 | /* | |
1534 | * The class does not exist or the requested function is out of range; | |
1535 | * the effective CPUID entry is the max basic leaf. Note, the index of | |
1536 | * the original requested leaf is observed! | |
1537 | */ | |
277ad7d5 | 1538 | return kvm_find_cpuid_entry_index(vcpu, basic->eax, index); |
00b27a3e AK |
1539 | } |
1540 | ||
e911eb3b | 1541 | bool kvm_cpuid(struct kvm_vcpu *vcpu, u32 *eax, u32 *ebx, |
f91af517 | 1542 | u32 *ecx, u32 *edx, bool exact_only) |
00b27a3e | 1543 | { |
b7fb8488 | 1544 | u32 orig_function = *eax, function = *eax, index = *ecx; |
43561123 | 1545 | struct kvm_cpuid_entry2 *entry; |
2b110b61 | 1546 | bool exact, used_max_basic = false; |
e911eb3b | 1547 | |
277ad7d5 | 1548 | entry = kvm_find_cpuid_entry_index(vcpu, function, index); |
f91af517 | 1549 | exact = !!entry; |
09c7431e | 1550 | |
2b110b61 | 1551 | if (!entry && !exact_only) { |
09c7431e | 1552 | entry = get_out_of_range_cpuid_entry(vcpu, &function, index); |
2b110b61 SC |
1553 | used_max_basic = !!entry; |
1554 | } | |
09c7431e | 1555 | |
43561123 JM |
1556 | if (entry) { |
1557 | *eax = entry->eax; | |
1558 | *ebx = entry->ebx; | |
1559 | *ecx = entry->ecx; | |
1560 | *edx = entry->edx; | |
edef5c36 PB |
1561 | if (function == 7 && index == 0) { |
1562 | u64 data; | |
1563 | if (!__kvm_get_msr(vcpu, MSR_IA32_TSX_CTRL, &data, true) && | |
1564 | (data & TSX_CTRL_CPUID_CLEAR)) | |
1565 | *ebx &= ~(F(RTM) | F(HLE)); | |
2be1bd3a VK |
1566 | } else if (function == 0x80000007) { |
1567 | if (kvm_hv_invtsc_suppressed(vcpu)) | |
1568 | *edx &= ~SF(CONSTANT_TSC); | |
edef5c36 | 1569 | } |
43561123 | 1570 | } else { |
62046e5a | 1571 | *eax = *ebx = *ecx = *edx = 0; |
43561123 JM |
1572 | /* |
1573 | * When leaf 0BH or 1FH is defined, CL is pass-through | |
1574 | * and EDX is always the x2APIC ID, even for undefined | |
1575 | * subleaves. Index 1 will exist iff the leaf is | |
1576 | * implemented, so we pass through CL iff leaf 1 | |
1577 | * exists. EDX can be copied from any existing index. | |
1578 | */ | |
1579 | if (function == 0xb || function == 0x1f) { | |
277ad7d5 | 1580 | entry = kvm_find_cpuid_entry_index(vcpu, function, 1); |
43561123 JM |
1581 | if (entry) { |
1582 | *ecx = index & 0xff; | |
1583 | *edx = entry->edx; | |
1584 | } | |
1585 | } | |
1586 | } | |
2b110b61 SC |
1587 | trace_kvm_cpuid(orig_function, index, *eax, *ebx, *ecx, *edx, exact, |
1588 | used_max_basic); | |
f91af517 | 1589 | return exact; |
62046e5a | 1590 | } |
66f7b72e | 1591 | EXPORT_SYMBOL_GPL(kvm_cpuid); |
62046e5a | 1592 | |
6a908b62 | 1593 | int kvm_emulate_cpuid(struct kvm_vcpu *vcpu) |
62046e5a | 1594 | { |
1e13175b | 1595 | u32 eax, ebx, ecx, edx; |
62046e5a | 1596 | |
db2336a8 KH |
1597 | if (cpuid_fault_enabled(vcpu) && !kvm_require_cpl(vcpu, 0)) |
1598 | return 1; | |
1599 | ||
de3cd117 SC |
1600 | eax = kvm_rax_read(vcpu); |
1601 | ecx = kvm_rcx_read(vcpu); | |
f91af517 | 1602 | kvm_cpuid(vcpu, &eax, &ebx, &ecx, &edx, false); |
de3cd117 SC |
1603 | kvm_rax_write(vcpu, eax); |
1604 | kvm_rbx_write(vcpu, ebx); | |
1605 | kvm_rcx_write(vcpu, ecx); | |
1606 | kvm_rdx_write(vcpu, edx); | |
6affcbed | 1607 | return kvm_skip_emulated_instruction(vcpu); |
00b27a3e AK |
1608 | } |
1609 | EXPORT_SYMBOL_GPL(kvm_emulate_cpuid); |