Commit | Line | Data |
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20c8ccb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
00b27a3e AK |
2 | /* |
3 | * Kernel-based Virtual Machine driver for Linux | |
4 | * cpuid support routines | |
5 | * | |
6 | * derived from arch/x86/kvm/x86.c | |
7 | * | |
8 | * Copyright 2011 Red Hat, Inc. and/or its affiliates. | |
9 | * Copyright IBM Corporation, 2008 | |
00b27a3e AK |
10 | */ |
11 | ||
12 | #include <linux/kvm_host.h> | |
1767e931 | 13 | #include <linux/export.h> |
bb5a798a JK |
14 | #include <linux/vmalloc.h> |
15 | #include <linux/uaccess.h> | |
3905f9ad IM |
16 | #include <linux/sched/stat.h> |
17 | ||
4504b5c9 | 18 | #include <asm/processor.h> |
00b27a3e | 19 | #include <asm/user.h> |
669ebabb | 20 | #include <asm/fpu/xstate.h> |
00b27a3e AK |
21 | #include "cpuid.h" |
22 | #include "lapic.h" | |
23 | #include "mmu.h" | |
24 | #include "trace.h" | |
474a5bb9 | 25 | #include "pmu.h" |
00b27a3e | 26 | |
66a6950f SC |
27 | /* |
28 | * Unlike "struct cpuinfo_x86.x86_capability", kvm_cpu_caps doesn't need to be | |
29 | * aligned to sizeof(unsigned long) because it's not accessed via bitops. | |
30 | */ | |
31 | u32 kvm_cpu_caps[NCAPINTS] __read_mostly; | |
32 | EXPORT_SYMBOL_GPL(kvm_cpu_caps); | |
33 | ||
412a3c41 | 34 | static u32 xstate_required_size(u64 xstate_bv, bool compacted) |
4344ee98 PB |
35 | { |
36 | int feature_bit = 0; | |
37 | u32 ret = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; | |
38 | ||
d91cab78 | 39 | xstate_bv &= XFEATURE_MASK_EXTEND; |
4344ee98 PB |
40 | while (xstate_bv) { |
41 | if (xstate_bv & 0x1) { | |
412a3c41 | 42 | u32 eax, ebx, ecx, edx, offset; |
4344ee98 | 43 | cpuid_count(0xD, feature_bit, &eax, &ebx, &ecx, &edx); |
412a3c41 PB |
44 | offset = compacted ? ret : ebx; |
45 | ret = max(ret, offset + eax); | |
4344ee98 PB |
46 | } |
47 | ||
48 | xstate_bv >>= 1; | |
49 | feature_bit++; | |
50 | } | |
51 | ||
52 | return ret; | |
53 | } | |
54 | ||
87382003 | 55 | #define F feature_bit |
5c404cab | 56 | |
dd598091 | 57 | int kvm_update_cpuid(struct kvm_vcpu *vcpu) |
00b27a3e AK |
58 | { |
59 | struct kvm_cpuid_entry2 *best; | |
60 | struct kvm_lapic *apic = vcpu->arch.apic; | |
61 | ||
62 | best = kvm_find_cpuid_entry(vcpu, 1, 0); | |
63 | if (!best) | |
dd598091 | 64 | return 0; |
00b27a3e AK |
65 | |
66 | /* Update OSXSAVE bit */ | |
b32666b1 SC |
67 | if (boot_cpu_has(X86_FEATURE_XSAVE) && best->function == 0x1) |
68 | cpuid_entry_change(best, X86_FEATURE_OSXSAVE, | |
69 | kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)); | |
00b27a3e | 70 | |
b32666b1 SC |
71 | cpuid_entry_change(best, X86_FEATURE_APIC, |
72 | vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE); | |
c7dd15b3 | 73 | |
00b27a3e | 74 | if (apic) { |
4c61534a | 75 | if (cpuid_entry_has(best, X86_FEATURE_TSC_DEADLINE_TIMER)) |
00b27a3e AK |
76 | apic->lapic_timer.timer_mode_mask = 3 << 17; |
77 | else | |
78 | apic->lapic_timer.timer_mode_mask = 1 << 17; | |
79 | } | |
f5132b01 | 80 | |
b9baba86 | 81 | best = kvm_find_cpuid_entry(vcpu, 7, 0); |
b32666b1 SC |
82 | if (best && boot_cpu_has(X86_FEATURE_PKU) && best->function == 0x7) |
83 | cpuid_entry_change(best, X86_FEATURE_OSPKE, | |
84 | kvm_read_cr4_bits(vcpu, X86_CR4_PKE)); | |
b9baba86 | 85 | |
d7876f1b | 86 | best = kvm_find_cpuid_entry(vcpu, 0xD, 0); |
4344ee98 | 87 | if (!best) { |
d7876f1b | 88 | vcpu->arch.guest_supported_xcr0 = 0; |
4344ee98 | 89 | } else { |
d7876f1b | 90 | vcpu->arch.guest_supported_xcr0 = |
cfc48181 | 91 | (best->eax | ((u64)best->edx << 32)) & supported_xcr0; |
a71936ab | 92 | best->ebx = xstate_required_size(vcpu->arch.xcr0, false); |
4344ee98 | 93 | } |
d7876f1b | 94 | |
412a3c41 | 95 | best = kvm_find_cpuid_entry(vcpu, 0xD, 1); |
4c61534a SC |
96 | if (best && (cpuid_entry_has(best, X86_FEATURE_XSAVES) || |
97 | cpuid_entry_has(best, X86_FEATURE_XSAVEC))) | |
412a3c41 PB |
98 | best->ebx = xstate_required_size(vcpu->arch.xcr0, true); |
99 | ||
dd598091 | 100 | /* |
fd8cb433 YZ |
101 | * The existing code assumes virtual address is 48-bit or 57-bit in the |
102 | * canonical address checks; exit if it is ever changed. | |
dd598091 NA |
103 | */ |
104 | best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0); | |
fd8cb433 YZ |
105 | if (best) { |
106 | int vaddr_bits = (best->eax & 0xff00) >> 8; | |
107 | ||
108 | if (vaddr_bits != 48 && vaddr_bits != 57 && vaddr_bits != 0) | |
109 | return -EINVAL; | |
110 | } | |
dd598091 | 111 | |
caa057a2 WL |
112 | best = kvm_find_cpuid_entry(vcpu, KVM_CPUID_FEATURES, 0); |
113 | if (kvm_hlt_in_guest(vcpu->kvm) && best && | |
114 | (best->eax & (1 << KVM_FEATURE_PV_UNHALT))) | |
115 | best->eax &= ~(1 << KVM_FEATURE_PV_UNHALT); | |
116 | ||
511a8556 WL |
117 | if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT)) { |
118 | best = kvm_find_cpuid_entry(vcpu, 0x1, 0); | |
b32666b1 SC |
119 | if (best) |
120 | cpuid_entry_change(best, X86_FEATURE_MWAIT, | |
121 | vcpu->arch.ia32_misc_enable_msr & | |
122 | MSR_IA32_MISC_ENABLE_MWAIT); | |
511a8556 WL |
123 | } |
124 | ||
e93fd3b3 | 125 | /* Note, maxphyaddr must be updated before tdp_level. */ |
5a4f55cd | 126 | vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); |
e93fd3b3 | 127 | vcpu->arch.tdp_level = kvm_x86_ops.get_tdp_level(vcpu); |
855feb67 | 128 | kvm_mmu_reset_context(vcpu); |
5a4f55cd | 129 | |
c6702c9d | 130 | kvm_pmu_refresh(vcpu); |
dd598091 | 131 | return 0; |
00b27a3e AK |
132 | } |
133 | ||
134 | static int is_efer_nx(void) | |
135 | { | |
91661989 | 136 | return host_efer & EFER_NX; |
00b27a3e AK |
137 | } |
138 | ||
139 | static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu) | |
140 | { | |
141 | int i; | |
142 | struct kvm_cpuid_entry2 *e, *entry; | |
143 | ||
144 | entry = NULL; | |
145 | for (i = 0; i < vcpu->arch.cpuid_nent; ++i) { | |
146 | e = &vcpu->arch.cpuid_entries[i]; | |
147 | if (e->function == 0x80000001) { | |
148 | entry = e; | |
149 | break; | |
150 | } | |
151 | } | |
4c61534a | 152 | if (entry && cpuid_entry_has(entry, X86_FEATURE_NX) && !is_efer_nx()) { |
b32666b1 | 153 | cpuid_entry_clear(entry, X86_FEATURE_NX); |
00b27a3e AK |
154 | printk(KERN_INFO "kvm: guest NX capability removed\n"); |
155 | } | |
156 | } | |
157 | ||
5a4f55cd EK |
158 | int cpuid_query_maxphyaddr(struct kvm_vcpu *vcpu) |
159 | { | |
160 | struct kvm_cpuid_entry2 *best; | |
161 | ||
162 | best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0); | |
163 | if (!best || best->eax < 0x80000008) | |
164 | goto not_found; | |
165 | best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0); | |
166 | if (best) | |
167 | return best->eax & 0xff; | |
168 | not_found: | |
169 | return 36; | |
170 | } | |
171 | EXPORT_SYMBOL_GPL(cpuid_query_maxphyaddr); | |
172 | ||
00b27a3e AK |
173 | /* when an old userspace process fills a new kernel module */ |
174 | int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu, | |
175 | struct kvm_cpuid *cpuid, | |
176 | struct kvm_cpuid_entry __user *entries) | |
177 | { | |
178 | int r, i; | |
83676e92 | 179 | struct kvm_cpuid_entry *cpuid_entries = NULL; |
00b27a3e AK |
180 | |
181 | r = -E2BIG; | |
182 | if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) | |
183 | goto out; | |
83676e92 | 184 | if (cpuid->nent) { |
7ec28e26 DE |
185 | cpuid_entries = vmemdup_user(entries, |
186 | array_size(sizeof(struct kvm_cpuid_entry), | |
187 | cpuid->nent)); | |
188 | if (IS_ERR(cpuid_entries)) { | |
189 | r = PTR_ERR(cpuid_entries); | |
83676e92 | 190 | goto out; |
7ec28e26 | 191 | } |
83676e92 | 192 | } |
00b27a3e AK |
193 | for (i = 0; i < cpuid->nent; i++) { |
194 | vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function; | |
195 | vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax; | |
196 | vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx; | |
197 | vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx; | |
198 | vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx; | |
199 | vcpu->arch.cpuid_entries[i].index = 0; | |
200 | vcpu->arch.cpuid_entries[i].flags = 0; | |
201 | vcpu->arch.cpuid_entries[i].padding[0] = 0; | |
202 | vcpu->arch.cpuid_entries[i].padding[1] = 0; | |
203 | vcpu->arch.cpuid_entries[i].padding[2] = 0; | |
204 | } | |
205 | vcpu->arch.cpuid_nent = cpuid->nent; | |
206 | cpuid_fix_nx_cap(vcpu); | |
00b27a3e | 207 | kvm_apic_set_version(vcpu); |
afaf0b2f | 208 | kvm_x86_ops.cpuid_update(vcpu); |
dd598091 | 209 | r = kvm_update_cpuid(vcpu); |
00b27a3e | 210 | |
7ec28e26 | 211 | kvfree(cpuid_entries); |
00b27a3e AK |
212 | out: |
213 | return r; | |
214 | } | |
215 | ||
216 | int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu, | |
217 | struct kvm_cpuid2 *cpuid, | |
218 | struct kvm_cpuid_entry2 __user *entries) | |
219 | { | |
220 | int r; | |
221 | ||
222 | r = -E2BIG; | |
223 | if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) | |
224 | goto out; | |
225 | r = -EFAULT; | |
226 | if (copy_from_user(&vcpu->arch.cpuid_entries, entries, | |
227 | cpuid->nent * sizeof(struct kvm_cpuid_entry2))) | |
228 | goto out; | |
229 | vcpu->arch.cpuid_nent = cpuid->nent; | |
230 | kvm_apic_set_version(vcpu); | |
afaf0b2f | 231 | kvm_x86_ops.cpuid_update(vcpu); |
dd598091 | 232 | r = kvm_update_cpuid(vcpu); |
00b27a3e AK |
233 | out: |
234 | return r; | |
235 | } | |
236 | ||
237 | int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu, | |
238 | struct kvm_cpuid2 *cpuid, | |
239 | struct kvm_cpuid_entry2 __user *entries) | |
240 | { | |
241 | int r; | |
242 | ||
243 | r = -E2BIG; | |
244 | if (cpuid->nent < vcpu->arch.cpuid_nent) | |
245 | goto out; | |
246 | r = -EFAULT; | |
247 | if (copy_to_user(entries, &vcpu->arch.cpuid_entries, | |
248 | vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2))) | |
249 | goto out; | |
250 | return 0; | |
251 | ||
252 | out: | |
253 | cpuid->nent = vcpu->arch.cpuid_nent; | |
254 | return r; | |
255 | } | |
256 | ||
66a6950f SC |
257 | static __always_inline void kvm_cpu_cap_mask(enum cpuid_leafs leaf, u32 mask) |
258 | { | |
d8577a4c SC |
259 | const struct cpuid_reg cpuid = x86_feature_cpuid(leaf * 32); |
260 | struct kvm_cpuid_entry2 entry; | |
261 | ||
66a6950f SC |
262 | reverse_cpuid_check(leaf); |
263 | kvm_cpu_caps[leaf] &= mask; | |
d8577a4c SC |
264 | |
265 | cpuid_count(cpuid.function, cpuid.index, | |
266 | &entry.eax, &entry.ebx, &entry.ecx, &entry.edx); | |
267 | ||
855c7e9b | 268 | kvm_cpu_caps[leaf] &= *__cpuid_entry_get_reg(&entry, cpuid.reg); |
66a6950f SC |
269 | } |
270 | ||
271 | void kvm_set_cpu_caps(void) | |
272 | { | |
273 | unsigned int f_nx = is_efer_nx() ? F(NX) : 0; | |
274 | #ifdef CONFIG_X86_64 | |
275 | unsigned int f_gbpages = F(GBPAGES); | |
276 | unsigned int f_lm = F(LM); | |
277 | #else | |
278 | unsigned int f_gbpages = 0; | |
279 | unsigned int f_lm = 0; | |
280 | #endif | |
281 | ||
282 | BUILD_BUG_ON(sizeof(kvm_cpu_caps) > | |
283 | sizeof(boot_cpu_data.x86_capability)); | |
284 | ||
285 | memcpy(&kvm_cpu_caps, &boot_cpu_data.x86_capability, | |
286 | sizeof(kvm_cpu_caps)); | |
287 | ||
288 | kvm_cpu_cap_mask(CPUID_1_ECX, | |
289 | /* | |
290 | * NOTE: MONITOR (and MWAIT) are emulated as NOP, but *not* | |
291 | * advertised to guests via CPUID! | |
292 | */ | |
293 | F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ | | |
294 | 0 /* DS-CPL, VMX, SMX, EST */ | | |
295 | 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ | | |
27461da3 | 296 | F(FMA) | F(CX16) | 0 /* xTPR Update */ | F(PDCM) | |
66a6950f SC |
297 | F(PCID) | 0 /* Reserved, DCA */ | F(XMM4_1) | |
298 | F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) | | |
299 | 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) | | |
300 | F(F16C) | F(RDRAND) | |
301 | ); | |
93c380e7 SC |
302 | /* KVM emulates x2apic in software irrespective of host support. */ |
303 | kvm_cpu_cap_set(X86_FEATURE_X2APIC); | |
66a6950f SC |
304 | |
305 | kvm_cpu_cap_mask(CPUID_1_EDX, | |
306 | F(FPU) | F(VME) | F(DE) | F(PSE) | | |
307 | F(TSC) | F(MSR) | F(PAE) | F(MCE) | | |
308 | F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) | | |
309 | F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | | |
310 | F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLUSH) | | |
311 | 0 /* Reserved, DS, ACPI */ | F(MMX) | | |
312 | F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) | | |
313 | 0 /* HTT, TM, Reserved, PBE */ | |
314 | ); | |
315 | ||
316 | kvm_cpu_cap_mask(CPUID_7_0_EBX, | |
317 | F(FSGSBASE) | F(BMI1) | F(HLE) | F(AVX2) | F(SMEP) | | |
318 | F(BMI2) | F(ERMS) | 0 /*INVPCID*/ | F(RTM) | 0 /*MPX*/ | F(RDSEED) | | |
319 | F(ADX) | F(SMAP) | F(AVX512IFMA) | F(AVX512F) | F(AVX512PF) | | |
320 | F(AVX512ER) | F(AVX512CD) | F(CLFLUSHOPT) | F(CLWB) | F(AVX512DQ) | | |
321 | F(SHA_NI) | F(AVX512BW) | F(AVX512VL) | 0 /*INTEL_PT*/ | |
322 | ); | |
323 | ||
324 | kvm_cpu_cap_mask(CPUID_7_ECX, | |
fa44b82e | 325 | F(AVX512VBMI) | F(LA57) | F(PKU) | 0 /*OSPKE*/ | F(RDPID) | |
66a6950f SC |
326 | F(AVX512_VPOPCNTDQ) | F(UMIP) | F(AVX512_VBMI2) | F(GFNI) | |
327 | F(VAES) | F(VPCLMULQDQ) | F(AVX512_VNNI) | F(AVX512_BITALG) | | |
328 | F(CLDEMOTE) | F(MOVDIRI) | F(MOVDIR64B) | 0 /*WAITPKG*/ | |
329 | ); | |
330 | /* Set LA57 based on hardware capability. */ | |
331 | if (cpuid_ecx(7) & F(LA57)) | |
332 | kvm_cpu_cap_set(X86_FEATURE_LA57); | |
333 | ||
fa44b82e BM |
334 | /* |
335 | * PKU not yet implemented for shadow paging and requires OSPKE | |
336 | * to be set on the host. Clear it if that is not the case | |
337 | */ | |
338 | if (!tdp_enabled || !boot_cpu_has(X86_FEATURE_OSPKE)) | |
339 | kvm_cpu_cap_clear(X86_FEATURE_PKU); | |
340 | ||
66a6950f SC |
341 | kvm_cpu_cap_mask(CPUID_7_EDX, |
342 | F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) | | |
343 | F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) | | |
e3747407 | 344 | F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) |
66a6950f SC |
345 | ); |
346 | ||
93c380e7 SC |
347 | /* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */ |
348 | kvm_cpu_cap_set(X86_FEATURE_TSC_ADJUST); | |
349 | kvm_cpu_cap_set(X86_FEATURE_ARCH_CAPABILITIES); | |
350 | ||
351 | if (boot_cpu_has(X86_FEATURE_IBPB) && boot_cpu_has(X86_FEATURE_IBRS)) | |
352 | kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL); | |
353 | if (boot_cpu_has(X86_FEATURE_STIBP)) | |
354 | kvm_cpu_cap_set(X86_FEATURE_INTEL_STIBP); | |
355 | if (boot_cpu_has(X86_FEATURE_AMD_SSBD)) | |
356 | kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD); | |
357 | ||
66a6950f SC |
358 | kvm_cpu_cap_mask(CPUID_7_1_EAX, |
359 | F(AVX512_BF16) | |
360 | ); | |
361 | ||
362 | kvm_cpu_cap_mask(CPUID_D_1_EAX, | |
363 | F(XSAVEOPT) | F(XSAVEC) | F(XGETBV1) | F(XSAVES) | |
364 | ); | |
365 | ||
366 | kvm_cpu_cap_mask(CPUID_8000_0001_ECX, | |
367 | F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ | | |
368 | F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) | | |
369 | F(3DNOWPREFETCH) | F(OSVW) | 0 /* IBS */ | F(XOP) | | |
370 | 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM) | | |
371 | F(TOPOEXT) | F(PERFCTR_CORE) | |
372 | ); | |
373 | ||
374 | kvm_cpu_cap_mask(CPUID_8000_0001_EDX, | |
375 | F(FPU) | F(VME) | F(DE) | F(PSE) | | |
376 | F(TSC) | F(MSR) | F(PAE) | F(MCE) | | |
377 | F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) | | |
378 | F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | | |
379 | F(PAT) | F(PSE36) | 0 /* Reserved */ | | |
380 | f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) | | |
381 | F(FXSR) | F(FXSR_OPT) | f_gbpages | F(RDTSCP) | | |
382 | 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW) | |
383 | ); | |
384 | ||
385 | if (!tdp_enabled && IS_ENABLED(CONFIG_X86_64)) | |
386 | kvm_cpu_cap_set(X86_FEATURE_GBPAGES); | |
387 | ||
388 | kvm_cpu_cap_mask(CPUID_8000_0008_EBX, | |
389 | F(CLZERO) | F(XSAVEERPTR) | | |
390 | F(WBNOINVD) | F(AMD_IBPB) | F(AMD_IBRS) | F(AMD_SSBD) | F(VIRT_SSBD) | | |
391 | F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_STIBP_ALWAYS_ON) | |
392 | ); | |
393 | ||
93c380e7 SC |
394 | /* |
395 | * AMD has separate bits for each SPEC_CTRL bit. | |
396 | * arch/x86/kernel/cpu/bugs.c is kind enough to | |
397 | * record that in cpufeatures so use them. | |
398 | */ | |
399 | if (boot_cpu_has(X86_FEATURE_IBPB)) | |
400 | kvm_cpu_cap_set(X86_FEATURE_AMD_IBPB); | |
401 | if (boot_cpu_has(X86_FEATURE_IBRS)) | |
402 | kvm_cpu_cap_set(X86_FEATURE_AMD_IBRS); | |
403 | if (boot_cpu_has(X86_FEATURE_STIBP)) | |
404 | kvm_cpu_cap_set(X86_FEATURE_AMD_STIBP); | |
405 | if (boot_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD)) | |
406 | kvm_cpu_cap_set(X86_FEATURE_AMD_SSBD); | |
407 | if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
408 | kvm_cpu_cap_set(X86_FEATURE_AMD_SSB_NO); | |
409 | /* | |
410 | * The preference is to use SPEC CTRL MSR instead of the | |
411 | * VIRT_SPEC MSR. | |
412 | */ | |
413 | if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) && | |
414 | !boot_cpu_has(X86_FEATURE_AMD_SSBD)) | |
415 | kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD); | |
416 | ||
9b58b985 SC |
417 | /* |
418 | * Hide all SVM features by default, SVM will set the cap bits for | |
419 | * features it emulates and/or exposes for L1. | |
420 | */ | |
421 | kvm_cpu_cap_mask(CPUID_8000_000A_EDX, 0); | |
422 | ||
66a6950f SC |
423 | kvm_cpu_cap_mask(CPUID_C000_0001_EDX, |
424 | F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) | | |
425 | F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) | | |
426 | F(PMM) | F(PMM_EN) | |
427 | ); | |
428 | } | |
429 | EXPORT_SYMBOL_GPL(kvm_set_cpu_caps); | |
430 | ||
e53c95e8 SC |
431 | struct kvm_cpuid_array { |
432 | struct kvm_cpuid_entry2 *entries; | |
65b18914 | 433 | int maxnent; |
e53c95e8 SC |
434 | int nent; |
435 | }; | |
436 | ||
437 | static struct kvm_cpuid_entry2 *do_host_cpuid(struct kvm_cpuid_array *array, | |
aa10a7dc | 438 | u32 function, u32 index) |
00b27a3e | 439 | { |
e53c95e8 SC |
440 | struct kvm_cpuid_entry2 *entry; |
441 | ||
442 | if (array->nent >= array->maxnent) | |
aa10a7dc | 443 | return NULL; |
e53c95e8 SC |
444 | |
445 | entry = &array->entries[array->nent++]; | |
aa10a7dc | 446 | |
00b27a3e AK |
447 | entry->function = function; |
448 | entry->index = index; | |
ab8bcf64 PB |
449 | entry->flags = 0; |
450 | ||
00b27a3e AK |
451 | cpuid_count(entry->function, entry->index, |
452 | &entry->eax, &entry->ebx, &entry->ecx, &entry->edx); | |
d9aadaf6 PB |
453 | |
454 | switch (function) { | |
d9aadaf6 PB |
455 | case 4: |
456 | case 7: | |
457 | case 0xb: | |
458 | case 0xd: | |
a06dcd62 JM |
459 | case 0xf: |
460 | case 0x10: | |
461 | case 0x12: | |
d9aadaf6 | 462 | case 0x14: |
a06dcd62 JM |
463 | case 0x17: |
464 | case 0x18: | |
465 | case 0x1f: | |
d9aadaf6 PB |
466 | case 0x8000001d: |
467 | entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
468 | break; | |
469 | } | |
aa10a7dc SC |
470 | |
471 | return entry; | |
00b27a3e AK |
472 | } |
473 | ||
e53c95e8 | 474 | static int __do_cpuid_func_emulated(struct kvm_cpuid_array *array, u32 func) |
9c15bb1d | 475 | { |
7c7f9548 SC |
476 | struct kvm_cpuid_entry2 *entry; |
477 | ||
478 | if (array->nent >= array->maxnent) | |
479 | return -E2BIG; | |
e53c95e8 | 480 | |
7c7f9548 | 481 | entry = &array->entries[array->nent]; |
ab8bcf64 PB |
482 | entry->function = func; |
483 | entry->index = 0; | |
484 | entry->flags = 0; | |
485 | ||
84cffe49 BP |
486 | switch (func) { |
487 | case 0: | |
fb6d4d34 | 488 | entry->eax = 7; |
e53c95e8 | 489 | ++array->nent; |
84cffe49 BP |
490 | break; |
491 | case 1: | |
492 | entry->ecx = F(MOVBE); | |
e53c95e8 | 493 | ++array->nent; |
84cffe49 | 494 | break; |
fb6d4d34 PB |
495 | case 7: |
496 | entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
ab8bcf64 PB |
497 | entry->eax = 0; |
498 | entry->ecx = F(RDPID); | |
e53c95e8 | 499 | ++array->nent; |
84cffe49 BP |
500 | default: |
501 | break; | |
502 | } | |
503 | ||
9c15bb1d BP |
504 | return 0; |
505 | } | |
506 | ||
e53c95e8 | 507 | static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) |
00b27a3e | 508 | { |
e53c95e8 | 509 | struct kvm_cpuid_entry2 *entry; |
74fa0bc7 | 510 | int r, i, max_idx; |
00b27a3e | 511 | |
00b27a3e AK |
512 | /* all calls to cpuid_count() should be made on the same cpu */ |
513 | get_cpu(); | |
831bf664 SL |
514 | |
515 | r = -E2BIG; | |
516 | ||
e53c95e8 | 517 | entry = do_host_cpuid(array, function, 0); |
7c7f9548 | 518 | if (!entry) |
831bf664 SL |
519 | goto out; |
520 | ||
00b27a3e AK |
521 | switch (function) { |
522 | case 0: | |
a87f2d3a LX |
523 | /* Limited to the highest leaf implemented in KVM. */ |
524 | entry->eax = min(entry->eax, 0x1fU); | |
00b27a3e AK |
525 | break; |
526 | case 1: | |
bd791999 SC |
527 | cpuid_entry_override(entry, CPUID_1_EDX); |
528 | cpuid_entry_override(entry, CPUID_1_ECX); | |
00b27a3e | 529 | break; |
74fa0bc7 | 530 | case 2: |
c571a144 SC |
531 | /* |
532 | * On ancient CPUs, function 2 entries are STATEFUL. That is, | |
533 | * CPUID(function=2, index=0) may return different results each | |
534 | * time, with the least-significant byte in EAX enumerating the | |
535 | * number of times software should do CPUID(2, 0). | |
536 | * | |
7ff6c035 SC |
537 | * Modern CPUs, i.e. every CPU KVM has *ever* run on are less |
538 | * idiotic. Intel's SDM states that EAX & 0xff "will always | |
539 | * return 01H. Software should ignore this value and not | |
c571a144 SC |
540 | * interpret it as an informational descriptor", while AMD's |
541 | * APM states that CPUID(2) is reserved. | |
7ff6c035 SC |
542 | * |
543 | * WARN if a frankenstein CPU that supports virtualization and | |
544 | * a stateful CPUID.0x2 is encountered. | |
c571a144 | 545 | */ |
7ff6c035 | 546 | WARN_ON_ONCE((entry->eax & 0xff) > 1); |
00b27a3e | 547 | break; |
32a243df JM |
548 | /* functions 4 and 0x8000001d have additional index. */ |
549 | case 4: | |
c8629039 SC |
550 | case 0x8000001d: |
551 | /* | |
552 | * Read entries until the cache type in the previous entry is | |
553 | * zero, i.e. indicates an invalid entry. | |
554 | */ | |
e53c95e8 SC |
555 | for (i = 1; entry->eax & 0x1f; ++i) { |
556 | entry = do_host_cpuid(array, function, i); | |
557 | if (!entry) | |
0fc62671 | 558 | goto out; |
00b27a3e AK |
559 | } |
560 | break; | |
e453aa0f JK |
561 | case 6: /* Thermal management */ |
562 | entry->eax = 0x4; /* allow ARAT */ | |
563 | entry->ebx = 0; | |
564 | entry->ecx = 0; | |
565 | entry->edx = 0; | |
566 | break; | |
54d360d4 | 567 | /* function 7 has additional index. */ |
74fa0bc7 | 568 | case 7: |
09f628a0 | 569 | entry->eax = min(entry->eax, 1u); |
bd791999 SC |
570 | cpuid_entry_override(entry, CPUID_7_0_EBX); |
571 | cpuid_entry_override(entry, CPUID_7_ECX); | |
572 | cpuid_entry_override(entry, CPUID_7_EDX); | |
09f628a0 | 573 | |
bcf600ca SC |
574 | /* KVM only supports 0x7.0 and 0x7.1, capped above via min(). */ |
575 | if (entry->eax == 1) { | |
576 | entry = do_host_cpuid(array, function, 1); | |
e53c95e8 | 577 | if (!entry) |
54d360d4 PB |
578 | goto out; |
579 | ||
bd791999 | 580 | cpuid_entry_override(entry, CPUID_7_1_EAX); |
09f628a0 SC |
581 | entry->ebx = 0; |
582 | entry->ecx = 0; | |
583 | entry->edx = 0; | |
54d360d4 | 584 | } |
00b27a3e | 585 | break; |
00b27a3e AK |
586 | case 9: |
587 | break; | |
a6c06ed1 GN |
588 | case 0xa: { /* Architectural Performance Monitoring */ |
589 | struct x86_pmu_capability cap; | |
590 | union cpuid10_eax eax; | |
591 | union cpuid10_edx edx; | |
592 | ||
593 | perf_get_x86_pmu_capability(&cap); | |
594 | ||
595 | /* | |
596 | * Only support guest architectural pmu on a host | |
597 | * with architectural pmu. | |
598 | */ | |
599 | if (!cap.version) | |
600 | memset(&cap, 0, sizeof(cap)); | |
601 | ||
602 | eax.split.version_id = min(cap.version, 2); | |
603 | eax.split.num_counters = cap.num_counters_gp; | |
604 | eax.split.bit_width = cap.bit_width_gp; | |
605 | eax.split.mask_length = cap.events_mask_len; | |
606 | ||
607 | edx.split.num_counters_fixed = cap.num_counters_fixed; | |
608 | edx.split.bit_width_fixed = cap.bit_width_fixed; | |
609 | edx.split.reserved = 0; | |
610 | ||
611 | entry->eax = eax.full; | |
612 | entry->ebx = cap.events_mask; | |
613 | entry->ecx = 0; | |
614 | entry->edx = edx.full; | |
615 | break; | |
616 | } | |
a87f2d3a LX |
617 | /* |
618 | * Per Intel's SDM, the 0x1f is a superset of 0xb, | |
619 | * thus they can be handled by common code. | |
620 | */ | |
621 | case 0x1f: | |
74fa0bc7 | 622 | case 0xb: |
a1a640b8 | 623 | /* |
e53c95e8 SC |
624 | * Populate entries until the level type (ECX[15:8]) of the |
625 | * previous entry is zero. Note, CPUID EAX.{0x1f,0xb}.0 is | |
626 | * the starting entry, filled by the primary do_host_cpuid(). | |
a1a640b8 | 627 | */ |
e53c95e8 SC |
628 | for (i = 1; entry->ecx & 0xff00; ++i) { |
629 | entry = do_host_cpuid(array, function, i); | |
630 | if (!entry) | |
831bf664 | 631 | goto out; |
00b27a3e AK |
632 | } |
633 | break; | |
cfc48181 SC |
634 | case 0xd: |
635 | entry->eax &= supported_xcr0; | |
636 | entry->ebx = xstate_required_size(supported_xcr0, false); | |
e08e8336 | 637 | entry->ecx = entry->ebx; |
cfc48181 SC |
638 | entry->edx &= supported_xcr0 >> 32; |
639 | if (!supported_xcr0) | |
b65d6e17 PB |
640 | break; |
641 | ||
e53c95e8 SC |
642 | entry = do_host_cpuid(array, function, 1); |
643 | if (!entry) | |
3dc4a9cf SC |
644 | goto out; |
645 | ||
bd791999 | 646 | cpuid_entry_override(entry, CPUID_D_1_EAX); |
e53c95e8 | 647 | if (entry->eax & (F(XSAVES)|F(XSAVEC))) |
408e9a31 PB |
648 | entry->ebx = xstate_required_size(supported_xcr0 | supported_xss, |
649 | true); | |
650 | else { | |
651 | WARN_ON_ONCE(supported_xss != 0); | |
e53c95e8 | 652 | entry->ebx = 0; |
408e9a31 PB |
653 | } |
654 | entry->ecx &= supported_xss; | |
655 | entry->edx &= supported_xss >> 32; | |
3dc4a9cf | 656 | |
0eee8f9d | 657 | for (i = 2; i < 64; ++i) { |
408e9a31 PB |
658 | bool s_state; |
659 | if (supported_xcr0 & BIT_ULL(i)) | |
660 | s_state = false; | |
661 | else if (supported_xss & BIT_ULL(i)) | |
662 | s_state = true; | |
663 | else | |
1893c941 | 664 | continue; |
3dc4a9cf | 665 | |
0eee8f9d | 666 | entry = do_host_cpuid(array, function, i); |
e53c95e8 | 667 | if (!entry) |
831bf664 SL |
668 | goto out; |
669 | ||
91001d40 | 670 | /* |
cfc48181 | 671 | * The supported check above should have filtered out |
408e9a31 | 672 | * invalid sub-leafs. Only valid sub-leafs should |
91001d40 | 673 | * reach this point, and they should have a non-zero |
408e9a31 PB |
674 | * save state size. Furthermore, check whether the |
675 | * processor agrees with supported_xcr0/supported_xss | |
676 | * on whether this is an XCR0- or IA32_XSS-managed area. | |
91001d40 | 677 | */ |
408e9a31 | 678 | if (WARN_ON_ONCE(!entry->eax || (entry->ecx & 0x1) != s_state)) { |
e53c95e8 | 679 | --array->nent; |
3dc4a9cf | 680 | continue; |
8b2fc445 | 681 | } |
e53c95e8 | 682 | entry->edx = 0; |
00b27a3e AK |
683 | } |
684 | break; | |
86f5201d | 685 | /* Intel PT */ |
74fa0bc7 | 686 | case 0x14: |
dd69cc25 | 687 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) { |
7392079c | 688 | entry->eax = entry->ebx = entry->ecx = entry->edx = 0; |
86f5201d | 689 | break; |
7392079c | 690 | } |
86f5201d | 691 | |
74fa0bc7 | 692 | for (i = 1, max_idx = entry->eax; i <= max_idx; ++i) { |
e53c95e8 | 693 | if (!do_host_cpuid(array, function, i)) |
86f5201d | 694 | goto out; |
86f5201d CP |
695 | } |
696 | break; | |
00b27a3e | 697 | case KVM_CPUID_SIGNATURE: { |
326d07cb MK |
698 | static const char signature[12] = "KVMKVMKVM\0\0"; |
699 | const u32 *sigptr = (const u32 *)signature; | |
57c22e5f | 700 | entry->eax = KVM_CPUID_FEATURES; |
00b27a3e AK |
701 | entry->ebx = sigptr[0]; |
702 | entry->ecx = sigptr[1]; | |
703 | entry->edx = sigptr[2]; | |
704 | break; | |
705 | } | |
706 | case KVM_CPUID_FEATURES: | |
707 | entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) | | |
708 | (1 << KVM_FEATURE_NOP_IO_DELAY) | | |
709 | (1 << KVM_FEATURE_CLOCKSOURCE2) | | |
710 | (1 << KVM_FEATURE_ASYNC_PF) | | |
ae7a2a3f | 711 | (1 << KVM_FEATURE_PV_EOI) | |
6aef266c | 712 | (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT) | |
f38a7b75 | 713 | (1 << KVM_FEATURE_PV_UNHALT) | |
fe2a3027 | 714 | (1 << KVM_FEATURE_PV_TLB_FLUSH) | |
4180bf1b | 715 | (1 << KVM_FEATURE_ASYNC_PF_VMEXIT) | |
2d5ba19b | 716 | (1 << KVM_FEATURE_PV_SEND_IPI) | |
32b72ecc | 717 | (1 << KVM_FEATURE_POLL_CONTROL) | |
72de5fa4 VK |
718 | (1 << KVM_FEATURE_PV_SCHED_YIELD) | |
719 | (1 << KVM_FEATURE_ASYNC_PF_INT); | |
00b27a3e AK |
720 | |
721 | if (sched_info_on()) | |
722 | entry->eax |= (1 << KVM_FEATURE_STEAL_TIME); | |
723 | ||
724 | entry->ebx = 0; | |
725 | entry->ecx = 0; | |
726 | entry->edx = 0; | |
727 | break; | |
728 | case 0x80000000: | |
8765d753 | 729 | entry->eax = min(entry->eax, 0x8000001f); |
00b27a3e AK |
730 | break; |
731 | case 0x80000001: | |
bd791999 SC |
732 | cpuid_entry_override(entry, CPUID_8000_0001_EDX); |
733 | cpuid_entry_override(entry, CPUID_8000_0001_ECX); | |
00b27a3e | 734 | break; |
43d05de2 EN |
735 | case 0x80000006: |
736 | /* L2 cache and TLB: pass through host info. */ | |
737 | break; | |
e4c9a5a1 MT |
738 | case 0x80000007: /* Advanced power management */ |
739 | /* invariant TSC is CPUID.80000007H:EDX[8] */ | |
740 | entry->edx &= (1 << 8); | |
741 | /* mask against host */ | |
742 | entry->edx &= boot_cpu_data.x86_power; | |
743 | entry->eax = entry->ebx = entry->ecx = 0; | |
744 | break; | |
00b27a3e AK |
745 | case 0x80000008: { |
746 | unsigned g_phys_as = (entry->eax >> 16) & 0xff; | |
747 | unsigned virt_as = max((entry->eax >> 8) & 0xff, 48U); | |
748 | unsigned phys_as = entry->eax & 0xff; | |
749 | ||
750 | if (!g_phys_as) | |
751 | g_phys_as = phys_as; | |
752 | entry->eax = g_phys_as | (virt_as << 8); | |
15d45071 | 753 | entry->edx = 0; |
bd791999 | 754 | cpuid_entry_override(entry, CPUID_8000_0008_EBX); |
00b27a3e AK |
755 | break; |
756 | } | |
25703874 SC |
757 | case 0x8000000A: |
758 | if (!kvm_cpu_cap_has(X86_FEATURE_SVM)) { | |
759 | entry->eax = entry->ebx = entry->ecx = entry->edx = 0; | |
760 | break; | |
761 | } | |
762 | entry->eax = 1; /* SVM revision 1 */ | |
763 | entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper | |
764 | ASID emulation to nested SVM */ | |
765 | entry->ecx = 0; /* Reserved */ | |
766 | cpuid_entry_override(entry, CPUID_8000_000A_EDX); | |
767 | break; | |
00b27a3e AK |
768 | case 0x80000019: |
769 | entry->ecx = entry->edx = 0; | |
770 | break; | |
771 | case 0x8000001a: | |
382409b4 | 772 | case 0x8000001e: |
00b27a3e | 773 | break; |
c1de0f25 PG |
774 | /* Support memory encryption cpuid if host supports it */ |
775 | case 0x8000001F: | |
776 | if (!boot_cpu_has(X86_FEATURE_SEV)) | |
777 | entry->eax = entry->ebx = entry->ecx = entry->edx = 0; | |
778 | break; | |
00b27a3e AK |
779 | /*Add support for Centaur's CPUID instruction*/ |
780 | case 0xC0000000: | |
781 | /*Just support up to 0xC0000004 now*/ | |
782 | entry->eax = min(entry->eax, 0xC0000004); | |
783 | break; | |
784 | case 0xC0000001: | |
bd791999 | 785 | cpuid_entry_override(entry, CPUID_C000_0001_EDX); |
00b27a3e AK |
786 | break; |
787 | case 3: /* Processor serial number */ | |
788 | case 5: /* MONITOR/MWAIT */ | |
00b27a3e AK |
789 | case 0xC0000002: |
790 | case 0xC0000003: | |
791 | case 0xC0000004: | |
792 | default: | |
793 | entry->eax = entry->ebx = entry->ecx = entry->edx = 0; | |
794 | break; | |
795 | } | |
796 | ||
831bf664 SL |
797 | r = 0; |
798 | ||
799 | out: | |
00b27a3e | 800 | put_cpu(); |
831bf664 SL |
801 | |
802 | return r; | |
00b27a3e AK |
803 | } |
804 | ||
e53c95e8 SC |
805 | static int do_cpuid_func(struct kvm_cpuid_array *array, u32 func, |
806 | unsigned int type) | |
9c15bb1d BP |
807 | { |
808 | if (type == KVM_GET_EMULATED_CPUID) | |
e53c95e8 | 809 | return __do_cpuid_func_emulated(array, func); |
9c15bb1d | 810 | |
e53c95e8 | 811 | return __do_cpuid_func(array, func); |
9c15bb1d BP |
812 | } |
813 | ||
8b86079c | 814 | #define CENTAUR_CPUID_SIGNATURE 0xC0000000 |
831bf664 | 815 | |
e53c95e8 SC |
816 | static int get_cpuid_func(struct kvm_cpuid_array *array, u32 func, |
817 | unsigned int type) | |
619a17f1 SC |
818 | { |
819 | u32 limit; | |
820 | int r; | |
821 | ||
8b86079c SC |
822 | if (func == CENTAUR_CPUID_SIGNATURE && |
823 | boot_cpu_data.x86_vendor != X86_VENDOR_CENTAUR) | |
824 | return 0; | |
825 | ||
e53c95e8 | 826 | r = do_cpuid_func(array, func, type); |
619a17f1 SC |
827 | if (r) |
828 | return r; | |
829 | ||
e53c95e8 | 830 | limit = array->entries[array->nent - 1].eax; |
619a17f1 | 831 | for (func = func + 1; func <= limit; ++func) { |
e53c95e8 | 832 | r = do_cpuid_func(array, func, type); |
619a17f1 SC |
833 | if (r) |
834 | break; | |
835 | } | |
836 | ||
837 | return r; | |
838 | } | |
839 | ||
9c15bb1d BP |
840 | static bool sanity_check_entries(struct kvm_cpuid_entry2 __user *entries, |
841 | __u32 num_entries, unsigned int ioctl_type) | |
842 | { | |
843 | int i; | |
1b2ca422 | 844 | __u32 pad[3]; |
9c15bb1d BP |
845 | |
846 | if (ioctl_type != KVM_GET_EMULATED_CPUID) | |
847 | return false; | |
848 | ||
849 | /* | |
850 | * We want to make sure that ->padding is being passed clean from | |
851 | * userspace in case we want to use it for something in the future. | |
852 | * | |
853 | * Sadly, this wasn't enforced for KVM_GET_SUPPORTED_CPUID and so we | |
854 | * have to give ourselves satisfied only with the emulated side. /me | |
855 | * sheds a tear. | |
856 | */ | |
857 | for (i = 0; i < num_entries; i++) { | |
1b2ca422 BP |
858 | if (copy_from_user(pad, entries[i].padding, sizeof(pad))) |
859 | return true; | |
860 | ||
861 | if (pad[0] || pad[1] || pad[2]) | |
9c15bb1d BP |
862 | return true; |
863 | } | |
864 | return false; | |
865 | } | |
866 | ||
867 | int kvm_dev_ioctl_get_cpuid(struct kvm_cpuid2 *cpuid, | |
868 | struct kvm_cpuid_entry2 __user *entries, | |
869 | unsigned int type) | |
00b27a3e | 870 | { |
8b86079c SC |
871 | static const u32 funcs[] = { |
872 | 0, 0x80000000, CENTAUR_CPUID_SIGNATURE, KVM_CPUID_SIGNATURE, | |
831bf664 | 873 | }; |
00b27a3e | 874 | |
e53c95e8 SC |
875 | struct kvm_cpuid_array array = { |
876 | .nent = 0, | |
e53c95e8 SC |
877 | }; |
878 | int r, i; | |
d5a661d1 | 879 | |
00b27a3e | 880 | if (cpuid->nent < 1) |
d5a661d1 | 881 | return -E2BIG; |
00b27a3e AK |
882 | if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) |
883 | cpuid->nent = KVM_MAX_CPUID_ENTRIES; | |
9c15bb1d BP |
884 | |
885 | if (sanity_check_entries(entries, cpuid->nent, type)) | |
886 | return -EINVAL; | |
887 | ||
e53c95e8 | 888 | array.entries = vzalloc(array_size(sizeof(struct kvm_cpuid_entry2), |
fad953ce | 889 | cpuid->nent)); |
e53c95e8 | 890 | if (!array.entries) |
d5a661d1 | 891 | return -ENOMEM; |
00b27a3e | 892 | |
65b18914 XL |
893 | array.maxnent = cpuid->nent; |
894 | ||
8b86079c | 895 | for (i = 0; i < ARRAY_SIZE(funcs); i++) { |
e53c95e8 | 896 | r = get_cpuid_func(&array, funcs[i], type); |
831bf664 | 897 | if (r) |
00b27a3e AK |
898 | goto out_free; |
899 | } | |
e53c95e8 | 900 | cpuid->nent = array.nent; |
00b27a3e | 901 | |
e53c95e8 SC |
902 | if (copy_to_user(entries, array.entries, |
903 | array.nent * sizeof(struct kvm_cpuid_entry2))) | |
d5a661d1 | 904 | r = -EFAULT; |
00b27a3e AK |
905 | |
906 | out_free: | |
e53c95e8 | 907 | vfree(array.entries); |
00b27a3e AK |
908 | return r; |
909 | } | |
910 | ||
00b27a3e AK |
911 | struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu, |
912 | u32 function, u32 index) | |
913 | { | |
7ff6c035 | 914 | struct kvm_cpuid_entry2 *e; |
00b27a3e | 915 | int i; |
00b27a3e AK |
916 | |
917 | for (i = 0; i < vcpu->arch.cpuid_nent; ++i) { | |
00b27a3e | 918 | e = &vcpu->arch.cpuid_entries[i]; |
7ff6c035 SC |
919 | |
920 | if (e->function == function && (e->index == index || | |
921 | !(e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX))) | |
922 | return e; | |
00b27a3e | 923 | } |
7ff6c035 | 924 | return NULL; |
00b27a3e AK |
925 | } |
926 | EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry); | |
927 | ||
00b27a3e | 928 | /* |
8d892311 SC |
929 | * Intel CPUID semantics treats any query for an out-of-range leaf as if the |
930 | * highest basic leaf (i.e. CPUID.0H:EAX) were requested. AMD CPUID semantics | |
931 | * returns all zeroes for any undefined leaf, whether or not the leaf is in | |
932 | * range. Centaur/VIA follows Intel semantics. | |
933 | * | |
934 | * A leaf is considered out-of-range if its function is higher than the maximum | |
935 | * supported leaf of its associated class or if its associated class does not | |
936 | * exist. | |
937 | * | |
938 | * There are three primary classes to be considered, with their respective | |
939 | * ranges described as "<base> - <top>[,<base2> - <top2>] inclusive. A primary | |
940 | * class exists if a guest CPUID entry for its <base> leaf exists. For a given | |
941 | * class, CPUID.<base>.EAX contains the max supported leaf for the class. | |
942 | * | |
943 | * - Basic: 0x00000000 - 0x3fffffff, 0x50000000 - 0x7fffffff | |
944 | * - Hypervisor: 0x40000000 - 0x4fffffff | |
945 | * - Extended: 0x80000000 - 0xbfffffff | |
946 | * - Centaur: 0xc0000000 - 0xcfffffff | |
947 | * | |
948 | * The Hypervisor class is further subdivided into sub-classes that each act as | |
949 | * their own indepdent class associated with a 0x100 byte range. E.g. if Qemu | |
950 | * is advertising support for both HyperV and KVM, the resulting Hypervisor | |
951 | * CPUID sub-classes are: | |
952 | * | |
953 | * - HyperV: 0x40000000 - 0x400000ff | |
954 | * - KVM: 0x40000100 - 0x400001ff | |
00b27a3e | 955 | */ |
09c7431e SC |
956 | static struct kvm_cpuid_entry2 * |
957 | get_out_of_range_cpuid_entry(struct kvm_vcpu *vcpu, u32 *fn_ptr, u32 index) | |
00b27a3e | 958 | { |
8d892311 | 959 | struct kvm_cpuid_entry2 *basic, *class; |
09c7431e | 960 | u32 function = *fn_ptr; |
8d892311 SC |
961 | |
962 | basic = kvm_find_cpuid_entry(vcpu, 0, 0); | |
963 | if (!basic) | |
09c7431e SC |
964 | return NULL; |
965 | ||
966 | if (is_guest_vendor_amd(basic->ebx, basic->ecx, basic->edx) || | |
967 | is_guest_vendor_hygon(basic->ebx, basic->ecx, basic->edx)) | |
968 | return NULL; | |
8d892311 SC |
969 | |
970 | if (function >= 0x40000000 && function <= 0x4fffffff) | |
971 | class = kvm_find_cpuid_entry(vcpu, function & 0xffffff00, 0); | |
972 | else if (function >= 0xc0000000) | |
973 | class = kvm_find_cpuid_entry(vcpu, 0xc0000000, 0); | |
974 | else | |
975 | class = kvm_find_cpuid_entry(vcpu, function & 0x80000000, 0); | |
43561123 | 976 | |
09c7431e SC |
977 | if (class && function <= class->eax) |
978 | return NULL; | |
979 | ||
980 | /* | |
981 | * Leaf specific adjustments are also applied when redirecting to the | |
982 | * max basic entry, e.g. if the max basic leaf is 0xb but there is no | |
983 | * entry for CPUID.0xb.index (see below), then the output value for EDX | |
984 | * needs to be pulled from CPUID.0xb.1. | |
985 | */ | |
986 | *fn_ptr = basic->eax; | |
987 | ||
988 | /* | |
989 | * The class does not exist or the requested function is out of range; | |
990 | * the effective CPUID entry is the max basic leaf. Note, the index of | |
991 | * the original requested leaf is observed! | |
992 | */ | |
993 | return kvm_find_cpuid_entry(vcpu, basic->eax, index); | |
00b27a3e AK |
994 | } |
995 | ||
e911eb3b | 996 | bool kvm_cpuid(struct kvm_vcpu *vcpu, u32 *eax, u32 *ebx, |
f91af517 | 997 | u32 *ecx, u32 *edx, bool exact_only) |
00b27a3e | 998 | { |
b7fb8488 | 999 | u32 orig_function = *eax, function = *eax, index = *ecx; |
43561123 | 1000 | struct kvm_cpuid_entry2 *entry; |
2b110b61 | 1001 | bool exact, used_max_basic = false; |
e911eb3b | 1002 | |
43561123 | 1003 | entry = kvm_find_cpuid_entry(vcpu, function, index); |
f91af517 | 1004 | exact = !!entry; |
09c7431e | 1005 | |
2b110b61 | 1006 | if (!entry && !exact_only) { |
09c7431e | 1007 | entry = get_out_of_range_cpuid_entry(vcpu, &function, index); |
2b110b61 SC |
1008 | used_max_basic = !!entry; |
1009 | } | |
09c7431e | 1010 | |
43561123 JM |
1011 | if (entry) { |
1012 | *eax = entry->eax; | |
1013 | *ebx = entry->ebx; | |
1014 | *ecx = entry->ecx; | |
1015 | *edx = entry->edx; | |
edef5c36 PB |
1016 | if (function == 7 && index == 0) { |
1017 | u64 data; | |
1018 | if (!__kvm_get_msr(vcpu, MSR_IA32_TSX_CTRL, &data, true) && | |
1019 | (data & TSX_CTRL_CPUID_CLEAR)) | |
1020 | *ebx &= ~(F(RTM) | F(HLE)); | |
1021 | } | |
43561123 | 1022 | } else { |
62046e5a | 1023 | *eax = *ebx = *ecx = *edx = 0; |
43561123 JM |
1024 | /* |
1025 | * When leaf 0BH or 1FH is defined, CL is pass-through | |
1026 | * and EDX is always the x2APIC ID, even for undefined | |
1027 | * subleaves. Index 1 will exist iff the leaf is | |
1028 | * implemented, so we pass through CL iff leaf 1 | |
1029 | * exists. EDX can be copied from any existing index. | |
1030 | */ | |
1031 | if (function == 0xb || function == 0x1f) { | |
1032 | entry = kvm_find_cpuid_entry(vcpu, function, 1); | |
1033 | if (entry) { | |
1034 | *ecx = index & 0xff; | |
1035 | *edx = entry->edx; | |
1036 | } | |
1037 | } | |
1038 | } | |
2b110b61 SC |
1039 | trace_kvm_cpuid(orig_function, index, *eax, *ebx, *ecx, *edx, exact, |
1040 | used_max_basic); | |
f91af517 | 1041 | return exact; |
62046e5a | 1042 | } |
66f7b72e | 1043 | EXPORT_SYMBOL_GPL(kvm_cpuid); |
62046e5a | 1044 | |
6a908b62 | 1045 | int kvm_emulate_cpuid(struct kvm_vcpu *vcpu) |
62046e5a | 1046 | { |
1e13175b | 1047 | u32 eax, ebx, ecx, edx; |
62046e5a | 1048 | |
db2336a8 KH |
1049 | if (cpuid_fault_enabled(vcpu) && !kvm_require_cpl(vcpu, 0)) |
1050 | return 1; | |
1051 | ||
de3cd117 SC |
1052 | eax = kvm_rax_read(vcpu); |
1053 | ecx = kvm_rcx_read(vcpu); | |
f91af517 | 1054 | kvm_cpuid(vcpu, &eax, &ebx, &ecx, &edx, false); |
de3cd117 SC |
1055 | kvm_rax_write(vcpu, eax); |
1056 | kvm_rbx_write(vcpu, ebx); | |
1057 | kvm_rcx_write(vcpu, ecx); | |
1058 | kvm_rdx_write(vcpu, edx); | |
6affcbed | 1059 | return kvm_skip_emulated_instruction(vcpu); |
00b27a3e AK |
1060 | } |
1061 | EXPORT_SYMBOL_GPL(kvm_emulate_cpuid); |