Commit | Line | Data |
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20c8ccb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
00b27a3e AK |
2 | /* |
3 | * Kernel-based Virtual Machine driver for Linux | |
4 | * cpuid support routines | |
5 | * | |
6 | * derived from arch/x86/kvm/x86.c | |
7 | * | |
8 | * Copyright 2011 Red Hat, Inc. and/or its affiliates. | |
9 | * Copyright IBM Corporation, 2008 | |
00b27a3e AK |
10 | */ |
11 | ||
12 | #include <linux/kvm_host.h> | |
1767e931 | 13 | #include <linux/export.h> |
bb5a798a JK |
14 | #include <linux/vmalloc.h> |
15 | #include <linux/uaccess.h> | |
3905f9ad IM |
16 | #include <linux/sched/stat.h> |
17 | ||
4504b5c9 | 18 | #include <asm/processor.h> |
00b27a3e | 19 | #include <asm/user.h> |
669ebabb | 20 | #include <asm/fpu/xstate.h> |
00b27a3e AK |
21 | #include "cpuid.h" |
22 | #include "lapic.h" | |
23 | #include "mmu.h" | |
24 | #include "trace.h" | |
474a5bb9 | 25 | #include "pmu.h" |
00b27a3e | 26 | |
66a6950f SC |
27 | /* |
28 | * Unlike "struct cpuinfo_x86.x86_capability", kvm_cpu_caps doesn't need to be | |
29 | * aligned to sizeof(unsigned long) because it's not accessed via bitops. | |
30 | */ | |
31 | u32 kvm_cpu_caps[NCAPINTS] __read_mostly; | |
32 | EXPORT_SYMBOL_GPL(kvm_cpu_caps); | |
33 | ||
412a3c41 | 34 | static u32 xstate_required_size(u64 xstate_bv, bool compacted) |
4344ee98 PB |
35 | { |
36 | int feature_bit = 0; | |
37 | u32 ret = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; | |
38 | ||
d91cab78 | 39 | xstate_bv &= XFEATURE_MASK_EXTEND; |
4344ee98 PB |
40 | while (xstate_bv) { |
41 | if (xstate_bv & 0x1) { | |
412a3c41 | 42 | u32 eax, ebx, ecx, edx, offset; |
4344ee98 | 43 | cpuid_count(0xD, feature_bit, &eax, &ebx, &ecx, &edx); |
412a3c41 PB |
44 | offset = compacted ? ret : ebx; |
45 | ret = max(ret, offset + eax); | |
4344ee98 PB |
46 | } |
47 | ||
48 | xstate_bv >>= 1; | |
49 | feature_bit++; | |
50 | } | |
51 | ||
52 | return ret; | |
53 | } | |
54 | ||
87382003 | 55 | #define F feature_bit |
5c404cab | 56 | |
f69858fc VK |
57 | static inline struct kvm_cpuid_entry2 *cpuid_entry2_find( |
58 | struct kvm_cpuid_entry2 *entries, int nent, u32 function, u32 index) | |
59 | { | |
60 | struct kvm_cpuid_entry2 *e; | |
61 | int i; | |
62 | ||
63 | for (i = 0; i < nent; i++) { | |
64 | e = &entries[i]; | |
65 | ||
66 | if (e->function == function && (e->index == index || | |
67 | !(e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX))) | |
68 | return e; | |
69 | } | |
70 | ||
71 | return NULL; | |
72 | } | |
73 | ||
74 | static int kvm_check_cpuid(struct kvm_cpuid_entry2 *entries, int nent) | |
a76733a9 XL |
75 | { |
76 | struct kvm_cpuid_entry2 *best; | |
77 | ||
78 | /* | |
79 | * The existing code assumes virtual address is 48-bit or 57-bit in the | |
80 | * canonical address checks; exit if it is ever changed. | |
81 | */ | |
f69858fc | 82 | best = cpuid_entry2_find(entries, nent, 0x80000008, 0); |
a76733a9 XL |
83 | if (best) { |
84 | int vaddr_bits = (best->eax & 0xff00) >> 8; | |
85 | ||
86 | if (vaddr_bits != 48 && vaddr_bits != 57 && vaddr_bits != 0) | |
87 | return -EINVAL; | |
88 | } | |
89 | ||
90 | return 0; | |
91 | } | |
92 | ||
01b4f510 OU |
93 | void kvm_update_pv_runtime(struct kvm_vcpu *vcpu) |
94 | { | |
95 | struct kvm_cpuid_entry2 *best; | |
96 | ||
97 | best = kvm_find_cpuid_entry(vcpu, KVM_CPUID_FEATURES, 0); | |
98 | ||
99 | /* | |
100 | * save the feature bitmap to avoid cpuid lookup for every PV | |
101 | * operation | |
102 | */ | |
103 | if (best) | |
104 | vcpu->arch.pv_cpuid.features = best->eax; | |
105 | } | |
106 | ||
aedbaf4f | 107 | void kvm_update_cpuid_runtime(struct kvm_vcpu *vcpu) |
00b27a3e AK |
108 | { |
109 | struct kvm_cpuid_entry2 *best; | |
00b27a3e AK |
110 | |
111 | best = kvm_find_cpuid_entry(vcpu, 1, 0); | |
0d3b2ba1 XL |
112 | if (best) { |
113 | /* Update OSXSAVE bit */ | |
114 | if (boot_cpu_has(X86_FEATURE_XSAVE)) | |
115 | cpuid_entry_change(best, X86_FEATURE_OSXSAVE, | |
b32666b1 | 116 | kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)); |
00b27a3e | 117 | |
0d3b2ba1 | 118 | cpuid_entry_change(best, X86_FEATURE_APIC, |
b32666b1 | 119 | vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE); |
0d3b2ba1 | 120 | } |
c7dd15b3 | 121 | |
b9baba86 | 122 | best = kvm_find_cpuid_entry(vcpu, 7, 0); |
b32666b1 SC |
123 | if (best && boot_cpu_has(X86_FEATURE_PKU) && best->function == 0x7) |
124 | cpuid_entry_change(best, X86_FEATURE_OSPKE, | |
125 | kvm_read_cr4_bits(vcpu, X86_CR4_PKE)); | |
b9baba86 | 126 | |
d7876f1b | 127 | best = kvm_find_cpuid_entry(vcpu, 0xD, 0); |
aedbaf4f | 128 | if (best) |
a71936ab | 129 | best->ebx = xstate_required_size(vcpu->arch.xcr0, false); |
d7876f1b | 130 | |
412a3c41 | 131 | best = kvm_find_cpuid_entry(vcpu, 0xD, 1); |
4c61534a SC |
132 | if (best && (cpuid_entry_has(best, X86_FEATURE_XSAVES) || |
133 | cpuid_entry_has(best, X86_FEATURE_XSAVEC))) | |
412a3c41 PB |
134 | best->ebx = xstate_required_size(vcpu->arch.xcr0, true); |
135 | ||
caa057a2 WL |
136 | best = kvm_find_cpuid_entry(vcpu, KVM_CPUID_FEATURES, 0); |
137 | if (kvm_hlt_in_guest(vcpu->kvm) && best && | |
138 | (best->eax & (1 << KVM_FEATURE_PV_UNHALT))) | |
139 | best->eax &= ~(1 << KVM_FEATURE_PV_UNHALT); | |
140 | ||
511a8556 WL |
141 | if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT)) { |
142 | best = kvm_find_cpuid_entry(vcpu, 0x1, 0); | |
b32666b1 SC |
143 | if (best) |
144 | cpuid_entry_change(best, X86_FEATURE_MWAIT, | |
145 | vcpu->arch.ia32_misc_enable_msr & | |
146 | MSR_IA32_MISC_ENABLE_MWAIT); | |
511a8556 | 147 | } |
aedbaf4f | 148 | } |
2259c17f | 149 | EXPORT_SYMBOL_GPL(kvm_update_cpuid_runtime); |
aedbaf4f | 150 | |
346ce359 | 151 | static void kvm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu) |
aedbaf4f XL |
152 | { |
153 | struct kvm_lapic *apic = vcpu->arch.apic; | |
154 | struct kvm_cpuid_entry2 *best; | |
155 | ||
156 | best = kvm_find_cpuid_entry(vcpu, 1, 0); | |
157 | if (best && apic) { | |
158 | if (cpuid_entry_has(best, X86_FEATURE_TSC_DEADLINE_TIMER)) | |
159 | apic->lapic_timer.timer_mode_mask = 3 << 17; | |
160 | else | |
161 | apic->lapic_timer.timer_mode_mask = 1 << 17; | |
162 | ||
163 | kvm_apic_set_version(vcpu); | |
164 | } | |
165 | ||
166 | best = kvm_find_cpuid_entry(vcpu, 0xD, 0); | |
167 | if (!best) | |
168 | vcpu->arch.guest_supported_xcr0 = 0; | |
169 | else | |
170 | vcpu->arch.guest_supported_xcr0 = | |
171 | (best->eax | ((u64)best->edx << 32)) & supported_xcr0; | |
511a8556 | 172 | |
01b4f510 OU |
173 | kvm_update_pv_runtime(vcpu); |
174 | ||
5a4f55cd | 175 | vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); |
a8ac864a | 176 | vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu); |
5a4f55cd | 177 | |
c6702c9d | 178 | kvm_pmu_refresh(vcpu); |
b899c132 KS |
179 | vcpu->arch.cr4_guest_rsvd_bits = |
180 | __cr4_reserved_bits(guest_cpuid_has, vcpu); | |
c44d9b34 | 181 | |
8f014550 VK |
182 | kvm_hv_set_cpuid(vcpu); |
183 | ||
c44d9b34 | 184 | /* Invoke the vendor callback only after the above state is updated. */ |
b3646477 | 185 | static_call(kvm_x86_vcpu_after_set_cpuid)(vcpu); |
5b7f575c SC |
186 | |
187 | /* | |
188 | * Except for the MMU, which needs to be reset after any vendor | |
189 | * specific adjustments to the reserved GPA bits. | |
190 | */ | |
191 | kvm_mmu_reset_context(vcpu); | |
00b27a3e AK |
192 | } |
193 | ||
194 | static int is_efer_nx(void) | |
195 | { | |
91661989 | 196 | return host_efer & EFER_NX; |
00b27a3e AK |
197 | } |
198 | ||
199 | static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu) | |
200 | { | |
201 | int i; | |
202 | struct kvm_cpuid_entry2 *e, *entry; | |
203 | ||
204 | entry = NULL; | |
205 | for (i = 0; i < vcpu->arch.cpuid_nent; ++i) { | |
206 | e = &vcpu->arch.cpuid_entries[i]; | |
207 | if (e->function == 0x80000001) { | |
208 | entry = e; | |
209 | break; | |
210 | } | |
211 | } | |
4c61534a | 212 | if (entry && cpuid_entry_has(entry, X86_FEATURE_NX) && !is_efer_nx()) { |
b32666b1 | 213 | cpuid_entry_clear(entry, X86_FEATURE_NX); |
00b27a3e AK |
214 | printk(KERN_INFO "kvm: guest NX capability removed\n"); |
215 | } | |
216 | } | |
217 | ||
5a4f55cd EK |
218 | int cpuid_query_maxphyaddr(struct kvm_vcpu *vcpu) |
219 | { | |
220 | struct kvm_cpuid_entry2 *best; | |
221 | ||
222 | best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0); | |
223 | if (!best || best->eax < 0x80000008) | |
224 | goto not_found; | |
225 | best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0); | |
226 | if (best) | |
227 | return best->eax & 0xff; | |
228 | not_found: | |
229 | return 36; | |
230 | } | |
5a4f55cd | 231 | |
a8ac864a SC |
232 | /* |
233 | * This "raw" version returns the reserved GPA bits without any adjustments for | |
234 | * encryption technologies that usurp bits. The raw mask should be used if and | |
235 | * only if hardware does _not_ strip the usurped bits, e.g. in virtual MTRRs. | |
236 | */ | |
237 | u64 kvm_vcpu_reserved_gpa_bits_raw(struct kvm_vcpu *vcpu) | |
238 | { | |
239 | return rsvd_bits(cpuid_maxphyaddr(vcpu), 63); | |
240 | } | |
241 | ||
00b27a3e AK |
242 | /* when an old userspace process fills a new kernel module */ |
243 | int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu, | |
244 | struct kvm_cpuid *cpuid, | |
245 | struct kvm_cpuid_entry __user *entries) | |
246 | { | |
247 | int r, i; | |
255cbecf VK |
248 | struct kvm_cpuid_entry *e = NULL; |
249 | struct kvm_cpuid_entry2 *e2 = NULL; | |
00b27a3e | 250 | |
00b27a3e | 251 | if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) |
255cbecf VK |
252 | return -E2BIG; |
253 | ||
83676e92 | 254 | if (cpuid->nent) { |
255cbecf VK |
255 | e = vmemdup_user(entries, array_size(sizeof(*e), cpuid->nent)); |
256 | if (IS_ERR(e)) | |
257 | return PTR_ERR(e); | |
258 | ||
259 | e2 = kvmalloc_array(cpuid->nent, sizeof(*e2), GFP_KERNEL_ACCOUNT); | |
260 | if (!e2) { | |
261 | r = -ENOMEM; | |
262 | goto out_free_cpuid; | |
7ec28e26 | 263 | } |
83676e92 | 264 | } |
00b27a3e | 265 | for (i = 0; i < cpuid->nent; i++) { |
255cbecf VK |
266 | e2[i].function = e[i].function; |
267 | e2[i].eax = e[i].eax; | |
268 | e2[i].ebx = e[i].ebx; | |
269 | e2[i].ecx = e[i].ecx; | |
270 | e2[i].edx = e[i].edx; | |
271 | e2[i].index = 0; | |
272 | e2[i].flags = 0; | |
273 | e2[i].padding[0] = 0; | |
274 | e2[i].padding[1] = 0; | |
275 | e2[i].padding[2] = 0; | |
00b27a3e | 276 | } |
255cbecf VK |
277 | |
278 | r = kvm_check_cpuid(e2, cpuid->nent); | |
a76733a9 | 279 | if (r) { |
255cbecf VK |
280 | kvfree(e2); |
281 | goto out_free_cpuid; | |
a76733a9 XL |
282 | } |
283 | ||
255cbecf VK |
284 | kvfree(vcpu->arch.cpuid_entries); |
285 | vcpu->arch.cpuid_entries = e2; | |
286 | vcpu->arch.cpuid_nent = cpuid->nent; | |
287 | ||
00b27a3e | 288 | cpuid_fix_nx_cap(vcpu); |
aedbaf4f | 289 | kvm_update_cpuid_runtime(vcpu); |
346ce359 | 290 | kvm_vcpu_after_set_cpuid(vcpu); |
00b27a3e | 291 | |
255cbecf VK |
292 | out_free_cpuid: |
293 | kvfree(e); | |
294 | ||
00b27a3e AK |
295 | return r; |
296 | } | |
297 | ||
298 | int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu, | |
299 | struct kvm_cpuid2 *cpuid, | |
300 | struct kvm_cpuid_entry2 __user *entries) | |
301 | { | |
255cbecf | 302 | struct kvm_cpuid_entry2 *e2 = NULL; |
00b27a3e AK |
303 | int r; |
304 | ||
00b27a3e | 305 | if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) |
255cbecf VK |
306 | return -E2BIG; |
307 | ||
308 | if (cpuid->nent) { | |
309 | e2 = vmemdup_user(entries, array_size(sizeof(*e2), cpuid->nent)); | |
310 | if (IS_ERR(e2)) | |
311 | return PTR_ERR(e2); | |
312 | } | |
313 | ||
314 | r = kvm_check_cpuid(e2, cpuid->nent); | |
a76733a9 | 315 | if (r) { |
255cbecf VK |
316 | kvfree(e2); |
317 | return r; | |
a76733a9 XL |
318 | } |
319 | ||
255cbecf VK |
320 | kvfree(vcpu->arch.cpuid_entries); |
321 | vcpu->arch.cpuid_entries = e2; | |
322 | vcpu->arch.cpuid_nent = cpuid->nent; | |
323 | ||
aedbaf4f | 324 | kvm_update_cpuid_runtime(vcpu); |
346ce359 | 325 | kvm_vcpu_after_set_cpuid(vcpu); |
255cbecf VK |
326 | |
327 | return 0; | |
00b27a3e AK |
328 | } |
329 | ||
330 | int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu, | |
331 | struct kvm_cpuid2 *cpuid, | |
332 | struct kvm_cpuid_entry2 __user *entries) | |
333 | { | |
334 | int r; | |
335 | ||
336 | r = -E2BIG; | |
337 | if (cpuid->nent < vcpu->arch.cpuid_nent) | |
338 | goto out; | |
339 | r = -EFAULT; | |
181f4948 | 340 | if (copy_to_user(entries, vcpu->arch.cpuid_entries, |
00b27a3e AK |
341 | vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2))) |
342 | goto out; | |
343 | return 0; | |
344 | ||
345 | out: | |
346 | cpuid->nent = vcpu->arch.cpuid_nent; | |
347 | return r; | |
348 | } | |
349 | ||
66a6950f SC |
350 | static __always_inline void kvm_cpu_cap_mask(enum cpuid_leafs leaf, u32 mask) |
351 | { | |
d8577a4c SC |
352 | const struct cpuid_reg cpuid = x86_feature_cpuid(leaf * 32); |
353 | struct kvm_cpuid_entry2 entry; | |
354 | ||
66a6950f SC |
355 | reverse_cpuid_check(leaf); |
356 | kvm_cpu_caps[leaf] &= mask; | |
d8577a4c SC |
357 | |
358 | cpuid_count(cpuid.function, cpuid.index, | |
359 | &entry.eax, &entry.ebx, &entry.ecx, &entry.edx); | |
360 | ||
855c7e9b | 361 | kvm_cpu_caps[leaf] &= *__cpuid_entry_get_reg(&entry, cpuid.reg); |
66a6950f SC |
362 | } |
363 | ||
364 | void kvm_set_cpu_caps(void) | |
365 | { | |
366 | unsigned int f_nx = is_efer_nx() ? F(NX) : 0; | |
367 | #ifdef CONFIG_X86_64 | |
368 | unsigned int f_gbpages = F(GBPAGES); | |
369 | unsigned int f_lm = F(LM); | |
370 | #else | |
371 | unsigned int f_gbpages = 0; | |
372 | unsigned int f_lm = 0; | |
373 | #endif | |
374 | ||
375 | BUILD_BUG_ON(sizeof(kvm_cpu_caps) > | |
376 | sizeof(boot_cpu_data.x86_capability)); | |
377 | ||
378 | memcpy(&kvm_cpu_caps, &boot_cpu_data.x86_capability, | |
379 | sizeof(kvm_cpu_caps)); | |
380 | ||
381 | kvm_cpu_cap_mask(CPUID_1_ECX, | |
382 | /* | |
383 | * NOTE: MONITOR (and MWAIT) are emulated as NOP, but *not* | |
384 | * advertised to guests via CPUID! | |
385 | */ | |
386 | F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ | | |
387 | 0 /* DS-CPL, VMX, SMX, EST */ | | |
388 | 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ | | |
27461da3 | 389 | F(FMA) | F(CX16) | 0 /* xTPR Update */ | F(PDCM) | |
66a6950f SC |
390 | F(PCID) | 0 /* Reserved, DCA */ | F(XMM4_1) | |
391 | F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) | | |
392 | 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) | | |
393 | F(F16C) | F(RDRAND) | |
394 | ); | |
93c380e7 SC |
395 | /* KVM emulates x2apic in software irrespective of host support. */ |
396 | kvm_cpu_cap_set(X86_FEATURE_X2APIC); | |
66a6950f SC |
397 | |
398 | kvm_cpu_cap_mask(CPUID_1_EDX, | |
399 | F(FPU) | F(VME) | F(DE) | F(PSE) | | |
400 | F(TSC) | F(MSR) | F(PAE) | F(MCE) | | |
401 | F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) | | |
402 | F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | | |
403 | F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLUSH) | | |
404 | 0 /* Reserved, DS, ACPI */ | F(MMX) | | |
405 | F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) | | |
406 | 0 /* HTT, TM, Reserved, PBE */ | |
407 | ); | |
408 | ||
409 | kvm_cpu_cap_mask(CPUID_7_0_EBX, | |
410 | F(FSGSBASE) | F(BMI1) | F(HLE) | F(AVX2) | F(SMEP) | | |
e4203334 | 411 | F(BMI2) | F(ERMS) | F(INVPCID) | F(RTM) | 0 /*MPX*/ | F(RDSEED) | |
66a6950f SC |
412 | F(ADX) | F(SMAP) | F(AVX512IFMA) | F(AVX512F) | F(AVX512PF) | |
413 | F(AVX512ER) | F(AVX512CD) | F(CLFLUSHOPT) | F(CLWB) | F(AVX512DQ) | | |
414 | F(SHA_NI) | F(AVX512BW) | F(AVX512VL) | 0 /*INTEL_PT*/ | |
415 | ); | |
416 | ||
417 | kvm_cpu_cap_mask(CPUID_7_ECX, | |
fa44b82e | 418 | F(AVX512VBMI) | F(LA57) | F(PKU) | 0 /*OSPKE*/ | F(RDPID) | |
66a6950f SC |
419 | F(AVX512_VPOPCNTDQ) | F(UMIP) | F(AVX512_VBMI2) | F(GFNI) | |
420 | F(VAES) | F(VPCLMULQDQ) | F(AVX512_VNNI) | F(AVX512_BITALG) | | |
421 | F(CLDEMOTE) | F(MOVDIRI) | F(MOVDIR64B) | 0 /*WAITPKG*/ | |
422 | ); | |
423 | /* Set LA57 based on hardware capability. */ | |
424 | if (cpuid_ecx(7) & F(LA57)) | |
425 | kvm_cpu_cap_set(X86_FEATURE_LA57); | |
426 | ||
fa44b82e BM |
427 | /* |
428 | * PKU not yet implemented for shadow paging and requires OSPKE | |
429 | * to be set on the host. Clear it if that is not the case | |
430 | */ | |
431 | if (!tdp_enabled || !boot_cpu_has(X86_FEATURE_OSPKE)) | |
432 | kvm_cpu_cap_clear(X86_FEATURE_PKU); | |
433 | ||
66a6950f SC |
434 | kvm_cpu_cap_mask(CPUID_7_EDX, |
435 | F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) | | |
436 | F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) | | |
43bd9ef4 | 437 | F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) | |
2224fc9e | 438 | F(SERIALIZE) | F(TSXLDTRK) | F(AVX512_FP16) |
66a6950f SC |
439 | ); |
440 | ||
93c380e7 SC |
441 | /* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */ |
442 | kvm_cpu_cap_set(X86_FEATURE_TSC_ADJUST); | |
443 | kvm_cpu_cap_set(X86_FEATURE_ARCH_CAPABILITIES); | |
444 | ||
445 | if (boot_cpu_has(X86_FEATURE_IBPB) && boot_cpu_has(X86_FEATURE_IBRS)) | |
446 | kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL); | |
447 | if (boot_cpu_has(X86_FEATURE_STIBP)) | |
448 | kvm_cpu_cap_set(X86_FEATURE_INTEL_STIBP); | |
449 | if (boot_cpu_has(X86_FEATURE_AMD_SSBD)) | |
450 | kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD); | |
451 | ||
66a6950f | 452 | kvm_cpu_cap_mask(CPUID_7_1_EAX, |
1085a6b5 | 453 | F(AVX_VNNI) | F(AVX512_BF16) |
66a6950f SC |
454 | ); |
455 | ||
456 | kvm_cpu_cap_mask(CPUID_D_1_EAX, | |
457 | F(XSAVEOPT) | F(XSAVEC) | F(XGETBV1) | F(XSAVES) | |
458 | ); | |
459 | ||
460 | kvm_cpu_cap_mask(CPUID_8000_0001_ECX, | |
461 | F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ | | |
462 | F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) | | |
463 | F(3DNOWPREFETCH) | F(OSVW) | 0 /* IBS */ | F(XOP) | | |
464 | 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM) | | |
465 | F(TOPOEXT) | F(PERFCTR_CORE) | |
466 | ); | |
467 | ||
468 | kvm_cpu_cap_mask(CPUID_8000_0001_EDX, | |
469 | F(FPU) | F(VME) | F(DE) | F(PSE) | | |
470 | F(TSC) | F(MSR) | F(PAE) | F(MCE) | | |
471 | F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) | | |
472 | F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | | |
473 | F(PAT) | F(PSE36) | 0 /* Reserved */ | | |
474 | f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) | | |
475 | F(FXSR) | F(FXSR_OPT) | f_gbpages | F(RDTSCP) | | |
476 | 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW) | |
477 | ); | |
478 | ||
479 | if (!tdp_enabled && IS_ENABLED(CONFIG_X86_64)) | |
480 | kvm_cpu_cap_set(X86_FEATURE_GBPAGES); | |
481 | ||
482 | kvm_cpu_cap_mask(CPUID_8000_0008_EBX, | |
483 | F(CLZERO) | F(XSAVEERPTR) | | |
484 | F(WBNOINVD) | F(AMD_IBPB) | F(AMD_IBRS) | F(AMD_SSBD) | F(VIRT_SSBD) | | |
485 | F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_STIBP_ALWAYS_ON) | |
486 | ); | |
487 | ||
93c380e7 SC |
488 | /* |
489 | * AMD has separate bits for each SPEC_CTRL bit. | |
490 | * arch/x86/kernel/cpu/bugs.c is kind enough to | |
491 | * record that in cpufeatures so use them. | |
492 | */ | |
493 | if (boot_cpu_has(X86_FEATURE_IBPB)) | |
494 | kvm_cpu_cap_set(X86_FEATURE_AMD_IBPB); | |
495 | if (boot_cpu_has(X86_FEATURE_IBRS)) | |
496 | kvm_cpu_cap_set(X86_FEATURE_AMD_IBRS); | |
497 | if (boot_cpu_has(X86_FEATURE_STIBP)) | |
498 | kvm_cpu_cap_set(X86_FEATURE_AMD_STIBP); | |
499 | if (boot_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD)) | |
500 | kvm_cpu_cap_set(X86_FEATURE_AMD_SSBD); | |
501 | if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
502 | kvm_cpu_cap_set(X86_FEATURE_AMD_SSB_NO); | |
503 | /* | |
504 | * The preference is to use SPEC CTRL MSR instead of the | |
505 | * VIRT_SPEC MSR. | |
506 | */ | |
507 | if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) && | |
508 | !boot_cpu_has(X86_FEATURE_AMD_SSBD)) | |
509 | kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD); | |
510 | ||
9b58b985 SC |
511 | /* |
512 | * Hide all SVM features by default, SVM will set the cap bits for | |
513 | * features it emulates and/or exposes for L1. | |
514 | */ | |
515 | kvm_cpu_cap_mask(CPUID_8000_000A_EDX, 0); | |
516 | ||
66a6950f SC |
517 | kvm_cpu_cap_mask(CPUID_C000_0001_EDX, |
518 | F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) | | |
519 | F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) | | |
520 | F(PMM) | F(PMM_EN) | |
521 | ); | |
522 | } | |
523 | EXPORT_SYMBOL_GPL(kvm_set_cpu_caps); | |
524 | ||
e53c95e8 SC |
525 | struct kvm_cpuid_array { |
526 | struct kvm_cpuid_entry2 *entries; | |
65b18914 | 527 | int maxnent; |
e53c95e8 SC |
528 | int nent; |
529 | }; | |
530 | ||
531 | static struct kvm_cpuid_entry2 *do_host_cpuid(struct kvm_cpuid_array *array, | |
aa10a7dc | 532 | u32 function, u32 index) |
00b27a3e | 533 | { |
e53c95e8 SC |
534 | struct kvm_cpuid_entry2 *entry; |
535 | ||
536 | if (array->nent >= array->maxnent) | |
aa10a7dc | 537 | return NULL; |
e53c95e8 SC |
538 | |
539 | entry = &array->entries[array->nent++]; | |
aa10a7dc | 540 | |
00b27a3e AK |
541 | entry->function = function; |
542 | entry->index = index; | |
ab8bcf64 PB |
543 | entry->flags = 0; |
544 | ||
00b27a3e AK |
545 | cpuid_count(entry->function, entry->index, |
546 | &entry->eax, &entry->ebx, &entry->ecx, &entry->edx); | |
d9aadaf6 PB |
547 | |
548 | switch (function) { | |
d9aadaf6 PB |
549 | case 4: |
550 | case 7: | |
551 | case 0xb: | |
552 | case 0xd: | |
a06dcd62 JM |
553 | case 0xf: |
554 | case 0x10: | |
555 | case 0x12: | |
d9aadaf6 | 556 | case 0x14: |
a06dcd62 JM |
557 | case 0x17: |
558 | case 0x18: | |
559 | case 0x1f: | |
d9aadaf6 PB |
560 | case 0x8000001d: |
561 | entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
562 | break; | |
563 | } | |
aa10a7dc SC |
564 | |
565 | return entry; | |
00b27a3e AK |
566 | } |
567 | ||
e53c95e8 | 568 | static int __do_cpuid_func_emulated(struct kvm_cpuid_array *array, u32 func) |
9c15bb1d | 569 | { |
7c7f9548 SC |
570 | struct kvm_cpuid_entry2 *entry; |
571 | ||
572 | if (array->nent >= array->maxnent) | |
573 | return -E2BIG; | |
e53c95e8 | 574 | |
7c7f9548 | 575 | entry = &array->entries[array->nent]; |
ab8bcf64 PB |
576 | entry->function = func; |
577 | entry->index = 0; | |
578 | entry->flags = 0; | |
579 | ||
84cffe49 BP |
580 | switch (func) { |
581 | case 0: | |
fb6d4d34 | 582 | entry->eax = 7; |
e53c95e8 | 583 | ++array->nent; |
84cffe49 BP |
584 | break; |
585 | case 1: | |
586 | entry->ecx = F(MOVBE); | |
e53c95e8 | 587 | ++array->nent; |
84cffe49 | 588 | break; |
fb6d4d34 PB |
589 | case 7: |
590 | entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
ab8bcf64 PB |
591 | entry->eax = 0; |
592 | entry->ecx = F(RDPID); | |
e53c95e8 | 593 | ++array->nent; |
84cffe49 BP |
594 | default: |
595 | break; | |
596 | } | |
597 | ||
9c15bb1d BP |
598 | return 0; |
599 | } | |
600 | ||
e53c95e8 | 601 | static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) |
00b27a3e | 602 | { |
e53c95e8 | 603 | struct kvm_cpuid_entry2 *entry; |
74fa0bc7 | 604 | int r, i, max_idx; |
00b27a3e | 605 | |
00b27a3e AK |
606 | /* all calls to cpuid_count() should be made on the same cpu */ |
607 | get_cpu(); | |
831bf664 SL |
608 | |
609 | r = -E2BIG; | |
610 | ||
e53c95e8 | 611 | entry = do_host_cpuid(array, function, 0); |
7c7f9548 | 612 | if (!entry) |
831bf664 SL |
613 | goto out; |
614 | ||
00b27a3e AK |
615 | switch (function) { |
616 | case 0: | |
a87f2d3a LX |
617 | /* Limited to the highest leaf implemented in KVM. */ |
618 | entry->eax = min(entry->eax, 0x1fU); | |
00b27a3e AK |
619 | break; |
620 | case 1: | |
bd791999 SC |
621 | cpuid_entry_override(entry, CPUID_1_EDX); |
622 | cpuid_entry_override(entry, CPUID_1_ECX); | |
00b27a3e | 623 | break; |
74fa0bc7 | 624 | case 2: |
c571a144 SC |
625 | /* |
626 | * On ancient CPUs, function 2 entries are STATEFUL. That is, | |
627 | * CPUID(function=2, index=0) may return different results each | |
628 | * time, with the least-significant byte in EAX enumerating the | |
629 | * number of times software should do CPUID(2, 0). | |
630 | * | |
7ff6c035 SC |
631 | * Modern CPUs, i.e. every CPU KVM has *ever* run on are less |
632 | * idiotic. Intel's SDM states that EAX & 0xff "will always | |
633 | * return 01H. Software should ignore this value and not | |
c571a144 SC |
634 | * interpret it as an informational descriptor", while AMD's |
635 | * APM states that CPUID(2) is reserved. | |
7ff6c035 SC |
636 | * |
637 | * WARN if a frankenstein CPU that supports virtualization and | |
638 | * a stateful CPUID.0x2 is encountered. | |
c571a144 | 639 | */ |
7ff6c035 | 640 | WARN_ON_ONCE((entry->eax & 0xff) > 1); |
00b27a3e | 641 | break; |
32a243df JM |
642 | /* functions 4 and 0x8000001d have additional index. */ |
643 | case 4: | |
c8629039 SC |
644 | case 0x8000001d: |
645 | /* | |
646 | * Read entries until the cache type in the previous entry is | |
647 | * zero, i.e. indicates an invalid entry. | |
648 | */ | |
e53c95e8 SC |
649 | for (i = 1; entry->eax & 0x1f; ++i) { |
650 | entry = do_host_cpuid(array, function, i); | |
651 | if (!entry) | |
0fc62671 | 652 | goto out; |
00b27a3e AK |
653 | } |
654 | break; | |
e453aa0f JK |
655 | case 6: /* Thermal management */ |
656 | entry->eax = 0x4; /* allow ARAT */ | |
657 | entry->ebx = 0; | |
658 | entry->ecx = 0; | |
659 | entry->edx = 0; | |
660 | break; | |
54d360d4 | 661 | /* function 7 has additional index. */ |
74fa0bc7 | 662 | case 7: |
09f628a0 | 663 | entry->eax = min(entry->eax, 1u); |
bd791999 SC |
664 | cpuid_entry_override(entry, CPUID_7_0_EBX); |
665 | cpuid_entry_override(entry, CPUID_7_ECX); | |
666 | cpuid_entry_override(entry, CPUID_7_EDX); | |
09f628a0 | 667 | |
bcf600ca SC |
668 | /* KVM only supports 0x7.0 and 0x7.1, capped above via min(). */ |
669 | if (entry->eax == 1) { | |
670 | entry = do_host_cpuid(array, function, 1); | |
e53c95e8 | 671 | if (!entry) |
54d360d4 PB |
672 | goto out; |
673 | ||
bd791999 | 674 | cpuid_entry_override(entry, CPUID_7_1_EAX); |
09f628a0 SC |
675 | entry->ebx = 0; |
676 | entry->ecx = 0; | |
677 | entry->edx = 0; | |
54d360d4 | 678 | } |
00b27a3e | 679 | break; |
00b27a3e AK |
680 | case 9: |
681 | break; | |
a6c06ed1 GN |
682 | case 0xa: { /* Architectural Performance Monitoring */ |
683 | struct x86_pmu_capability cap; | |
684 | union cpuid10_eax eax; | |
685 | union cpuid10_edx edx; | |
686 | ||
687 | perf_get_x86_pmu_capability(&cap); | |
688 | ||
689 | /* | |
690 | * Only support guest architectural pmu on a host | |
691 | * with architectural pmu. | |
692 | */ | |
693 | if (!cap.version) | |
694 | memset(&cap, 0, sizeof(cap)); | |
695 | ||
696 | eax.split.version_id = min(cap.version, 2); | |
697 | eax.split.num_counters = cap.num_counters_gp; | |
698 | eax.split.bit_width = cap.bit_width_gp; | |
699 | eax.split.mask_length = cap.events_mask_len; | |
700 | ||
2e8cd7a3 | 701 | edx.split.num_counters_fixed = min(cap.num_counters_fixed, MAX_FIXED_COUNTERS); |
a6c06ed1 | 702 | edx.split.bit_width_fixed = cap.bit_width_fixed; |
cadbaa03 SE |
703 | edx.split.anythread_deprecated = 1; |
704 | edx.split.reserved1 = 0; | |
705 | edx.split.reserved2 = 0; | |
a6c06ed1 GN |
706 | |
707 | entry->eax = eax.full; | |
708 | entry->ebx = cap.events_mask; | |
709 | entry->ecx = 0; | |
710 | entry->edx = edx.full; | |
711 | break; | |
712 | } | |
a87f2d3a LX |
713 | /* |
714 | * Per Intel's SDM, the 0x1f is a superset of 0xb, | |
715 | * thus they can be handled by common code. | |
716 | */ | |
717 | case 0x1f: | |
74fa0bc7 | 718 | case 0xb: |
a1a640b8 | 719 | /* |
e53c95e8 SC |
720 | * Populate entries until the level type (ECX[15:8]) of the |
721 | * previous entry is zero. Note, CPUID EAX.{0x1f,0xb}.0 is | |
722 | * the starting entry, filled by the primary do_host_cpuid(). | |
a1a640b8 | 723 | */ |
e53c95e8 SC |
724 | for (i = 1; entry->ecx & 0xff00; ++i) { |
725 | entry = do_host_cpuid(array, function, i); | |
726 | if (!entry) | |
831bf664 | 727 | goto out; |
00b27a3e AK |
728 | } |
729 | break; | |
cfc48181 SC |
730 | case 0xd: |
731 | entry->eax &= supported_xcr0; | |
732 | entry->ebx = xstate_required_size(supported_xcr0, false); | |
e08e8336 | 733 | entry->ecx = entry->ebx; |
cfc48181 SC |
734 | entry->edx &= supported_xcr0 >> 32; |
735 | if (!supported_xcr0) | |
b65d6e17 PB |
736 | break; |
737 | ||
e53c95e8 SC |
738 | entry = do_host_cpuid(array, function, 1); |
739 | if (!entry) | |
3dc4a9cf SC |
740 | goto out; |
741 | ||
bd791999 | 742 | cpuid_entry_override(entry, CPUID_D_1_EAX); |
e53c95e8 | 743 | if (entry->eax & (F(XSAVES)|F(XSAVEC))) |
408e9a31 PB |
744 | entry->ebx = xstate_required_size(supported_xcr0 | supported_xss, |
745 | true); | |
746 | else { | |
747 | WARN_ON_ONCE(supported_xss != 0); | |
e53c95e8 | 748 | entry->ebx = 0; |
408e9a31 PB |
749 | } |
750 | entry->ecx &= supported_xss; | |
751 | entry->edx &= supported_xss >> 32; | |
3dc4a9cf | 752 | |
0eee8f9d | 753 | for (i = 2; i < 64; ++i) { |
408e9a31 PB |
754 | bool s_state; |
755 | if (supported_xcr0 & BIT_ULL(i)) | |
756 | s_state = false; | |
757 | else if (supported_xss & BIT_ULL(i)) | |
758 | s_state = true; | |
759 | else | |
1893c941 | 760 | continue; |
3dc4a9cf | 761 | |
0eee8f9d | 762 | entry = do_host_cpuid(array, function, i); |
e53c95e8 | 763 | if (!entry) |
831bf664 SL |
764 | goto out; |
765 | ||
91001d40 | 766 | /* |
cfc48181 | 767 | * The supported check above should have filtered out |
408e9a31 | 768 | * invalid sub-leafs. Only valid sub-leafs should |
91001d40 | 769 | * reach this point, and they should have a non-zero |
408e9a31 PB |
770 | * save state size. Furthermore, check whether the |
771 | * processor agrees with supported_xcr0/supported_xss | |
772 | * on whether this is an XCR0- or IA32_XSS-managed area. | |
91001d40 | 773 | */ |
408e9a31 | 774 | if (WARN_ON_ONCE(!entry->eax || (entry->ecx & 0x1) != s_state)) { |
e53c95e8 | 775 | --array->nent; |
3dc4a9cf | 776 | continue; |
8b2fc445 | 777 | } |
e53c95e8 | 778 | entry->edx = 0; |
00b27a3e AK |
779 | } |
780 | break; | |
86f5201d | 781 | /* Intel PT */ |
74fa0bc7 | 782 | case 0x14: |
dd69cc25 | 783 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) { |
7392079c | 784 | entry->eax = entry->ebx = entry->ecx = entry->edx = 0; |
86f5201d | 785 | break; |
7392079c | 786 | } |
86f5201d | 787 | |
74fa0bc7 | 788 | for (i = 1, max_idx = entry->eax; i <= max_idx; ++i) { |
e53c95e8 | 789 | if (!do_host_cpuid(array, function, i)) |
86f5201d | 790 | goto out; |
86f5201d CP |
791 | } |
792 | break; | |
00b27a3e | 793 | case KVM_CPUID_SIGNATURE: { |
326d07cb MK |
794 | static const char signature[12] = "KVMKVMKVM\0\0"; |
795 | const u32 *sigptr = (const u32 *)signature; | |
57c22e5f | 796 | entry->eax = KVM_CPUID_FEATURES; |
00b27a3e AK |
797 | entry->ebx = sigptr[0]; |
798 | entry->ecx = sigptr[1]; | |
799 | entry->edx = sigptr[2]; | |
800 | break; | |
801 | } | |
802 | case KVM_CPUID_FEATURES: | |
803 | entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) | | |
804 | (1 << KVM_FEATURE_NOP_IO_DELAY) | | |
805 | (1 << KVM_FEATURE_CLOCKSOURCE2) | | |
806 | (1 << KVM_FEATURE_ASYNC_PF) | | |
ae7a2a3f | 807 | (1 << KVM_FEATURE_PV_EOI) | |
6aef266c | 808 | (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT) | |
f38a7b75 | 809 | (1 << KVM_FEATURE_PV_UNHALT) | |
fe2a3027 | 810 | (1 << KVM_FEATURE_PV_TLB_FLUSH) | |
4180bf1b | 811 | (1 << KVM_FEATURE_ASYNC_PF_VMEXIT) | |
2d5ba19b | 812 | (1 << KVM_FEATURE_PV_SEND_IPI) | |
32b72ecc | 813 | (1 << KVM_FEATURE_POLL_CONTROL) | |
72de5fa4 VK |
814 | (1 << KVM_FEATURE_PV_SCHED_YIELD) | |
815 | (1 << KVM_FEATURE_ASYNC_PF_INT); | |
00b27a3e AK |
816 | |
817 | if (sched_info_on()) | |
818 | entry->eax |= (1 << KVM_FEATURE_STEAL_TIME); | |
819 | ||
820 | entry->ebx = 0; | |
821 | entry->ecx = 0; | |
822 | entry->edx = 0; | |
823 | break; | |
824 | case 0x80000000: | |
8765d753 | 825 | entry->eax = min(entry->eax, 0x8000001f); |
00b27a3e AK |
826 | break; |
827 | case 0x80000001: | |
bd791999 SC |
828 | cpuid_entry_override(entry, CPUID_8000_0001_EDX); |
829 | cpuid_entry_override(entry, CPUID_8000_0001_ECX); | |
00b27a3e | 830 | break; |
43d05de2 EN |
831 | case 0x80000006: |
832 | /* L2 cache and TLB: pass through host info. */ | |
833 | break; | |
e4c9a5a1 MT |
834 | case 0x80000007: /* Advanced power management */ |
835 | /* invariant TSC is CPUID.80000007H:EDX[8] */ | |
836 | entry->edx &= (1 << 8); | |
837 | /* mask against host */ | |
838 | entry->edx &= boot_cpu_data.x86_power; | |
839 | entry->eax = entry->ebx = entry->ecx = 0; | |
840 | break; | |
00b27a3e AK |
841 | case 0x80000008: { |
842 | unsigned g_phys_as = (entry->eax >> 16) & 0xff; | |
843 | unsigned virt_as = max((entry->eax >> 8) & 0xff, 48U); | |
844 | unsigned phys_as = entry->eax & 0xff; | |
845 | ||
846 | if (!g_phys_as) | |
847 | g_phys_as = phys_as; | |
848 | entry->eax = g_phys_as | (virt_as << 8); | |
15d45071 | 849 | entry->edx = 0; |
bd791999 | 850 | cpuid_entry_override(entry, CPUID_8000_0008_EBX); |
00b27a3e AK |
851 | break; |
852 | } | |
25703874 SC |
853 | case 0x8000000A: |
854 | if (!kvm_cpu_cap_has(X86_FEATURE_SVM)) { | |
855 | entry->eax = entry->ebx = entry->ecx = entry->edx = 0; | |
856 | break; | |
857 | } | |
858 | entry->eax = 1; /* SVM revision 1 */ | |
859 | entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper | |
860 | ASID emulation to nested SVM */ | |
861 | entry->ecx = 0; /* Reserved */ | |
862 | cpuid_entry_override(entry, CPUID_8000_000A_EDX); | |
863 | break; | |
00b27a3e AK |
864 | case 0x80000019: |
865 | entry->ecx = entry->edx = 0; | |
866 | break; | |
867 | case 0x8000001a: | |
382409b4 | 868 | case 0x8000001e: |
00b27a3e | 869 | break; |
c1de0f25 PG |
870 | /* Support memory encryption cpuid if host supports it */ |
871 | case 0x8000001F: | |
872 | if (!boot_cpu_has(X86_FEATURE_SEV)) | |
873 | entry->eax = entry->ebx = entry->ecx = entry->edx = 0; | |
874 | break; | |
00b27a3e AK |
875 | /*Add support for Centaur's CPUID instruction*/ |
876 | case 0xC0000000: | |
877 | /*Just support up to 0xC0000004 now*/ | |
878 | entry->eax = min(entry->eax, 0xC0000004); | |
879 | break; | |
880 | case 0xC0000001: | |
bd791999 | 881 | cpuid_entry_override(entry, CPUID_C000_0001_EDX); |
00b27a3e AK |
882 | break; |
883 | case 3: /* Processor serial number */ | |
884 | case 5: /* MONITOR/MWAIT */ | |
00b27a3e AK |
885 | case 0xC0000002: |
886 | case 0xC0000003: | |
887 | case 0xC0000004: | |
888 | default: | |
889 | entry->eax = entry->ebx = entry->ecx = entry->edx = 0; | |
890 | break; | |
891 | } | |
892 | ||
831bf664 SL |
893 | r = 0; |
894 | ||
895 | out: | |
00b27a3e | 896 | put_cpu(); |
831bf664 SL |
897 | |
898 | return r; | |
00b27a3e AK |
899 | } |
900 | ||
e53c95e8 SC |
901 | static int do_cpuid_func(struct kvm_cpuid_array *array, u32 func, |
902 | unsigned int type) | |
9c15bb1d BP |
903 | { |
904 | if (type == KVM_GET_EMULATED_CPUID) | |
e53c95e8 | 905 | return __do_cpuid_func_emulated(array, func); |
9c15bb1d | 906 | |
e53c95e8 | 907 | return __do_cpuid_func(array, func); |
9c15bb1d BP |
908 | } |
909 | ||
8b86079c | 910 | #define CENTAUR_CPUID_SIGNATURE 0xC0000000 |
831bf664 | 911 | |
e53c95e8 SC |
912 | static int get_cpuid_func(struct kvm_cpuid_array *array, u32 func, |
913 | unsigned int type) | |
619a17f1 SC |
914 | { |
915 | u32 limit; | |
916 | int r; | |
917 | ||
8b86079c SC |
918 | if (func == CENTAUR_CPUID_SIGNATURE && |
919 | boot_cpu_data.x86_vendor != X86_VENDOR_CENTAUR) | |
920 | return 0; | |
921 | ||
e53c95e8 | 922 | r = do_cpuid_func(array, func, type); |
619a17f1 SC |
923 | if (r) |
924 | return r; | |
925 | ||
e53c95e8 | 926 | limit = array->entries[array->nent - 1].eax; |
619a17f1 | 927 | for (func = func + 1; func <= limit; ++func) { |
e53c95e8 | 928 | r = do_cpuid_func(array, func, type); |
619a17f1 SC |
929 | if (r) |
930 | break; | |
931 | } | |
932 | ||
933 | return r; | |
934 | } | |
935 | ||
9c15bb1d BP |
936 | static bool sanity_check_entries(struct kvm_cpuid_entry2 __user *entries, |
937 | __u32 num_entries, unsigned int ioctl_type) | |
938 | { | |
939 | int i; | |
1b2ca422 | 940 | __u32 pad[3]; |
9c15bb1d BP |
941 | |
942 | if (ioctl_type != KVM_GET_EMULATED_CPUID) | |
943 | return false; | |
944 | ||
945 | /* | |
946 | * We want to make sure that ->padding is being passed clean from | |
947 | * userspace in case we want to use it for something in the future. | |
948 | * | |
949 | * Sadly, this wasn't enforced for KVM_GET_SUPPORTED_CPUID and so we | |
950 | * have to give ourselves satisfied only with the emulated side. /me | |
951 | * sheds a tear. | |
952 | */ | |
953 | for (i = 0; i < num_entries; i++) { | |
1b2ca422 BP |
954 | if (copy_from_user(pad, entries[i].padding, sizeof(pad))) |
955 | return true; | |
956 | ||
957 | if (pad[0] || pad[1] || pad[2]) | |
9c15bb1d BP |
958 | return true; |
959 | } | |
960 | return false; | |
961 | } | |
962 | ||
963 | int kvm_dev_ioctl_get_cpuid(struct kvm_cpuid2 *cpuid, | |
964 | struct kvm_cpuid_entry2 __user *entries, | |
965 | unsigned int type) | |
00b27a3e | 966 | { |
8b86079c SC |
967 | static const u32 funcs[] = { |
968 | 0, 0x80000000, CENTAUR_CPUID_SIGNATURE, KVM_CPUID_SIGNATURE, | |
831bf664 | 969 | }; |
00b27a3e | 970 | |
e53c95e8 SC |
971 | struct kvm_cpuid_array array = { |
972 | .nent = 0, | |
e53c95e8 SC |
973 | }; |
974 | int r, i; | |
d5a661d1 | 975 | |
00b27a3e | 976 | if (cpuid->nent < 1) |
d5a661d1 | 977 | return -E2BIG; |
00b27a3e AK |
978 | if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) |
979 | cpuid->nent = KVM_MAX_CPUID_ENTRIES; | |
9c15bb1d BP |
980 | |
981 | if (sanity_check_entries(entries, cpuid->nent, type)) | |
982 | return -EINVAL; | |
983 | ||
e53c95e8 | 984 | array.entries = vzalloc(array_size(sizeof(struct kvm_cpuid_entry2), |
fad953ce | 985 | cpuid->nent)); |
e53c95e8 | 986 | if (!array.entries) |
d5a661d1 | 987 | return -ENOMEM; |
00b27a3e | 988 | |
65b18914 XL |
989 | array.maxnent = cpuid->nent; |
990 | ||
8b86079c | 991 | for (i = 0; i < ARRAY_SIZE(funcs); i++) { |
e53c95e8 | 992 | r = get_cpuid_func(&array, funcs[i], type); |
831bf664 | 993 | if (r) |
00b27a3e AK |
994 | goto out_free; |
995 | } | |
e53c95e8 | 996 | cpuid->nent = array.nent; |
00b27a3e | 997 | |
e53c95e8 SC |
998 | if (copy_to_user(entries, array.entries, |
999 | array.nent * sizeof(struct kvm_cpuid_entry2))) | |
d5a661d1 | 1000 | r = -EFAULT; |
00b27a3e AK |
1001 | |
1002 | out_free: | |
e53c95e8 | 1003 | vfree(array.entries); |
00b27a3e AK |
1004 | return r; |
1005 | } | |
1006 | ||
00b27a3e AK |
1007 | struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu, |
1008 | u32 function, u32 index) | |
1009 | { | |
f69858fc VK |
1010 | return cpuid_entry2_find(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent, |
1011 | function, index); | |
00b27a3e AK |
1012 | } |
1013 | EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry); | |
1014 | ||
00b27a3e | 1015 | /* |
8d892311 SC |
1016 | * Intel CPUID semantics treats any query for an out-of-range leaf as if the |
1017 | * highest basic leaf (i.e. CPUID.0H:EAX) were requested. AMD CPUID semantics | |
1018 | * returns all zeroes for any undefined leaf, whether or not the leaf is in | |
1019 | * range. Centaur/VIA follows Intel semantics. | |
1020 | * | |
1021 | * A leaf is considered out-of-range if its function is higher than the maximum | |
1022 | * supported leaf of its associated class or if its associated class does not | |
1023 | * exist. | |
1024 | * | |
1025 | * There are three primary classes to be considered, with their respective | |
1026 | * ranges described as "<base> - <top>[,<base2> - <top2>] inclusive. A primary | |
1027 | * class exists if a guest CPUID entry for its <base> leaf exists. For a given | |
1028 | * class, CPUID.<base>.EAX contains the max supported leaf for the class. | |
1029 | * | |
1030 | * - Basic: 0x00000000 - 0x3fffffff, 0x50000000 - 0x7fffffff | |
1031 | * - Hypervisor: 0x40000000 - 0x4fffffff | |
1032 | * - Extended: 0x80000000 - 0xbfffffff | |
1033 | * - Centaur: 0xc0000000 - 0xcfffffff | |
1034 | * | |
1035 | * The Hypervisor class is further subdivided into sub-classes that each act as | |
1036 | * their own indepdent class associated with a 0x100 byte range. E.g. if Qemu | |
1037 | * is advertising support for both HyperV and KVM, the resulting Hypervisor | |
1038 | * CPUID sub-classes are: | |
1039 | * | |
1040 | * - HyperV: 0x40000000 - 0x400000ff | |
1041 | * - KVM: 0x40000100 - 0x400001ff | |
00b27a3e | 1042 | */ |
09c7431e SC |
1043 | static struct kvm_cpuid_entry2 * |
1044 | get_out_of_range_cpuid_entry(struct kvm_vcpu *vcpu, u32 *fn_ptr, u32 index) | |
00b27a3e | 1045 | { |
8d892311 | 1046 | struct kvm_cpuid_entry2 *basic, *class; |
09c7431e | 1047 | u32 function = *fn_ptr; |
8d892311 SC |
1048 | |
1049 | basic = kvm_find_cpuid_entry(vcpu, 0, 0); | |
1050 | if (!basic) | |
09c7431e SC |
1051 | return NULL; |
1052 | ||
1053 | if (is_guest_vendor_amd(basic->ebx, basic->ecx, basic->edx) || | |
1054 | is_guest_vendor_hygon(basic->ebx, basic->ecx, basic->edx)) | |
1055 | return NULL; | |
8d892311 SC |
1056 | |
1057 | if (function >= 0x40000000 && function <= 0x4fffffff) | |
1058 | class = kvm_find_cpuid_entry(vcpu, function & 0xffffff00, 0); | |
1059 | else if (function >= 0xc0000000) | |
1060 | class = kvm_find_cpuid_entry(vcpu, 0xc0000000, 0); | |
1061 | else | |
1062 | class = kvm_find_cpuid_entry(vcpu, function & 0x80000000, 0); | |
43561123 | 1063 | |
09c7431e SC |
1064 | if (class && function <= class->eax) |
1065 | return NULL; | |
1066 | ||
1067 | /* | |
1068 | * Leaf specific adjustments are also applied when redirecting to the | |
1069 | * max basic entry, e.g. if the max basic leaf is 0xb but there is no | |
1070 | * entry for CPUID.0xb.index (see below), then the output value for EDX | |
1071 | * needs to be pulled from CPUID.0xb.1. | |
1072 | */ | |
1073 | *fn_ptr = basic->eax; | |
1074 | ||
1075 | /* | |
1076 | * The class does not exist or the requested function is out of range; | |
1077 | * the effective CPUID entry is the max basic leaf. Note, the index of | |
1078 | * the original requested leaf is observed! | |
1079 | */ | |
1080 | return kvm_find_cpuid_entry(vcpu, basic->eax, index); | |
00b27a3e AK |
1081 | } |
1082 | ||
e911eb3b | 1083 | bool kvm_cpuid(struct kvm_vcpu *vcpu, u32 *eax, u32 *ebx, |
f91af517 | 1084 | u32 *ecx, u32 *edx, bool exact_only) |
00b27a3e | 1085 | { |
b7fb8488 | 1086 | u32 orig_function = *eax, function = *eax, index = *ecx; |
43561123 | 1087 | struct kvm_cpuid_entry2 *entry; |
2b110b61 | 1088 | bool exact, used_max_basic = false; |
e911eb3b | 1089 | |
43561123 | 1090 | entry = kvm_find_cpuid_entry(vcpu, function, index); |
f91af517 | 1091 | exact = !!entry; |
09c7431e | 1092 | |
2b110b61 | 1093 | if (!entry && !exact_only) { |
09c7431e | 1094 | entry = get_out_of_range_cpuid_entry(vcpu, &function, index); |
2b110b61 SC |
1095 | used_max_basic = !!entry; |
1096 | } | |
09c7431e | 1097 | |
43561123 JM |
1098 | if (entry) { |
1099 | *eax = entry->eax; | |
1100 | *ebx = entry->ebx; | |
1101 | *ecx = entry->ecx; | |
1102 | *edx = entry->edx; | |
edef5c36 PB |
1103 | if (function == 7 && index == 0) { |
1104 | u64 data; | |
1105 | if (!__kvm_get_msr(vcpu, MSR_IA32_TSX_CTRL, &data, true) && | |
1106 | (data & TSX_CTRL_CPUID_CLEAR)) | |
1107 | *ebx &= ~(F(RTM) | F(HLE)); | |
1108 | } | |
43561123 | 1109 | } else { |
62046e5a | 1110 | *eax = *ebx = *ecx = *edx = 0; |
43561123 JM |
1111 | /* |
1112 | * When leaf 0BH or 1FH is defined, CL is pass-through | |
1113 | * and EDX is always the x2APIC ID, even for undefined | |
1114 | * subleaves. Index 1 will exist iff the leaf is | |
1115 | * implemented, so we pass through CL iff leaf 1 | |
1116 | * exists. EDX can be copied from any existing index. | |
1117 | */ | |
1118 | if (function == 0xb || function == 0x1f) { | |
1119 | entry = kvm_find_cpuid_entry(vcpu, function, 1); | |
1120 | if (entry) { | |
1121 | *ecx = index & 0xff; | |
1122 | *edx = entry->edx; | |
1123 | } | |
1124 | } | |
1125 | } | |
2b110b61 SC |
1126 | trace_kvm_cpuid(orig_function, index, *eax, *ebx, *ecx, *edx, exact, |
1127 | used_max_basic); | |
f91af517 | 1128 | return exact; |
62046e5a | 1129 | } |
66f7b72e | 1130 | EXPORT_SYMBOL_GPL(kvm_cpuid); |
62046e5a | 1131 | |
6a908b62 | 1132 | int kvm_emulate_cpuid(struct kvm_vcpu *vcpu) |
62046e5a | 1133 | { |
1e13175b | 1134 | u32 eax, ebx, ecx, edx; |
62046e5a | 1135 | |
db2336a8 KH |
1136 | if (cpuid_fault_enabled(vcpu) && !kvm_require_cpl(vcpu, 0)) |
1137 | return 1; | |
1138 | ||
de3cd117 SC |
1139 | eax = kvm_rax_read(vcpu); |
1140 | ecx = kvm_rcx_read(vcpu); | |
f91af517 | 1141 | kvm_cpuid(vcpu, &eax, &ebx, &ecx, &edx, false); |
de3cd117 SC |
1142 | kvm_rax_write(vcpu, eax); |
1143 | kvm_rbx_write(vcpu, ebx); | |
1144 | kvm_rcx_write(vcpu, ecx); | |
1145 | kvm_rdx_write(vcpu, edx); | |
6affcbed | 1146 | return kvm_skip_emulated_instruction(vcpu); |
00b27a3e AK |
1147 | } |
1148 | EXPORT_SYMBOL_GPL(kvm_emulate_cpuid); |