Commit | Line | Data |
---|---|---|
dc1e35c6 SS |
1 | /* |
2 | * xsave/xrstor support. | |
3 | * | |
4 | * Author: Suresh Siddha <suresh.b.siddha@intel.com> | |
5 | */ | |
c767a54b JP |
6 | |
7 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
8 | ||
dc1e35c6 SS |
9 | #include <linux/bootmem.h> |
10 | #include <linux/compat.h> | |
11 | #include <asm/i387.h> | |
1361b83a | 12 | #include <asm/fpu-internal.h> |
72a671ce | 13 | #include <asm/sigframe.h> |
6152e4b1 | 14 | #include <asm/xcr.h> |
dc1e35c6 SS |
15 | |
16 | /* | |
17 | * Supported feature mask by the CPU and the kernel. | |
18 | */ | |
6152e4b1 | 19 | u64 pcntxt_mask; |
dc1e35c6 | 20 | |
45c2d7f4 RR |
21 | /* |
22 | * Represents init state for the supported extended state. | |
23 | */ | |
304bceda | 24 | struct xsave_struct *init_xstate_buf; |
45c2d7f4 | 25 | |
72a671ce | 26 | static struct _fpx_sw_bytes fx_sw_reserved, fx_sw_reserved_ia32; |
a1488f8b SS |
27 | static unsigned int *xstate_offsets, *xstate_sizes, xstate_features; |
28 | ||
29104e10 SS |
29 | /* |
30 | * If a processor implementation discern that a processor state component is | |
31 | * in its initialized state it may modify the corresponding bit in the | |
32 | * xsave_hdr.xstate_bv as '0', with out modifying the corresponding memory | |
33 | * layout in the case of xsaveopt. While presenting the xstate information to | |
34 | * the user, we always ensure that the memory layout of a feature will be in | |
35 | * the init state if the corresponding header bit is zero. This is to ensure | |
36 | * that the user doesn't see some stale state in the memory layout during | |
37 | * signal handling, debugging etc. | |
38 | */ | |
39 | void __sanitize_i387_state(struct task_struct *tsk) | |
40 | { | |
29104e10 | 41 | struct i387_fxsave_struct *fx = &tsk->thread.fpu.state->fxsave; |
72a671ce SS |
42 | int feature_bit = 0x2; |
43 | u64 xstate_bv; | |
29104e10 SS |
44 | |
45 | if (!fx) | |
46 | return; | |
47 | ||
29104e10 SS |
48 | xstate_bv = tsk->thread.fpu.state->xsave.xsave_hdr.xstate_bv; |
49 | ||
50 | /* | |
51 | * None of the feature bits are in init state. So nothing else | |
0d2eb44f | 52 | * to do for us, as the memory layout is up to date. |
29104e10 SS |
53 | */ |
54 | if ((xstate_bv & pcntxt_mask) == pcntxt_mask) | |
55 | return; | |
56 | ||
57 | /* | |
58 | * FP is in init state | |
59 | */ | |
60 | if (!(xstate_bv & XSTATE_FP)) { | |
61 | fx->cwd = 0x37f; | |
62 | fx->swd = 0; | |
63 | fx->twd = 0; | |
64 | fx->fop = 0; | |
65 | fx->rip = 0; | |
66 | fx->rdp = 0; | |
67 | memset(&fx->st_space[0], 0, 128); | |
68 | } | |
69 | ||
70 | /* | |
71 | * SSE is in init state | |
72 | */ | |
73 | if (!(xstate_bv & XSTATE_SSE)) | |
74 | memset(&fx->xmm_space[0], 0, 256); | |
75 | ||
76 | xstate_bv = (pcntxt_mask & ~xstate_bv) >> 2; | |
77 | ||
78 | /* | |
79 | * Update all the other memory layouts for which the corresponding | |
80 | * header bit is in the init state. | |
81 | */ | |
82 | while (xstate_bv) { | |
83 | if (xstate_bv & 0x1) { | |
84 | int offset = xstate_offsets[feature_bit]; | |
85 | int size = xstate_sizes[feature_bit]; | |
86 | ||
87 | memcpy(((void *) fx) + offset, | |
88 | ((void *) init_xstate_buf) + offset, | |
89 | size); | |
90 | } | |
91 | ||
92 | xstate_bv >>= 1; | |
93 | feature_bit++; | |
94 | } | |
95 | } | |
96 | ||
c37b5efe SS |
97 | /* |
98 | * Check for the presence of extended state information in the | |
99 | * user fpstate pointer in the sigcontext. | |
100 | */ | |
72a671ce SS |
101 | static inline int check_for_xstate(struct i387_fxsave_struct __user *buf, |
102 | void __user *fpstate, | |
103 | struct _fpx_sw_bytes *fx_sw) | |
c37b5efe SS |
104 | { |
105 | int min_xstate_size = sizeof(struct i387_fxsave_struct) + | |
106 | sizeof(struct xsave_hdr_struct); | |
107 | unsigned int magic2; | |
c37b5efe | 108 | |
72a671ce SS |
109 | if (__copy_from_user(fx_sw, &buf->sw_reserved[0], sizeof(*fx_sw))) |
110 | return -1; | |
c37b5efe | 111 | |
72a671ce SS |
112 | /* Check for the first magic field and other error scenarios. */ |
113 | if (fx_sw->magic1 != FP_XSTATE_MAGIC1 || | |
114 | fx_sw->xstate_size < min_xstate_size || | |
115 | fx_sw->xstate_size > xstate_size || | |
116 | fx_sw->xstate_size > fx_sw->extended_size) | |
117 | return -1; | |
c37b5efe | 118 | |
c37b5efe SS |
119 | /* |
120 | * Check for the presence of second magic word at the end of memory | |
121 | * layout. This detects the case where the user just copied the legacy | |
122 | * fpstate layout with out copying the extended state information | |
123 | * in the memory layout. | |
124 | */ | |
72a671ce SS |
125 | if (__get_user(magic2, (__u32 __user *)(fpstate + fx_sw->xstate_size)) |
126 | || magic2 != FP_XSTATE_MAGIC2) | |
127 | return -1; | |
c37b5efe SS |
128 | |
129 | return 0; | |
130 | } | |
131 | ||
ab513701 SS |
132 | /* |
133 | * Signal frame handlers. | |
134 | */ | |
72a671ce SS |
135 | static inline int save_fsave_header(struct task_struct *tsk, void __user *buf) |
136 | { | |
137 | if (use_fxsr()) { | |
138 | struct xsave_struct *xsave = &tsk->thread.fpu.state->xsave; | |
139 | struct user_i387_ia32_struct env; | |
140 | struct _fpstate_ia32 __user *fp = buf; | |
ab513701 | 141 | |
72a671ce SS |
142 | convert_from_fxsr(&env, tsk); |
143 | ||
144 | if (__copy_to_user(buf, &env, sizeof(env)) || | |
145 | __put_user(xsave->i387.swd, &fp->status) || | |
146 | __put_user(X86_FXSR_MAGIC, &fp->magic)) | |
147 | return -1; | |
148 | } else { | |
149 | struct i387_fsave_struct __user *fp = buf; | |
150 | u32 swd; | |
151 | if (__get_user(swd, &fp->swd) || __put_user(swd, &fp->status)) | |
152 | return -1; | |
153 | } | |
154 | ||
155 | return 0; | |
156 | } | |
157 | ||
158 | static inline int save_xstate_epilog(void __user *buf, int ia32_frame) | |
ab513701 | 159 | { |
72a671ce SS |
160 | struct xsave_struct __user *x = buf; |
161 | struct _fpx_sw_bytes *sw_bytes; | |
162 | u32 xstate_bv; | |
163 | int err; | |
ab513701 | 164 | |
72a671ce SS |
165 | /* Setup the bytes not touched by the [f]xsave and reserved for SW. */ |
166 | sw_bytes = ia32_frame ? &fx_sw_reserved_ia32 : &fx_sw_reserved; | |
167 | err = __copy_to_user(&x->i387.sw_reserved, sw_bytes, sizeof(*sw_bytes)); | |
ab513701 | 168 | |
72a671ce SS |
169 | if (!use_xsave()) |
170 | return err; | |
ab513701 | 171 | |
72a671ce | 172 | err |= __put_user(FP_XSTATE_MAGIC2, (__u32 *)(buf + xstate_size)); |
ab513701 | 173 | |
72a671ce SS |
174 | /* |
175 | * Read the xstate_bv which we copied (directly from the cpu or | |
176 | * from the state in task struct) to the user buffers. | |
177 | */ | |
178 | err |= __get_user(xstate_bv, (__u32 *)&x->xsave_hdr.xstate_bv); | |
06c38d5e | 179 | |
72a671ce SS |
180 | /* |
181 | * For legacy compatible, we always set FP/SSE bits in the bit | |
182 | * vector while saving the state to the user context. This will | |
183 | * enable us capturing any changes(during sigreturn) to | |
184 | * the FP/SSE bits by the legacy applications which don't touch | |
185 | * xstate_bv in the xsave header. | |
186 | * | |
187 | * xsave aware apps can change the xstate_bv in the xsave | |
188 | * header as well as change any contents in the memory layout. | |
189 | * xrestore as part of sigreturn will capture all the changes. | |
190 | */ | |
191 | xstate_bv |= XSTATE_FPSSE; | |
c37b5efe | 192 | |
72a671ce SS |
193 | err |= __put_user(xstate_bv, (__u32 *)&x->xsave_hdr.xstate_bv); |
194 | ||
195 | return err; | |
196 | } | |
197 | ||
198 | static inline int save_user_xstate(struct xsave_struct __user *buf) | |
199 | { | |
200 | int err; | |
201 | ||
202 | if (use_xsave()) | |
203 | err = xsave_user(buf); | |
204 | else if (use_fxsr()) | |
205 | err = fxsave_user((struct i387_fxsave_struct __user *) buf); | |
206 | else | |
207 | err = fsave_user((struct i387_fsave_struct __user *) buf); | |
208 | ||
209 | if (unlikely(err) && __clear_user(buf, xstate_size)) | |
210 | err = -EFAULT; | |
211 | return err; | |
212 | } | |
213 | ||
214 | /* | |
215 | * Save the fpu, extended register state to the user signal frame. | |
216 | * | |
217 | * 'buf_fx' is the 64-byte aligned pointer at which the [f|fx|x]save | |
218 | * state is copied. | |
219 | * 'buf' points to the 'buf_fx' or to the fsave header followed by 'buf_fx'. | |
220 | * | |
221 | * buf == buf_fx for 64-bit frames and 32-bit fsave frame. | |
222 | * buf != buf_fx for 32-bit frames with fxstate. | |
223 | * | |
224 | * If the fpu, extended register state is live, save the state directly | |
225 | * to the user frame pointed by the aligned pointer 'buf_fx'. Otherwise, | |
226 | * copy the thread's fpu state to the user frame starting at 'buf_fx'. | |
227 | * | |
228 | * If this is a 32-bit frame with fxstate, put a fsave header before | |
229 | * the aligned state at 'buf_fx'. | |
230 | * | |
231 | * For [f]xsave state, update the SW reserved fields in the [f]xsave frame | |
232 | * indicating the absence/presence of the extended state to the user. | |
233 | */ | |
234 | int save_xstate_sig(void __user *buf, void __user *buf_fx, int size) | |
235 | { | |
236 | struct xsave_struct *xsave = ¤t->thread.fpu.state->xsave; | |
237 | struct task_struct *tsk = current; | |
238 | int ia32_fxstate = (buf != buf_fx); | |
239 | ||
240 | ia32_fxstate &= (config_enabled(CONFIG_X86_32) || | |
241 | config_enabled(CONFIG_IA32_EMULATION)); | |
242 | ||
243 | if (!access_ok(VERIFY_WRITE, buf, size)) | |
244 | return -EACCES; | |
245 | ||
60e019eb | 246 | if (!static_cpu_has(X86_FEATURE_FPU)) |
72a671ce SS |
247 | return fpregs_soft_get(current, NULL, 0, |
248 | sizeof(struct user_i387_ia32_struct), NULL, | |
249 | (struct _fpstate_ia32 __user *) buf) ? -1 : 1; | |
250 | ||
251 | if (user_has_fpu()) { | |
252 | /* Save the live register state to the user directly. */ | |
253 | if (save_user_xstate(buf_fx)) | |
254 | return -1; | |
255 | /* Update the thread's fxstate to save the fsave header. */ | |
256 | if (ia32_fxstate) | |
257 | fpu_fxsave(&tsk->thread.fpu); | |
ab513701 | 258 | } else { |
29104e10 | 259 | sanitize_i387_state(tsk); |
72a671ce | 260 | if (__copy_to_user(buf_fx, xsave, xstate_size)) |
ab513701 SS |
261 | return -1; |
262 | } | |
c37b5efe | 263 | |
72a671ce SS |
264 | /* Save the fsave header for the 32-bit frames. */ |
265 | if ((ia32_fxstate || !use_fxsr()) && save_fsave_header(tsk, buf)) | |
266 | return -1; | |
06c38d5e | 267 | |
72a671ce SS |
268 | if (use_fxsr() && save_xstate_epilog(buf_fx, ia32_fxstate)) |
269 | return -1; | |
270 | ||
304bceda | 271 | drop_init_fpu(tsk); /* trigger finit */ |
72a671ce SS |
272 | |
273 | return 0; | |
274 | } | |
c37b5efe | 275 | |
72a671ce SS |
276 | static inline void |
277 | sanitize_restored_xstate(struct task_struct *tsk, | |
278 | struct user_i387_ia32_struct *ia32_env, | |
279 | u64 xstate_bv, int fx_only) | |
280 | { | |
281 | struct xsave_struct *xsave = &tsk->thread.fpu.state->xsave; | |
282 | struct xsave_hdr_struct *xsave_hdr = &xsave->xsave_hdr; | |
c37b5efe | 283 | |
72a671ce SS |
284 | if (use_xsave()) { |
285 | /* These bits must be zero. */ | |
286 | xsave_hdr->reserved1[0] = xsave_hdr->reserved1[1] = 0; | |
04944b79 SS |
287 | |
288 | /* | |
72a671ce SS |
289 | * Init the state that is not present in the memory |
290 | * layout and not enabled by the OS. | |
04944b79 | 291 | */ |
72a671ce SS |
292 | if (fx_only) |
293 | xsave_hdr->xstate_bv = XSTATE_FPSSE; | |
294 | else | |
295 | xsave_hdr->xstate_bv &= (pcntxt_mask & xstate_bv); | |
296 | } | |
04944b79 | 297 | |
72a671ce | 298 | if (use_fxsr()) { |
04944b79 | 299 | /* |
72a671ce SS |
300 | * mscsr reserved bits must be masked to zero for security |
301 | * reasons. | |
04944b79 | 302 | */ |
72a671ce | 303 | xsave->i387.mxcsr &= mxcsr_feature_mask; |
04944b79 | 304 | |
72a671ce | 305 | convert_to_fxsr(tsk, ia32_env); |
c37b5efe | 306 | } |
ab513701 SS |
307 | } |
308 | ||
c37b5efe | 309 | /* |
72a671ce | 310 | * Restore the extended state if present. Otherwise, restore the FP/SSE state. |
c37b5efe | 311 | */ |
72a671ce | 312 | static inline int restore_user_xstate(void __user *buf, u64 xbv, int fx_only) |
c37b5efe | 313 | { |
72a671ce SS |
314 | if (use_xsave()) { |
315 | if ((unsigned long)buf % 64 || fx_only) { | |
316 | u64 init_bv = pcntxt_mask & ~XSTATE_FPSSE; | |
317 | xrstor_state(init_xstate_buf, init_bv); | |
e139e955 | 318 | return fxrstor_user(buf); |
72a671ce SS |
319 | } else { |
320 | u64 init_bv = pcntxt_mask & ~xbv; | |
321 | if (unlikely(init_bv)) | |
322 | xrstor_state(init_xstate_buf, init_bv); | |
323 | return xrestore_user(buf, xbv); | |
324 | } | |
325 | } else if (use_fxsr()) { | |
e139e955 | 326 | return fxrstor_user(buf); |
72a671ce | 327 | } else |
e139e955 | 328 | return frstor_user(buf); |
c37b5efe SS |
329 | } |
330 | ||
72a671ce | 331 | int __restore_xstate_sig(void __user *buf, void __user *buf_fx, int size) |
ab513701 | 332 | { |
72a671ce | 333 | int ia32_fxstate = (buf != buf_fx); |
ab513701 | 334 | struct task_struct *tsk = current; |
72a671ce SS |
335 | int state_size = xstate_size; |
336 | u64 xstate_bv = 0; | |
337 | int fx_only = 0; | |
338 | ||
339 | ia32_fxstate &= (config_enabled(CONFIG_X86_32) || | |
340 | config_enabled(CONFIG_IA32_EMULATION)); | |
ab513701 SS |
341 | |
342 | if (!buf) { | |
304bceda | 343 | drop_init_fpu(tsk); |
ab513701 | 344 | return 0; |
72a671ce SS |
345 | } |
346 | ||
347 | if (!access_ok(VERIFY_READ, buf, size)) | |
348 | return -EACCES; | |
349 | ||
350 | if (!used_math() && init_fpu(tsk)) | |
351 | return -1; | |
ab513701 | 352 | |
60e019eb | 353 | if (!static_cpu_has(X86_FEATURE_FPU)) |
72a671ce SS |
354 | return fpregs_soft_set(current, NULL, |
355 | 0, sizeof(struct user_i387_ia32_struct), | |
356 | NULL, buf) != 0; | |
ab513701 | 357 | |
72a671ce SS |
358 | if (use_xsave()) { |
359 | struct _fpx_sw_bytes fx_sw_user; | |
360 | if (unlikely(check_for_xstate(buf_fx, buf_fx, &fx_sw_user))) { | |
361 | /* | |
362 | * Couldn't find the extended state information in the | |
363 | * memory layout. Restore just the FP/SSE and init all | |
364 | * the other extended state. | |
365 | */ | |
366 | state_size = sizeof(struct i387_fxsave_struct); | |
367 | fx_only = 1; | |
368 | } else { | |
369 | state_size = fx_sw_user.xstate_size; | |
370 | xstate_bv = fx_sw_user.xstate_bv; | |
371 | } | |
372 | } | |
373 | ||
374 | if (ia32_fxstate) { | |
375 | /* | |
376 | * For 32-bit frames with fxstate, copy the user state to the | |
377 | * thread's fpu state, reconstruct fxstate from the fsave | |
378 | * header. Sanitize the copied state etc. | |
379 | */ | |
380 | struct xsave_struct *xsave = &tsk->thread.fpu.state->xsave; | |
381 | struct user_i387_ia32_struct env; | |
304bceda | 382 | int err = 0; |
72a671ce | 383 | |
304bceda SS |
384 | /* |
385 | * Drop the current fpu which clears used_math(). This ensures | |
386 | * that any context-switch during the copy of the new state, | |
387 | * avoids the intermediate state from getting restored/saved. | |
388 | * Thus avoiding the new restored state from getting corrupted. | |
389 | * We will be ready to restore/save the state only after | |
390 | * set_used_math() is again set. | |
391 | */ | |
e9625917 | 392 | drop_fpu(tsk); |
72a671ce SS |
393 | |
394 | if (__copy_from_user(xsave, buf_fx, state_size) || | |
304bceda SS |
395 | __copy_from_user(&env, buf, sizeof(env))) { |
396 | err = -1; | |
397 | } else { | |
398 | sanitize_restored_xstate(tsk, &env, xstate_bv, fx_only); | |
399 | set_used_math(); | |
400 | } | |
72a671ce | 401 | |
5d2bd700 | 402 | if (use_eager_fpu()) |
304bceda SS |
403 | math_state_restore(); |
404 | ||
405 | return err; | |
72a671ce | 406 | } else { |
ab513701 | 407 | /* |
72a671ce SS |
408 | * For 64-bit frames and 32-bit fsave frames, restore the user |
409 | * state to the registers directly (with exceptions handled). | |
ab513701 | 410 | */ |
72a671ce SS |
411 | user_fpu_begin(); |
412 | if (restore_user_xstate(buf_fx, xstate_bv, fx_only)) { | |
304bceda | 413 | drop_init_fpu(tsk); |
72a671ce SS |
414 | return -1; |
415 | } | |
ab513701 | 416 | } |
72a671ce SS |
417 | |
418 | return 0; | |
ab513701 | 419 | } |
ab513701 | 420 | |
c37b5efe SS |
421 | /* |
422 | * Prepare the SW reserved portion of the fxsave memory layout, indicating | |
423 | * the presence of the extended state information in the memory layout | |
424 | * pointed by the fpstate pointer in the sigcontext. | |
425 | * This will be saved when ever the FP and extended state context is | |
426 | * saved on the user stack during the signal handler delivery to the user. | |
427 | */ | |
8bcad30f | 428 | static void prepare_fx_sw_frame(void) |
c37b5efe | 429 | { |
72a671ce SS |
430 | int fsave_header_size = sizeof(struct i387_fsave_struct); |
431 | int size = xstate_size + FP_XSTATE_MAGIC2_SIZE; | |
c37b5efe | 432 | |
72a671ce SS |
433 | if (config_enabled(CONFIG_X86_32)) |
434 | size += fsave_header_size; | |
c37b5efe SS |
435 | |
436 | fx_sw_reserved.magic1 = FP_XSTATE_MAGIC1; | |
72a671ce | 437 | fx_sw_reserved.extended_size = size; |
6152e4b1 | 438 | fx_sw_reserved.xstate_bv = pcntxt_mask; |
c37b5efe | 439 | fx_sw_reserved.xstate_size = xstate_size; |
c37b5efe | 440 | |
72a671ce SS |
441 | if (config_enabled(CONFIG_IA32_EMULATION)) { |
442 | fx_sw_reserved_ia32 = fx_sw_reserved; | |
443 | fx_sw_reserved_ia32.extended_size += fsave_header_size; | |
444 | } | |
445 | } | |
3c1c7f10 | 446 | |
dc1e35c6 SS |
447 | /* |
448 | * Enable the extended processor state save/restore feature | |
449 | */ | |
1cff92d8 | 450 | static inline void xstate_enable(void) |
dc1e35c6 | 451 | { |
dc1e35c6 | 452 | set_in_cr4(X86_CR4_OSXSAVE); |
6152e4b1 | 453 | xsetbv(XCR_XFEATURE_ENABLED_MASK, pcntxt_mask); |
dc1e35c6 SS |
454 | } |
455 | ||
a1488f8b SS |
456 | /* |
457 | * Record the offsets and sizes of different state managed by the xsave | |
458 | * memory layout. | |
459 | */ | |
4995b9db | 460 | static void __init setup_xstate_features(void) |
a1488f8b SS |
461 | { |
462 | int eax, ebx, ecx, edx, leaf = 0x2; | |
463 | ||
464 | xstate_features = fls64(pcntxt_mask); | |
465 | xstate_offsets = alloc_bootmem(xstate_features * sizeof(int)); | |
466 | xstate_sizes = alloc_bootmem(xstate_features * sizeof(int)); | |
467 | ||
468 | do { | |
ee813d53 | 469 | cpuid_count(XSTATE_CPUID, leaf, &eax, &ebx, &ecx, &edx); |
a1488f8b SS |
470 | |
471 | if (eax == 0) | |
472 | break; | |
473 | ||
474 | xstate_offsets[leaf] = ebx; | |
475 | xstate_sizes[leaf] = eax; | |
476 | ||
477 | leaf++; | |
478 | } while (1); | |
479 | } | |
480 | ||
dc1e35c6 SS |
481 | /* |
482 | * setup the xstate image representing the init state | |
483 | */ | |
5d2bd700 | 484 | static void __init setup_init_fpu_buf(void) |
dc1e35c6 | 485 | { |
29104e10 SS |
486 | /* |
487 | * Setup init_xstate_buf to represent the init state of | |
488 | * all the features managed by the xsave | |
489 | */ | |
10340ae1 SS |
490 | init_xstate_buf = alloc_bootmem_align(xstate_size, |
491 | __alignof__(struct xsave_struct)); | |
5d2bd700 SS |
492 | fx_finit(&init_xstate_buf->i387); |
493 | ||
494 | if (!cpu_has_xsave) | |
495 | return; | |
496 | ||
497 | setup_xstate_features(); | |
a1488f8b | 498 | |
29104e10 SS |
499 | /* |
500 | * Init all the features state with header_bv being 0x0 | |
501 | */ | |
502 | xrstor_state(init_xstate_buf, -1); | |
503 | /* | |
504 | * Dump the init state again. This is to identify the init state | |
505 | * of any feature which is not represented by all zero's. | |
506 | */ | |
507 | xsave_state(init_xstate_buf, -1); | |
dc1e35c6 SS |
508 | } |
509 | ||
e0022981 | 510 | static enum { AUTO, ENABLE, DISABLE } eagerfpu = AUTO; |
5d2bd700 SS |
511 | static int __init eager_fpu_setup(char *s) |
512 | { | |
513 | if (!strcmp(s, "on")) | |
e0022981 | 514 | eagerfpu = ENABLE; |
5d2bd700 | 515 | else if (!strcmp(s, "off")) |
e0022981 SS |
516 | eagerfpu = DISABLE; |
517 | else if (!strcmp(s, "auto")) | |
518 | eagerfpu = AUTO; | |
5d2bd700 SS |
519 | return 1; |
520 | } | |
521 | __setup("eagerfpu=", eager_fpu_setup); | |
522 | ||
dc1e35c6 SS |
523 | /* |
524 | * Enable and initialize the xsave feature. | |
525 | */ | |
1cff92d8 | 526 | static void __init xstate_enable_boot_cpu(void) |
dc1e35c6 SS |
527 | { |
528 | unsigned int eax, ebx, ecx, edx; | |
529 | ||
ee813d53 RR |
530 | if (boot_cpu_data.cpuid_level < XSTATE_CPUID) { |
531 | WARN(1, KERN_ERR "XSTATE_CPUID missing\n"); | |
532 | return; | |
533 | } | |
534 | ||
535 | cpuid_count(XSTATE_CPUID, 0, &eax, &ebx, &ecx, &edx); | |
6152e4b1 | 536 | pcntxt_mask = eax + ((u64)edx << 32); |
dc1e35c6 | 537 | |
6152e4b1 | 538 | if ((pcntxt_mask & XSTATE_FPSSE) != XSTATE_FPSSE) { |
c767a54b | 539 | pr_err("FP/SSE not shown under xsave features 0x%llx\n", |
6152e4b1 | 540 | pcntxt_mask); |
dc1e35c6 SS |
541 | BUG(); |
542 | } | |
543 | ||
544 | /* | |
a30469e7 | 545 | * Support only the state known to OS. |
dc1e35c6 | 546 | */ |
6152e4b1 | 547 | pcntxt_mask = pcntxt_mask & XCNTXT_MASK; |
97e80a70 | 548 | |
1cff92d8 | 549 | xstate_enable(); |
dc1e35c6 SS |
550 | |
551 | /* | |
552 | * Recompute the context size for enabled features | |
553 | */ | |
ee813d53 | 554 | cpuid_count(XSTATE_CPUID, 0, &eax, &ebx, &ecx, &edx); |
dc1e35c6 SS |
555 | xstate_size = ebx; |
556 | ||
5b3efd50 | 557 | update_regset_xstate_info(xstate_size, pcntxt_mask); |
c37b5efe | 558 | prepare_fx_sw_frame(); |
5d2bd700 | 559 | setup_init_fpu_buf(); |
dc1e35c6 | 560 | |
e0022981 SS |
561 | /* Auto enable eagerfpu for xsaveopt */ |
562 | if (cpu_has_xsaveopt && eagerfpu != DISABLE) | |
563 | eagerfpu = ENABLE; | |
212b0212 | 564 | |
c767a54b JP |
565 | pr_info("enabled xstate_bv 0x%llx, cntxt size 0x%x\n", |
566 | pcntxt_mask, xstate_size); | |
dc1e35c6 | 567 | } |
82d4150c | 568 | |
1cff92d8 PA |
569 | /* |
570 | * For the very first instance, this calls xstate_enable_boot_cpu(); | |
571 | * for all subsequent instances, this calls xstate_enable(). | |
572 | * | |
573 | * This is somewhat obfuscated due to the lack of powerful enough | |
574 | * overrides for the section checks. | |
575 | */ | |
148f9bb8 | 576 | void xsave_init(void) |
82d4150c | 577 | { |
1cff92d8 PA |
578 | static __refdata void (*next_func)(void) = xstate_enable_boot_cpu; |
579 | void (*this_func)(void); | |
580 | ||
0e49bf66 RR |
581 | if (!cpu_has_xsave) |
582 | return; | |
583 | ||
1cff92d8 | 584 | this_func = next_func; |
5d2bd700 | 585 | next_func = xstate_enable; |
1cff92d8 | 586 | this_func(); |
82d4150c | 587 | } |
5d2bd700 SS |
588 | |
589 | static inline void __init eager_fpu_init_bp(void) | |
590 | { | |
591 | current->thread.fpu.state = | |
592 | alloc_bootmem_align(xstate_size, __alignof__(struct xsave_struct)); | |
593 | if (!init_xstate_buf) | |
594 | setup_init_fpu_buf(); | |
595 | } | |
596 | ||
148f9bb8 | 597 | void eager_fpu_init(void) |
5d2bd700 SS |
598 | { |
599 | static __refdata void (*boot_func)(void) = eager_fpu_init_bp; | |
600 | ||
601 | clear_used_math(); | |
602 | current_thread_info()->status = 0; | |
e0022981 SS |
603 | |
604 | if (eagerfpu == ENABLE) | |
605 | setup_force_cpu_cap(X86_FEATURE_EAGER_FPU); | |
606 | ||
5d2bd700 SS |
607 | if (!cpu_has_eager_fpu) { |
608 | stts(); | |
609 | return; | |
610 | } | |
611 | ||
612 | if (boot_func) { | |
613 | boot_func(); | |
614 | boot_func = NULL; | |
615 | } | |
616 | ||
617 | /* | |
618 | * This is same as math_state_restore(). But use_xsave() is | |
619 | * not yet patched to use math_state_restore(). | |
620 | */ | |
621 | init_fpu(current); | |
622 | __thread_fpu_begin(current); | |
623 | if (cpu_has_xsave) | |
624 | xrstor_state(init_xstate_buf, -1); | |
625 | else | |
626 | fxrstor_checking(&init_xstate_buf->i387); | |
627 | } |