Commit | Line | Data |
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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
17ce265d SR |
2 | /* |
3 | * ld script for the x86 kernel | |
4 | * | |
5 | * Historic 32-bit version written by Martin Mares <mj@atrey.karlin.mff.cuni.cz> | |
6 | * | |
91fd7fe8 IM |
7 | * Modernisation, unification and other changes and fixes: |
8 | * Copyright (C) 2007-2009 Sam Ravnborg <sam@ravnborg.org> | |
17ce265d SR |
9 | * |
10 | * | |
11 | * Don't define absolute symbols until and unless you know that symbol | |
12 | * value is should remain constant even if kernel image is relocated | |
13 | * at run time. Absolute symbols are not relocated. If symbol value should | |
14 | * change if kernel is relocated, make the symbol section relative and | |
15 | * put it inside the section definition. | |
16 | */ | |
17 | ||
17ce265d | 18 | #define LOAD_OFFSET __START_KERNEL_map |
17ce265d | 19 | |
84d5f77f | 20 | #define RUNTIME_DISCARD_EXIT |
441110a5 | 21 | #define EMITS_PT_NOTE |
f0d7ee17 | 22 | #define RO_EXCEPTION_TABLE_ALIGN 16 |
441110a5 | 23 | |
17ce265d SR |
24 | #include <asm-generic/vmlinux.lds.h> |
25 | #include <asm/asm-offsets.h> | |
26 | #include <asm/thread_info.h> | |
27 | #include <asm/page_types.h> | |
ee9f8fce | 28 | #include <asm/orc_lookup.h> |
17ce265d SR |
29 | #include <asm/cache.h> |
30 | #include <asm/boot.h> | |
31 | ||
32 | #undef i386 /* in case the preprocessor is a 32bit one */ | |
33 | ||
e6d7bc0b | 34 | OUTPUT_FORMAT(CONFIG_OUTPUT_FORMAT) |
17ce265d SR |
35 | |
36 | #ifdef CONFIG_X86_32 | |
37 | OUTPUT_ARCH(i386) | |
38 | ENTRY(phys_startup_32) | |
17ce265d SR |
39 | #else |
40 | OUTPUT_ARCH(i386:x86-64) | |
41 | ENTRY(phys_startup_64) | |
17ce265d SR |
42 | #endif |
43 | ||
d8ad6d39 | 44 | jiffies = jiffies_64; |
ed2f752e | 45 | const_pcpu_hot = pcpu_hot; |
d8ad6d39 | 46 | |
9ccaf77c | 47 | #if defined(CONFIG_X86_64) |
d6cc1c3a | 48 | /* |
9ccaf77c KC |
49 | * On 64-bit, align RODATA to 2MB so we retain large page mappings for |
50 | * boundaries spanning kernel text, rodata and data sections. | |
d6cc1c3a SS |
51 | * |
52 | * However, kernel identity mappings will have different RWX permissions | |
53 | * to the pages mapping to text and to the pages padding (which are freed) the | |
54 | * text section. Hence kernel identity mappings will be broken to smaller | |
55 | * pages. For 64-bit, kernel text and kernel identity mappings are different, | |
9ccaf77c KC |
56 | * so we can enable protection checks as well as retain 2MB large page |
57 | * mappings for kernel text. | |
d6cc1c3a | 58 | */ |
39d668e0 | 59 | #define X86_ALIGN_RODATA_BEGIN . = ALIGN(HPAGE_SIZE); |
74e08179 | 60 | |
39d668e0 | 61 | #define X86_ALIGN_RODATA_END \ |
74e08179 | 62 | . = ALIGN(HPAGE_SIZE); \ |
39d668e0 JR |
63 | __end_rodata_hpage_align = .; \ |
64 | __end_rodata_aligned = .; | |
74e08179 | 65 | |
2f7412ba TG |
66 | #define ALIGN_ENTRY_TEXT_BEGIN . = ALIGN(PMD_SIZE); |
67 | #define ALIGN_ENTRY_TEXT_END . = ALIGN(PMD_SIZE); | |
68 | ||
b3f0907c BS |
69 | /* |
70 | * This section contains data which will be mapped as decrypted. Memory | |
71 | * encryption operates on a page basis. Make this section PMD-aligned | |
72 | * to avoid splitting the pages while mapping the section early. | |
73 | * | |
74 | * Note: We use a separate section so that only this section gets | |
75 | * decrypted to avoid exposing more than we wish. | |
76 | */ | |
77 | #define BSS_DECRYPTED \ | |
78 | . = ALIGN(PMD_SIZE); \ | |
79 | __start_bss_decrypted = .; \ | |
80 | *(.bss..decrypted); \ | |
81 | . = ALIGN(PAGE_SIZE); \ | |
82 | __start_bss_decrypted_unused = .; \ | |
83 | . = ALIGN(PMD_SIZE); \ | |
84 | __end_bss_decrypted = .; \ | |
85 | ||
74e08179 SS |
86 | #else |
87 | ||
39d668e0 JR |
88 | #define X86_ALIGN_RODATA_BEGIN |
89 | #define X86_ALIGN_RODATA_END \ | |
90 | . = ALIGN(PAGE_SIZE); \ | |
91 | __end_rodata_aligned = .; | |
74e08179 | 92 | |
2f7412ba TG |
93 | #define ALIGN_ENTRY_TEXT_BEGIN |
94 | #define ALIGN_ENTRY_TEXT_END | |
b3f0907c | 95 | #define BSS_DECRYPTED |
2f7412ba | 96 | |
74e08179 SS |
97 | #endif |
98 | ||
afb8095a SR |
99 | PHDRS { |
100 | text PT_LOAD FLAGS(5); /* R_E */ | |
5bd5a452 | 101 | data PT_LOAD FLAGS(6); /* RW_ */ |
afb8095a | 102 | #ifdef CONFIG_X86_64 |
afb8095a | 103 | #ifdef CONFIG_SMP |
8d0cc631 | 104 | percpu PT_LOAD FLAGS(6); /* RW_ */ |
afb8095a | 105 | #endif |
c62e4320 | 106 | init PT_LOAD FLAGS(7); /* RWE */ |
afb8095a SR |
107 | #endif |
108 | note PT_NOTE FLAGS(0); /* ___ */ | |
109 | } | |
17ce265d | 110 | |
444e0ae4 SR |
111 | SECTIONS |
112 | { | |
9b67ce2c | 113 | . = __START_KERNEL; |
444e0ae4 | 114 | #ifdef CONFIG_X86_32 |
142b9e6c | 115 | phys_startup_32 = ABSOLUTE(startup_32 - LOAD_OFFSET); |
444e0ae4 | 116 | #else |
142b9e6c | 117 | phys_startup_64 = ABSOLUTE(startup_64 - LOAD_OFFSET); |
444e0ae4 SR |
118 | #endif |
119 | ||
dfc20895 | 120 | /* Text and read-only data */ |
dfc20895 | 121 | .text : AT(ADDR(.text) - LOAD_OFFSET) { |
4ae59b91 | 122 | _text = .; |
e728f61c | 123 | _stext = .; |
4ae59b91 TA |
124 | /* bootstrapping code */ |
125 | HEAD_TEXT | |
dfc20895 SR |
126 | TEXT_TEXT |
127 | SCHED_TEXT | |
128 | LOCK_TEXT | |
129 | KPROBES_TEXT | |
be7635e7 | 130 | SOFTIRQENTRY_TEXT |
aefb2f2e | 131 | #ifdef CONFIG_MITIGATION_RETPOLINE |
79cd2a11 PP |
132 | *(.text..__x86.indirect_thunk) |
133 | *(.text..__x86.return_thunk) | |
736e80a4 | 134 | #endif |
24a9c543 TG |
135 | STATIC_CALL_TEXT |
136 | ||
137 | ALIGN_ENTRY_TEXT_BEGIN | |
79cd2a11 | 138 | *(.text..__x86.rethunk_untrain) |
24a9c543 | 139 | ENTRY_TEXT |
fb3bd914 | 140 | |
a033eec9 | 141 | #ifdef CONFIG_MITIGATION_SRSO |
fb3bd914 | 142 | /* |
42be649d | 143 | * See the comment above srso_alias_untrain_ret()'s |
fb3bd914 BPA |
144 | * definition. |
145 | */ | |
42be649d | 146 | . = srso_alias_untrain_ret | (1 << 2) | (1 << 8) | (1 << 14) | (1 << 20); |
79cd2a11 | 147 | *(.text..__x86.rethunk_safe) |
fb3bd914 | 148 | #endif |
24a9c543 TG |
149 | ALIGN_ENTRY_TEXT_END |
150 | *(.gnu.warning) | |
151 | ||
65e71089 | 152 | } :text = 0xcccccccc |
392bef70 | 153 | |
b9076938 KC |
154 | /* End of text section, which should occupy whole number of pages */ |
155 | _etext = .; | |
5bd5a452 | 156 | . = ALIGN(PAGE_SIZE); |
b9076938 | 157 | |
39d668e0 | 158 | X86_ALIGN_RODATA_BEGIN |
c62e4320 | 159 | RO_DATA(PAGE_SIZE) |
39d668e0 | 160 | X86_ALIGN_RODATA_END |
448bc3ab | 161 | |
1f6397ba | 162 | /* Data */ |
1f6397ba | 163 | .data : AT(ADDR(.data) - LOAD_OFFSET) { |
1260866a CM |
164 | /* Start of data section */ |
165 | _sdata = .; | |
c62e4320 JB |
166 | |
167 | /* init_task */ | |
168 | INIT_TASK_DATA(THREAD_SIZE) | |
1f6397ba | 169 | |
2cb16181 | 170 | /* equivalent to task_pt_regs(&init_task) */ |
8f69cba0 | 171 | __top_init_kernel_stack = __end_init_stack - TOP_OF_KERNEL_STACK_PADDING - PTREGS_SIZE; |
2cb16181 | 172 | |
1f6397ba | 173 | #ifdef CONFIG_X86_32 |
c62e4320 JB |
174 | /* 32 bit has nosave before _edata */ |
175 | NOSAVE_DATA | |
1f6397ba SR |
176 | #endif |
177 | ||
c62e4320 | 178 | PAGE_ALIGNED_DATA(PAGE_SIZE) |
1f6397ba | 179 | |
350f8f56 | 180 | CACHELINE_ALIGNED_DATA(L1_CACHE_BYTES) |
1f6397ba | 181 | |
c62e4320 JB |
182 | DATA_DATA |
183 | CONSTRUCTORS | |
184 | ||
185 | /* rarely changed data like cpu maps */ | |
350f8f56 | 186 | READ_MOSTLY_DATA(INTERNODE_CACHE_BYTES) |
1f6397ba | 187 | |
1f6397ba SR |
188 | /* End of data section */ |
189 | _edata = .; | |
c62e4320 | 190 | } :data |
1f6397ba | 191 | |
b5effd38 | 192 | BUG_TABLE |
ff6f87e1 | 193 | |
ee9f8fce JP |
194 | ORC_UNWIND_TABLE |
195 | ||
9c40818d AL |
196 | . = ALIGN(PAGE_SIZE); |
197 | __vvar_page = .; | |
198 | ||
199 | .vvar : AT(ADDR(.vvar) - LOAD_OFFSET) { | |
f670bb76 AL |
200 | /* work around gold bug 13023 */ |
201 | __vvar_beginning_hack = .; | |
9c40818d | 202 | |
f670bb76 | 203 | /* Place all vvars at the offsets in asm/vvar.h. */ |
64b302ab | 204 | #define EMIT_VVAR(name, offset) \ |
f670bb76 | 205 | . = __vvar_beginning_hack + offset; \ |
9c40818d | 206 | *(.vvar_ ## name) |
9c40818d | 207 | #include <asm/vvar.h> |
9c40818d AL |
208 | #undef EMIT_VVAR |
209 | ||
309944be AL |
210 | /* |
211 | * Pad the rest of the page with zeros. Otherwise the loader | |
212 | * can leave garbage here. | |
213 | */ | |
214 | . = __vvar_beginning_hack + PAGE_SIZE; | |
9c40818d AL |
215 | } :data |
216 | ||
a06cc94f | 217 | . = ALIGN(__vvar_page + PAGE_SIZE, PAGE_SIZE); |
9c40818d | 218 | |
c62e4320 JB |
219 | /* Init code and data - will be freed after init */ |
220 | . = ALIGN(PAGE_SIZE); | |
221 | .init.begin : AT(ADDR(.init.begin) - LOAD_OFFSET) { | |
222 | __init_begin = .; /* paired with __init_end */ | |
e58bdaa8 | 223 | } |
e58bdaa8 | 224 | |
c62e4320 | 225 | #if defined(CONFIG_X86_64) && defined(CONFIG_SMP) |
e58bdaa8 | 226 | /* |
c62e4320 JB |
227 | * percpu offsets are zero-based on SMP. PERCPU_VADDR() changes the |
228 | * output PHDR, so the next output section - .init.text - should | |
229 | * start another segment - init. | |
e58bdaa8 | 230 | */ |
19df0c2f | 231 | PERCPU_VADDR(INTERNODE_CACHE_BYTES, 0, :percpu) |
97b67ae5 JB |
232 | ASSERT(SIZEOF(.data..percpu) < CONFIG_PHYSICAL_START, |
233 | "per-CPU data too large - increase CONFIG_PHYSICAL_START") | |
c62e4320 | 234 | #endif |
e58bdaa8 | 235 | |
123f3e1d | 236 | INIT_TEXT_SECTION(PAGE_SIZE) |
c62e4320 JB |
237 | #ifdef CONFIG_X86_64 |
238 | :init | |
239 | #endif | |
e58bdaa8 | 240 | |
337e4cc8 BP |
241 | /* |
242 | * Section for code used exclusively before alternatives are run. All | |
243 | * references to such code must be patched out by alternatives, normally | |
244 | * by using X86_FEATURE_ALWAYS CPU feature bit. | |
245 | * | |
246 | * See static_cpu_has() for an example. | |
247 | */ | |
248 | .altinstr_aux : AT(ADDR(.altinstr_aux) - LOAD_OFFSET) { | |
249 | *(.altinstr_aux) | |
250 | } | |
251 | ||
123f3e1d | 252 | INIT_DATA_SECTION(16) |
e58bdaa8 SR |
253 | |
254 | .x86_cpu_dev.init : AT(ADDR(.x86_cpu_dev.init) - LOAD_OFFSET) { | |
255 | __x86_cpu_dev_start = .; | |
256 | *(.x86_cpu_dev.init) | |
257 | __x86_cpu_dev_end = .; | |
258 | } | |
259 | ||
66ac5013 DC |
260 | #ifdef CONFIG_X86_INTEL_MID |
261 | .x86_intel_mid_dev.init : AT(ADDR(.x86_intel_mid_dev.init) - \ | |
262 | LOAD_OFFSET) { | |
263 | __x86_intel_mid_dev_start = .; | |
264 | *(.x86_intel_mid_dev.init) | |
265 | __x86_intel_mid_dev_end = .; | |
266 | } | |
267 | #endif | |
268 | ||
aefb2f2e | 269 | #ifdef CONFIG_MITIGATION_RETPOLINE |
134ab5bd PZ |
270 | /* |
271 | * List of instructions that call/jmp/jcc to retpoline thunks | |
272 | * __x86_indirect_thunk_*(). These instructions can be patched along | |
273 | * with alternatives, after which the section can be freed. | |
274 | */ | |
275 | . = ALIGN(8); | |
276 | .retpoline_sites : AT(ADDR(.retpoline_sites) - LOAD_OFFSET) { | |
277 | __retpoline_sites = .; | |
278 | *(.retpoline_sites) | |
279 | __retpoline_sites_end = .; | |
280 | } | |
15e67227 PZ |
281 | |
282 | . = ALIGN(8); | |
283 | .return_sites : AT(ADDR(.return_sites) - LOAD_OFFSET) { | |
284 | __return_sites = .; | |
285 | *(.return_sites) | |
286 | __return_sites_end = .; | |
287 | } | |
00abd384 PZ |
288 | |
289 | . = ALIGN(8); | |
290 | .call_sites : AT(ADDR(.call_sites) - LOAD_OFFSET) { | |
291 | __call_sites = .; | |
292 | *(.call_sites) | |
293 | __call_sites_end = .; | |
294 | } | |
134ab5bd PZ |
295 | #endif |
296 | ||
89bc853e PZ |
297 | #ifdef CONFIG_X86_KERNEL_IBT |
298 | . = ALIGN(8); | |
299 | .ibt_endbr_seal : AT(ADDR(.ibt_endbr_seal) - LOAD_OFFSET) { | |
300 | __ibt_endbr_seal = .; | |
301 | *(.ibt_endbr_seal) | |
302 | __ibt_endbr_seal_end = .; | |
303 | } | |
304 | #endif | |
305 | ||
931ab636 PZ |
306 | #ifdef CONFIG_FINEIBT |
307 | . = ALIGN(8); | |
308 | .cfi_sites : AT(ADDR(.cfi_sites) - LOAD_OFFSET) { | |
309 | __cfi_sites = .; | |
310 | *(.cfi_sites) | |
311 | __cfi_sites_end = .; | |
312 | } | |
313 | #endif | |
314 | ||
6f44d033 KRW |
315 | /* |
316 | * struct alt_inst entries. From the header (alternative.h): | |
317 | * "Alternative instructions for different CPU types or capabilities" | |
318 | * Think locking instructions on spinlocks. | |
319 | */ | |
ae618362 SR |
320 | . = ALIGN(8); |
321 | .altinstructions : AT(ADDR(.altinstructions) - LOAD_OFFSET) { | |
322 | __alt_instructions = .; | |
323 | *(.altinstructions) | |
324 | __alt_instructions_end = .; | |
325 | } | |
326 | ||
6f44d033 KRW |
327 | /* |
328 | * And here are the replacement instructions. The linker sticks | |
329 | * them as binary blobs. The .altinstructions has enough data to | |
330 | * get the address and the length of them to patch the kernel safely. | |
331 | */ | |
ae618362 SR |
332 | .altinstr_replacement : AT(ADDR(.altinstr_replacement) - LOAD_OFFSET) { |
333 | *(.altinstr_replacement) | |
334 | } | |
335 | ||
107e0e0c SS |
336 | . = ALIGN(8); |
337 | .apicdrivers : AT(ADDR(.apicdrivers) - LOAD_OFFSET) { | |
338 | __apicdrivers = .; | |
339 | *(.apicdrivers); | |
340 | __apicdrivers_end = .; | |
341 | } | |
342 | ||
7ac41ccf | 343 | . = ALIGN(8); |
bf6a5741 | 344 | /* |
6f8f0dc9 AS |
345 | * .exit.text is discarded at runtime, not link time, to deal with |
346 | * references from .altinstructions | |
bf6a5741 SR |
347 | */ |
348 | .exit.text : AT(ADDR(.exit.text) - LOAD_OFFSET) { | |
349 | EXIT_TEXT | |
350 | } | |
351 | ||
352 | .exit.data : AT(ADDR(.exit.data) - LOAD_OFFSET) { | |
353 | EXIT_DATA | |
354 | } | |
355 | ||
c62e4320 | 356 | #if !defined(CONFIG_X86_64) || !defined(CONFIG_SMP) |
0415b00d | 357 | PERCPU_SECTION(INTERNODE_CACHE_BYTES) |
9d16e783 SR |
358 | #endif |
359 | ||
360 | . = ALIGN(PAGE_SIZE); | |
fd073194 | 361 | |
9d16e783 | 362 | /* freed after init ends here */ |
fd073194 IM |
363 | .init.end : AT(ADDR(.init.end) - LOAD_OFFSET) { |
364 | __init_end = .; | |
365 | } | |
9d16e783 | 366 | |
c62e4320 JB |
367 | /* |
368 | * smp_locks might be freed after init | |
369 | * start/end must be page aligned | |
370 | */ | |
371 | . = ALIGN(PAGE_SIZE); | |
372 | .smp_locks : AT(ADDR(.smp_locks) - LOAD_OFFSET) { | |
373 | __smp_locks = .; | |
374 | *(.smp_locks) | |
c62e4320 | 375 | . = ALIGN(PAGE_SIZE); |
596b711e | 376 | __smp_locks_end = .; |
c62e4320 JB |
377 | } |
378 | ||
9d16e783 SR |
379 | #ifdef CONFIG_X86_64 |
380 | .data_nosave : AT(ADDR(.data_nosave) - LOAD_OFFSET) { | |
c62e4320 JB |
381 | NOSAVE_DATA |
382 | } | |
9d16e783 SR |
383 | #endif |
384 | ||
091e52c3 SR |
385 | /* BSS */ |
386 | . = ALIGN(PAGE_SIZE); | |
387 | .bss : AT(ADDR(.bss) - LOAD_OFFSET) { | |
388 | __bss_start = .; | |
7c74df07 | 389 | *(.bss..page_aligned) |
de2b41be | 390 | . = ALIGN(PAGE_SIZE); |
6a03469a | 391 | *(BSS_MAIN) |
b3f0907c | 392 | BSS_DECRYPTED |
5bd5a452 | 393 | . = ALIGN(PAGE_SIZE); |
091e52c3 SR |
394 | __bss_stop = .; |
395 | } | |
9d16e783 | 396 | |
c603a309 TL |
397 | /* |
398 | * The memory occupied from _text to here, __end_of_kernel_reserve, is | |
399 | * automatically reserved in setup_arch(). Anything after here must be | |
400 | * explicitly reserved using memblock_reserve() or it will be discarded | |
401 | * and treated as available memory. | |
402 | */ | |
403 | __end_of_kernel_reserve = .; | |
404 | ||
091e52c3 | 405 | . = ALIGN(PAGE_SIZE); |
7e09ac27 | 406 | .brk : AT(ADDR(.brk) - LOAD_OFFSET) { |
091e52c3 SR |
407 | __brk_base = .; |
408 | . += 64 * 1024; /* 64k alignment slop space */ | |
e32683c6 | 409 | *(.bss..brk) /* areas brk users have reserved */ |
091e52c3 SR |
410 | __brk_limit = .; |
411 | } | |
412 | ||
974f221c | 413 | . = ALIGN(PAGE_SIZE); /* keep VO_INIT_SIZE page aligned */ |
873b5271 | 414 | _end = .; |
091e52c3 | 415 | |
e1bfa873 TL |
416 | #ifdef CONFIG_AMD_MEM_ENCRYPT |
417 | /* | |
418 | * Early scratch/workarea section: Lives outside of the kernel proper | |
419 | * (_text - _end). | |
420 | * | |
421 | * Resides after _end because even though the .brk section is after | |
422 | * __end_of_kernel_reserve, the .brk section is later reserved as a | |
423 | * part of the kernel. Since it is located after __end_of_kernel_reserve | |
424 | * it will be discarded and become part of the available memory. As | |
425 | * such, it can only be used by very early boot code and must not be | |
426 | * needed afterwards. | |
427 | * | |
428 | * Currently used by SME for performing in-place encryption of the | |
429 | * kernel during boot. Resides on a 2MB boundary to simplify the | |
430 | * pagetable setup used for SME in-place encryption. | |
431 | */ | |
432 | . = ALIGN(HPAGE_SIZE); | |
433 | .init.scratch : AT(ADDR(.init.scratch) - LOAD_OFFSET) { | |
434 | __init_scratch_begin = .; | |
435 | *(.init.scratch) | |
436 | . = ALIGN(HPAGE_SIZE); | |
437 | __init_scratch_end = .; | |
438 | } | |
439 | #endif | |
440 | ||
a06cc94f C |
441 | STABS_DEBUG |
442 | DWARF_DEBUG | |
c604abc3 | 443 | ELF_DETAILS |
023bf6f1 | 444 | |
023bf6f1 | 445 | DISCARDS |
444e0ae4 | 446 | |
815d6807 KC |
447 | /* |
448 | * Make sure that the .got.plt is either completely empty or it | |
449 | * contains only the lazy dispatch entries. | |
450 | */ | |
451 | .got.plt (INFO) : { *(.got.plt) } | |
452 | ASSERT(SIZEOF(.got.plt) == 0 || | |
453 | #ifdef CONFIG_X86_64 | |
454 | SIZEOF(.got.plt) == 0x18, | |
455 | #else | |
456 | SIZEOF(.got.plt) == 0xc, | |
457 | #endif | |
458 | "Unexpected GOT/PLT entries detected!") | |
5354e845 KC |
459 | |
460 | /* | |
461 | * Sections that should stay zero sized, which is safer to | |
462 | * explicitly check instead of blindly discarding. | |
463 | */ | |
464 | .got : { | |
465 | *(.got) *(.igot.*) | |
466 | } | |
467 | ASSERT(SIZEOF(.got) == 0, "Unexpected GOT entries detected!") | |
468 | ||
469 | .plt : { | |
470 | *(.plt) *(.plt.*) *(.iplt) | |
471 | } | |
472 | ASSERT(SIZEOF(.plt) == 0, "Unexpected run-time procedure linkages detected!") | |
473 | ||
474 | .rel.dyn : { | |
475 | *(.rel.*) *(.rel_*) | |
476 | } | |
477 | ASSERT(SIZEOF(.rel.dyn) == 0, "Unexpected run-time relocations (.rel) detected!") | |
478 | ||
479 | .rela.dyn : { | |
480 | *(.rela.*) *(.rela_*) | |
481 | } | |
482 | ASSERT(SIZEOF(.rela.dyn) == 0, "Unexpected run-time relocations (.rela) detected!") | |
815d6807 | 483 | } |
17ce265d | 484 | |
a5912f6b IM |
485 | /* |
486 | * The ASSERT() sink to . is intentional, for binutils 2.14 compatibility: | |
487 | */ | |
d2ba8b21 PA |
488 | . = ASSERT((_end - LOAD_OFFSET <= KERNEL_IMAGE_SIZE), |
489 | "kernel image bigger than KERNEL_IMAGE_SIZE"); | |
ea3186b9 AS |
490 | |
491 | #ifdef CONFIG_X86_64 | |
17ce265d SR |
492 | /* |
493 | * Per-cpu symbols which need to be offset from __per_cpu_load | |
494 | * for the boot processor. | |
495 | */ | |
d071ae09 | 496 | #define INIT_PER_CPU(x) init_per_cpu__##x = ABSOLUTE(x) + __per_cpu_load |
17ce265d | 497 | INIT_PER_CPU(gdt_page); |
e6401c13 AL |
498 | INIT_PER_CPU(fixed_percpu_data); |
499 | INIT_PER_CPU(irq_stack_backing_store); | |
17ce265d | 500 | |
17ce265d | 501 | #ifdef CONFIG_SMP |
e6401c13 AL |
502 | . = ASSERT((fixed_percpu_data == 0), |
503 | "fixed_percpu_data is not at start of per-cpu area"); | |
17ce265d SR |
504 | #endif |
505 | ||
ac61d439 | 506 | #ifdef CONFIG_MITIGATION_UNRET_ENTRY |
d025b7ba | 507 | . = ASSERT((retbleed_return_thunk & 0x3f) == 0, "retbleed_return_thunk not cacheline-aligned"); |
fb3bd914 BPA |
508 | #endif |
509 | ||
a033eec9 | 510 | #ifdef CONFIG_MITIGATION_SRSO |
34a3cae7 | 511 | . = ASSERT((srso_safe_ret & 0x3f) == 0, "srso_safe_ret not cacheline-aligned"); |
fb3bd914 | 512 | /* |
cbe8ded4 ND |
513 | * GNU ld cannot do XOR until 2.41. |
514 | * https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=f6f78318fca803c4907fb8d7f6ded8295f1947b1 | |
515 | * | |
516 | * LLVM lld cannot do XOR until lld-17. | |
517 | * https://github.com/llvm/llvm-project/commit/fae96104d4378166cbe5c875ef8ed808a356f3fb | |
518 | * | |
519 | * Instead do: (A | B) - (A & B) in order to compute the XOR | |
fb3bd914 BPA |
520 | * of the two function addresses: |
521 | */ | |
42be649d PZ |
522 | . = ASSERT(((ABSOLUTE(srso_alias_untrain_ret) | srso_alias_safe_ret) - |
523 | (ABSOLUTE(srso_alias_untrain_ret) & srso_alias_safe_ret)) == ((1 << 2) | (1 << 8) | (1 << 14) | (1 << 20)), | |
fb3bd914 | 524 | "SRSO function pair won't alias"); |
f220125b BPA |
525 | #endif |
526 | ||
ea3186b9 | 527 | #endif /* CONFIG_X86_64 */ |