x86, x2apic: Move the common bits to x2apic.h
[linux-2.6-block.git] / arch / x86 / kernel / vmlinux.lds.S
CommitLineData
17ce265d
SR
1/*
2 * ld script for the x86 kernel
3 *
4 * Historic 32-bit version written by Martin Mares <mj@atrey.karlin.mff.cuni.cz>
5 *
91fd7fe8
IM
6 * Modernisation, unification and other changes and fixes:
7 * Copyright (C) 2007-2009 Sam Ravnborg <sam@ravnborg.org>
17ce265d
SR
8 *
9 *
10 * Don't define absolute symbols until and unless you know that symbol
11 * value is should remain constant even if kernel image is relocated
12 * at run time. Absolute symbols are not relocated. If symbol value should
13 * change if kernel is relocated, make the symbol section relative and
14 * put it inside the section definition.
15 */
16
17#ifdef CONFIG_X86_32
18#define LOAD_OFFSET __PAGE_OFFSET
19#else
20#define LOAD_OFFSET __START_KERNEL_map
21#endif
22
23#include <asm-generic/vmlinux.lds.h>
24#include <asm/asm-offsets.h>
25#include <asm/thread_info.h>
26#include <asm/page_types.h>
27#include <asm/cache.h>
28#include <asm/boot.h>
29
30#undef i386 /* in case the preprocessor is a 32bit one */
31
32OUTPUT_FORMAT(CONFIG_OUTPUT_FORMAT, CONFIG_OUTPUT_FORMAT, CONFIG_OUTPUT_FORMAT)
33
34#ifdef CONFIG_X86_32
35OUTPUT_ARCH(i386)
36ENTRY(phys_startup_32)
6b35eb9d 37jiffies = jiffies_64;
17ce265d
SR
38#else
39OUTPUT_ARCH(i386:x86-64)
40ENTRY(phys_startup_64)
6b35eb9d 41jiffies_64 = jiffies;
17ce265d
SR
42#endif
43
74e08179 44#if defined(CONFIG_X86_64) && defined(CONFIG_DEBUG_RODATA)
d6cc1c3a
SS
45/*
46 * On 64-bit, align RODATA to 2MB so that even with CONFIG_DEBUG_RODATA
47 * we retain large page mappings for boundaries spanning kernel text, rodata
48 * and data sections.
49 *
50 * However, kernel identity mappings will have different RWX permissions
51 * to the pages mapping to text and to the pages padding (which are freed) the
52 * text section. Hence kernel identity mappings will be broken to smaller
53 * pages. For 64-bit, kernel text and kernel identity mappings are different,
54 * so we can enable protection checks that come with CONFIG_DEBUG_RODATA,
55 * as well as retain 2MB large page mappings for kernel text.
56 */
74e08179
SS
57#define X64_ALIGN_DEBUG_RODATA_BEGIN . = ALIGN(HPAGE_SIZE);
58
59#define X64_ALIGN_DEBUG_RODATA_END \
60 . = ALIGN(HPAGE_SIZE); \
61 __end_rodata_hpage_align = .;
62
63#else
64
65#define X64_ALIGN_DEBUG_RODATA_BEGIN
66#define X64_ALIGN_DEBUG_RODATA_END
67
68#endif
69
afb8095a
SR
70PHDRS {
71 text PT_LOAD FLAGS(5); /* R_E */
5bd5a452 72 data PT_LOAD FLAGS(6); /* RW_ */
afb8095a 73#ifdef CONFIG_X86_64
8d0cc631 74 user PT_LOAD FLAGS(5); /* R_E */
afb8095a 75#ifdef CONFIG_SMP
8d0cc631 76 percpu PT_LOAD FLAGS(6); /* RW_ */
afb8095a 77#endif
c62e4320 78 init PT_LOAD FLAGS(7); /* RWE */
afb8095a
SR
79#endif
80 note PT_NOTE FLAGS(0); /* ___ */
81}
17ce265d 82
444e0ae4
SR
83SECTIONS
84{
85#ifdef CONFIG_X86_32
86 . = LOAD_OFFSET + LOAD_PHYSICAL_ADDR;
87 phys_startup_32 = startup_32 - LOAD_OFFSET;
88#else
89 . = __START_KERNEL;
90 phys_startup_64 = startup_64 - LOAD_OFFSET;
91#endif
92
dfc20895 93 /* Text and read-only data */
dfc20895 94 .text : AT(ADDR(.text) - LOAD_OFFSET) {
4ae59b91
TA
95 _text = .;
96 /* bootstrapping code */
97 HEAD_TEXT
dfc20895 98#ifdef CONFIG_X86_32
dfc20895 99 . = ALIGN(PAGE_SIZE);
819d6762 100 *(.text..page_aligned)
dfc20895
SR
101#endif
102 . = ALIGN(8);
103 _stext = .;
104 TEXT_TEXT
105 SCHED_TEXT
106 LOCK_TEXT
107 KPROBES_TEXT
ea714547 108 ENTRY_TEXT
dfc20895
SR
109 IRQENTRY_TEXT
110 *(.fixup)
111 *(.gnu.warning)
112 /* End of text section */
113 _etext = .;
114 } :text = 0x9090
115
116 NOTES :text :note
117
123f3e1d 118 EXCEPTION_TABLE(16) :text = 0x9090
448bc3ab 119
5bd5a452
MC
120#if defined(CONFIG_DEBUG_RODATA)
121 /* .text should occupy whole number of pages */
122 . = ALIGN(PAGE_SIZE);
123#endif
74e08179 124 X64_ALIGN_DEBUG_RODATA_BEGIN
c62e4320 125 RO_DATA(PAGE_SIZE)
74e08179 126 X64_ALIGN_DEBUG_RODATA_END
448bc3ab 127
1f6397ba 128 /* Data */
1f6397ba 129 .data : AT(ADDR(.data) - LOAD_OFFSET) {
1260866a
CM
130 /* Start of data section */
131 _sdata = .;
c62e4320
JB
132
133 /* init_task */
134 INIT_TASK_DATA(THREAD_SIZE)
1f6397ba
SR
135
136#ifdef CONFIG_X86_32
c62e4320
JB
137 /* 32 bit has nosave before _edata */
138 NOSAVE_DATA
1f6397ba
SR
139#endif
140
c62e4320 141 PAGE_ALIGNED_DATA(PAGE_SIZE)
1f6397ba 142
350f8f56 143 CACHELINE_ALIGNED_DATA(L1_CACHE_BYTES)
1f6397ba 144
c62e4320
JB
145 DATA_DATA
146 CONSTRUCTORS
147
148 /* rarely changed data like cpu maps */
350f8f56 149 READ_MOSTLY_DATA(INTERNODE_CACHE_BYTES)
1f6397ba 150
1f6397ba
SR
151 /* End of data section */
152 _edata = .;
c62e4320 153 } :data
1f6397ba 154
ff6f87e1
SR
155#ifdef CONFIG_X86_64
156
157#define VSYSCALL_ADDR (-10*1024*1024)
ff6f87e1 158
d223246e 159#define VLOAD_OFFSET (VSYSCALL_ADDR - __vsyscall_0 + LOAD_OFFSET)
ff6f87e1
SR
160#define VLOAD(x) (ADDR(x) - VLOAD_OFFSET)
161
d223246e 162#define VVIRT_OFFSET (VSYSCALL_ADDR - __vsyscall_0)
ff6f87e1
SR
163#define VVIRT(x) (ADDR(x) - VVIRT_OFFSET)
164
d223246e
AK
165 . = ALIGN(4096);
166 __vsyscall_0 = .;
167
ff6f87e1 168 . = VSYSCALL_ADDR;
d223246e 169 .vsyscall_0 : AT(VLOAD(.vsyscall_0)) {
ff6f87e1
SR
170 *(.vsyscall_0)
171 } :user
172
350f8f56 173 . = ALIGN(L1_CACHE_BYTES);
ff6f87e1
SR
174 .vsyscall_fn : AT(VLOAD(.vsyscall_fn)) {
175 *(.vsyscall_fn)
176 }
177
350f8f56 178 . = ALIGN(L1_CACHE_BYTES);
ff6f87e1
SR
179 .vsyscall_gtod_data : AT(VLOAD(.vsyscall_gtod_data)) {
180 *(.vsyscall_gtod_data)
181 }
182
183 vsyscall_gtod_data = VVIRT(.vsyscall_gtod_data);
184 .vsyscall_clock : AT(VLOAD(.vsyscall_clock)) {
185 *(.vsyscall_clock)
186 }
187 vsyscall_clock = VVIRT(.vsyscall_clock);
188
189
190 .vsyscall_1 ADDR(.vsyscall_0) + 1024: AT(VLOAD(.vsyscall_1)) {
191 *(.vsyscall_1)
192 }
193 .vsyscall_2 ADDR(.vsyscall_0) + 2048: AT(VLOAD(.vsyscall_2)) {
194 *(.vsyscall_2)
195 }
196
197 .vgetcpu_mode : AT(VLOAD(.vgetcpu_mode)) {
198 *(.vgetcpu_mode)
199 }
200 vgetcpu_mode = VVIRT(.vgetcpu_mode);
201
350f8f56 202 . = ALIGN(L1_CACHE_BYTES);
ff6f87e1
SR
203 .jiffies : AT(VLOAD(.jiffies)) {
204 *(.jiffies)
205 }
206 jiffies = VVIRT(.jiffies);
207
208 .vsyscall_3 ADDR(.vsyscall_0) + 3072: AT(VLOAD(.vsyscall_3)) {
209 *(.vsyscall_3)
210 }
211
d223246e 212 . = __vsyscall_0 + PAGE_SIZE;
ff6f87e1
SR
213
214#undef VSYSCALL_ADDR
ff6f87e1
SR
215#undef VLOAD_OFFSET
216#undef VLOAD
217#undef VVIRT_OFFSET
218#undef VVIRT
219
220#endif /* CONFIG_X86_64 */
dfc20895 221
c62e4320
JB
222 /* Init code and data - will be freed after init */
223 . = ALIGN(PAGE_SIZE);
224 .init.begin : AT(ADDR(.init.begin) - LOAD_OFFSET) {
225 __init_begin = .; /* paired with __init_end */
e58bdaa8 226 }
e58bdaa8 227
c62e4320 228#if defined(CONFIG_X86_64) && defined(CONFIG_SMP)
e58bdaa8 229 /*
c62e4320
JB
230 * percpu offsets are zero-based on SMP. PERCPU_VADDR() changes the
231 * output PHDR, so the next output section - .init.text - should
232 * start another segment - init.
e58bdaa8 233 */
19df0c2f 234 PERCPU_VADDR(INTERNODE_CACHE_BYTES, 0, :percpu)
c62e4320 235#endif
e58bdaa8 236
123f3e1d 237 INIT_TEXT_SECTION(PAGE_SIZE)
c62e4320
JB
238#ifdef CONFIG_X86_64
239 :init
240#endif
e58bdaa8 241
123f3e1d 242 INIT_DATA_SECTION(16)
e58bdaa8 243
4822b7fc
PA
244 /*
245 * Code and data for a variety of lowlevel trampolines, to be
246 * copied into base memory (< 1 MiB) during initialization.
247 * Since it is copied early, the main copy can be discarded
248 * afterwards.
249 */
250 .x86_trampoline : AT(ADDR(.x86_trampoline) - LOAD_OFFSET) {
251 x86_trampoline_start = .;
252 *(.x86_trampoline)
253 x86_trampoline_end = .;
254 }
255
e58bdaa8
SR
256 .x86_cpu_dev.init : AT(ADDR(.x86_cpu_dev.init) - LOAD_OFFSET) {
257 __x86_cpu_dev_start = .;
258 *(.x86_cpu_dev.init)
259 __x86_cpu_dev_end = .;
260 }
261
6f44d033
KRW
262 /*
263 * start address and size of operations which during runtime
264 * can be patched with virtualization friendly instructions or
265 * baremetal native ones. Think page table operations.
266 * Details in paravirt_types.h
267 */
ae618362
SR
268 . = ALIGN(8);
269 .parainstructions : AT(ADDR(.parainstructions) - LOAD_OFFSET) {
270 __parainstructions = .;
271 *(.parainstructions)
272 __parainstructions_end = .;
273 }
274
6f44d033
KRW
275 /*
276 * struct alt_inst entries. From the header (alternative.h):
277 * "Alternative instructions for different CPU types or capabilities"
278 * Think locking instructions on spinlocks.
279 */
ae618362
SR
280 . = ALIGN(8);
281 .altinstructions : AT(ADDR(.altinstructions) - LOAD_OFFSET) {
282 __alt_instructions = .;
283 *(.altinstructions)
284 __alt_instructions_end = .;
285 }
286
6f44d033
KRW
287 /*
288 * And here are the replacement instructions. The linker sticks
289 * them as binary blobs. The .altinstructions has enough data to
290 * get the address and the length of them to patch the kernel safely.
291 */
ae618362
SR
292 .altinstr_replacement : AT(ADDR(.altinstr_replacement) - LOAD_OFFSET) {
293 *(.altinstr_replacement)
294 }
295
6f44d033
KRW
296 /*
297 * struct iommu_table_entry entries are injected in this section.
298 * It is an array of IOMMUs which during run time gets sorted depending
299 * on its dependency order. After rootfs_initcall is complete
300 * this section can be safely removed.
301 */
0444ad93
KRW
302 .iommu_table : AT(ADDR(.iommu_table) - LOAD_OFFSET) {
303 __iommu_table = .;
304 *(.iommu_table)
0444ad93
KRW
305 __iommu_table_end = .;
306 }
4822b7fc 307
7ac41ccf 308 . = ALIGN(8);
bf6a5741
SR
309 /*
310 * .exit.text is discard at runtime, not link time, to deal with
311 * references from .altinstructions and .eh_frame
312 */
313 .exit.text : AT(ADDR(.exit.text) - LOAD_OFFSET) {
314 EXIT_TEXT
315 }
316
317 .exit.data : AT(ADDR(.exit.data) - LOAD_OFFSET) {
318 EXIT_DATA
319 }
320
c62e4320 321#if !defined(CONFIG_X86_64) || !defined(CONFIG_SMP)
79d8a8f7 322 PERCPU(INTERNODE_CACHE_BYTES, PAGE_SIZE)
9d16e783
SR
323#endif
324
325 . = ALIGN(PAGE_SIZE);
fd073194 326
9d16e783 327 /* freed after init ends here */
fd073194
IM
328 .init.end : AT(ADDR(.init.end) - LOAD_OFFSET) {
329 __init_end = .;
330 }
9d16e783 331
c62e4320
JB
332 /*
333 * smp_locks might be freed after init
334 * start/end must be page aligned
335 */
336 . = ALIGN(PAGE_SIZE);
337 .smp_locks : AT(ADDR(.smp_locks) - LOAD_OFFSET) {
338 __smp_locks = .;
339 *(.smp_locks)
c62e4320 340 . = ALIGN(PAGE_SIZE);
596b711e 341 __smp_locks_end = .;
c62e4320
JB
342 }
343
9d16e783
SR
344#ifdef CONFIG_X86_64
345 .data_nosave : AT(ADDR(.data_nosave) - LOAD_OFFSET) {
c62e4320
JB
346 NOSAVE_DATA
347 }
9d16e783
SR
348#endif
349
091e52c3
SR
350 /* BSS */
351 . = ALIGN(PAGE_SIZE);
352 .bss : AT(ADDR(.bss) - LOAD_OFFSET) {
353 __bss_start = .;
7c74df07 354 *(.bss..page_aligned)
091e52c3 355 *(.bss)
5bd5a452 356 . = ALIGN(PAGE_SIZE);
091e52c3
SR
357 __bss_stop = .;
358 }
9d16e783 359
091e52c3
SR
360 . = ALIGN(PAGE_SIZE);
361 .brk : AT(ADDR(.brk) - LOAD_OFFSET) {
362 __brk_base = .;
363 . += 64 * 1024; /* 64k alignment slop space */
364 *(.brk_reservation) /* areas brk users have reserved */
365 __brk_limit = .;
366 }
367
873b5271 368 _end = .;
091e52c3 369
444e0ae4
SR
370 STABS_DEBUG
371 DWARF_DEBUG
023bf6f1
TH
372
373 /* Sections to be discarded */
374 DISCARDS
375 /DISCARD/ : { *(.eh_frame) }
444e0ae4
SR
376}
377
17ce265d
SR
378
379#ifdef CONFIG_X86_32
a5912f6b
IM
380/*
381 * The ASSERT() sink to . is intentional, for binutils 2.14 compatibility:
382 */
d2ba8b21
PA
383. = ASSERT((_end - LOAD_OFFSET <= KERNEL_IMAGE_SIZE),
384 "kernel image bigger than KERNEL_IMAGE_SIZE");
17ce265d
SR
385#else
386/*
387 * Per-cpu symbols which need to be offset from __per_cpu_load
388 * for the boot processor.
389 */
dd17c8f7 390#define INIT_PER_CPU(x) init_per_cpu__##x = x + __per_cpu_load
17ce265d
SR
391INIT_PER_CPU(gdt_page);
392INIT_PER_CPU(irq_stack_union);
393
394/*
395 * Build-time check on the image size:
396 */
d2ba8b21
PA
397. = ASSERT((_end - _text <= KERNEL_IMAGE_SIZE),
398 "kernel image bigger than KERNEL_IMAGE_SIZE");
17ce265d
SR
399
400#ifdef CONFIG_SMP
dd17c8f7 401. = ASSERT((irq_stack_union == 0),
d2ba8b21 402 "irq_stack_union is not at start of per-cpu area");
17ce265d
SR
403#endif
404
405#endif /* CONFIG_X86_32 */
406
407#ifdef CONFIG_KEXEC
408#include <asm/kexec.h>
409
d2ba8b21
PA
410. = ASSERT(kexec_control_code_size <= KEXEC_CONTROL_CODE_MAX_SIZE,
411 "kexec control code size is too big");
17ce265d
SR
412#endif
413