Commit | Line | Data |
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17ce265d SR |
1 | /* |
2 | * ld script for the x86 kernel | |
3 | * | |
4 | * Historic 32-bit version written by Martin Mares <mj@atrey.karlin.mff.cuni.cz> | |
5 | * | |
91fd7fe8 IM |
6 | * Modernisation, unification and other changes and fixes: |
7 | * Copyright (C) 2007-2009 Sam Ravnborg <sam@ravnborg.org> | |
17ce265d SR |
8 | * |
9 | * | |
10 | * Don't define absolute symbols until and unless you know that symbol | |
11 | * value is should remain constant even if kernel image is relocated | |
12 | * at run time. Absolute symbols are not relocated. If symbol value should | |
13 | * change if kernel is relocated, make the symbol section relative and | |
14 | * put it inside the section definition. | |
15 | */ | |
16 | ||
17 | #ifdef CONFIG_X86_32 | |
18 | #define LOAD_OFFSET __PAGE_OFFSET | |
19 | #else | |
20 | #define LOAD_OFFSET __START_KERNEL_map | |
21 | #endif | |
22 | ||
23 | #include <asm-generic/vmlinux.lds.h> | |
24 | #include <asm/asm-offsets.h> | |
25 | #include <asm/thread_info.h> | |
26 | #include <asm/page_types.h> | |
27 | #include <asm/cache.h> | |
28 | #include <asm/boot.h> | |
29 | ||
30 | #undef i386 /* in case the preprocessor is a 32bit one */ | |
31 | ||
32 | OUTPUT_FORMAT(CONFIG_OUTPUT_FORMAT, CONFIG_OUTPUT_FORMAT, CONFIG_OUTPUT_FORMAT) | |
33 | ||
34 | #ifdef CONFIG_X86_32 | |
35 | OUTPUT_ARCH(i386) | |
36 | ENTRY(phys_startup_32) | |
6b35eb9d | 37 | jiffies = jiffies_64; |
17ce265d SR |
38 | #else |
39 | OUTPUT_ARCH(i386:x86-64) | |
40 | ENTRY(phys_startup_64) | |
6b35eb9d | 41 | jiffies_64 = jiffies; |
17ce265d SR |
42 | #endif |
43 | ||
74e08179 | 44 | #if defined(CONFIG_X86_64) && defined(CONFIG_DEBUG_RODATA) |
d6cc1c3a SS |
45 | /* |
46 | * On 64-bit, align RODATA to 2MB so that even with CONFIG_DEBUG_RODATA | |
47 | * we retain large page mappings for boundaries spanning kernel text, rodata | |
48 | * and data sections. | |
49 | * | |
50 | * However, kernel identity mappings will have different RWX permissions | |
51 | * to the pages mapping to text and to the pages padding (which are freed) the | |
52 | * text section. Hence kernel identity mappings will be broken to smaller | |
53 | * pages. For 64-bit, kernel text and kernel identity mappings are different, | |
54 | * so we can enable protection checks that come with CONFIG_DEBUG_RODATA, | |
55 | * as well as retain 2MB large page mappings for kernel text. | |
56 | */ | |
74e08179 SS |
57 | #define X64_ALIGN_DEBUG_RODATA_BEGIN . = ALIGN(HPAGE_SIZE); |
58 | ||
59 | #define X64_ALIGN_DEBUG_RODATA_END \ | |
60 | . = ALIGN(HPAGE_SIZE); \ | |
61 | __end_rodata_hpage_align = .; | |
62 | ||
63 | #else | |
64 | ||
65 | #define X64_ALIGN_DEBUG_RODATA_BEGIN | |
66 | #define X64_ALIGN_DEBUG_RODATA_END | |
67 | ||
68 | #endif | |
69 | ||
afb8095a SR |
70 | PHDRS { |
71 | text PT_LOAD FLAGS(5); /* R_E */ | |
5bd5a452 | 72 | data PT_LOAD FLAGS(6); /* RW_ */ |
afb8095a | 73 | #ifdef CONFIG_X86_64 |
afb8095a | 74 | #ifdef CONFIG_SMP |
8d0cc631 | 75 | percpu PT_LOAD FLAGS(6); /* RW_ */ |
afb8095a | 76 | #endif |
c62e4320 | 77 | init PT_LOAD FLAGS(7); /* RWE */ |
afb8095a SR |
78 | #endif |
79 | note PT_NOTE FLAGS(0); /* ___ */ | |
80 | } | |
17ce265d | 81 | |
444e0ae4 SR |
82 | SECTIONS |
83 | { | |
84 | #ifdef CONFIG_X86_32 | |
85 | . = LOAD_OFFSET + LOAD_PHYSICAL_ADDR; | |
86 | phys_startup_32 = startup_32 - LOAD_OFFSET; | |
87 | #else | |
88 | . = __START_KERNEL; | |
89 | phys_startup_64 = startup_64 - LOAD_OFFSET; | |
90 | #endif | |
91 | ||
dfc20895 | 92 | /* Text and read-only data */ |
dfc20895 | 93 | .text : AT(ADDR(.text) - LOAD_OFFSET) { |
4ae59b91 TA |
94 | _text = .; |
95 | /* bootstrapping code */ | |
96 | HEAD_TEXT | |
dfc20895 SR |
97 | . = ALIGN(8); |
98 | _stext = .; | |
99 | TEXT_TEXT | |
100 | SCHED_TEXT | |
101 | LOCK_TEXT | |
102 | KPROBES_TEXT | |
ea714547 | 103 | ENTRY_TEXT |
dfc20895 SR |
104 | IRQENTRY_TEXT |
105 | *(.fixup) | |
106 | *(.gnu.warning) | |
107 | /* End of text section */ | |
108 | _etext = .; | |
109 | } :text = 0x9090 | |
110 | ||
111 | NOTES :text :note | |
112 | ||
123f3e1d | 113 | EXCEPTION_TABLE(16) :text = 0x9090 |
448bc3ab | 114 | |
5bd5a452 MC |
115 | #if defined(CONFIG_DEBUG_RODATA) |
116 | /* .text should occupy whole number of pages */ | |
117 | . = ALIGN(PAGE_SIZE); | |
118 | #endif | |
74e08179 | 119 | X64_ALIGN_DEBUG_RODATA_BEGIN |
c62e4320 | 120 | RO_DATA(PAGE_SIZE) |
74e08179 | 121 | X64_ALIGN_DEBUG_RODATA_END |
448bc3ab | 122 | |
1f6397ba | 123 | /* Data */ |
1f6397ba | 124 | .data : AT(ADDR(.data) - LOAD_OFFSET) { |
1260866a CM |
125 | /* Start of data section */ |
126 | _sdata = .; | |
c62e4320 JB |
127 | |
128 | /* init_task */ | |
129 | INIT_TASK_DATA(THREAD_SIZE) | |
1f6397ba SR |
130 | |
131 | #ifdef CONFIG_X86_32 | |
c62e4320 JB |
132 | /* 32 bit has nosave before _edata */ |
133 | NOSAVE_DATA | |
1f6397ba SR |
134 | #endif |
135 | ||
c62e4320 | 136 | PAGE_ALIGNED_DATA(PAGE_SIZE) |
1f6397ba | 137 | |
350f8f56 | 138 | CACHELINE_ALIGNED_DATA(L1_CACHE_BYTES) |
1f6397ba | 139 | |
c62e4320 JB |
140 | DATA_DATA |
141 | CONSTRUCTORS | |
142 | ||
143 | /* rarely changed data like cpu maps */ | |
350f8f56 | 144 | READ_MOSTLY_DATA(INTERNODE_CACHE_BYTES) |
1f6397ba | 145 | |
1f6397ba SR |
146 | /* End of data section */ |
147 | _edata = .; | |
c62e4320 | 148 | } :data |
1f6397ba | 149 | |
ff6f87e1 SR |
150 | #ifdef CONFIG_X86_64 |
151 | ||
9c40818d AL |
152 | . = ALIGN(PAGE_SIZE); |
153 | __vvar_page = .; | |
154 | ||
155 | .vvar : AT(ADDR(.vvar) - LOAD_OFFSET) { | |
f670bb76 AL |
156 | /* work around gold bug 13023 */ |
157 | __vvar_beginning_hack = .; | |
9c40818d | 158 | |
f670bb76 AL |
159 | /* Place all vvars at the offsets in asm/vvar.h. */ |
160 | #define EMIT_VVAR(name, offset) \ | |
161 | . = __vvar_beginning_hack + offset; \ | |
9c40818d AL |
162 | *(.vvar_ ## name) |
163 | #define __VVAR_KERNEL_LDS | |
164 | #include <asm/vvar.h> | |
165 | #undef __VVAR_KERNEL_LDS | |
166 | #undef EMIT_VVAR | |
167 | ||
168 | } :data | |
169 | ||
170 | . = ALIGN(__vvar_page + PAGE_SIZE, PAGE_SIZE); | |
171 | ||
ff6f87e1 | 172 | #endif /* CONFIG_X86_64 */ |
dfc20895 | 173 | |
c62e4320 JB |
174 | /* Init code and data - will be freed after init */ |
175 | . = ALIGN(PAGE_SIZE); | |
176 | .init.begin : AT(ADDR(.init.begin) - LOAD_OFFSET) { | |
177 | __init_begin = .; /* paired with __init_end */ | |
e58bdaa8 | 178 | } |
e58bdaa8 | 179 | |
c62e4320 | 180 | #if defined(CONFIG_X86_64) && defined(CONFIG_SMP) |
e58bdaa8 | 181 | /* |
c62e4320 JB |
182 | * percpu offsets are zero-based on SMP. PERCPU_VADDR() changes the |
183 | * output PHDR, so the next output section - .init.text - should | |
184 | * start another segment - init. | |
e58bdaa8 | 185 | */ |
19df0c2f | 186 | PERCPU_VADDR(INTERNODE_CACHE_BYTES, 0, :percpu) |
c62e4320 | 187 | #endif |
e58bdaa8 | 188 | |
123f3e1d | 189 | INIT_TEXT_SECTION(PAGE_SIZE) |
c62e4320 JB |
190 | #ifdef CONFIG_X86_64 |
191 | :init | |
192 | #endif | |
e58bdaa8 | 193 | |
123f3e1d | 194 | INIT_DATA_SECTION(16) |
e58bdaa8 SR |
195 | |
196 | .x86_cpu_dev.init : AT(ADDR(.x86_cpu_dev.init) - LOAD_OFFSET) { | |
197 | __x86_cpu_dev_start = .; | |
198 | *(.x86_cpu_dev.init) | |
199 | __x86_cpu_dev_end = .; | |
200 | } | |
201 | ||
66ac5013 DC |
202 | #ifdef CONFIG_X86_INTEL_MID |
203 | .x86_intel_mid_dev.init : AT(ADDR(.x86_intel_mid_dev.init) - \ | |
204 | LOAD_OFFSET) { | |
205 | __x86_intel_mid_dev_start = .; | |
206 | *(.x86_intel_mid_dev.init) | |
207 | __x86_intel_mid_dev_end = .; | |
208 | } | |
209 | #endif | |
210 | ||
6f44d033 KRW |
211 | /* |
212 | * start address and size of operations which during runtime | |
213 | * can be patched with virtualization friendly instructions or | |
214 | * baremetal native ones. Think page table operations. | |
215 | * Details in paravirt_types.h | |
216 | */ | |
ae618362 SR |
217 | . = ALIGN(8); |
218 | .parainstructions : AT(ADDR(.parainstructions) - LOAD_OFFSET) { | |
219 | __parainstructions = .; | |
220 | *(.parainstructions) | |
221 | __parainstructions_end = .; | |
222 | } | |
223 | ||
6f44d033 KRW |
224 | /* |
225 | * struct alt_inst entries. From the header (alternative.h): | |
226 | * "Alternative instructions for different CPU types or capabilities" | |
227 | * Think locking instructions on spinlocks. | |
228 | */ | |
ae618362 SR |
229 | . = ALIGN(8); |
230 | .altinstructions : AT(ADDR(.altinstructions) - LOAD_OFFSET) { | |
231 | __alt_instructions = .; | |
232 | *(.altinstructions) | |
233 | __alt_instructions_end = .; | |
234 | } | |
235 | ||
6f44d033 KRW |
236 | /* |
237 | * And here are the replacement instructions. The linker sticks | |
238 | * them as binary blobs. The .altinstructions has enough data to | |
239 | * get the address and the length of them to patch the kernel safely. | |
240 | */ | |
ae618362 SR |
241 | .altinstr_replacement : AT(ADDR(.altinstr_replacement) - LOAD_OFFSET) { |
242 | *(.altinstr_replacement) | |
243 | } | |
244 | ||
6f44d033 KRW |
245 | /* |
246 | * struct iommu_table_entry entries are injected in this section. | |
247 | * It is an array of IOMMUs which during run time gets sorted depending | |
248 | * on its dependency order. After rootfs_initcall is complete | |
249 | * this section can be safely removed. | |
250 | */ | |
0444ad93 KRW |
251 | .iommu_table : AT(ADDR(.iommu_table) - LOAD_OFFSET) { |
252 | __iommu_table = .; | |
253 | *(.iommu_table) | |
0444ad93 KRW |
254 | __iommu_table_end = .; |
255 | } | |
4822b7fc | 256 | |
107e0e0c SS |
257 | . = ALIGN(8); |
258 | .apicdrivers : AT(ADDR(.apicdrivers) - LOAD_OFFSET) { | |
259 | __apicdrivers = .; | |
260 | *(.apicdrivers); | |
261 | __apicdrivers_end = .; | |
262 | } | |
263 | ||
7ac41ccf | 264 | . = ALIGN(8); |
bf6a5741 SR |
265 | /* |
266 | * .exit.text is discard at runtime, not link time, to deal with | |
267 | * references from .altinstructions and .eh_frame | |
268 | */ | |
269 | .exit.text : AT(ADDR(.exit.text) - LOAD_OFFSET) { | |
270 | EXIT_TEXT | |
271 | } | |
272 | ||
273 | .exit.data : AT(ADDR(.exit.data) - LOAD_OFFSET) { | |
274 | EXIT_DATA | |
275 | } | |
276 | ||
c62e4320 | 277 | #if !defined(CONFIG_X86_64) || !defined(CONFIG_SMP) |
0415b00d | 278 | PERCPU_SECTION(INTERNODE_CACHE_BYTES) |
9d16e783 SR |
279 | #endif |
280 | ||
281 | . = ALIGN(PAGE_SIZE); | |
fd073194 | 282 | |
9d16e783 | 283 | /* freed after init ends here */ |
fd073194 IM |
284 | .init.end : AT(ADDR(.init.end) - LOAD_OFFSET) { |
285 | __init_end = .; | |
286 | } | |
9d16e783 | 287 | |
c62e4320 JB |
288 | /* |
289 | * smp_locks might be freed after init | |
290 | * start/end must be page aligned | |
291 | */ | |
292 | . = ALIGN(PAGE_SIZE); | |
293 | .smp_locks : AT(ADDR(.smp_locks) - LOAD_OFFSET) { | |
294 | __smp_locks = .; | |
295 | *(.smp_locks) | |
c62e4320 | 296 | . = ALIGN(PAGE_SIZE); |
596b711e | 297 | __smp_locks_end = .; |
c62e4320 JB |
298 | } |
299 | ||
9d16e783 SR |
300 | #ifdef CONFIG_X86_64 |
301 | .data_nosave : AT(ADDR(.data_nosave) - LOAD_OFFSET) { | |
c62e4320 JB |
302 | NOSAVE_DATA |
303 | } | |
9d16e783 SR |
304 | #endif |
305 | ||
091e52c3 SR |
306 | /* BSS */ |
307 | . = ALIGN(PAGE_SIZE); | |
308 | .bss : AT(ADDR(.bss) - LOAD_OFFSET) { | |
309 | __bss_start = .; | |
7c74df07 | 310 | *(.bss..page_aligned) |
091e52c3 | 311 | *(.bss) |
5bd5a452 | 312 | . = ALIGN(PAGE_SIZE); |
091e52c3 SR |
313 | __bss_stop = .; |
314 | } | |
9d16e783 | 315 | |
091e52c3 SR |
316 | . = ALIGN(PAGE_SIZE); |
317 | .brk : AT(ADDR(.brk) - LOAD_OFFSET) { | |
318 | __brk_base = .; | |
319 | . += 64 * 1024; /* 64k alignment slop space */ | |
320 | *(.brk_reservation) /* areas brk users have reserved */ | |
321 | __brk_limit = .; | |
322 | } | |
323 | ||
873b5271 | 324 | _end = .; |
091e52c3 | 325 | |
444e0ae4 SR |
326 | STABS_DEBUG |
327 | DWARF_DEBUG | |
023bf6f1 TH |
328 | |
329 | /* Sections to be discarded */ | |
330 | DISCARDS | |
331 | /DISCARD/ : { *(.eh_frame) } | |
444e0ae4 SR |
332 | } |
333 | ||
17ce265d SR |
334 | |
335 | #ifdef CONFIG_X86_32 | |
a5912f6b IM |
336 | /* |
337 | * The ASSERT() sink to . is intentional, for binutils 2.14 compatibility: | |
338 | */ | |
d2ba8b21 PA |
339 | . = ASSERT((_end - LOAD_OFFSET <= KERNEL_IMAGE_SIZE), |
340 | "kernel image bigger than KERNEL_IMAGE_SIZE"); | |
17ce265d SR |
341 | #else |
342 | /* | |
343 | * Per-cpu symbols which need to be offset from __per_cpu_load | |
344 | * for the boot processor. | |
345 | */ | |
dd17c8f7 | 346 | #define INIT_PER_CPU(x) init_per_cpu__##x = x + __per_cpu_load |
17ce265d SR |
347 | INIT_PER_CPU(gdt_page); |
348 | INIT_PER_CPU(irq_stack_union); | |
349 | ||
350 | /* | |
351 | * Build-time check on the image size: | |
352 | */ | |
d2ba8b21 PA |
353 | . = ASSERT((_end - _text <= KERNEL_IMAGE_SIZE), |
354 | "kernel image bigger than KERNEL_IMAGE_SIZE"); | |
17ce265d SR |
355 | |
356 | #ifdef CONFIG_SMP | |
dd17c8f7 | 357 | . = ASSERT((irq_stack_union == 0), |
d2ba8b21 | 358 | "irq_stack_union is not at start of per-cpu area"); |
17ce265d SR |
359 | #endif |
360 | ||
361 | #endif /* CONFIG_X86_32 */ | |
362 | ||
363 | #ifdef CONFIG_KEXEC | |
364 | #include <asm/kexec.h> | |
365 | ||
d2ba8b21 PA |
366 | . = ASSERT(kexec_control_code_size <= KEXEC_CONTROL_CODE_MAX_SIZE, |
367 | "kexec control code size is too big"); | |
17ce265d SR |
368 | #endif |
369 |