[linux-2.6-block.git] / arch / x86 / kernel / uv_time.c

/*
 * SGI RTC clock/timer routines.
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the Free Software
 *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 *
 *  Copyright (c) 2009 Silicon Graphics, Inc.  All Rights Reserved.
 *  Copyright (c) Dimitri Sivanich
 */
#include <linux/clockchips.h>

#include <asm/uv/uv_mmrs.h>
#include <asm/uv/uv_hub.h>
#include <asm/uv/bios.h>
#include <asm/uv/uv.h>
#include <asm/apic.h>
#include <asm/cpu.h>

#define RTC_NAME		"sgi_rtc"

static cycle_t uv_read_rtc(struct clocksource *cs);
static int uv_rtc_next_event(unsigned long, struct clock_event_device *);
static void uv_rtc_timer_setup(enum clock_event_mode,
				struct clock_event_device *);

static struct clocksource clocksource_uv = {
	.name		= RTC_NAME,
	.rating		= 400,
	.read		= uv_read_rtc,
	.mask		= (cycle_t)UVH_RTC_REAL_TIME_CLOCK_MASK,
	.shift		= 10,
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
};

static struct clock_event_device clock_event_device_uv = {
	.name		= RTC_NAME,
	.features	= CLOCK_EVT_FEAT_ONESHOT,
	.shift		= 20,
	.rating		= 400,
	.irq		= -1,
	.set_next_event	= uv_rtc_next_event,
	.set_mode	= uv_rtc_timer_setup,
	.event_handler	= NULL,
};

static DEFINE_PER_CPU(struct clock_event_device, cpu_ced);

/* There is one of these allocated per node */
struct uv_rtc_timer_head {
	spinlock_t	lock;
	/* next cpu waiting for timer, local node relative: */
	int		next_cpu;
	/* number of cpus on this node: */
	int		ncpus;
	struct {
		int	lcpu;		/* systemwide logical cpu number */
		u64	expires;	/* next timer expiration for this cpu */
	} cpu[1];
};

/*
 * Access to uv_rtc_timer_head via blade id.
 */
static struct uv_rtc_timer_head		**blade_info __read_mostly;

static int				uv_rtc_evt_enable;

/*
 * Hardware interface routines
 */

/* Send IPIs to another node */
static void uv_rtc_send_IPI(int cpu)
{
	unsigned long apicid, val;
	int pnode;

	apicid = cpu_physical_id(cpu);
	pnode = uv_apicid_to_pnode(apicid);
	val = (1UL << UVH_IPI_INT_SEND_SHFT) |
	      (apicid << UVH_IPI_INT_APIC_ID_SHFT) |
	      (X86_PLATFORM_IPI_VECTOR << UVH_IPI_INT_VECTOR_SHFT);

	uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
}

/* Check for an RTC interrupt pending */
static int uv_intr_pending(int pnode)
{
	return uv_read_global_mmr64(pnode, UVH_EVENT_OCCURRED0) &
		UVH_EVENT_OCCURRED0_RTC1_MASK;
}

/* Setup interrupt and return non-zero if early expiration occurred. */
static int uv_setup_intr(int cpu, u64 expires)
{
	u64 val;
	int pnode = uv_cpu_to_pnode(cpu);

	uv_write_global_mmr64(pnode, UVH_RTC1_INT_CONFIG,
		UVH_RTC1_INT_CONFIG_M_MASK);
	uv_write_global_mmr64(pnode, UVH_INT_CMPB, -1L);

	uv_write_global_mmr64(pnode, UVH_EVENT_OCCURRED0_ALIAS,
		UVH_EVENT_OCCURRED0_RTC1_MASK);

	val = (X86_PLATFORM_IPI_VECTOR << UVH_RTC1_INT_CONFIG_VECTOR_SHFT) |
		((u64)cpu_physical_id(cpu) << UVH_RTC1_INT_CONFIG_APIC_ID_SHFT);

	/* Set configuration */
	uv_write_global_mmr64(pnode, UVH_RTC1_INT_CONFIG, val);
	/* Initialize comparator value */
	uv_write_global_mmr64(pnode, UVH_INT_CMPB, expires);

	if (uv_read_rtc(NULL) <= expires)
		return 0;

	return !uv_intr_pending(pnode);
}

/*
 * Per-cpu timer tracking routines
 */

static __init void uv_rtc_deallocate_timers(void)
{
	int bid;

	for_each_possible_blade(bid) {
		kfree(blade_info[bid]);
	}
	kfree(blade_info);
}

/* Allocate per-node list of cpu timer expiration times. */
static __init int uv_rtc_allocate_timers(void)
{
	int cpu;

	blade_info = kmalloc(uv_possible_blades * sizeof(void *), GFP_KERNEL);
	if (!blade_info)
		return -ENOMEM;
	memset(blade_info, 0, uv_possible_blades * sizeof(void *));

	for_each_present_cpu(cpu) {
		int nid = cpu_to_node(cpu);
		int bid = uv_cpu_to_blade_id(cpu);
		int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id;
		struct uv_rtc_timer_head *head = blade_info[bid];

		if (!head) {
			head = kmalloc_node(sizeof(struct uv_rtc_timer_head) +
				(uv_blade_nr_possible_cpus(bid) *
					2 * sizeof(u64)),
				GFP_KERNEL, nid);
			if (!head) {
				uv_rtc_deallocate_timers();
				return -ENOMEM;
			}
			spin_lock_init(&head->lock);
			head->ncpus = uv_blade_nr_possible_cpus(bid);
			head->next_cpu = -1;
			blade_info[bid] = head;
		}

		head->cpu[bcpu].lcpu = cpu;
		head->cpu[bcpu].expires = ULLONG_MAX;
	}

	return 0;
}

/* Find and set the next expiring timer.  */
static void uv_rtc_find_next_timer(struct uv_rtc_timer_head *head, int pnode)
{
	u64 lowest = ULLONG_MAX;
	int c, bcpu = -1;

	head->next_cpu = -1;
	for (c = 0; c < head->ncpus; c++) {
		u64 exp = head->cpu[c].expires;
		if (exp < lowest) {
			bcpu = c;
			lowest = exp;
		}
	}
	if (bcpu >= 0) {
		head->next_cpu = bcpu;
		c = head->cpu[bcpu].lcpu;
		if (uv_setup_intr(c, lowest))
			/* If we didn't set it up in time, trigger */
			uv_rtc_send_IPI(c);
	} else {
		uv_write_global_mmr64(pnode, UVH_RTC1_INT_CONFIG,
			UVH_RTC1_INT_CONFIG_M_MASK);
	}
}

/*
 * Set expiration time for current cpu.
 *
 * Returns 1 if we missed the expiration time.
 */
static int uv_rtc_set_timer(int cpu, u64 expires)
{
	int pnode = uv_cpu_to_pnode(cpu);
	int bid = uv_cpu_to_blade_id(cpu);
	struct uv_rtc_timer_head *head = blade_info[bid];
	int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id;
	u64 *t = &head->cpu[bcpu].expires;
	unsigned long flags;
	int next_cpu;

	spin_lock_irqsave(&head->lock, flags);

	next_cpu = head->next_cpu;
	*t = expires;

	/* Will this one be next to go off? */
	if (next_cpu < 0 || bcpu == next_cpu ||
			expires < head->cpu[next_cpu].expires) {
		head->next_cpu = bcpu;
		if (uv_setup_intr(cpu, expires)) {
			*t = ULLONG_MAX;
			uv_rtc_find_next_timer(head, pnode);
			spin_unlock_irqrestore(&head->lock, flags);
			return -ETIME;
		}
	}

	spin_unlock_irqrestore(&head->lock, flags);
	return 0;
}

/*
 * Unset expiration time for current cpu.
 *
 * Returns 1 if this timer was pending.
 */
static int uv_rtc_unset_timer(int cpu, int force)
{
	int pnode = uv_cpu_to_pnode(cpu);
	int bid = uv_cpu_to_blade_id(cpu);
	struct uv_rtc_timer_head *head = blade_info[bid];
	int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id;
	u64 *t = &head->cpu[bcpu].expires;
	unsigned long flags;
	int rc = 0;

	spin_lock_irqsave(&head->lock, flags);

	if ((head->next_cpu == bcpu && uv_read_rtc(NULL) >= *t) || force)
		rc = 1;

	if (rc) {
		*t = ULLONG_MAX;
		/* Was the hardware setup for this timer? */
		if (head->next_cpu == bcpu)
			uv_rtc_find_next_timer(head, pnode);
	}

	spin_unlock_irqrestore(&head->lock, flags);

	return rc;
}


/*
 * Kernel interface routines.
 */

/*
 * Read the RTC.
 *
 * Starting with HUB rev 2.0, the UV RTC register is replicated across all
 * cachelines of it's own page.  This allows faster simultaneous reads
 * from a given socket.
 */
static cycle_t uv_read_rtc(struct clocksource *cs)
{
	unsigned long offset;

	if (uv_get_min_hub_revision_id() == 1)
		offset = 0;
	else
		offset = (uv_blade_processor_id() * L1_CACHE_BYTES) % PAGE_SIZE;

	return (cycle_t)uv_read_local_mmr(UVH_RTC | offset);
}

/*
 * Program the next event, relative to now
 */
static int uv_rtc_next_event(unsigned long delta,
			     struct clock_event_device *ced)
{
	int ced_cpu = cpumask_first(ced->cpumask);

	return uv_rtc_set_timer(ced_cpu, delta + uv_read_rtc(NULL));
}

/*
 * Setup the RTC timer in oneshot mode
 */
static void uv_rtc_timer_setup(enum clock_event_mode mode,
			       struct clock_event_device *evt)
{
	int ced_cpu = cpumask_first(evt->cpumask);

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
	case CLOCK_EVT_MODE_ONESHOT:
	case CLOCK_EVT_MODE_RESUME:
		/* Nothing to do here yet */
		break;
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
		uv_rtc_unset_timer(ced_cpu, 1);
		break;
	}
}

static void uv_rtc_interrupt(void)
{
	int cpu = smp_processor_id();
	struct clock_event_device *ced = &per_cpu(cpu_ced, cpu);

	if (!ced || !ced->event_handler)
		return;

	if (uv_rtc_unset_timer(cpu, 0) != 1)
		return;

	ced->event_handler(ced);
}

static int __init uv_enable_evt_rtc(char *str)
{
	uv_rtc_evt_enable = 1;

	return 1;
}
__setup("uvrtcevt", uv_enable_evt_rtc);

static __init void uv_rtc_register_clockevents(struct work_struct *dummy)
{
	struct clock_event_device *ced = &__get_cpu_var(cpu_ced);

	*ced = clock_event_device_uv;
	ced->cpumask = cpumask_of(smp_processor_id());
	clockevents_register_device(ced);
}

static __init int uv_rtc_setup_clock(void)
{
	int rc;

	if (!is_uv_system())
		return -ENODEV;

	clocksource_uv.mult = clocksource_hz2mult(sn_rtc_cycles_per_second,
				clocksource_uv.shift);

	/* If single blade, prefer tsc */
	if (uv_num_possible_blades() == 1)
		clocksource_uv.rating = 250;

	rc = clocksource_register(&clocksource_uv);
	if (rc)
		printk(KERN_INFO "UV RTC clocksource failed rc %d\n", rc);
	else
		printk(KERN_INFO "UV RTC clocksource registered freq %lu MHz\n",
			sn_rtc_cycles_per_second/(unsigned long)1E6);

	if (rc || !uv_rtc_evt_enable || x86_platform_ipi_callback)
		return rc;

	/* Setup and register clockevents */
	rc = uv_rtc_allocate_timers();
	if (rc)
		goto error;

	x86_platform_ipi_callback = uv_rtc_interrupt;

	clock_event_device_uv.mult = div_sc(sn_rtc_cycles_per_second,
				NSEC_PER_SEC, clock_event_device_uv.shift);

	clock_event_device_uv.min_delta_ns = NSEC_PER_SEC /
						sn_rtc_cycles_per_second;

	clock_event_device_uv.max_delta_ns = clocksource_uv.mask *
				(NSEC_PER_SEC / sn_rtc_cycles_per_second);

	rc = schedule_on_each_cpu(uv_rtc_register_clockevents);
	if (rc) {
		x86_platform_ipi_callback = NULL;
		uv_rtc_deallocate_timers();
		goto error;
	}

	printk(KERN_INFO "UV RTC clockevents registered\n");

	return 0;

error:
	clocksource_unregister(&clocksource_uv);
	printk(KERN_INFO "UV RTC clockevents failed rc %d\n", rc);

	return rc;
}
arch_initcall(uv_rtc_setup_clock);
Commit	Line	Data
5ab5ab34 DS	1	/*
	2	* SGI RTC clock/timer routines.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; either version 2 of the License, or
	7	* (at your option) any later version.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	17	*
	18	* Copyright (c) 2009 Silicon Graphics, Inc. All Rights Reserved.
	19	* Copyright (c) Dimitri Sivanich
	20	*/
	21	#include <linux/clockchips.h>
	22
	23	#include <asm/uv/uv_mmrs.h>
	24	#include <asm/uv/uv_hub.h>
	25	#include <asm/uv/bios.h>
	26	#include <asm/uv/uv.h>
1400b3fa DS	27	#include <asm/apic.h>
1400b3fa DS	28	#include <asm/cpu.h>
5ab5ab34 DS	29
	30	#define RTC_NAME "sgi_rtc"
	31
c5428e95	32	static cycle_t uv_read_rtc(struct clocksource *cs);
5ab5ab34 DS	33	static int uv_rtc_next_event(unsigned long, struct clock_event_device *);
	34	static void uv_rtc_timer_setup(enum clock_event_mode,
	35	struct clock_event_device *);
	36
	37	static struct clocksource clocksource_uv = {
	38	.name = RTC_NAME,
	39	.rating = 400,
	40	.read = uv_read_rtc,
	41	.mask = (cycle_t)UVH_RTC_REAL_TIME_CLOCK_MASK,
	42	.shift = 10,
	43	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	44	};
	45
	46	static struct clock_event_device clock_event_device_uv = {
	47	.name = RTC_NAME,
	48	.features = CLOCK_EVT_FEAT_ONESHOT,
	49	.shift = 20,
	50	.rating = 400,
	51	.irq = -1,
	52	.set_next_event = uv_rtc_next_event,
	53	.set_mode = uv_rtc_timer_setup,
	54	.event_handler = NULL,
	55	};
	56
	57	static DEFINE_PER_CPU(struct clock_event_device, cpu_ced);
	58
	59	/* There is one of these allocated per node */
	60	struct uv_rtc_timer_head {
	61	spinlock_t lock;
	62	/* next cpu waiting for timer, local node relative: */
	63	int next_cpu;
	64	/* number of cpus on this node: */
	65	int ncpus;
	66	struct {
	67	int lcpu; /* systemwide logical cpu number */
	68	u64 expires; /* next timer expiration for this cpu */
	69	} cpu[1];
	70	};
	71
	72	/*
	73	* Access to uv_rtc_timer_head via blade id.
	74	*/
	75	static struct uv_rtc_timer_head **blade_info __read_mostly;
	76
8c28de4d	77	static int uv_rtc_evt_enable;
5ab5ab34 DS	78
	79	/*
	80	* Hardware interface routines
	81	*/
	82
	83	/* Send IPIs to another node */
	84	static void uv_rtc_send_IPI(int cpu)
	85	{
	86	unsigned long apicid, val;
	87	int pnode;
	88
1400b3fa	89	apicid = cpu_physical_id(cpu);
5ab5ab34 DS	90	pnode = uv_apicid_to_pnode(apicid);
	91	val = (1UL << UVH_IPI_INT_SEND_SHFT) \|
	92	(apicid << UVH_IPI_INT_APIC_ID_SHFT) \|
4a4de9c7	93	(X86_PLATFORM_IPI_VECTOR << UVH_IPI_INT_VECTOR_SHFT);
5ab5ab34 DS	94
	95	uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
	96	}
	97
	98	/* Check for an RTC interrupt pending */
	99	static int uv_intr_pending(int pnode)
	100	{
	101	return uv_read_global_mmr64(pnode, UVH_EVENT_OCCURRED0) &
	102	UVH_EVENT_OCCURRED0_RTC1_MASK;
	103	}
	104
	105	/* Setup interrupt and return non-zero if early expiration occurred. */
	106	static int uv_setup_intr(int cpu, u64 expires)
	107	{
	108	u64 val;
	109	int pnode = uv_cpu_to_pnode(cpu);
	110
	111	uv_write_global_mmr64(pnode, UVH_RTC1_INT_CONFIG,
	112	UVH_RTC1_INT_CONFIG_M_MASK);
	113	uv_write_global_mmr64(pnode, UVH_INT_CMPB, -1L);
	114
	115	uv_write_global_mmr64(pnode, UVH_EVENT_OCCURRED0_ALIAS,
	116	UVH_EVENT_OCCURRED0_RTC1_MASK);
	117
4a4de9c7	118	val = (X86_PLATFORM_IPI_VECTOR << UVH_RTC1_INT_CONFIG_VECTOR_SHFT) \|
5ab5ab34 DS	119	((u64)cpu_physical_id(cpu) << UVH_RTC1_INT_CONFIG_APIC_ID_SHFT);
	120
	121	/* Set configuration */
	122	uv_write_global_mmr64(pnode, UVH_RTC1_INT_CONFIG, val);
	123	/* Initialize comparator value */
	124	uv_write_global_mmr64(pnode, UVH_INT_CMPB, expires);
	125
e47938b1 DS	126	if (uv_read_rtc(NULL) <= expires)
	127	return 0;
	128
	129	return !uv_intr_pending(pnode);
5ab5ab34 DS	130	}
	131
	132	/*
	133	* Per-cpu timer tracking routines
	134	*/
	135
	136	static __init void uv_rtc_deallocate_timers(void)
	137	{
	138	int bid;
	139
	140	for_each_possible_blade(bid) {
	141	kfree(blade_info[bid]);
	142	}
	143	kfree(blade_info);
	144	}
	145
	146	/* Allocate per-node list of cpu timer expiration times. */
	147	static __init int uv_rtc_allocate_timers(void)
	148	{
	149	int cpu;
	150
	151	blade_info = kmalloc(uv_possible_blades * sizeof(void *), GFP_KERNEL);
	152	if (!blade_info)
	153	return -ENOMEM;
	154	memset(blade_info, 0, uv_possible_blades * sizeof(void *));
	155
	156	for_each_present_cpu(cpu) {
	157	int nid = cpu_to_node(cpu);
	158	int bid = uv_cpu_to_blade_id(cpu);
	159	int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id;
	160	struct uv_rtc_timer_head *head = blade_info[bid];
	161
	162	if (!head) {
	163	head = kmalloc_node(sizeof(struct uv_rtc_timer_head) +
	164	(uv_blade_nr_possible_cpus(bid) *
	165	2 * sizeof(u64)),
	166	GFP_KERNEL, nid);
	167	if (!head) {
	168	uv_rtc_deallocate_timers();
	169	return -ENOMEM;
	170	}
	171	spin_lock_init(&head->lock);
	172	head->ncpus = uv_blade_nr_possible_cpus(bid);
	173	head->next_cpu = -1;
	174	blade_info[bid] = head;
	175	}
	176
	177	head->cpu[bcpu].lcpu = cpu;
	178	head->cpu[bcpu].expires = ULLONG_MAX;
	179	}
	180
	181	return 0;
	182	}
	183
	184	/* Find and set the next expiring timer. */
	185	static void uv_rtc_find_next_timer(struct uv_rtc_timer_head *head, int pnode)
	186	{
	187	u64 lowest = ULLONG_MAX;
	188	int c, bcpu = -1;
	189
	190	head->next_cpu = -1;
	191	for (c = 0; c < head->ncpus; c++) {
	192	u64 exp = head->cpu[c].expires;
	193	if (exp < lowest) {
194	bcpu = c;
195	lowest = exp;
196	}
197	}
198	if (bcpu >= 0) {
199	head->next_cpu = bcpu;
200	c = head->cpu[bcpu].lcpu;
201	if (uv_setup_intr(c, lowest))
202	/* If we didn't set it up in time, trigger */
203	uv_rtc_send_IPI(c);
204	} else {
205	uv_write_global_mmr64(pnode, UVH_RTC1_INT_CONFIG,
206	UVH_RTC1_INT_CONFIG_M_MASK);
207	}
208	}
209
210	/*
211	* Set expiration time for current cpu.
212	*
213	* Returns 1 if we missed the expiration time.
214	*/
215	static int uv_rtc_set_timer(int cpu, u64 expires)
216	{
217	int pnode = uv_cpu_to_pnode(cpu);
218	int bid = uv_cpu_to_blade_id(cpu);
219	struct uv_rtc_timer_head *head = blade_info[bid];
220	int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id;
221	u64 *t = &head->cpu[bcpu].expires;
222	unsigned long flags;
223	int next_cpu;
224
225	spin_lock_irqsave(&head->lock, flags);
226
227	next_cpu = head->next_cpu;
228	*t = expires;
e47938b1	229
5ab5ab34 DS	230	/* Will this one be next to go off? */
	231	if (next_cpu < 0 \|\| bcpu == next_cpu \|\|
	232	expires < head->cpu[next_cpu].expires) {
	233	head->next_cpu = bcpu;
	234	if (uv_setup_intr(cpu, expires)) {
	235	*t = ULLONG_MAX;
	236	uv_rtc_find_next_timer(head, pnode);
	237	spin_unlock_irqrestore(&head->lock, flags);
e47938b1	238	return -ETIME;
5ab5ab34 DS	239	}
	240	}
	241
	242	spin_unlock_irqrestore(&head->lock, flags);
	243	return 0;
	244	}
	245
	246	/*
	247	* Unset expiration time for current cpu.
	248	*
	249	* Returns 1 if this timer was pending.
	250	*/
e47938b1	251	static int uv_rtc_unset_timer(int cpu, int force)
5ab5ab34 DS	252	{
	253	int pnode = uv_cpu_to_pnode(cpu);
	254	int bid = uv_cpu_to_blade_id(cpu);
	255	struct uv_rtc_timer_head *head = blade_info[bid];
	256	int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id;
	257	u64 *t = &head->cpu[bcpu].expires;
	258	unsigned long flags;
	259	int rc = 0;
	260
	261	spin_lock_irqsave(&head->lock, flags);
	262
e47938b1	263	if ((head->next_cpu == bcpu && uv_read_rtc(NULL) >= *t) \|\| force)
5ab5ab34 DS	264	rc = 1;
5ab5ab34 DS	265
e47938b1 DS	266	if (rc) {
	267	*t = ULLONG_MAX;
	268	/* Was the hardware setup for this timer? */
	269	if (head->next_cpu == bcpu)
	270	uv_rtc_find_next_timer(head, pnode);
	271	}
5ab5ab34 DS	272
	273	spin_unlock_irqrestore(&head->lock, flags);
	274
	275	return rc;
	276	}
	277
	278
	279	/*
	280	* Kernel interface routines.
	281	*/
	282
	283	/*
	284	* Read the RTC.
aca3bb59 DS	285	*
	286	* Starting with HUB rev 2.0, the UV RTC register is replicated across all
	287	* cachelines of it's own page. This allows faster simultaneous reads
	288	* from a given socket.
5ab5ab34	289	*/
c5428e95	290	static cycle_t uv_read_rtc(struct clocksource *cs)
5ab5ab34	291	{
aca3bb59 DS	292	unsigned long offset;
	293
	294	if (uv_get_min_hub_revision_id() == 1)
	295	offset = 0;
	296	else
	297	offset = (uv_blade_processor_id() * L1_CACHE_BYTES) % PAGE_SIZE;
	298
	299	return (cycle_t)uv_read_local_mmr(UVH_RTC \| offset);
5ab5ab34 DS	300	}
	301
	302	/*
	303	* Program the next event, relative to now
	304	*/
	305	static int uv_rtc_next_event(unsigned long delta,
	306	struct clock_event_device *ced)
	307	{
	308	int ced_cpu = cpumask_first(ced->cpumask);
	309
c5428e95	310	return uv_rtc_set_timer(ced_cpu, delta + uv_read_rtc(NULL));
5ab5ab34 DS	311	}
	312
	313	/*
	314	* Setup the RTC timer in oneshot mode
	315	*/
	316	static void uv_rtc_timer_setup(enum clock_event_mode mode,
	317	struct clock_event_device *evt)
	318	{
	319	int ced_cpu = cpumask_first(evt->cpumask);
	320
	321	switch (mode) {
	322	case CLOCK_EVT_MODE_PERIODIC:
	323	case CLOCK_EVT_MODE_ONESHOT:
	324	case CLOCK_EVT_MODE_RESUME:
	325	/* Nothing to do here yet */
	326	break;
	327	case CLOCK_EVT_MODE_UNUSED:
	328	case CLOCK_EVT_MODE_SHUTDOWN:
e47938b1	329	uv_rtc_unset_timer(ced_cpu, 1);
5ab5ab34 DS	330	break;
	331	}
	332	}
	333
	334	static void uv_rtc_interrupt(void)
	335	{
5ab5ab34	336	int cpu = smp_processor_id();
e47938b1	337	struct clock_event_device *ced = &per_cpu(cpu_ced, cpu);
5ab5ab34 DS	338
	339	if (!ced \|\| !ced->event_handler)
	340	return;
	341
e47938b1	342	if (uv_rtc_unset_timer(cpu, 0) != 1)
5ab5ab34 DS	343	return;
	344
	345	ced->event_handler(ced);
	346	}
	347
8c28de4d DS	348	static int __init uv_enable_evt_rtc(char *str)
	349	{
	350	uv_rtc_evt_enable = 1;
	351
	352	return 1;
	353	}
	354	__setup("uvrtcevt", uv_enable_evt_rtc);
	355
5ab5ab34 DS	356	static __init void uv_rtc_register_clockevents(struct work_struct *dummy)
	357	{
	358	struct clock_event_device *ced = &__get_cpu_var(cpu_ced);
	359
	360	*ced = clock_event_device_uv;
	361	ced->cpumask = cpumask_of(smp_processor_id());
	362	clockevents_register_device(ced);
	363	}
	364
	365	static __init int uv_rtc_setup_clock(void)
	366	{
	367	int rc;
	368
581f202b	369	if (!is_uv_system())
5ab5ab34 DS	370	return -ENODEV;
5ab5ab34 DS	371
5ab5ab34 DS	372	clocksource_uv.mult = clocksource_hz2mult(sn_rtc_cycles_per_second,
	373	clocksource_uv.shift);
	374
581f202b DS	375	/* If single blade, prefer tsc */
	376	if (uv_num_possible_blades() == 1)
	377	clocksource_uv.rating = 250;
	378
5ab5ab34	379	rc = clocksource_register(&clocksource_uv);
8c28de4d DS	380	if (rc)
	381	printk(KERN_INFO "UV RTC clocksource failed rc %d\n", rc);
	382	else
	383	printk(KERN_INFO "UV RTC clocksource registered freq %lu MHz\n",
	384	sn_rtc_cycles_per_second/(unsigned long)1E6);
	385
581f202b	386	if (rc \|\| !uv_rtc_evt_enable \|\| x86_platform_ipi_callback)
5ab5ab34	387	return rc;
8c28de4d	388
5ab5ab34 DS	389	/* Setup and register clockevents */
5ab5ab34 DS	390	rc = uv_rtc_allocate_timers();
d5991ff2 DS	391	if (rc)
	392	goto error;
	393
4a4de9c7	394	x86_platform_ipi_callback = uv_rtc_interrupt;
5ab5ab34 DS	395
	396	clock_event_device_uv.mult = div_sc(sn_rtc_cycles_per_second,
	397	NSEC_PER_SEC, clock_event_device_uv.shift);
	398
	399	clock_event_device_uv.min_delta_ns = NSEC_PER_SEC /
	400	sn_rtc_cycles_per_second;
	401
	402	clock_event_device_uv.max_delta_ns = clocksource_uv.mask *
	403	(NSEC_PER_SEC / sn_rtc_cycles_per_second);
	404
	405	rc = schedule_on_each_cpu(uv_rtc_register_clockevents);
	406	if (rc) {
4a4de9c7	407	x86_platform_ipi_callback = NULL;
5ab5ab34	408	uv_rtc_deallocate_timers();
d5991ff2	409	goto error;
5ab5ab34 DS	410	}
5ab5ab34 DS	411
d5991ff2 DS	412	printk(KERN_INFO "UV RTC clockevents registered\n");
	413
	414	return 0;
	415
	416	error:
	417	clocksource_unregister(&clocksource_uv);
	418	printk(KERN_INFO "UV RTC clockevents failed rc %d\n", rc);
	419
5ab5ab34 DS	420	return rc;
	421	}
	422	arch_initcall(uv_rtc_setup_clock);