[linux-2.6-block.git] / arch / x86 / kernel / uv_irq.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * SGI UV IRQ functions
 *
 * Copyright (C) 2008 Silicon Graphics, Inc. All rights reserved.
 */

#include <linux/module.h>
#include <linux/rbtree.h>
#include <linux/irq.h>

#include <asm/apic.h>
#include <asm/uv/uv_irq.h>
#include <asm/uv/uv_hub.h>

/* MMR offset and pnode of hub sourcing interrupts for a given irq */
struct uv_irq_2_mmr_pnode{
	struct rb_node		list;
	unsigned long		offset;
	int			pnode;
	int			irq;
};

static spinlock_t		uv_irq_lock;
static struct rb_root		uv_irq_root;

static int uv_set_irq_affinity(unsigned int, const struct cpumask *);

static void uv_noop(unsigned int irq)
{
}

static unsigned int uv_noop_ret(unsigned int irq)
{
	return 0;
}

static void uv_ack_apic(unsigned int irq)
{
	ack_APIC_irq();
}

struct irq_chip uv_irq_chip = {
	.name		= "UV-CORE",
	.startup	= uv_noop_ret,
	.shutdown	= uv_noop,
	.enable		= uv_noop,
	.disable	= uv_noop,
	.ack		= uv_noop,
	.mask		= uv_noop,
	.unmask		= uv_noop,
	.eoi		= uv_ack_apic,
	.end		= uv_noop,
	.set_affinity	= uv_set_irq_affinity,
};

/*
 * Add offset and pnode information of the hub sourcing interrupts to the
 * rb tree for a specific irq.
 */
static int uv_set_irq_2_mmr_info(int irq, unsigned long offset, unsigned blade)
{
	struct rb_node **link = &uv_irq_root.rb_node;
	struct rb_node *parent = NULL;
	struct uv_irq_2_mmr_pnode *n;
	struct uv_irq_2_mmr_pnode *e;
	unsigned long irqflags;

	n = kmalloc_node(sizeof(struct uv_irq_2_mmr_pnode), GFP_KERNEL,
				uv_blade_to_memory_nid(blade));
	if (!n)
		return -ENOMEM;

	n->irq = irq;
	n->offset = offset;
	n->pnode = uv_blade_to_pnode(blade);
	spin_lock_irqsave(&uv_irq_lock, irqflags);
	/* Find the right place in the rbtree: */
	while (*link) {
		parent = *link;
		e = rb_entry(parent, struct uv_irq_2_mmr_pnode, list);

		if (unlikely(irq == e->irq)) {
			/* irq entry exists */
			e->pnode = uv_blade_to_pnode(blade);
			e->offset = offset;
			spin_unlock_irqrestore(&uv_irq_lock, irqflags);
			kfree(n);
			return 0;
		}

		if (irq < e->irq)
			link = &(*link)->rb_left;
		else
			link = &(*link)->rb_right;
	}

	/* Insert the node into the rbtree. */
	rb_link_node(&n->list, parent, link);
	rb_insert_color(&n->list, &uv_irq_root);

	spin_unlock_irqrestore(&uv_irq_lock, irqflags);
	return 0;
}

/* Retrieve offset and pnode information from the rb tree for a specific irq */
int uv_irq_2_mmr_info(int irq, unsigned long *offset, int *pnode)
{
	struct uv_irq_2_mmr_pnode *e;
	struct rb_node *n;
	unsigned long irqflags;

	spin_lock_irqsave(&uv_irq_lock, irqflags);
	n = uv_irq_root.rb_node;
	while (n) {
		e = rb_entry(n, struct uv_irq_2_mmr_pnode, list);

		if (e->irq == irq) {
			*offset = e->offset;
			*pnode = e->pnode;
			spin_unlock_irqrestore(&uv_irq_lock, irqflags);
			return 0;
		}

		if (irq < e->irq)
			n = n->rb_left;
		else
			n = n->rb_right;
	}
	spin_unlock_irqrestore(&uv_irq_lock, irqflags);
	return -1;
}

/*
 * Re-target the irq to the specified CPU and enable the specified MMR located
 * on the specified blade to allow the sending of MSIs to the specified CPU.
 */
static int
arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
		       unsigned long mmr_offset, int restrict)
{
	const struct cpumask *eligible_cpu = cpumask_of(cpu);
	struct irq_desc *desc = irq_to_desc(irq);
	struct irq_cfg *cfg;
	int mmr_pnode;
	unsigned long mmr_value;
	struct uv_IO_APIC_route_entry *entry;
	int err;

	BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry) !=
			sizeof(unsigned long));

	cfg = irq_cfg(irq);

	err = assign_irq_vector(irq, cfg, eligible_cpu);
	if (err != 0)
		return err;

	if (restrict == UV_AFFINITY_CPU)
		desc->status |= IRQ_NO_BALANCING;
	else
		desc->status |= IRQ_MOVE_PCNTXT;

	set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq,
				      irq_name);

	mmr_value = 0;
	entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
	entry->vector		= cfg->vector;
	entry->delivery_mode	= apic->irq_delivery_mode;
	entry->dest_mode	= apic->irq_dest_mode;
	entry->polarity		= 0;
	entry->trigger		= 0;
	entry->mask		= 0;
	entry->dest		= apic->cpu_mask_to_apicid(eligible_cpu);

	mmr_pnode = uv_blade_to_pnode(mmr_blade);
	uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);

	if (cfg->move_in_progress)
		send_cleanup_vector(cfg);

	return irq;
}

/*
 * Disable the specified MMR located on the specified blade so that MSIs are
 * longer allowed to be sent.
 */
static void arch_disable_uv_irq(int mmr_pnode, unsigned long mmr_offset)
{
	unsigned long mmr_value;
	struct uv_IO_APIC_route_entry *entry;

	BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry) !=
			sizeof(unsigned long));

	mmr_value = 0;
	entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
	entry->mask = 1;

	uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
}

static int uv_set_irq_affinity(unsigned int irq, const struct cpumask *mask)
{
	struct irq_desc *desc = irq_to_desc(irq);
	struct irq_cfg *cfg = desc->chip_data;
	unsigned int dest;
	unsigned long mmr_value;
	struct uv_IO_APIC_route_entry *entry;
	unsigned long mmr_offset;
	unsigned mmr_pnode;

	dest = set_desc_affinity(desc, mask);
	if (dest == BAD_APICID)
		return -1;

	mmr_value = 0;
	entry = (struct uv_IO_APIC_route_entry *)&mmr_value;

	entry->vector		= cfg->vector;
	entry->delivery_mode	= apic->irq_delivery_mode;
	entry->dest_mode	= apic->irq_dest_mode;
	entry->polarity		= 0;
	entry->trigger		= 0;
	entry->mask		= 0;
	entry->dest		= dest;

	/* Get previously stored MMR and pnode of hub sourcing interrupts */
	if (uv_irq_2_mmr_info(irq, &mmr_offset, &mmr_pnode))
		return -1;

	uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);

	if (cfg->move_in_progress)
		send_cleanup_vector(cfg);

	return 0;
}

/*
 * Set up a mapping of an available irq and vector, and enable the specified
 * MMR that defines the MSI that is to be sent to the specified CPU when an
 * interrupt is raised.
 */
int uv_setup_irq(char *irq_name, int cpu, int mmr_blade,
		 unsigned long mmr_offset, int restrict)
{
	int irq, ret;

	irq = create_irq_nr(NR_IRQS_LEGACY, uv_blade_to_memory_nid(mmr_blade));

	if (irq <= 0)
		return -EBUSY;

	ret = arch_enable_uv_irq(irq_name, irq, cpu, mmr_blade, mmr_offset,
		restrict);
	if (ret == irq)
		uv_set_irq_2_mmr_info(irq, mmr_offset, mmr_blade);
	else
		destroy_irq(irq);

	return ret;
}
EXPORT_SYMBOL_GPL(uv_setup_irq);

/*
 * Tear down a mapping of an irq and vector, and disable the specified MMR that
 * defined the MSI that was to be sent to the specified CPU when an interrupt
 * was raised.
 *
 * Set mmr_blade and mmr_offset to what was passed in on uv_setup_irq().
 */
void uv_teardown_irq(unsigned int irq)
{
	struct uv_irq_2_mmr_pnode *e;
	struct rb_node *n;
	unsigned long irqflags;

	spin_lock_irqsave(&uv_irq_lock, irqflags);
	n = uv_irq_root.rb_node;
	while (n) {
		e = rb_entry(n, struct uv_irq_2_mmr_pnode, list);
		if (e->irq == irq) {
			arch_disable_uv_irq(e->pnode, e->offset);
			rb_erase(n, &uv_irq_root);
			kfree(e);
			break;
		}
		if (irq < e->irq)
			n = n->rb_left;
		else
			n = n->rb_right;
	}
	spin_unlock_irqrestore(&uv_irq_lock, irqflags);
	destroy_irq(irq);
}
EXPORT_SYMBOL_GPL(uv_teardown_irq);
Commit	Line	Data
4173a0e7 DN	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* SGI UV IRQ functions
	7	*
	8	* Copyright (C) 2008 Silicon Graphics, Inc. All rights reserved.
	9	*/
	10
	11	#include <linux/module.h>
6c2c5029	12	#include <linux/rbtree.h>
4173a0e7	13	#include <linux/irq.h>
37762b6f IM	14
37762b6f IM	15	#include <asm/apic.h>
4173a0e7	16	#include <asm/uv/uv_irq.h>
6c2c5029 DS	17	#include <asm/uv/uv_hub.h>
	18
	19	/* MMR offset and pnode of hub sourcing interrupts for a given irq */
	20	struct uv_irq_2_mmr_pnode{
9338ad6f DS	21	struct rb_node list;
	22	unsigned long offset;
	23	int pnode;
	24	int irq;
6c2c5029	25	};
9338ad6f DS	26
	27	static spinlock_t uv_irq_lock;
	28	static struct rb_root uv_irq_root;
	29
	30	static int uv_set_irq_affinity(unsigned int, const struct cpumask *);
4173a0e7 DN	31
	32	static void uv_noop(unsigned int irq)
	33	{
	34	}
	35
	36	static unsigned int uv_noop_ret(unsigned int irq)
	37	{
	38	return 0;
	39	}
	40
	41	static void uv_ack_apic(unsigned int irq)
	42	{
	43	ack_APIC_irq();
	44	}
	45
	46	struct irq_chip uv_irq_chip = {
	47	.name = "UV-CORE",
	48	.startup = uv_noop_ret,
	49	.shutdown = uv_noop,
	50	.enable = uv_noop,
	51	.disable = uv_noop,
	52	.ack = uv_noop,
	53	.mask = uv_noop,
	54	.unmask = uv_noop,
	55	.eoi = uv_ack_apic,
	56	.end = uv_noop,
6c2c5029	57	.set_affinity = uv_set_irq_affinity,
4173a0e7 DN	58	};
4173a0e7 DN	59
6c2c5029 DS	60	/*
	61	* Add offset and pnode information of the hub sourcing interrupts to the
	62	* rb tree for a specific irq.
	63	*/
	64	static int uv_set_irq_2_mmr_info(int irq, unsigned long offset, unsigned blade)
	65	{
	66	struct rb_node **link = &uv_irq_root.rb_node;
	67	struct rb_node *parent = NULL;
	68	struct uv_irq_2_mmr_pnode *n;
	69	struct uv_irq_2_mmr_pnode *e;
	70	unsigned long irqflags;
	71
	72	n = kmalloc_node(sizeof(struct uv_irq_2_mmr_pnode), GFP_KERNEL,
	73	uv_blade_to_memory_nid(blade));
	74	if (!n)
	75	return -ENOMEM;
	76
	77	n->irq = irq;
	78	n->offset = offset;
	79	n->pnode = uv_blade_to_pnode(blade);
	80	spin_lock_irqsave(&uv_irq_lock, irqflags);
	81	/* Find the right place in the rbtree: */
	82	while (*link) {
	83	parent = *link;
	84	e = rb_entry(parent, struct uv_irq_2_mmr_pnode, list);
	85
	86	if (unlikely(irq == e->irq)) {
	87	/* irq entry exists */
	88	e->pnode = uv_blade_to_pnode(blade);
	89	e->offset = offset;
	90	spin_unlock_irqrestore(&uv_irq_lock, irqflags);
	91	kfree(n);
	92	return 0;
	93	}
	94
	95	if (irq < e->irq)
	96	link = &(*link)->rb_left;
	97	else
	98	link = &(*link)->rb_right;
	99	}
	100
	101	/* Insert the node into the rbtree. */
	102	rb_link_node(&n->list, parent, link);
	103	rb_insert_color(&n->list, &uv_irq_root);
	104
	105	spin_unlock_irqrestore(&uv_irq_lock, irqflags);
	106	return 0;
	107	}
	108
	109	/* Retrieve offset and pnode information from the rb tree for a specific irq */
	110	int uv_irq_2_mmr_info(int irq, unsigned long offset, int pnode)
	111	{
	112	struct uv_irq_2_mmr_pnode *e;
	113	struct rb_node *n;
	114	unsigned long irqflags;
	115
	116	spin_lock_irqsave(&uv_irq_lock, irqflags);
	117	n = uv_irq_root.rb_node;
	118	while (n) {
	119	e = rb_entry(n, struct uv_irq_2_mmr_pnode, list);
	120
	121	if (e->irq == irq) {
	122	*offset = e->offset;
	123	*pnode = e->pnode;
124	spin_unlock_irqrestore(&uv_irq_lock, irqflags);
125	return 0;
126	}
127
128	if (irq < e->irq)
129	n = n->rb_left;
130	else
131	n = n->rb_right;
132	}
133	spin_unlock_irqrestore(&uv_irq_lock, irqflags);
134	return -1;
135	}
136
9338ad6f DS	137	/*
	138	* Re-target the irq to the specified CPU and enable the specified MMR located
	139	* on the specified blade to allow the sending of MSIs to the specified CPU.
	140	*/
	141	static int
	142	arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
	143	unsigned long mmr_offset, int restrict)
	144	{
	145	const struct cpumask *eligible_cpu = cpumask_of(cpu);
	146	struct irq_desc *desc = irq_to_desc(irq);
	147	struct irq_cfg *cfg;
	148	int mmr_pnode;
	149	unsigned long mmr_value;
	150	struct uv_IO_APIC_route_entry *entry;
	151	int err;
	152
	153	BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry) !=
	154	sizeof(unsigned long));
	155
	156	cfg = irq_cfg(irq);
	157
	158	err = assign_irq_vector(irq, cfg, eligible_cpu);
	159	if (err != 0)
	160	return err;
	161
	162	if (restrict == UV_AFFINITY_CPU)
	163	desc->status \|= IRQ_NO_BALANCING;
	164	else
	165	desc->status \|= IRQ_MOVE_PCNTXT;
	166
	167	set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq,
	168	irq_name);
	169
	170	mmr_value = 0;
	171	entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
	172	entry->vector = cfg->vector;
	173	entry->delivery_mode = apic->irq_delivery_mode;
	174	entry->dest_mode = apic->irq_dest_mode;
	175	entry->polarity = 0;
	176	entry->trigger = 0;
	177	entry->mask = 0;
	178	entry->dest = apic->cpu_mask_to_apicid(eligible_cpu);
	179
	180	mmr_pnode = uv_blade_to_pnode(mmr_blade);
	181	uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
	182
	183	if (cfg->move_in_progress)
	184	send_cleanup_vector(cfg);
	185
	186	return irq;
	187	}
	188
	189	/*
	190	* Disable the specified MMR located on the specified blade so that MSIs are
	191	* longer allowed to be sent.
	192	*/
	193	static void arch_disable_uv_irq(int mmr_pnode, unsigned long mmr_offset)
	194	{
	195	unsigned long mmr_value;
	196	struct uv_IO_APIC_route_entry *entry;
	197
	198	BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry) !=
	199	sizeof(unsigned long));
	200
201	mmr_value = 0;
202	entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
203	entry->mask = 1;
204
205	uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
206	}
207
208	static int uv_set_irq_affinity(unsigned int irq, const struct cpumask *mask)
209	{
210	struct irq_desc *desc = irq_to_desc(irq);
211	struct irq_cfg *cfg = desc->chip_data;
212	unsigned int dest;
213	unsigned long mmr_value;
214	struct uv_IO_APIC_route_entry *entry;
215	unsigned long mmr_offset;
216	unsigned mmr_pnode;
217
218	dest = set_desc_affinity(desc, mask);
219	if (dest == BAD_APICID)
220	return -1;
221
222	mmr_value = 0;
223	entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
224
225	entry->vector = cfg->vector;
226	entry->delivery_mode = apic->irq_delivery_mode;
227	entry->dest_mode = apic->irq_dest_mode;
228	entry->polarity = 0;
229	entry->trigger = 0;
230	entry->mask = 0;
231	entry->dest = dest;
232
233	/* Get previously stored MMR and pnode of hub sourcing interrupts */
234	if (uv_irq_2_mmr_info(irq, &mmr_offset, &mmr_pnode))
235	return -1;
236
237	uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
238
239	if (cfg->move_in_progress)
240	send_cleanup_vector(cfg);
241
242	return 0;
243	}
244
4173a0e7 DN	245	/*
	246	* Set up a mapping of an available irq and vector, and enable the specified
	247	* MMR that defines the MSI that is to be sent to the specified CPU when an
	248	* interrupt is raised.
	249	*/
	250	int uv_setup_irq(char *irq_name, int cpu, int mmr_blade,
6c2c5029	251	unsigned long mmr_offset, int restrict)
4173a0e7	252	{
6c2c5029 DS	253	int irq, ret;
	254
	255	irq = create_irq_nr(NR_IRQS_LEGACY, uv_blade_to_memory_nid(mmr_blade));
4173a0e7	256
4173a0e7 DN	257	if (irq <= 0)
	258	return -EBUSY;
	259
6c2c5029 DS	260	ret = arch_enable_uv_irq(irq_name, irq, cpu, mmr_blade, mmr_offset,
	261	restrict);
	262	if (ret == irq)
	263	uv_set_irq_2_mmr_info(irq, mmr_offset, mmr_blade);
	264	else
4173a0e7 DN	265	destroy_irq(irq);
	266
	267	return ret;
	268	}
	269	EXPORT_SYMBOL_GPL(uv_setup_irq);
	270
	271	/*
	272	* Tear down a mapping of an irq and vector, and disable the specified MMR that
	273	* defined the MSI that was to be sent to the specified CPU when an interrupt
	274	* was raised.
	275	*
	276	* Set mmr_blade and mmr_offset to what was passed in on uv_setup_irq().
	277	*/
6c2c5029	278	void uv_teardown_irq(unsigned int irq)
4173a0e7	279	{
6c2c5029 DS	280	struct uv_irq_2_mmr_pnode *e;
	281	struct rb_node *n;
	282	unsigned long irqflags;
	283
	284	spin_lock_irqsave(&uv_irq_lock, irqflags);
	285	n = uv_irq_root.rb_node;
	286	while (n) {
	287	e = rb_entry(n, struct uv_irq_2_mmr_pnode, list);
	288	if (e->irq == irq) {
	289	arch_disable_uv_irq(e->pnode, e->offset);
	290	rb_erase(n, &uv_irq_root);
	291	kfree(e);
	292	break;
	293	}
	294	if (irq < e->irq)
	295	n = n->rb_left;
	296	else
	297	n = n->rb_right;
	298	}
	299	spin_unlock_irqrestore(&uv_irq_lock, irqflags);
4173a0e7 DN	300	destroy_irq(irq);
	301	}
	302	EXPORT_SYMBOL_GPL(uv_teardown_irq);