Commit | Line | Data |
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bfc0f594 | 1 | #include <linux/kernel.h> |
0ef95533 AK |
2 | #include <linux/sched.h> |
3 | #include <linux/init.h> | |
4 | #include <linux/module.h> | |
5 | #include <linux/timer.h> | |
bfc0f594 | 6 | #include <linux/acpi_pmtmr.h> |
2dbe06fa | 7 | #include <linux/cpufreq.h> |
8fbbc4b4 AK |
8 | #include <linux/dmi.h> |
9 | #include <linux/delay.h> | |
10 | #include <linux/clocksource.h> | |
11 | #include <linux/percpu.h> | |
bfc0f594 AK |
12 | |
13 | #include <asm/hpet.h> | |
8fbbc4b4 AK |
14 | #include <asm/timer.h> |
15 | #include <asm/vgtod.h> | |
16 | #include <asm/time.h> | |
17 | #include <asm/delay.h> | |
88b094fb | 18 | #include <asm/hypervisor.h> |
0ef95533 | 19 | |
f24ade3a | 20 | unsigned int __read_mostly cpu_khz; /* TSC clocks / usec, not used here */ |
0ef95533 | 21 | EXPORT_SYMBOL(cpu_khz); |
f24ade3a IM |
22 | |
23 | unsigned int __read_mostly tsc_khz; | |
0ef95533 AK |
24 | EXPORT_SYMBOL(tsc_khz); |
25 | ||
26 | /* | |
27 | * TSC can be unstable due to cpufreq or due to unsynced TSCs | |
28 | */ | |
f24ade3a | 29 | static int __read_mostly tsc_unstable; |
0ef95533 AK |
30 | |
31 | /* native_sched_clock() is called before tsc_init(), so | |
32 | we must start with the TSC soft disabled to prevent | |
33 | erroneous rdtsc usage on !cpu_has_tsc processors */ | |
f24ade3a | 34 | static int __read_mostly tsc_disabled = -1; |
0ef95533 | 35 | |
395628ef | 36 | static int tsc_clocksource_reliable; |
0ef95533 AK |
37 | /* |
38 | * Scheduler clock - returns current time in nanosec units. | |
39 | */ | |
40 | u64 native_sched_clock(void) | |
41 | { | |
42 | u64 this_offset; | |
43 | ||
44 | /* | |
45 | * Fall back to jiffies if there's no TSC available: | |
46 | * ( But note that we still use it if the TSC is marked | |
47 | * unstable. We do this because unlike Time Of Day, | |
48 | * the scheduler clock tolerates small errors and it's | |
49 | * very important for it to be as fast as the platform | |
50 | * can achive it. ) | |
51 | */ | |
52 | if (unlikely(tsc_disabled)) { | |
53 | /* No locking but a rare wrong value is not a big deal: */ | |
54 | return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ); | |
55 | } | |
56 | ||
57 | /* read the Time Stamp Counter: */ | |
58 | rdtscll(this_offset); | |
59 | ||
60 | /* return the value in ns */ | |
7cbaef9c | 61 | return __cycles_2_ns(this_offset); |
0ef95533 AK |
62 | } |
63 | ||
64 | /* We need to define a real function for sched_clock, to override the | |
65 | weak default version */ | |
66 | #ifdef CONFIG_PARAVIRT | |
67 | unsigned long long sched_clock(void) | |
68 | { | |
69 | return paravirt_sched_clock(); | |
70 | } | |
71 | #else | |
72 | unsigned long long | |
73 | sched_clock(void) __attribute__((alias("native_sched_clock"))); | |
74 | #endif | |
75 | ||
76 | int check_tsc_unstable(void) | |
77 | { | |
78 | return tsc_unstable; | |
79 | } | |
80 | EXPORT_SYMBOL_GPL(check_tsc_unstable); | |
81 | ||
82 | #ifdef CONFIG_X86_TSC | |
83 | int __init notsc_setup(char *str) | |
84 | { | |
85 | printk(KERN_WARNING "notsc: Kernel compiled with CONFIG_X86_TSC, " | |
86 | "cannot disable TSC completely.\n"); | |
87 | tsc_disabled = 1; | |
88 | return 1; | |
89 | } | |
90 | #else | |
91 | /* | |
92 | * disable flag for tsc. Takes effect by clearing the TSC cpu flag | |
93 | * in cpu/common.c | |
94 | */ | |
95 | int __init notsc_setup(char *str) | |
96 | { | |
97 | setup_clear_cpu_cap(X86_FEATURE_TSC); | |
98 | return 1; | |
99 | } | |
100 | #endif | |
101 | ||
102 | __setup("notsc", notsc_setup); | |
bfc0f594 | 103 | |
395628ef AK |
104 | static int __init tsc_setup(char *str) |
105 | { | |
106 | if (!strcmp(str, "reliable")) | |
107 | tsc_clocksource_reliable = 1; | |
108 | return 1; | |
109 | } | |
110 | ||
111 | __setup("tsc=", tsc_setup); | |
112 | ||
bfc0f594 AK |
113 | #define MAX_RETRIES 5 |
114 | #define SMI_TRESHOLD 50000 | |
115 | ||
116 | /* | |
117 | * Read TSC and the reference counters. Take care of SMI disturbance | |
118 | */ | |
827014be | 119 | static u64 tsc_read_refs(u64 *p, int hpet) |
bfc0f594 AK |
120 | { |
121 | u64 t1, t2; | |
122 | int i; | |
123 | ||
124 | for (i = 0; i < MAX_RETRIES; i++) { | |
125 | t1 = get_cycles(); | |
126 | if (hpet) | |
827014be | 127 | *p = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF; |
bfc0f594 | 128 | else |
827014be | 129 | *p = acpi_pm_read_early(); |
bfc0f594 AK |
130 | t2 = get_cycles(); |
131 | if ((t2 - t1) < SMI_TRESHOLD) | |
132 | return t2; | |
133 | } | |
134 | return ULLONG_MAX; | |
135 | } | |
136 | ||
d683ef7a TG |
137 | /* |
138 | * Calculate the TSC frequency from HPET reference | |
bfc0f594 | 139 | */ |
d683ef7a | 140 | static unsigned long calc_hpet_ref(u64 deltatsc, u64 hpet1, u64 hpet2) |
bfc0f594 | 141 | { |
d683ef7a | 142 | u64 tmp; |
bfc0f594 | 143 | |
d683ef7a TG |
144 | if (hpet2 < hpet1) |
145 | hpet2 += 0x100000000ULL; | |
146 | hpet2 -= hpet1; | |
147 | tmp = ((u64)hpet2 * hpet_readl(HPET_PERIOD)); | |
148 | do_div(tmp, 1000000); | |
149 | do_div(deltatsc, tmp); | |
150 | ||
151 | return (unsigned long) deltatsc; | |
152 | } | |
153 | ||
154 | /* | |
155 | * Calculate the TSC frequency from PMTimer reference | |
156 | */ | |
157 | static unsigned long calc_pmtimer_ref(u64 deltatsc, u64 pm1, u64 pm2) | |
158 | { | |
159 | u64 tmp; | |
bfc0f594 | 160 | |
d683ef7a TG |
161 | if (!pm1 && !pm2) |
162 | return ULONG_MAX; | |
163 | ||
164 | if (pm2 < pm1) | |
165 | pm2 += (u64)ACPI_PM_OVRRUN; | |
166 | pm2 -= pm1; | |
167 | tmp = pm2 * 1000000000LL; | |
168 | do_div(tmp, PMTMR_TICKS_PER_SEC); | |
169 | do_div(deltatsc, tmp); | |
170 | ||
171 | return (unsigned long) deltatsc; | |
172 | } | |
173 | ||
a977c400 | 174 | #define CAL_MS 10 |
cce3e057 | 175 | #define CAL_LATCH (CLOCK_TICK_RATE / (1000 / CAL_MS)) |
a977c400 TG |
176 | #define CAL_PIT_LOOPS 1000 |
177 | ||
178 | #define CAL2_MS 50 | |
179 | #define CAL2_LATCH (CLOCK_TICK_RATE / (1000 / CAL2_MS)) | |
180 | #define CAL2_PIT_LOOPS 5000 | |
181 | ||
cce3e057 | 182 | |
ec0c15af LT |
183 | /* |
184 | * Try to calibrate the TSC against the Programmable | |
185 | * Interrupt Timer and return the frequency of the TSC | |
186 | * in kHz. | |
187 | * | |
188 | * Return ULONG_MAX on failure to calibrate. | |
189 | */ | |
a977c400 | 190 | static unsigned long pit_calibrate_tsc(u32 latch, unsigned long ms, int loopmin) |
ec0c15af LT |
191 | { |
192 | u64 tsc, t1, t2, delta; | |
193 | unsigned long tscmin, tscmax; | |
194 | int pitcnt; | |
195 | ||
196 | /* Set the Gate high, disable speaker */ | |
197 | outb((inb(0x61) & ~0x02) | 0x01, 0x61); | |
198 | ||
199 | /* | |
200 | * Setup CTC channel 2* for mode 0, (interrupt on terminal | |
201 | * count mode), binary count. Set the latch register to 50ms | |
202 | * (LSB then MSB) to begin countdown. | |
203 | */ | |
204 | outb(0xb0, 0x43); | |
a977c400 TG |
205 | outb(latch & 0xff, 0x42); |
206 | outb(latch >> 8, 0x42); | |
ec0c15af LT |
207 | |
208 | tsc = t1 = t2 = get_cycles(); | |
209 | ||
210 | pitcnt = 0; | |
211 | tscmax = 0; | |
212 | tscmin = ULONG_MAX; | |
213 | while ((inb(0x61) & 0x20) == 0) { | |
214 | t2 = get_cycles(); | |
215 | delta = t2 - tsc; | |
216 | tsc = t2; | |
217 | if ((unsigned long) delta < tscmin) | |
218 | tscmin = (unsigned int) delta; | |
219 | if ((unsigned long) delta > tscmax) | |
220 | tscmax = (unsigned int) delta; | |
221 | pitcnt++; | |
222 | } | |
223 | ||
224 | /* | |
225 | * Sanity checks: | |
226 | * | |
a977c400 | 227 | * If we were not able to read the PIT more than loopmin |
ec0c15af LT |
228 | * times, then we have been hit by a massive SMI |
229 | * | |
230 | * If the maximum is 10 times larger than the minimum, | |
231 | * then we got hit by an SMI as well. | |
232 | */ | |
a977c400 | 233 | if (pitcnt < loopmin || tscmax > 10 * tscmin) |
ec0c15af LT |
234 | return ULONG_MAX; |
235 | ||
236 | /* Calculate the PIT value */ | |
237 | delta = t2 - t1; | |
a977c400 | 238 | do_div(delta, ms); |
ec0c15af LT |
239 | return delta; |
240 | } | |
241 | ||
6ac40ed0 LT |
242 | /* |
243 | * This reads the current MSB of the PIT counter, and | |
244 | * checks if we are running on sufficiently fast and | |
245 | * non-virtualized hardware. | |
246 | * | |
247 | * Our expectations are: | |
248 | * | |
249 | * - the PIT is running at roughly 1.19MHz | |
250 | * | |
251 | * - each IO is going to take about 1us on real hardware, | |
252 | * but we allow it to be much faster (by a factor of 10) or | |
253 | * _slightly_ slower (ie we allow up to a 2us read+counter | |
254 | * update - anything else implies a unacceptably slow CPU | |
255 | * or PIT for the fast calibration to work. | |
256 | * | |
257 | * - with 256 PIT ticks to read the value, we have 214us to | |
258 | * see the same MSB (and overhead like doing a single TSC | |
259 | * read per MSB value etc). | |
260 | * | |
261 | * - We're doing 2 reads per loop (LSB, MSB), and we expect | |
262 | * them each to take about a microsecond on real hardware. | |
263 | * So we expect a count value of around 100. But we'll be | |
264 | * generous, and accept anything over 50. | |
265 | * | |
266 | * - if the PIT is stuck, and we see *many* more reads, we | |
267 | * return early (and the next caller of pit_expect_msb() | |
268 | * then consider it a failure when they don't see the | |
269 | * next expected value). | |
270 | * | |
271 | * These expectations mean that we know that we have seen the | |
272 | * transition from one expected value to another with a fairly | |
273 | * high accuracy, and we didn't miss any events. We can thus | |
274 | * use the TSC value at the transitions to calculate a pretty | |
275 | * good value for the TSC frequencty. | |
276 | */ | |
9e8912e0 | 277 | static inline int pit_expect_msb(unsigned char val, u64 *tscp, unsigned long *deltap) |
6ac40ed0 | 278 | { |
9e8912e0 LT |
279 | int count; |
280 | u64 tsc = 0; | |
bfc0f594 | 281 | |
6ac40ed0 LT |
282 | for (count = 0; count < 50000; count++) { |
283 | /* Ignore LSB */ | |
284 | inb(0x42); | |
285 | if (inb(0x42) != val) | |
286 | break; | |
9e8912e0 | 287 | tsc = get_cycles(); |
6ac40ed0 | 288 | } |
9e8912e0 LT |
289 | *deltap = get_cycles() - tsc; |
290 | *tscp = tsc; | |
291 | ||
292 | /* | |
293 | * We require _some_ success, but the quality control | |
294 | * will be based on the error terms on the TSC values. | |
295 | */ | |
296 | return count > 5; | |
6ac40ed0 LT |
297 | } |
298 | ||
299 | /* | |
9e8912e0 LT |
300 | * How many MSB values do we want to see? We aim for |
301 | * a maximum error rate of 500ppm (in practice the | |
302 | * real error is much smaller), but refuse to spend | |
303 | * more than 25ms on it. | |
6ac40ed0 | 304 | */ |
9e8912e0 LT |
305 | #define MAX_QUICK_PIT_MS 25 |
306 | #define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256) | |
bfc0f594 | 307 | |
6ac40ed0 LT |
308 | static unsigned long quick_pit_calibrate(void) |
309 | { | |
9e8912e0 LT |
310 | int i; |
311 | u64 tsc, delta; | |
312 | unsigned long d1, d2; | |
313 | ||
6ac40ed0 | 314 | /* Set the Gate high, disable speaker */ |
bfc0f594 AK |
315 | outb((inb(0x61) & ~0x02) | 0x01, 0x61); |
316 | ||
6ac40ed0 LT |
317 | /* |
318 | * Counter 2, mode 0 (one-shot), binary count | |
319 | * | |
320 | * NOTE! Mode 2 decrements by two (and then the | |
321 | * output is flipped each time, giving the same | |
322 | * final output frequency as a decrement-by-one), | |
323 | * so mode 0 is much better when looking at the | |
324 | * individual counts. | |
325 | */ | |
bfc0f594 | 326 | outb(0xb0, 0x43); |
bfc0f594 | 327 | |
6ac40ed0 LT |
328 | /* Start at 0xffff */ |
329 | outb(0xff, 0x42); | |
330 | outb(0xff, 0x42); | |
331 | ||
a6a80e1d LT |
332 | /* |
333 | * The PIT starts counting at the next edge, so we | |
334 | * need to delay for a microsecond. The easiest way | |
335 | * to do that is to just read back the 16-bit counter | |
336 | * once from the PIT. | |
337 | */ | |
338 | inb(0x42); | |
339 | inb(0x42); | |
340 | ||
9e8912e0 LT |
341 | if (pit_expect_msb(0xff, &tsc, &d1)) { |
342 | for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) { | |
343 | if (!pit_expect_msb(0xff-i, &delta, &d2)) | |
344 | break; | |
345 | ||
346 | /* | |
347 | * Iterate until the error is less than 500 ppm | |
348 | */ | |
349 | delta -= tsc; | |
350 | if (d1+d2 < delta >> 11) | |
351 | goto success; | |
6ac40ed0 | 352 | } |
6ac40ed0 | 353 | } |
9e8912e0 | 354 | printk("Fast TSC calibration failed\n"); |
6ac40ed0 | 355 | return 0; |
9e8912e0 LT |
356 | |
357 | success: | |
358 | /* | |
359 | * Ok, if we get here, then we've seen the | |
360 | * MSB of the PIT decrement 'i' times, and the | |
361 | * error has shrunk to less than 500 ppm. | |
362 | * | |
363 | * As a result, we can depend on there not being | |
364 | * any odd delays anywhere, and the TSC reads are | |
365 | * reliable (within the error). We also adjust the | |
366 | * delta to the middle of the error bars, just | |
367 | * because it looks nicer. | |
368 | * | |
369 | * kHz = ticks / time-in-seconds / 1000; | |
370 | * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000 | |
371 | * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000) | |
372 | */ | |
373 | delta += (long)(d2 - d1)/2; | |
374 | delta *= PIT_TICK_RATE; | |
375 | do_div(delta, i*256*1000); | |
376 | printk("Fast TSC calibration using PIT\n"); | |
377 | return delta; | |
6ac40ed0 | 378 | } |
ec0c15af | 379 | |
bfc0f594 | 380 | /** |
e93ef949 | 381 | * native_calibrate_tsc - calibrate the tsc on boot |
bfc0f594 | 382 | */ |
e93ef949 | 383 | unsigned long native_calibrate_tsc(void) |
bfc0f594 | 384 | { |
827014be | 385 | u64 tsc1, tsc2, delta, ref1, ref2; |
fbb16e24 | 386 | unsigned long tsc_pit_min = ULONG_MAX, tsc_ref_min = ULONG_MAX; |
2c1b284e | 387 | unsigned long flags, latch, ms, fast_calibrate, hv_tsc_khz; |
a977c400 | 388 | int hpet = is_hpet_enabled(), i, loopmin; |
bfc0f594 | 389 | |
2c1b284e JSR |
390 | hv_tsc_khz = get_hypervisor_tsc_freq(); |
391 | if (hv_tsc_khz) { | |
88b094fb | 392 | printk(KERN_INFO "TSC: Frequency read from the hypervisor\n"); |
2c1b284e | 393 | return hv_tsc_khz; |
88b094fb AK |
394 | } |
395 | ||
6ac40ed0 LT |
396 | local_irq_save(flags); |
397 | fast_calibrate = quick_pit_calibrate(); | |
bfc0f594 | 398 | local_irq_restore(flags); |
6ac40ed0 LT |
399 | if (fast_calibrate) |
400 | return fast_calibrate; | |
bfc0f594 | 401 | |
fbb16e24 TG |
402 | /* |
403 | * Run 5 calibration loops to get the lowest frequency value | |
404 | * (the best estimate). We use two different calibration modes | |
405 | * here: | |
406 | * | |
407 | * 1) PIT loop. We set the PIT Channel 2 to oneshot mode and | |
408 | * load a timeout of 50ms. We read the time right after we | |
409 | * started the timer and wait until the PIT count down reaches | |
410 | * zero. In each wait loop iteration we read the TSC and check | |
411 | * the delta to the previous read. We keep track of the min | |
412 | * and max values of that delta. The delta is mostly defined | |
413 | * by the IO time of the PIT access, so we can detect when a | |
414 | * SMI/SMM disturbance happend between the two reads. If the | |
415 | * maximum time is significantly larger than the minimum time, | |
416 | * then we discard the result and have another try. | |
417 | * | |
418 | * 2) Reference counter. If available we use the HPET or the | |
419 | * PMTIMER as a reference to check the sanity of that value. | |
420 | * We use separate TSC readouts and check inside of the | |
421 | * reference read for a SMI/SMM disturbance. We dicard | |
422 | * disturbed values here as well. We do that around the PIT | |
423 | * calibration delay loop as we have to wait for a certain | |
424 | * amount of time anyway. | |
425 | */ | |
a977c400 TG |
426 | |
427 | /* Preset PIT loop values */ | |
428 | latch = CAL_LATCH; | |
429 | ms = CAL_MS; | |
430 | loopmin = CAL_PIT_LOOPS; | |
431 | ||
432 | for (i = 0; i < 3; i++) { | |
ec0c15af | 433 | unsigned long tsc_pit_khz; |
fbb16e24 TG |
434 | |
435 | /* | |
436 | * Read the start value and the reference count of | |
ec0c15af LT |
437 | * hpet/pmtimer when available. Then do the PIT |
438 | * calibration, which will take at least 50ms, and | |
439 | * read the end value. | |
fbb16e24 | 440 | */ |
ec0c15af | 441 | local_irq_save(flags); |
827014be | 442 | tsc1 = tsc_read_refs(&ref1, hpet); |
a977c400 | 443 | tsc_pit_khz = pit_calibrate_tsc(latch, ms, loopmin); |
827014be | 444 | tsc2 = tsc_read_refs(&ref2, hpet); |
fbb16e24 TG |
445 | local_irq_restore(flags); |
446 | ||
ec0c15af LT |
447 | /* Pick the lowest PIT TSC calibration so far */ |
448 | tsc_pit_min = min(tsc_pit_min, tsc_pit_khz); | |
fbb16e24 TG |
449 | |
450 | /* hpet or pmtimer available ? */ | |
827014be | 451 | if (!hpet && !ref1 && !ref2) |
fbb16e24 TG |
452 | continue; |
453 | ||
454 | /* Check, whether the sampling was disturbed by an SMI */ | |
455 | if (tsc1 == ULLONG_MAX || tsc2 == ULLONG_MAX) | |
456 | continue; | |
457 | ||
458 | tsc2 = (tsc2 - tsc1) * 1000000LL; | |
d683ef7a | 459 | if (hpet) |
827014be | 460 | tsc2 = calc_hpet_ref(tsc2, ref1, ref2); |
d683ef7a | 461 | else |
827014be | 462 | tsc2 = calc_pmtimer_ref(tsc2, ref1, ref2); |
fbb16e24 | 463 | |
fbb16e24 | 464 | tsc_ref_min = min(tsc_ref_min, (unsigned long) tsc2); |
a977c400 TG |
465 | |
466 | /* Check the reference deviation */ | |
467 | delta = ((u64) tsc_pit_min) * 100; | |
468 | do_div(delta, tsc_ref_min); | |
469 | ||
470 | /* | |
471 | * If both calibration results are inside a 10% window | |
472 | * then we can be sure, that the calibration | |
473 | * succeeded. We break out of the loop right away. We | |
474 | * use the reference value, as it is more precise. | |
475 | */ | |
476 | if (delta >= 90 && delta <= 110) { | |
477 | printk(KERN_INFO | |
478 | "TSC: PIT calibration matches %s. %d loops\n", | |
479 | hpet ? "HPET" : "PMTIMER", i + 1); | |
480 | return tsc_ref_min; | |
fbb16e24 TG |
481 | } |
482 | ||
a977c400 TG |
483 | /* |
484 | * Check whether PIT failed more than once. This | |
485 | * happens in virtualized environments. We need to | |
486 | * give the virtual PC a slightly longer timeframe for | |
487 | * the HPET/PMTIMER to make the result precise. | |
488 | */ | |
489 | if (i == 1 && tsc_pit_min == ULONG_MAX) { | |
490 | latch = CAL2_LATCH; | |
491 | ms = CAL2_MS; | |
492 | loopmin = CAL2_PIT_LOOPS; | |
493 | } | |
fbb16e24 | 494 | } |
bfc0f594 AK |
495 | |
496 | /* | |
fbb16e24 | 497 | * Now check the results. |
bfc0f594 | 498 | */ |
fbb16e24 TG |
499 | if (tsc_pit_min == ULONG_MAX) { |
500 | /* PIT gave no useful value */ | |
de014d61 | 501 | printk(KERN_WARNING "TSC: Unable to calibrate against PIT\n"); |
fbb16e24 TG |
502 | |
503 | /* We don't have an alternative source, disable TSC */ | |
827014be | 504 | if (!hpet && !ref1 && !ref2) { |
fbb16e24 TG |
505 | printk("TSC: No reference (HPET/PMTIMER) available\n"); |
506 | return 0; | |
507 | } | |
508 | ||
509 | /* The alternative source failed as well, disable TSC */ | |
510 | if (tsc_ref_min == ULONG_MAX) { | |
511 | printk(KERN_WARNING "TSC: HPET/PMTIMER calibration " | |
a977c400 | 512 | "failed.\n"); |
fbb16e24 TG |
513 | return 0; |
514 | } | |
515 | ||
516 | /* Use the alternative source */ | |
517 | printk(KERN_INFO "TSC: using %s reference calibration\n", | |
518 | hpet ? "HPET" : "PMTIMER"); | |
519 | ||
520 | return tsc_ref_min; | |
521 | } | |
bfc0f594 | 522 | |
fbb16e24 | 523 | /* We don't have an alternative source, use the PIT calibration value */ |
827014be | 524 | if (!hpet && !ref1 && !ref2) { |
fbb16e24 TG |
525 | printk(KERN_INFO "TSC: Using PIT calibration value\n"); |
526 | return tsc_pit_min; | |
bfc0f594 AK |
527 | } |
528 | ||
fbb16e24 TG |
529 | /* The alternative source failed, use the PIT calibration value */ |
530 | if (tsc_ref_min == ULONG_MAX) { | |
a977c400 TG |
531 | printk(KERN_WARNING "TSC: HPET/PMTIMER calibration failed. " |
532 | "Using PIT calibration\n"); | |
fbb16e24 | 533 | return tsc_pit_min; |
bfc0f594 AK |
534 | } |
535 | ||
fbb16e24 TG |
536 | /* |
537 | * The calibration values differ too much. In doubt, we use | |
538 | * the PIT value as we know that there are PMTIMERs around | |
a977c400 | 539 | * running at double speed. At least we let the user know: |
fbb16e24 | 540 | */ |
a977c400 TG |
541 | printk(KERN_WARNING "TSC: PIT calibration deviates from %s: %lu %lu.\n", |
542 | hpet ? "HPET" : "PMTIMER", tsc_pit_min, tsc_ref_min); | |
fbb16e24 TG |
543 | printk(KERN_INFO "TSC: Using PIT calibration value\n"); |
544 | return tsc_pit_min; | |
bfc0f594 AK |
545 | } |
546 | ||
bfc0f594 AK |
547 | int recalibrate_cpu_khz(void) |
548 | { | |
549 | #ifndef CONFIG_SMP | |
550 | unsigned long cpu_khz_old = cpu_khz; | |
551 | ||
552 | if (cpu_has_tsc) { | |
e93ef949 AK |
553 | tsc_khz = calibrate_tsc(); |
554 | cpu_khz = tsc_khz; | |
bfc0f594 AK |
555 | cpu_data(0).loops_per_jiffy = |
556 | cpufreq_scale(cpu_data(0).loops_per_jiffy, | |
557 | cpu_khz_old, cpu_khz); | |
558 | return 0; | |
559 | } else | |
560 | return -ENODEV; | |
561 | #else | |
562 | return -ENODEV; | |
563 | #endif | |
564 | } | |
565 | ||
566 | EXPORT_SYMBOL(recalibrate_cpu_khz); | |
567 | ||
2dbe06fa AK |
568 | |
569 | /* Accelerators for sched_clock() | |
570 | * convert from cycles(64bits) => nanoseconds (64bits) | |
571 | * basic equation: | |
572 | * ns = cycles / (freq / ns_per_sec) | |
573 | * ns = cycles * (ns_per_sec / freq) | |
574 | * ns = cycles * (10^9 / (cpu_khz * 10^3)) | |
575 | * ns = cycles * (10^6 / cpu_khz) | |
576 | * | |
577 | * Then we use scaling math (suggested by george@mvista.com) to get: | |
578 | * ns = cycles * (10^6 * SC / cpu_khz) / SC | |
579 | * ns = cycles * cyc2ns_scale / SC | |
580 | * | |
581 | * And since SC is a constant power of two, we can convert the div | |
582 | * into a shift. | |
583 | * | |
584 | * We can use khz divisor instead of mhz to keep a better precision, since | |
585 | * cyc2ns_scale is limited to 10^6 * 2^10, which fits in 32 bits. | |
586 | * (mathieu.desnoyers@polymtl.ca) | |
587 | * | |
588 | * -johnstul@us.ibm.com "math is hard, lets go shopping!" | |
589 | */ | |
590 | ||
591 | DEFINE_PER_CPU(unsigned long, cyc2ns); | |
592 | ||
8fbbc4b4 | 593 | static void set_cyc2ns_scale(unsigned long cpu_khz, int cpu) |
2dbe06fa AK |
594 | { |
595 | unsigned long long tsc_now, ns_now; | |
596 | unsigned long flags, *scale; | |
597 | ||
598 | local_irq_save(flags); | |
599 | sched_clock_idle_sleep_event(); | |
600 | ||
601 | scale = &per_cpu(cyc2ns, cpu); | |
602 | ||
603 | rdtscll(tsc_now); | |
604 | ns_now = __cycles_2_ns(tsc_now); | |
605 | ||
606 | if (cpu_khz) | |
607 | *scale = (NSEC_PER_MSEC << CYC2NS_SCALE_FACTOR)/cpu_khz; | |
608 | ||
609 | sched_clock_idle_wakeup_event(0); | |
610 | local_irq_restore(flags); | |
611 | } | |
612 | ||
613 | #ifdef CONFIG_CPU_FREQ | |
614 | ||
615 | /* Frequency scaling support. Adjust the TSC based timer when the cpu frequency | |
616 | * changes. | |
617 | * | |
618 | * RED-PEN: On SMP we assume all CPUs run with the same frequency. It's | |
619 | * not that important because current Opteron setups do not support | |
620 | * scaling on SMP anyroads. | |
621 | * | |
622 | * Should fix up last_tsc too. Currently gettimeofday in the | |
623 | * first tick after the change will be slightly wrong. | |
624 | */ | |
625 | ||
626 | static unsigned int ref_freq; | |
627 | static unsigned long loops_per_jiffy_ref; | |
628 | static unsigned long tsc_khz_ref; | |
629 | ||
630 | static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val, | |
631 | void *data) | |
632 | { | |
633 | struct cpufreq_freqs *freq = data; | |
634 | unsigned long *lpj, dummy; | |
635 | ||
636 | if (cpu_has(&cpu_data(freq->cpu), X86_FEATURE_CONSTANT_TSC)) | |
637 | return 0; | |
638 | ||
639 | lpj = &dummy; | |
640 | if (!(freq->flags & CPUFREQ_CONST_LOOPS)) | |
641 | #ifdef CONFIG_SMP | |
642 | lpj = &cpu_data(freq->cpu).loops_per_jiffy; | |
643 | #else | |
644 | lpj = &boot_cpu_data.loops_per_jiffy; | |
645 | #endif | |
646 | ||
647 | if (!ref_freq) { | |
648 | ref_freq = freq->old; | |
649 | loops_per_jiffy_ref = *lpj; | |
650 | tsc_khz_ref = tsc_khz; | |
651 | } | |
652 | if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) || | |
653 | (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) || | |
654 | (val == CPUFREQ_RESUMECHANGE)) { | |
655 | *lpj = cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new); | |
656 | ||
657 | tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new); | |
658 | if (!(freq->flags & CPUFREQ_CONST_LOOPS)) | |
659 | mark_tsc_unstable("cpufreq changes"); | |
660 | } | |
661 | ||
52a8968c | 662 | set_cyc2ns_scale(tsc_khz, freq->cpu); |
2dbe06fa AK |
663 | |
664 | return 0; | |
665 | } | |
666 | ||
667 | static struct notifier_block time_cpufreq_notifier_block = { | |
668 | .notifier_call = time_cpufreq_notifier | |
669 | }; | |
670 | ||
671 | static int __init cpufreq_tsc(void) | |
672 | { | |
060700b5 LT |
673 | if (!cpu_has_tsc) |
674 | return 0; | |
675 | if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) | |
676 | return 0; | |
2dbe06fa AK |
677 | cpufreq_register_notifier(&time_cpufreq_notifier_block, |
678 | CPUFREQ_TRANSITION_NOTIFIER); | |
679 | return 0; | |
680 | } | |
681 | ||
682 | core_initcall(cpufreq_tsc); | |
683 | ||
684 | #endif /* CONFIG_CPU_FREQ */ | |
8fbbc4b4 AK |
685 | |
686 | /* clocksource code */ | |
687 | ||
688 | static struct clocksource clocksource_tsc; | |
689 | ||
690 | /* | |
691 | * We compare the TSC to the cycle_last value in the clocksource | |
692 | * structure to avoid a nasty time-warp. This can be observed in a | |
693 | * very small window right after one CPU updated cycle_last under | |
694 | * xtime/vsyscall_gtod lock and the other CPU reads a TSC value which | |
695 | * is smaller than the cycle_last reference value due to a TSC which | |
696 | * is slighty behind. This delta is nowhere else observable, but in | |
697 | * that case it results in a forward time jump in the range of hours | |
698 | * due to the unsigned delta calculation of the time keeping core | |
699 | * code, which is necessary to support wrapping clocksources like pm | |
700 | * timer. | |
701 | */ | |
702 | static cycle_t read_tsc(void) | |
703 | { | |
704 | cycle_t ret = (cycle_t)get_cycles(); | |
705 | ||
706 | return ret >= clocksource_tsc.cycle_last ? | |
707 | ret : clocksource_tsc.cycle_last; | |
708 | } | |
709 | ||
431ceb83 | 710 | #ifdef CONFIG_X86_64 |
8fbbc4b4 AK |
711 | static cycle_t __vsyscall_fn vread_tsc(void) |
712 | { | |
713 | cycle_t ret = (cycle_t)vget_cycles(); | |
714 | ||
715 | return ret >= __vsyscall_gtod_data.clock.cycle_last ? | |
716 | ret : __vsyscall_gtod_data.clock.cycle_last; | |
717 | } | |
431ceb83 | 718 | #endif |
8fbbc4b4 AK |
719 | |
720 | static struct clocksource clocksource_tsc = { | |
721 | .name = "tsc", | |
722 | .rating = 300, | |
723 | .read = read_tsc, | |
724 | .mask = CLOCKSOURCE_MASK(64), | |
725 | .shift = 22, | |
726 | .flags = CLOCK_SOURCE_IS_CONTINUOUS | | |
727 | CLOCK_SOURCE_MUST_VERIFY, | |
728 | #ifdef CONFIG_X86_64 | |
729 | .vread = vread_tsc, | |
730 | #endif | |
731 | }; | |
732 | ||
733 | void mark_tsc_unstable(char *reason) | |
734 | { | |
735 | if (!tsc_unstable) { | |
736 | tsc_unstable = 1; | |
737 | printk("Marking TSC unstable due to %s\n", reason); | |
738 | /* Change only the rating, when not registered */ | |
739 | if (clocksource_tsc.mult) | |
740 | clocksource_change_rating(&clocksource_tsc, 0); | |
741 | else | |
742 | clocksource_tsc.rating = 0; | |
743 | } | |
744 | } | |
745 | ||
746 | EXPORT_SYMBOL_GPL(mark_tsc_unstable); | |
747 | ||
748 | static int __init dmi_mark_tsc_unstable(const struct dmi_system_id *d) | |
749 | { | |
750 | printk(KERN_NOTICE "%s detected: marking TSC unstable.\n", | |
751 | d->ident); | |
752 | tsc_unstable = 1; | |
753 | return 0; | |
754 | } | |
755 | ||
756 | /* List of systems that have known TSC problems */ | |
757 | static struct dmi_system_id __initdata bad_tsc_dmi_table[] = { | |
758 | { | |
759 | .callback = dmi_mark_tsc_unstable, | |
760 | .ident = "IBM Thinkpad 380XD", | |
761 | .matches = { | |
762 | DMI_MATCH(DMI_BOARD_VENDOR, "IBM"), | |
763 | DMI_MATCH(DMI_BOARD_NAME, "2635FA0"), | |
764 | }, | |
765 | }, | |
766 | {} | |
767 | }; | |
768 | ||
395628ef AK |
769 | static void __init check_system_tsc_reliable(void) |
770 | { | |
8fbbc4b4 | 771 | #ifdef CONFIG_MGEODE_LX |
395628ef | 772 | /* RTSC counts during suspend */ |
8fbbc4b4 | 773 | #define RTSC_SUSP 0x100 |
8fbbc4b4 AK |
774 | unsigned long res_low, res_high; |
775 | ||
776 | rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high); | |
395628ef | 777 | /* Geode_LX - the OLPC CPU has a possibly a very reliable TSC */ |
8fbbc4b4 | 778 | if (res_low & RTSC_SUSP) |
395628ef | 779 | tsc_clocksource_reliable = 1; |
8fbbc4b4 | 780 | #endif |
395628ef AK |
781 | if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE)) |
782 | tsc_clocksource_reliable = 1; | |
783 | } | |
8fbbc4b4 AK |
784 | |
785 | /* | |
786 | * Make an educated guess if the TSC is trustworthy and synchronized | |
787 | * over all CPUs. | |
788 | */ | |
789 | __cpuinit int unsynchronized_tsc(void) | |
790 | { | |
791 | if (!cpu_has_tsc || tsc_unstable) | |
792 | return 1; | |
793 | ||
3e5095d1 | 794 | #ifdef CONFIG_SMP |
8fbbc4b4 AK |
795 | if (apic_is_clustered_box()) |
796 | return 1; | |
797 | #endif | |
798 | ||
799 | if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) | |
800 | return 0; | |
801 | /* | |
802 | * Intel systems are normally all synchronized. | |
803 | * Exceptions must mark TSC as unstable: | |
804 | */ | |
805 | if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) { | |
806 | /* assume multi socket systems are not synchronized: */ | |
807 | if (num_possible_cpus() > 1) | |
808 | tsc_unstable = 1; | |
809 | } | |
810 | ||
811 | return tsc_unstable; | |
812 | } | |
813 | ||
814 | static void __init init_tsc_clocksource(void) | |
815 | { | |
816 | clocksource_tsc.mult = clocksource_khz2mult(tsc_khz, | |
817 | clocksource_tsc.shift); | |
395628ef AK |
818 | if (tsc_clocksource_reliable) |
819 | clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY; | |
8fbbc4b4 AK |
820 | /* lower the rating if we already know its unstable: */ |
821 | if (check_tsc_unstable()) { | |
822 | clocksource_tsc.rating = 0; | |
823 | clocksource_tsc.flags &= ~CLOCK_SOURCE_IS_CONTINUOUS; | |
824 | } | |
825 | clocksource_register(&clocksource_tsc); | |
826 | } | |
827 | ||
828 | void __init tsc_init(void) | |
829 | { | |
830 | u64 lpj; | |
831 | int cpu; | |
832 | ||
833 | if (!cpu_has_tsc) | |
834 | return; | |
835 | ||
e93ef949 AK |
836 | tsc_khz = calibrate_tsc(); |
837 | cpu_khz = tsc_khz; | |
8fbbc4b4 | 838 | |
e93ef949 | 839 | if (!tsc_khz) { |
8fbbc4b4 AK |
840 | mark_tsc_unstable("could not calculate TSC khz"); |
841 | return; | |
842 | } | |
843 | ||
844 | #ifdef CONFIG_X86_64 | |
845 | if (cpu_has(&boot_cpu_data, X86_FEATURE_CONSTANT_TSC) && | |
846 | (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)) | |
847 | cpu_khz = calibrate_cpu(); | |
848 | #endif | |
849 | ||
8fbbc4b4 AK |
850 | printk("Detected %lu.%03lu MHz processor.\n", |
851 | (unsigned long)cpu_khz / 1000, | |
852 | (unsigned long)cpu_khz % 1000); | |
853 | ||
854 | /* | |
855 | * Secondary CPUs do not run through tsc_init(), so set up | |
856 | * all the scale factors for all CPUs, assuming the same | |
857 | * speed as the bootup CPU. (cpufreq notifiers will fix this | |
858 | * up if their speed diverges) | |
859 | */ | |
860 | for_each_possible_cpu(cpu) | |
861 | set_cyc2ns_scale(cpu_khz, cpu); | |
862 | ||
863 | if (tsc_disabled > 0) | |
864 | return; | |
865 | ||
866 | /* now allow native_sched_clock() to use rdtsc */ | |
867 | tsc_disabled = 0; | |
868 | ||
70de9a97 AK |
869 | lpj = ((u64)tsc_khz * 1000); |
870 | do_div(lpj, HZ); | |
871 | lpj_fine = lpj; | |
872 | ||
8fbbc4b4 AK |
873 | use_tsc_delay(); |
874 | /* Check and install the TSC clocksource */ | |
875 | dmi_check_system(bad_tsc_dmi_table); | |
876 | ||
877 | if (unsynchronized_tsc()) | |
878 | mark_tsc_unstable("TSCs unsynchronized"); | |
879 | ||
395628ef | 880 | check_system_tsc_reliable(); |
8fbbc4b4 AK |
881 | init_tsc_clocksource(); |
882 | } | |
883 |