Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 | 2 | * Copyright (C) 1991, 1992 Linus Torvalds |
a8c1be9d | 3 | * Copyright (C) 2000, 2001, 2002 Andi Kleen, SuSE Labs |
1da177e4 LT |
4 | * |
5 | * Pentium III FXSR, SSE support | |
6 | * Gareth Hughes <gareth@valinux.com>, May 2000 | |
7 | */ | |
8 | ||
9 | /* | |
c1d518c8 | 10 | * Handle hardware traps and faults. |
1da177e4 | 11 | */ |
c767a54b JP |
12 | |
13 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
14 | ||
56dd9470 | 15 | #include <linux/context_tracking.h> |
b5964405 IM |
16 | #include <linux/interrupt.h> |
17 | #include <linux/kallsyms.h> | |
18 | #include <linux/spinlock.h> | |
b5964405 IM |
19 | #include <linux/kprobes.h> |
20 | #include <linux/uaccess.h> | |
b5964405 | 21 | #include <linux/kdebug.h> |
f503b5ae | 22 | #include <linux/kgdb.h> |
1da177e4 | 23 | #include <linux/kernel.h> |
186f4360 | 24 | #include <linux/export.h> |
b5964405 | 25 | #include <linux/ptrace.h> |
b02ef20a | 26 | #include <linux/uprobes.h> |
1da177e4 | 27 | #include <linux/string.h> |
b5964405 | 28 | #include <linux/delay.h> |
1da177e4 | 29 | #include <linux/errno.h> |
b5964405 IM |
30 | #include <linux/kexec.h> |
31 | #include <linux/sched.h> | |
68db0cf1 | 32 | #include <linux/sched/task_stack.h> |
1da177e4 | 33 | #include <linux/timer.h> |
1da177e4 | 34 | #include <linux/init.h> |
91768d6c | 35 | #include <linux/bug.h> |
b5964405 IM |
36 | #include <linux/nmi.h> |
37 | #include <linux/mm.h> | |
c1d518c8 AH |
38 | #include <linux/smp.h> |
39 | #include <linux/io.h> | |
1da177e4 LT |
40 | |
41 | #ifdef CONFIG_EISA | |
42 | #include <linux/ioport.h> | |
43 | #include <linux/eisa.h> | |
44 | #endif | |
45 | ||
c0d12172 DJ |
46 | #if defined(CONFIG_EDAC) |
47 | #include <linux/edac.h> | |
48 | #endif | |
49 | ||
f8561296 | 50 | #include <asm/kmemcheck.h> |
b5964405 | 51 | #include <asm/stacktrace.h> |
1da177e4 | 52 | #include <asm/processor.h> |
1da177e4 | 53 | #include <asm/debugreg.h> |
60063497 | 54 | #include <linux/atomic.h> |
35de5b06 | 55 | #include <asm/text-patching.h> |
08d636b6 | 56 | #include <asm/ftrace.h> |
c1d518c8 | 57 | #include <asm/traps.h> |
1da177e4 | 58 | #include <asm/desc.h> |
78f7f1e5 | 59 | #include <asm/fpu/internal.h> |
9e55e44e | 60 | #include <asm/mce.h> |
4eefbe79 | 61 | #include <asm/fixmap.h> |
1164dd00 | 62 | #include <asm/mach_traps.h> |
17f41571 | 63 | #include <asm/alternative.h> |
a84eeaa9 | 64 | #include <asm/fpu/xstate.h> |
e7126cf5 | 65 | #include <asm/trace/mpx.h> |
fe3d197f | 66 | #include <asm/mpx.h> |
ba3e127e | 67 | #include <asm/vm86.h> |
c1d518c8 | 68 | |
081f75bb | 69 | #ifdef CONFIG_X86_64 |
428cf902 | 70 | #include <asm/x86_init.h> |
081f75bb AH |
71 | #include <asm/pgalloc.h> |
72 | #include <asm/proto.h> | |
4df05f36 KC |
73 | |
74 | /* No need to be aligned, but done to keep all IDTs defined the same way. */ | |
75 | gate_desc debug_idt_table[NR_VECTORS] __page_aligned_bss; | |
081f75bb | 76 | #else |
c1d518c8 | 77 | #include <asm/processor-flags.h> |
8e6dafd6 | 78 | #include <asm/setup.h> |
b2502b41 | 79 | #include <asm/proto.h> |
081f75bb | 80 | #endif |
1da177e4 | 81 | |
4df05f36 KC |
82 | /* Must be page-aligned because the real IDT is used in a fixmap. */ |
83 | gate_desc idt_table[NR_VECTORS] __page_aligned_bss; | |
84 | ||
b77b881f YL |
85 | DECLARE_BITMAP(used_vectors, NR_VECTORS); |
86 | EXPORT_SYMBOL_GPL(used_vectors); | |
87 | ||
d99e1bd1 | 88 | static inline void cond_local_irq_enable(struct pt_regs *regs) |
762db434 AH |
89 | { |
90 | if (regs->flags & X86_EFLAGS_IF) | |
91 | local_irq_enable(); | |
92 | } | |
93 | ||
d99e1bd1 | 94 | static inline void cond_local_irq_disable(struct pt_regs *regs) |
3d2a71a5 AH |
95 | { |
96 | if (regs->flags & X86_EFLAGS_IF) | |
97 | local_irq_disable(); | |
3d2a71a5 AH |
98 | } |
99 | ||
aaee8c3c AL |
100 | /* |
101 | * In IST context, we explicitly disable preemption. This serves two | |
102 | * purposes: it makes it much less likely that we would accidentally | |
103 | * schedule in IST context and it will force a warning if we somehow | |
104 | * manage to schedule by accident. | |
105 | */ | |
8c84014f | 106 | void ist_enter(struct pt_regs *regs) |
95927475 | 107 | { |
f39b6f0e | 108 | if (user_mode(regs)) { |
5778077d | 109 | RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU"); |
95927475 AL |
110 | } else { |
111 | /* | |
112 | * We might have interrupted pretty much anything. In | |
113 | * fact, if we're a machine check, we can even interrupt | |
114 | * NMI processing. We don't want in_nmi() to return true, | |
115 | * but we need to notify RCU. | |
116 | */ | |
117 | rcu_nmi_enter(); | |
95927475 | 118 | } |
b926e6f6 | 119 | |
aaee8c3c | 120 | preempt_disable(); |
b926e6f6 AL |
121 | |
122 | /* This code is a bit fragile. Test it. */ | |
f78f5b90 | 123 | RCU_LOCKDEP_WARN(!rcu_is_watching(), "ist_enter didn't work"); |
95927475 AL |
124 | } |
125 | ||
8c84014f | 126 | void ist_exit(struct pt_regs *regs) |
95927475 | 127 | { |
aaee8c3c | 128 | preempt_enable_no_resched(); |
95927475 | 129 | |
8c84014f | 130 | if (!user_mode(regs)) |
95927475 AL |
131 | rcu_nmi_exit(); |
132 | } | |
133 | ||
bced35b6 AL |
134 | /** |
135 | * ist_begin_non_atomic() - begin a non-atomic section in an IST exception | |
136 | * @regs: regs passed to the IST exception handler | |
137 | * | |
138 | * IST exception handlers normally cannot schedule. As a special | |
139 | * exception, if the exception interrupted userspace code (i.e. | |
f39b6f0e | 140 | * user_mode(regs) would return true) and the exception was not |
bced35b6 AL |
141 | * a double fault, it can be safe to schedule. ist_begin_non_atomic() |
142 | * begins a non-atomic section within an ist_enter()/ist_exit() region. | |
143 | * Callers are responsible for enabling interrupts themselves inside | |
8c84014f | 144 | * the non-atomic section, and callers must call ist_end_non_atomic() |
bced35b6 AL |
145 | * before ist_exit(). |
146 | */ | |
147 | void ist_begin_non_atomic(struct pt_regs *regs) | |
148 | { | |
f39b6f0e | 149 | BUG_ON(!user_mode(regs)); |
bced35b6 AL |
150 | |
151 | /* | |
152 | * Sanity check: we need to be on the normal thread stack. This | |
153 | * will catch asm bugs and any attempt to use ist_preempt_enable | |
154 | * from double_fault. | |
155 | */ | |
a7fcf28d AL |
156 | BUG_ON((unsigned long)(current_top_of_stack() - |
157 | current_stack_pointer()) >= THREAD_SIZE); | |
bced35b6 | 158 | |
aaee8c3c | 159 | preempt_enable_no_resched(); |
bced35b6 AL |
160 | } |
161 | ||
162 | /** | |
163 | * ist_end_non_atomic() - begin a non-atomic section in an IST exception | |
164 | * | |
165 | * Ends a non-atomic section started with ist_begin_non_atomic(). | |
166 | */ | |
167 | void ist_end_non_atomic(void) | |
168 | { | |
aaee8c3c | 169 | preempt_disable(); |
bced35b6 AL |
170 | } |
171 | ||
9a93848f PZ |
172 | int is_valid_bugaddr(unsigned long addr) |
173 | { | |
174 | unsigned short ud; | |
175 | ||
176 | if (addr < TASK_SIZE_MAX) | |
177 | return 0; | |
178 | ||
179 | if (probe_kernel_address((unsigned short *)addr, ud)) | |
180 | return 0; | |
181 | ||
182 | return ud == INSN_UD0 || ud == INSN_UD2; | |
183 | } | |
184 | ||
185 | static int fixup_bug(struct pt_regs *regs, int trapnr) | |
186 | { | |
187 | if (trapnr != X86_TRAP_UD) | |
188 | return 0; | |
189 | ||
190 | switch (report_bug(regs->ip, regs)) { | |
191 | case BUG_TRAP_TYPE_NONE: | |
192 | case BUG_TRAP_TYPE_BUG: | |
193 | break; | |
194 | ||
195 | case BUG_TRAP_TYPE_WARN: | |
196 | regs->ip += LEN_UD0; | |
197 | return 1; | |
198 | } | |
199 | ||
200 | return 0; | |
201 | } | |
202 | ||
9326638c | 203 | static nokprobe_inline int |
c416ddf5 FW |
204 | do_trap_no_signal(struct task_struct *tsk, int trapnr, char *str, |
205 | struct pt_regs *regs, long error_code) | |
1da177e4 | 206 | { |
d74ef111 | 207 | if (v8086_mode(regs)) { |
3c1326f8 | 208 | /* |
c416ddf5 | 209 | * Traps 0, 1, 3, 4, and 5 should be forwarded to vm86. |
3c1326f8 AH |
210 | * On nmi (interrupt 2), do_trap should not be called. |
211 | */ | |
c416ddf5 FW |
212 | if (trapnr < X86_TRAP_UD) { |
213 | if (!handle_vm86_trap((struct kernel_vm86_regs *) regs, | |
214 | error_code, trapnr)) | |
215 | return 0; | |
216 | } | |
217 | return -1; | |
1da177e4 | 218 | } |
d74ef111 | 219 | |
55474c48 | 220 | if (!user_mode(regs)) { |
9a93848f PZ |
221 | if (fixup_exception(regs, trapnr)) |
222 | return 0; | |
223 | ||
224 | if (fixup_bug(regs, trapnr)) | |
225 | return 0; | |
226 | ||
227 | tsk->thread.error_code = error_code; | |
228 | tsk->thread.trap_nr = trapnr; | |
229 | die(str, regs, error_code); | |
c416ddf5 | 230 | } |
1da177e4 | 231 | |
c416ddf5 FW |
232 | return -1; |
233 | } | |
1da177e4 | 234 | |
1c326c4d ON |
235 | static siginfo_t *fill_trap_info(struct pt_regs *regs, int signr, int trapnr, |
236 | siginfo_t *info) | |
958d3d72 ON |
237 | { |
238 | unsigned long siaddr; | |
239 | int sicode; | |
240 | ||
241 | switch (trapnr) { | |
1c326c4d ON |
242 | default: |
243 | return SEND_SIG_PRIV; | |
244 | ||
958d3d72 ON |
245 | case X86_TRAP_DE: |
246 | sicode = FPE_INTDIV; | |
b02ef20a | 247 | siaddr = uprobe_get_trap_addr(regs); |
958d3d72 ON |
248 | break; |
249 | case X86_TRAP_UD: | |
250 | sicode = ILL_ILLOPN; | |
b02ef20a | 251 | siaddr = uprobe_get_trap_addr(regs); |
958d3d72 ON |
252 | break; |
253 | case X86_TRAP_AC: | |
254 | sicode = BUS_ADRALN; | |
255 | siaddr = 0; | |
256 | break; | |
257 | } | |
258 | ||
259 | info->si_signo = signr; | |
260 | info->si_errno = 0; | |
261 | info->si_code = sicode; | |
262 | info->si_addr = (void __user *)siaddr; | |
1c326c4d | 263 | return info; |
958d3d72 ON |
264 | } |
265 | ||
9326638c | 266 | static void |
c416ddf5 FW |
267 | do_trap(int trapnr, int signr, char *str, struct pt_regs *regs, |
268 | long error_code, siginfo_t *info) | |
269 | { | |
270 | struct task_struct *tsk = current; | |
271 | ||
272 | ||
273 | if (!do_trap_no_signal(tsk, trapnr, str, regs, error_code)) | |
274 | return; | |
b5964405 | 275 | /* |
51e7dc70 | 276 | * We want error_code and trap_nr set for userspace faults and |
b5964405 IM |
277 | * kernelspace faults which result in die(), but not |
278 | * kernelspace faults which are fixed up. die() gives the | |
279 | * process no chance to handle the signal and notice the | |
280 | * kernel fault information, so that won't result in polluting | |
281 | * the information about previously queued, but not yet | |
282 | * delivered, faults. See also do_general_protection below. | |
283 | */ | |
284 | tsk->thread.error_code = error_code; | |
51e7dc70 | 285 | tsk->thread.trap_nr = trapnr; |
d1895183 | 286 | |
081f75bb AH |
287 | if (show_unhandled_signals && unhandled_signal(tsk, signr) && |
288 | printk_ratelimit()) { | |
c767a54b JP |
289 | pr_info("%s[%d] trap %s ip:%lx sp:%lx error:%lx", |
290 | tsk->comm, tsk->pid, str, | |
291 | regs->ip, regs->sp, error_code); | |
081f75bb | 292 | print_vma_addr(" in ", regs->ip); |
c767a54b | 293 | pr_cont("\n"); |
081f75bb | 294 | } |
081f75bb | 295 | |
38cad57b | 296 | force_sig_info(signr, info ?: SEND_SIG_PRIV, tsk); |
1da177e4 | 297 | } |
9326638c | 298 | NOKPROBE_SYMBOL(do_trap); |
1da177e4 | 299 | |
dff0796e | 300 | static void do_error_trap(struct pt_regs *regs, long error_code, char *str, |
1c326c4d | 301 | unsigned long trapnr, int signr) |
dff0796e | 302 | { |
1c326c4d | 303 | siginfo_t info; |
dff0796e | 304 | |
5778077d | 305 | RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU"); |
02fdcd5e | 306 | |
dff0796e ON |
307 | if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, signr) != |
308 | NOTIFY_STOP) { | |
d99e1bd1 | 309 | cond_local_irq_enable(regs); |
1c326c4d ON |
310 | do_trap(trapnr, signr, str, regs, error_code, |
311 | fill_trap_info(regs, signr, trapnr, &info)); | |
dff0796e | 312 | } |
dff0796e ON |
313 | } |
314 | ||
b5964405 | 315 | #define DO_ERROR(trapnr, signr, str, name) \ |
e407d620 | 316 | dotraplinkage void do_##name(struct pt_regs *regs, long error_code) \ |
b5964405 | 317 | { \ |
1c326c4d | 318 | do_error_trap(regs, error_code, str, trapnr, signr); \ |
1da177e4 LT |
319 | } |
320 | ||
0eb14833 ON |
321 | DO_ERROR(X86_TRAP_DE, SIGFPE, "divide error", divide_error) |
322 | DO_ERROR(X86_TRAP_OF, SIGSEGV, "overflow", overflow) | |
0eb14833 ON |
323 | DO_ERROR(X86_TRAP_UD, SIGILL, "invalid opcode", invalid_op) |
324 | DO_ERROR(X86_TRAP_OLD_MF, SIGFPE, "coprocessor segment overrun",coprocessor_segment_overrun) | |
325 | DO_ERROR(X86_TRAP_TS, SIGSEGV, "invalid TSS", invalid_TSS) | |
326 | DO_ERROR(X86_TRAP_NP, SIGBUS, "segment not present", segment_not_present) | |
0eb14833 | 327 | DO_ERROR(X86_TRAP_SS, SIGBUS, "stack segment", stack_segment) |
0eb14833 | 328 | DO_ERROR(X86_TRAP_AC, SIGBUS, "alignment check", alignment_check) |
1da177e4 | 329 | |
e37e43a4 | 330 | #ifdef CONFIG_VMAP_STACK |
6271cfdf AL |
331 | __visible void __noreturn handle_stack_overflow(const char *message, |
332 | struct pt_regs *regs, | |
333 | unsigned long fault_address) | |
e37e43a4 AL |
334 | { |
335 | printk(KERN_EMERG "BUG: stack guard page was hit at %p (stack is %p..%p)\n", | |
336 | (void *)fault_address, current->stack, | |
337 | (char *)current->stack + THREAD_SIZE - 1); | |
338 | die(message, regs, 0); | |
339 | ||
340 | /* Be absolutely certain we don't return. */ | |
341 | panic(message); | |
342 | } | |
343 | #endif | |
344 | ||
081f75bb AH |
345 | #ifdef CONFIG_X86_64 |
346 | /* Runs on IST stack */ | |
081f75bb AH |
347 | dotraplinkage void do_double_fault(struct pt_regs *regs, long error_code) |
348 | { | |
349 | static const char str[] = "double fault"; | |
350 | struct task_struct *tsk = current; | |
e37e43a4 AL |
351 | #ifdef CONFIG_VMAP_STACK |
352 | unsigned long cr2; | |
353 | #endif | |
081f75bb | 354 | |
af726f21 AL |
355 | #ifdef CONFIG_X86_ESPFIX64 |
356 | extern unsigned char native_irq_return_iret[]; | |
357 | ||
358 | /* | |
359 | * If IRET takes a non-IST fault on the espfix64 stack, then we | |
360 | * end up promoting it to a doublefault. In that case, modify | |
361 | * the stack to make it look like we just entered the #GP | |
362 | * handler from user space, similar to bad_iret. | |
95927475 AL |
363 | * |
364 | * No need for ist_enter here because we don't use RCU. | |
af726f21 AL |
365 | */ |
366 | if (((long)regs->sp >> PGDIR_SHIFT) == ESPFIX_PGD_ENTRY && | |
367 | regs->cs == __KERNEL_CS && | |
368 | regs->ip == (unsigned long)native_irq_return_iret) | |
369 | { | |
370 | struct pt_regs *normal_regs = task_pt_regs(current); | |
371 | ||
372 | /* Fake a #GP(0) from userspace. */ | |
373 | memmove(&normal_regs->ip, (void *)regs->sp, 5*8); | |
374 | normal_regs->orig_ax = 0; /* Missing (lost) #GP error code */ | |
375 | regs->ip = (unsigned long)general_protection; | |
376 | regs->sp = (unsigned long)&normal_regs->orig_ax; | |
95927475 | 377 | |
af726f21 AL |
378 | return; |
379 | } | |
380 | #endif | |
381 | ||
8c84014f | 382 | ist_enter(regs); |
c9408265 | 383 | notify_die(DIE_TRAP, str, regs, error_code, X86_TRAP_DF, SIGSEGV); |
081f75bb AH |
384 | |
385 | tsk->thread.error_code = error_code; | |
51e7dc70 | 386 | tsk->thread.trap_nr = X86_TRAP_DF; |
081f75bb | 387 | |
e37e43a4 AL |
388 | #ifdef CONFIG_VMAP_STACK |
389 | /* | |
390 | * If we overflow the stack into a guard page, the CPU will fail | |
391 | * to deliver #PF and will send #DF instead. Similarly, if we | |
392 | * take any non-IST exception while too close to the bottom of | |
393 | * the stack, the processor will get a page fault while | |
394 | * delivering the exception and will generate a double fault. | |
395 | * | |
396 | * According to the SDM (footnote in 6.15 under "Interrupt 14 - | |
397 | * Page-Fault Exception (#PF): | |
398 | * | |
399 | * Processors update CR2 whenever a page fault is detected. If a | |
400 | * second page fault occurs while an earlier page fault is being | |
401 | * deliv- ered, the faulting linear address of the second fault will | |
402 | * overwrite the contents of CR2 (replacing the previous | |
403 | * address). These updates to CR2 occur even if the page fault | |
404 | * results in a double fault or occurs during the delivery of a | |
405 | * double fault. | |
406 | * | |
407 | * The logic below has a small possibility of incorrectly diagnosing | |
408 | * some errors as stack overflows. For example, if the IDT or GDT | |
409 | * gets corrupted such that #GP delivery fails due to a bad descriptor | |
410 | * causing #GP and we hit this condition while CR2 coincidentally | |
411 | * points to the stack guard page, we'll think we overflowed the | |
412 | * stack. Given that we're going to panic one way or another | |
413 | * if this happens, this isn't necessarily worth fixing. | |
414 | * | |
415 | * If necessary, we could improve the test by only diagnosing | |
416 | * a stack overflow if the saved RSP points within 47 bytes of | |
417 | * the bottom of the stack: if RSP == tsk_stack + 48 and we | |
418 | * take an exception, the stack is already aligned and there | |
419 | * will be enough room SS, RSP, RFLAGS, CS, RIP, and a | |
420 | * possible error code, so a stack overflow would *not* double | |
421 | * fault. With any less space left, exception delivery could | |
422 | * fail, and, as a practical matter, we've overflowed the | |
423 | * stack even if the actual trigger for the double fault was | |
424 | * something else. | |
425 | */ | |
426 | cr2 = read_cr2(); | |
427 | if ((unsigned long)task_stack_page(tsk) - 1 - cr2 < PAGE_SIZE) | |
428 | handle_stack_overflow("kernel stack overflow (double-fault)", regs, cr2); | |
429 | #endif | |
430 | ||
4d067d8e BP |
431 | #ifdef CONFIG_DOUBLEFAULT |
432 | df_debug(regs, error_code); | |
433 | #endif | |
bd8b96df IM |
434 | /* |
435 | * This is always a kernel trap and never fixable (and thus must | |
436 | * never return). | |
437 | */ | |
081f75bb AH |
438 | for (;;) |
439 | die(str, regs, error_code); | |
440 | } | |
441 | #endif | |
442 | ||
fe3d197f DH |
443 | dotraplinkage void do_bounds(struct pt_regs *regs, long error_code) |
444 | { | |
1126cb45 | 445 | const struct mpx_bndcsr *bndcsr; |
fe3d197f DH |
446 | siginfo_t *info; |
447 | ||
5778077d | 448 | RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU"); |
fe3d197f DH |
449 | if (notify_die(DIE_TRAP, "bounds", regs, error_code, |
450 | X86_TRAP_BR, SIGSEGV) == NOTIFY_STOP) | |
8c84014f | 451 | return; |
d99e1bd1 | 452 | cond_local_irq_enable(regs); |
fe3d197f | 453 | |
f39b6f0e | 454 | if (!user_mode(regs)) |
fe3d197f DH |
455 | die("bounds", regs, error_code); |
456 | ||
457 | if (!cpu_feature_enabled(X86_FEATURE_MPX)) { | |
458 | /* The exception is not from Intel MPX */ | |
459 | goto exit_trap; | |
460 | } | |
461 | ||
462 | /* | |
463 | * We need to look at BNDSTATUS to resolve this exception. | |
a84eeaa9 DH |
464 | * A NULL here might mean that it is in its 'init state', |
465 | * which is all zeros which indicates MPX was not | |
466 | * responsible for the exception. | |
fe3d197f | 467 | */ |
d91cab78 | 468 | bndcsr = get_xsave_field_ptr(XFEATURE_MASK_BNDCSR); |
fe3d197f DH |
469 | if (!bndcsr) |
470 | goto exit_trap; | |
471 | ||
e7126cf5 | 472 | trace_bounds_exception_mpx(bndcsr); |
fe3d197f DH |
473 | /* |
474 | * The error code field of the BNDSTATUS register communicates status | |
475 | * information of a bound range exception #BR or operation involving | |
476 | * bound directory. | |
477 | */ | |
478 | switch (bndcsr->bndstatus & MPX_BNDSTA_ERROR_CODE) { | |
479 | case 2: /* Bound directory has invalid entry. */ | |
46a6e0cf | 480 | if (mpx_handle_bd_fault()) |
fe3d197f DH |
481 | goto exit_trap; |
482 | break; /* Success, it was handled */ | |
483 | case 1: /* Bound violation. */ | |
46a6e0cf | 484 | info = mpx_generate_siginfo(regs); |
e10abb2f | 485 | if (IS_ERR(info)) { |
fe3d197f DH |
486 | /* |
487 | * We failed to decode the MPX instruction. Act as if | |
488 | * the exception was not caused by MPX. | |
489 | */ | |
490 | goto exit_trap; | |
491 | } | |
492 | /* | |
493 | * Success, we decoded the instruction and retrieved | |
494 | * an 'info' containing the address being accessed | |
495 | * which caused the exception. This information | |
496 | * allows and application to possibly handle the | |
497 | * #BR exception itself. | |
498 | */ | |
499 | do_trap(X86_TRAP_BR, SIGSEGV, "bounds", regs, error_code, info); | |
500 | kfree(info); | |
501 | break; | |
502 | case 0: /* No exception caused by Intel MPX operations. */ | |
503 | goto exit_trap; | |
504 | default: | |
505 | die("bounds", regs, error_code); | |
506 | } | |
507 | ||
fe3d197f | 508 | return; |
8c84014f | 509 | |
fe3d197f DH |
510 | exit_trap: |
511 | /* | |
512 | * This path out is for all the cases where we could not | |
513 | * handle the exception in some way (like allocating a | |
514 | * table or telling userspace about it. We will also end | |
515 | * up here if the kernel has MPX turned off at compile | |
516 | * time.. | |
517 | */ | |
518 | do_trap(X86_TRAP_BR, SIGSEGV, "bounds", regs, error_code, NULL); | |
fe3d197f DH |
519 | } |
520 | ||
9326638c | 521 | dotraplinkage void |
13485ab5 | 522 | do_general_protection(struct pt_regs *regs, long error_code) |
1da177e4 | 523 | { |
13485ab5 | 524 | struct task_struct *tsk; |
b5964405 | 525 | |
5778077d | 526 | RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU"); |
d99e1bd1 | 527 | cond_local_irq_enable(regs); |
c6df0d71 | 528 | |
d74ef111 | 529 | if (v8086_mode(regs)) { |
ef3f6288 FW |
530 | local_irq_enable(); |
531 | handle_vm86_fault((struct kernel_vm86_regs *) regs, error_code); | |
8c84014f | 532 | return; |
ef3f6288 | 533 | } |
1da177e4 | 534 | |
13485ab5 | 535 | tsk = current; |
55474c48 | 536 | if (!user_mode(regs)) { |
548acf19 | 537 | if (fixup_exception(regs, X86_TRAP_GP)) |
8c84014f | 538 | return; |
ef3f6288 FW |
539 | |
540 | tsk->thread.error_code = error_code; | |
541 | tsk->thread.trap_nr = X86_TRAP_GP; | |
6ba3c97a FW |
542 | if (notify_die(DIE_GPF, "general protection fault", regs, error_code, |
543 | X86_TRAP_GP, SIGSEGV) != NOTIFY_STOP) | |
ef3f6288 | 544 | die("general protection fault", regs, error_code); |
8c84014f | 545 | return; |
ef3f6288 | 546 | } |
1da177e4 | 547 | |
13485ab5 | 548 | tsk->thread.error_code = error_code; |
51e7dc70 | 549 | tsk->thread.trap_nr = X86_TRAP_GP; |
b5964405 | 550 | |
13485ab5 AH |
551 | if (show_unhandled_signals && unhandled_signal(tsk, SIGSEGV) && |
552 | printk_ratelimit()) { | |
c767a54b | 553 | pr_info("%s[%d] general protection ip:%lx sp:%lx error:%lx", |
13485ab5 AH |
554 | tsk->comm, task_pid_nr(tsk), |
555 | regs->ip, regs->sp, error_code); | |
03252919 | 556 | print_vma_addr(" in ", regs->ip); |
c767a54b | 557 | pr_cont("\n"); |
03252919 | 558 | } |
abd4f750 | 559 | |
38cad57b | 560 | force_sig_info(SIGSEGV, SEND_SIG_PRIV, tsk); |
1da177e4 | 561 | } |
9326638c | 562 | NOKPROBE_SYMBOL(do_general_protection); |
1da177e4 | 563 | |
c1d518c8 | 564 | /* May run on IST stack. */ |
9326638c | 565 | dotraplinkage void notrace do_int3(struct pt_regs *regs, long error_code) |
1da177e4 | 566 | { |
08d636b6 | 567 | #ifdef CONFIG_DYNAMIC_FTRACE |
a192cd04 SR |
568 | /* |
569 | * ftrace must be first, everything else may cause a recursive crash. | |
570 | * See note by declaration of modifying_ftrace_code in ftrace.c | |
571 | */ | |
572 | if (unlikely(atomic_read(&modifying_ftrace_code)) && | |
573 | ftrace_int3_handler(regs)) | |
08d636b6 SR |
574 | return; |
575 | #endif | |
17f41571 JK |
576 | if (poke_int3_handler(regs)) |
577 | return; | |
578 | ||
8c84014f | 579 | ist_enter(regs); |
5778077d | 580 | RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU"); |
f503b5ae | 581 | #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP |
c9408265 KC |
582 | if (kgdb_ll_trap(DIE_INT3, "int3", regs, error_code, X86_TRAP_BP, |
583 | SIGTRAP) == NOTIFY_STOP) | |
6ba3c97a | 584 | goto exit; |
f503b5ae | 585 | #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */ |
cc3a1bf5 | 586 | |
6f6343f5 MH |
587 | #ifdef CONFIG_KPROBES |
588 | if (kprobe_int3_handler(regs)) | |
4cdf77a8 | 589 | goto exit; |
6f6343f5 MH |
590 | #endif |
591 | ||
c9408265 KC |
592 | if (notify_die(DIE_INT3, "int3", regs, error_code, X86_TRAP_BP, |
593 | SIGTRAP) == NOTIFY_STOP) | |
6ba3c97a | 594 | goto exit; |
b5964405 | 595 | |
42181186 SR |
596 | /* |
597 | * Let others (NMI) know that the debug stack is in use | |
598 | * as we may switch to the interrupt stack. | |
599 | */ | |
600 | debug_stack_usage_inc(); | |
d99e1bd1 | 601 | cond_local_irq_enable(regs); |
c9408265 | 602 | do_trap(X86_TRAP_BP, SIGTRAP, "int3", regs, error_code, NULL); |
d99e1bd1 | 603 | cond_local_irq_disable(regs); |
42181186 | 604 | debug_stack_usage_dec(); |
6ba3c97a | 605 | exit: |
8c84014f | 606 | ist_exit(regs); |
1da177e4 | 607 | } |
9326638c | 608 | NOKPROBE_SYMBOL(do_int3); |
1da177e4 | 609 | |
081f75bb | 610 | #ifdef CONFIG_X86_64 |
bd8b96df | 611 | /* |
48e08d0f AL |
612 | * Help handler running on IST stack to switch off the IST stack if the |
613 | * interrupted code was in user mode. The actual stack switch is done in | |
614 | * entry_64.S | |
bd8b96df | 615 | */ |
7ddc6a21 | 616 | asmlinkage __visible notrace struct pt_regs *sync_regs(struct pt_regs *eregs) |
081f75bb | 617 | { |
48e08d0f AL |
618 | struct pt_regs *regs = task_pt_regs(current); |
619 | *regs = *eregs; | |
081f75bb AH |
620 | return regs; |
621 | } | |
9326638c | 622 | NOKPROBE_SYMBOL(sync_regs); |
b645af2d AL |
623 | |
624 | struct bad_iret_stack { | |
625 | void *error_entry_ret; | |
626 | struct pt_regs regs; | |
627 | }; | |
628 | ||
7ddc6a21 | 629 | asmlinkage __visible notrace |
b645af2d AL |
630 | struct bad_iret_stack *fixup_bad_iret(struct bad_iret_stack *s) |
631 | { | |
632 | /* | |
633 | * This is called from entry_64.S early in handling a fault | |
634 | * caused by a bad iret to user mode. To handle the fault | |
635 | * correctly, we want move our stack frame to task_pt_regs | |
636 | * and we want to pretend that the exception came from the | |
637 | * iret target. | |
638 | */ | |
639 | struct bad_iret_stack *new_stack = | |
640 | container_of(task_pt_regs(current), | |
641 | struct bad_iret_stack, regs); | |
642 | ||
643 | /* Copy the IRET target to the new stack. */ | |
644 | memmove(&new_stack->regs.ip, (void *)s->regs.sp, 5*8); | |
645 | ||
646 | /* Copy the remainder of the stack from the current stack. */ | |
647 | memmove(new_stack, s, offsetof(struct bad_iret_stack, regs.ip)); | |
648 | ||
f39b6f0e | 649 | BUG_ON(!user_mode(&new_stack->regs)); |
b645af2d AL |
650 | return new_stack; |
651 | } | |
7ddc6a21 | 652 | NOKPROBE_SYMBOL(fixup_bad_iret); |
081f75bb AH |
653 | #endif |
654 | ||
f2b37575 AL |
655 | static bool is_sysenter_singlestep(struct pt_regs *regs) |
656 | { | |
657 | /* | |
658 | * We don't try for precision here. If we're anywhere in the region of | |
659 | * code that can be single-stepped in the SYSENTER entry path, then | |
660 | * assume that this is a useless single-step trap due to SYSENTER | |
661 | * being invoked with TF set. (We don't know in advance exactly | |
662 | * which instructions will be hit because BTF could plausibly | |
663 | * be set.) | |
664 | */ | |
665 | #ifdef CONFIG_X86_32 | |
666 | return (regs->ip - (unsigned long)__begin_SYSENTER_singlestep_region) < | |
667 | (unsigned long)__end_SYSENTER_singlestep_region - | |
668 | (unsigned long)__begin_SYSENTER_singlestep_region; | |
669 | #elif defined(CONFIG_IA32_EMULATION) | |
670 | return (regs->ip - (unsigned long)entry_SYSENTER_compat) < | |
671 | (unsigned long)__end_entry_SYSENTER_compat - | |
672 | (unsigned long)entry_SYSENTER_compat; | |
673 | #else | |
674 | return false; | |
675 | #endif | |
676 | } | |
677 | ||
1da177e4 LT |
678 | /* |
679 | * Our handling of the processor debug registers is non-trivial. | |
680 | * We do not clear them on entry and exit from the kernel. Therefore | |
681 | * it is possible to get a watchpoint trap here from inside the kernel. | |
682 | * However, the code in ./ptrace.c has ensured that the user can | |
683 | * only set watchpoints on userspace addresses. Therefore the in-kernel | |
684 | * watchpoint trap can only occur in code which is reading/writing | |
685 | * from user space. Such code must not hold kernel locks (since it | |
686 | * can equally take a page fault), therefore it is safe to call | |
687 | * force_sig_info even though that claims and releases locks. | |
b5964405 | 688 | * |
1da177e4 LT |
689 | * Code in ./signal.c ensures that the debug control register |
690 | * is restored before we deliver any signal, and therefore that | |
691 | * user code runs with the correct debug control register even though | |
692 | * we clear it here. | |
693 | * | |
694 | * Being careful here means that we don't have to be as careful in a | |
695 | * lot of more complicated places (task switching can be a bit lazy | |
696 | * about restoring all the debug state, and ptrace doesn't have to | |
697 | * find every occurrence of the TF bit that could be saved away even | |
698 | * by user code) | |
c1d518c8 AH |
699 | * |
700 | * May run on IST stack. | |
1da177e4 | 701 | */ |
9326638c | 702 | dotraplinkage void do_debug(struct pt_regs *regs, long error_code) |
1da177e4 | 703 | { |
1da177e4 | 704 | struct task_struct *tsk = current; |
a1e80faf | 705 | int user_icebp = 0; |
08d68323 | 706 | unsigned long dr6; |
da654b74 | 707 | int si_code; |
1da177e4 | 708 | |
8c84014f | 709 | ist_enter(regs); |
4cdf77a8 | 710 | |
08d68323 | 711 | get_debugreg(dr6, 6); |
8bb56436 AL |
712 | /* |
713 | * The Intel SDM says: | |
714 | * | |
715 | * Certain debug exceptions may clear bits 0-3. The remaining | |
716 | * contents of the DR6 register are never cleared by the | |
717 | * processor. To avoid confusion in identifying debug | |
718 | * exceptions, debug handlers should clear the register before | |
719 | * returning to the interrupted task. | |
720 | * | |
721 | * Keep it simple: clear DR6 immediately. | |
722 | */ | |
723 | set_debugreg(0, 6); | |
1da177e4 | 724 | |
40f9249a P |
725 | /* Filter out all the reserved bits which are preset to 1 */ |
726 | dr6 &= ~DR6_RESERVED; | |
727 | ||
81edd9f6 AL |
728 | /* |
729 | * The SDM says "The processor clears the BTF flag when it | |
730 | * generates a debug exception." Clear TIF_BLOCKSTEP to keep | |
731 | * TIF_BLOCKSTEP in sync with the hardware BTF flag. | |
732 | */ | |
733 | clear_tsk_thread_flag(tsk, TIF_BLOCKSTEP); | |
734 | ||
f2b37575 AL |
735 | if (unlikely(!user_mode(regs) && (dr6 & DR_STEP) && |
736 | is_sysenter_singlestep(regs))) { | |
737 | dr6 &= ~DR_STEP; | |
738 | if (!dr6) | |
739 | goto exit; | |
740 | /* | |
741 | * else we might have gotten a single-step trap and hit a | |
742 | * watchpoint at the same time, in which case we should fall | |
743 | * through and handle the watchpoint. | |
744 | */ | |
745 | } | |
746 | ||
a1e80faf FW |
747 | /* |
748 | * If dr6 has no reason to give us about the origin of this trap, | |
749 | * then it's very likely the result of an icebp/int01 trap. | |
750 | * User wants a sigtrap for that. | |
751 | */ | |
f39b6f0e | 752 | if (!dr6 && user_mode(regs)) |
a1e80faf FW |
753 | user_icebp = 1; |
754 | ||
f2b37575 | 755 | /* Catch kmemcheck conditions! */ |
eadb8a09 | 756 | if ((dr6 & DR_STEP) && kmemcheck_trap(regs)) |
6ba3c97a | 757 | goto exit; |
f8561296 | 758 | |
08d68323 P |
759 | /* Store the virtualized DR6 value */ |
760 | tsk->thread.debugreg6 = dr6; | |
761 | ||
6f6343f5 MH |
762 | #ifdef CONFIG_KPROBES |
763 | if (kprobe_debug_handler(regs)) | |
764 | goto exit; | |
765 | #endif | |
766 | ||
5a802e15 | 767 | if (notify_die(DIE_DEBUG, "debug", regs, (long)&dr6, error_code, |
62edab90 | 768 | SIGTRAP) == NOTIFY_STOP) |
6ba3c97a | 769 | goto exit; |
3d2a71a5 | 770 | |
42181186 SR |
771 | /* |
772 | * Let others (NMI) know that the debug stack is in use | |
773 | * as we may switch to the interrupt stack. | |
774 | */ | |
775 | debug_stack_usage_inc(); | |
776 | ||
1da177e4 | 777 | /* It's safe to allow irq's after DR6 has been saved */ |
d99e1bd1 | 778 | cond_local_irq_enable(regs); |
1da177e4 | 779 | |
d74ef111 | 780 | if (v8086_mode(regs)) { |
c9408265 KC |
781 | handle_vm86_trap((struct kernel_vm86_regs *) regs, error_code, |
782 | X86_TRAP_DB); | |
d99e1bd1 | 783 | cond_local_irq_disable(regs); |
42181186 | 784 | debug_stack_usage_dec(); |
6ba3c97a | 785 | goto exit; |
1da177e4 LT |
786 | } |
787 | ||
f2b37575 AL |
788 | if (WARN_ON_ONCE((dr6 & DR_STEP) && !user_mode(regs))) { |
789 | /* | |
790 | * Historical junk that used to handle SYSENTER single-stepping. | |
791 | * This should be unreachable now. If we survive for a while | |
792 | * without anyone hitting this warning, we'll turn this into | |
793 | * an oops. | |
794 | */ | |
08d68323 P |
795 | tsk->thread.debugreg6 &= ~DR_STEP; |
796 | set_tsk_thread_flag(tsk, TIF_SINGLESTEP); | |
797 | regs->flags &= ~X86_EFLAGS_TF; | |
1da177e4 | 798 | } |
08d68323 | 799 | si_code = get_si_code(tsk->thread.debugreg6); |
a1e80faf | 800 | if (tsk->thread.debugreg6 & (DR_STEP | DR_TRAP_BITS) || user_icebp) |
08d68323 | 801 | send_sigtrap(tsk, regs, error_code, si_code); |
d99e1bd1 | 802 | cond_local_irq_disable(regs); |
42181186 | 803 | debug_stack_usage_dec(); |
1da177e4 | 804 | |
6ba3c97a | 805 | exit: |
2a41aa4f AL |
806 | #if defined(CONFIG_X86_32) |
807 | /* | |
808 | * This is the most likely code path that involves non-trivial use | |
809 | * of the SYSENTER stack. Check that we haven't overrun it. | |
810 | */ | |
811 | WARN(this_cpu_read(cpu_tss.SYSENTER_stack_canary) != STACK_END_MAGIC, | |
812 | "Overran or corrupted SYSENTER stack\n"); | |
813 | #endif | |
8c84014f | 814 | ist_exit(regs); |
1da177e4 | 815 | } |
9326638c | 816 | NOKPROBE_SYMBOL(do_debug); |
1da177e4 LT |
817 | |
818 | /* | |
819 | * Note that we play around with the 'TS' bit in an attempt to get | |
820 | * the correct behaviour even in the presence of the asynchronous | |
821 | * IRQ13 behaviour | |
822 | */ | |
5e1b05be | 823 | static void math_error(struct pt_regs *regs, int error_code, int trapnr) |
1da177e4 | 824 | { |
e2e75c91 | 825 | struct task_struct *task = current; |
e1cebad4 | 826 | struct fpu *fpu = &task->thread.fpu; |
1da177e4 | 827 | siginfo_t info; |
c9408265 KC |
828 | char *str = (trapnr == X86_TRAP_MF) ? "fpu exception" : |
829 | "simd exception"; | |
e2e75c91 BG |
830 | |
831 | if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, SIGFPE) == NOTIFY_STOP) | |
832 | return; | |
d99e1bd1 | 833 | cond_local_irq_enable(regs); |
e2e75c91 | 834 | |
e1cebad4 | 835 | if (!user_mode(regs)) { |
548acf19 | 836 | if (!fixup_exception(regs, trapnr)) { |
e2e75c91 | 837 | task->thread.error_code = error_code; |
51e7dc70 | 838 | task->thread.trap_nr = trapnr; |
e2e75c91 BG |
839 | die(str, regs, error_code); |
840 | } | |
841 | return; | |
842 | } | |
1da177e4 LT |
843 | |
844 | /* | |
845 | * Save the info for the exception handler and clear the error. | |
846 | */ | |
e1cebad4 IM |
847 | fpu__save(fpu); |
848 | ||
849 | task->thread.trap_nr = trapnr; | |
9b6dba9e | 850 | task->thread.error_code = error_code; |
e1cebad4 IM |
851 | info.si_signo = SIGFPE; |
852 | info.si_errno = 0; | |
853 | info.si_addr = (void __user *)uprobe_get_trap_addr(regs); | |
adf77bac | 854 | |
e1cebad4 | 855 | info.si_code = fpu__exception_code(fpu, trapnr); |
adf77bac | 856 | |
e1cebad4 IM |
857 | /* Retry when we get spurious exceptions: */ |
858 | if (!info.si_code) | |
c9408265 | 859 | return; |
e1cebad4 | 860 | |
1da177e4 LT |
861 | force_sig_info(SIGFPE, &info, task); |
862 | } | |
863 | ||
e407d620 | 864 | dotraplinkage void do_coprocessor_error(struct pt_regs *regs, long error_code) |
1da177e4 | 865 | { |
5778077d | 866 | RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU"); |
c9408265 | 867 | math_error(regs, error_code, X86_TRAP_MF); |
1da177e4 LT |
868 | } |
869 | ||
e407d620 AH |
870 | dotraplinkage void |
871 | do_simd_coprocessor_error(struct pt_regs *regs, long error_code) | |
1da177e4 | 872 | { |
5778077d | 873 | RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU"); |
c9408265 | 874 | math_error(regs, error_code, X86_TRAP_XF); |
1da177e4 LT |
875 | } |
876 | ||
e407d620 AH |
877 | dotraplinkage void |
878 | do_spurious_interrupt_bug(struct pt_regs *regs, long error_code) | |
1da177e4 | 879 | { |
d99e1bd1 | 880 | cond_local_irq_enable(regs); |
081f75bb AH |
881 | } |
882 | ||
9326638c | 883 | dotraplinkage void |
aa78bcfa | 884 | do_device_not_available(struct pt_regs *regs, long error_code) |
7643e9b9 | 885 | { |
bef8b6da AL |
886 | unsigned long cr0; |
887 | ||
5778077d | 888 | RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU"); |
304bceda | 889 | |
a334fe43 | 890 | #ifdef CONFIG_MATH_EMULATION |
c6ab109f | 891 | if (!boot_cpu_has(X86_FEATURE_FPU) && (read_cr0() & X86_CR0_EM)) { |
d315760f TH |
892 | struct math_emu_info info = { }; |
893 | ||
d99e1bd1 | 894 | cond_local_irq_enable(regs); |
d315760f | 895 | |
aa78bcfa | 896 | info.regs = regs; |
d315760f | 897 | math_emulate(&info); |
a334fe43 | 898 | return; |
7643e9b9 | 899 | } |
a334fe43 | 900 | #endif |
bef8b6da AL |
901 | |
902 | /* This should not happen. */ | |
903 | cr0 = read_cr0(); | |
904 | if (WARN(cr0 & X86_CR0_TS, "CR0.TS was set")) { | |
905 | /* Try to fix it up and carry on. */ | |
906 | write_cr0(cr0 & ~X86_CR0_TS); | |
907 | } else { | |
908 | /* | |
909 | * Something terrible happened, and we're better off trying | |
910 | * to kill the task than getting stuck in a never-ending | |
911 | * loop of #NM faults. | |
912 | */ | |
913 | die("unexpected #NM exception", regs, error_code); | |
914 | } | |
7643e9b9 | 915 | } |
9326638c | 916 | NOKPROBE_SYMBOL(do_device_not_available); |
7643e9b9 | 917 | |
081f75bb | 918 | #ifdef CONFIG_X86_32 |
e407d620 | 919 | dotraplinkage void do_iret_error(struct pt_regs *regs, long error_code) |
f8e0870f AH |
920 | { |
921 | siginfo_t info; | |
6ba3c97a | 922 | |
5778077d | 923 | RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU"); |
f8e0870f AH |
924 | local_irq_enable(); |
925 | ||
926 | info.si_signo = SIGILL; | |
927 | info.si_errno = 0; | |
928 | info.si_code = ILL_BADSTK; | |
fc6fcdfb | 929 | info.si_addr = NULL; |
c9408265 | 930 | if (notify_die(DIE_TRAP, "iret exception", regs, error_code, |
6ba3c97a FW |
931 | X86_TRAP_IRET, SIGILL) != NOTIFY_STOP) { |
932 | do_trap(X86_TRAP_IRET, SIGILL, "iret exception", regs, error_code, | |
933 | &info); | |
934 | } | |
f8e0870f | 935 | } |
081f75bb | 936 | #endif |
f8e0870f | 937 | |
29c84391 JK |
938 | /* Set of traps needed for early debugging. */ |
939 | void __init early_trap_init(void) | |
940 | { | |
b4d83270 | 941 | /* |
5eca7453 WN |
942 | * Don't use IST to set DEBUG_STACK as it doesn't work until TSS |
943 | * is ready in cpu_init() <-- trap_init(). Before trap_init(), | |
944 | * CPU runs at ring 0 so it is impossible to hit an invalid | |
945 | * stack. Using the original stack works well enough at this | |
946 | * early stage. DEBUG_STACK will be equipped after cpu_init() in | |
b4d83270 | 947 | * trap_init(). |
5eca7453 WN |
948 | * |
949 | * We don't need to set trace_idt_table like set_intr_gate(), | |
950 | * since we don't have trace_debug and it will be reset to | |
951 | * 'debug' in trap_init() by set_intr_gate_ist(). | |
b4d83270 | 952 | */ |
5eca7453 | 953 | set_intr_gate_notrace(X86_TRAP_DB, debug); |
29c84391 | 954 | /* int3 can be called from all */ |
5eca7453 | 955 | set_system_intr_gate(X86_TRAP_BP, &int3); |
8170e6be | 956 | #ifdef CONFIG_X86_32 |
25c74b10 | 957 | set_intr_gate(X86_TRAP_PF, page_fault); |
8170e6be | 958 | #endif |
29c84391 JK |
959 | load_idt(&idt_descr); |
960 | } | |
961 | ||
8170e6be PA |
962 | void __init early_trap_pf_init(void) |
963 | { | |
964 | #ifdef CONFIG_X86_64 | |
25c74b10 | 965 | set_intr_gate(X86_TRAP_PF, page_fault); |
8170e6be PA |
966 | #endif |
967 | } | |
968 | ||
1da177e4 LT |
969 | void __init trap_init(void) |
970 | { | |
dbeb2be2 RR |
971 | int i; |
972 | ||
1da177e4 | 973 | #ifdef CONFIG_EISA |
927222b1 | 974 | void __iomem *p = early_ioremap(0x0FFFD9, 4); |
b5964405 IM |
975 | |
976 | if (readl(p) == 'E' + ('I'<<8) + ('S'<<16) + ('A'<<24)) | |
1da177e4 | 977 | EISA_bus = 1; |
927222b1 | 978 | early_iounmap(p, 4); |
1da177e4 LT |
979 | #endif |
980 | ||
25c74b10 | 981 | set_intr_gate(X86_TRAP_DE, divide_error); |
c9408265 | 982 | set_intr_gate_ist(X86_TRAP_NMI, &nmi, NMI_STACK); |
699d2937 | 983 | /* int4 can be called from all */ |
c9408265 | 984 | set_system_intr_gate(X86_TRAP_OF, &overflow); |
25c74b10 SA |
985 | set_intr_gate(X86_TRAP_BR, bounds); |
986 | set_intr_gate(X86_TRAP_UD, invalid_op); | |
987 | set_intr_gate(X86_TRAP_NM, device_not_available); | |
081f75bb | 988 | #ifdef CONFIG_X86_32 |
c9408265 | 989 | set_task_gate(X86_TRAP_DF, GDT_ENTRY_DOUBLEFAULT_TSS); |
081f75bb | 990 | #else |
c9408265 | 991 | set_intr_gate_ist(X86_TRAP_DF, &double_fault, DOUBLEFAULT_STACK); |
081f75bb | 992 | #endif |
25c74b10 SA |
993 | set_intr_gate(X86_TRAP_OLD_MF, coprocessor_segment_overrun); |
994 | set_intr_gate(X86_TRAP_TS, invalid_TSS); | |
995 | set_intr_gate(X86_TRAP_NP, segment_not_present); | |
6f442be2 | 996 | set_intr_gate(X86_TRAP_SS, stack_segment); |
25c74b10 SA |
997 | set_intr_gate(X86_TRAP_GP, general_protection); |
998 | set_intr_gate(X86_TRAP_SPURIOUS, spurious_interrupt_bug); | |
999 | set_intr_gate(X86_TRAP_MF, coprocessor_error); | |
1000 | set_intr_gate(X86_TRAP_AC, alignment_check); | |
1da177e4 | 1001 | #ifdef CONFIG_X86_MCE |
c9408265 | 1002 | set_intr_gate_ist(X86_TRAP_MC, &machine_check, MCE_STACK); |
1da177e4 | 1003 | #endif |
25c74b10 | 1004 | set_intr_gate(X86_TRAP_XF, simd_coprocessor_error); |
1da177e4 | 1005 | |
bb3f0b59 YL |
1006 | /* Reserve all the builtin and the syscall vector: */ |
1007 | for (i = 0; i < FIRST_EXTERNAL_VECTOR; i++) | |
1008 | set_bit(i, used_vectors); | |
1009 | ||
081f75bb | 1010 | #ifdef CONFIG_IA32_EMULATION |
2cd23553 | 1011 | set_system_intr_gate(IA32_SYSCALL_VECTOR, entry_INT80_compat); |
bb3f0b59 | 1012 | set_bit(IA32_SYSCALL_VECTOR, used_vectors); |
081f75bb AH |
1013 | #endif |
1014 | ||
1015 | #ifdef CONFIG_X86_32 | |
a798f091 | 1016 | set_system_intr_gate(IA32_SYSCALL_VECTOR, entry_INT80_32); |
51bb9284 | 1017 | set_bit(IA32_SYSCALL_VECTOR, used_vectors); |
081f75bb | 1018 | #endif |
bb3f0b59 | 1019 | |
4eefbe79 KC |
1020 | /* |
1021 | * Set the IDT descriptor to a fixed read-only location, so that the | |
1022 | * "sidt" instruction will not leak the location of the kernel, and | |
1023 | * to defend the IDT against arbitrary memory write vulnerabilities. | |
1024 | * It will be reloaded in cpu_init() */ | |
1025 | __set_fixmap(FIX_RO_IDT, __pa_symbol(idt_table), PAGE_KERNEL_RO); | |
1026 | idt_descr.address = fix_to_virt(FIX_RO_IDT); | |
1027 | ||
1da177e4 | 1028 | /* |
b5964405 | 1029 | * Should be a barrier for any external CPU state: |
1da177e4 LT |
1030 | */ |
1031 | cpu_init(); | |
1032 | ||
b4d83270 WN |
1033 | /* |
1034 | * X86_TRAP_DB and X86_TRAP_BP have been set | |
5eca7453 | 1035 | * in early_trap_init(). However, ITS works only after |
b4d83270 WN |
1036 | * cpu_init() loads TSS. See comments in early_trap_init(). |
1037 | */ | |
1038 | set_intr_gate_ist(X86_TRAP_DB, &debug, DEBUG_STACK); | |
1039 | /* int3 can be called from all */ | |
1040 | set_system_intr_gate_ist(X86_TRAP_BP, &int3, DEBUG_STACK); | |
1041 | ||
428cf902 | 1042 | x86_init.irqs.trap_init(); |
228bdaa9 SR |
1043 | |
1044 | #ifdef CONFIG_X86_64 | |
629f4f9d | 1045 | memcpy(&debug_idt_table, &idt_table, IDT_ENTRIES * 16); |
c9408265 KC |
1046 | set_nmi_gate(X86_TRAP_DB, &debug); |
1047 | set_nmi_gate(X86_TRAP_BP, &int3); | |
228bdaa9 | 1048 | #endif |
1da177e4 | 1049 | } |