Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 | 2 | * Copyright (C) 1991, 1992 Linus Torvalds |
a8c1be9d | 3 | * Copyright (C) 2000, 2001, 2002 Andi Kleen, SuSE Labs |
1da177e4 LT |
4 | * |
5 | * Pentium III FXSR, SSE support | |
6 | * Gareth Hughes <gareth@valinux.com>, May 2000 | |
7 | */ | |
8 | ||
9 | /* | |
c1d518c8 | 10 | * Handle hardware traps and faults. |
1da177e4 | 11 | */ |
c767a54b JP |
12 | |
13 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
14 | ||
56dd9470 | 15 | #include <linux/context_tracking.h> |
b5964405 IM |
16 | #include <linux/interrupt.h> |
17 | #include <linux/kallsyms.h> | |
18 | #include <linux/spinlock.h> | |
b5964405 IM |
19 | #include <linux/kprobes.h> |
20 | #include <linux/uaccess.h> | |
b5964405 | 21 | #include <linux/kdebug.h> |
f503b5ae | 22 | #include <linux/kgdb.h> |
1da177e4 | 23 | #include <linux/kernel.h> |
186f4360 | 24 | #include <linux/export.h> |
b5964405 | 25 | #include <linux/ptrace.h> |
b02ef20a | 26 | #include <linux/uprobes.h> |
1da177e4 | 27 | #include <linux/string.h> |
b5964405 | 28 | #include <linux/delay.h> |
1da177e4 | 29 | #include <linux/errno.h> |
b5964405 IM |
30 | #include <linux/kexec.h> |
31 | #include <linux/sched.h> | |
68db0cf1 | 32 | #include <linux/sched/task_stack.h> |
1da177e4 | 33 | #include <linux/timer.h> |
1da177e4 | 34 | #include <linux/init.h> |
91768d6c | 35 | #include <linux/bug.h> |
b5964405 IM |
36 | #include <linux/nmi.h> |
37 | #include <linux/mm.h> | |
c1d518c8 AH |
38 | #include <linux/smp.h> |
39 | #include <linux/io.h> | |
0d00449c PZ |
40 | #include <linux/hardirq.h> |
41 | #include <linux/atomic.h> | |
42 | ||
b5964405 | 43 | #include <asm/stacktrace.h> |
1da177e4 | 44 | #include <asm/processor.h> |
1da177e4 | 45 | #include <asm/debugreg.h> |
35de5b06 | 46 | #include <asm/text-patching.h> |
08d636b6 | 47 | #include <asm/ftrace.h> |
c1d518c8 | 48 | #include <asm/traps.h> |
1da177e4 | 49 | #include <asm/desc.h> |
78f7f1e5 | 50 | #include <asm/fpu/internal.h> |
6650cdd9 | 51 | #include <asm/cpu.h> |
ed1bbc40 | 52 | #include <asm/cpu_entry_area.h> |
9e55e44e | 53 | #include <asm/mce.h> |
4eefbe79 | 54 | #include <asm/fixmap.h> |
1164dd00 | 55 | #include <asm/mach_traps.h> |
17f41571 | 56 | #include <asm/alternative.h> |
a84eeaa9 | 57 | #include <asm/fpu/xstate.h> |
ba3e127e | 58 | #include <asm/vm86.h> |
6fc9dc81 | 59 | #include <asm/umip.h> |
59c1dcbe JH |
60 | #include <asm/insn.h> |
61 | #include <asm/insn-eval.h> | |
c1d518c8 | 62 | |
081f75bb | 63 | #ifdef CONFIG_X86_64 |
428cf902 | 64 | #include <asm/x86_init.h> |
081f75bb AH |
65 | #include <asm/pgalloc.h> |
66 | #include <asm/proto.h> | |
081f75bb | 67 | #else |
c1d518c8 | 68 | #include <asm/processor-flags.h> |
8e6dafd6 | 69 | #include <asm/setup.h> |
b2502b41 | 70 | #include <asm/proto.h> |
081f75bb | 71 | #endif |
1da177e4 | 72 | |
7854f822 | 73 | DECLARE_BITMAP(system_vectors, NR_VECTORS); |
b77b881f | 74 | |
d99e1bd1 | 75 | static inline void cond_local_irq_enable(struct pt_regs *regs) |
762db434 AH |
76 | { |
77 | if (regs->flags & X86_EFLAGS_IF) | |
78 | local_irq_enable(); | |
79 | } | |
80 | ||
d99e1bd1 | 81 | static inline void cond_local_irq_disable(struct pt_regs *regs) |
3d2a71a5 AH |
82 | { |
83 | if (regs->flags & X86_EFLAGS_IF) | |
84 | local_irq_disable(); | |
3d2a71a5 AH |
85 | } |
86 | ||
9a93848f PZ |
87 | int is_valid_bugaddr(unsigned long addr) |
88 | { | |
89 | unsigned short ud; | |
90 | ||
91 | if (addr < TASK_SIZE_MAX) | |
92 | return 0; | |
93 | ||
94 | if (probe_kernel_address((unsigned short *)addr, ud)) | |
95 | return 0; | |
96 | ||
97 | return ud == INSN_UD0 || ud == INSN_UD2; | |
98 | } | |
99 | ||
8a524f80 | 100 | int fixup_bug(struct pt_regs *regs, int trapnr) |
9a93848f PZ |
101 | { |
102 | if (trapnr != X86_TRAP_UD) | |
103 | return 0; | |
104 | ||
105 | switch (report_bug(regs->ip, regs)) { | |
106 | case BUG_TRAP_TYPE_NONE: | |
107 | case BUG_TRAP_TYPE_BUG: | |
108 | break; | |
109 | ||
110 | case BUG_TRAP_TYPE_WARN: | |
3b3a371c | 111 | regs->ip += LEN_UD2; |
9a93848f PZ |
112 | return 1; |
113 | } | |
114 | ||
115 | return 0; | |
116 | } | |
117 | ||
9326638c | 118 | static nokprobe_inline int |
79e21d65 | 119 | do_trap_no_signal(struct task_struct *tsk, int trapnr, const char *str, |
c416ddf5 | 120 | struct pt_regs *regs, long error_code) |
1da177e4 | 121 | { |
d74ef111 | 122 | if (v8086_mode(regs)) { |
3c1326f8 | 123 | /* |
c416ddf5 | 124 | * Traps 0, 1, 3, 4, and 5 should be forwarded to vm86. |
3c1326f8 AH |
125 | * On nmi (interrupt 2), do_trap should not be called. |
126 | */ | |
c416ddf5 FW |
127 | if (trapnr < X86_TRAP_UD) { |
128 | if (!handle_vm86_trap((struct kernel_vm86_regs *) regs, | |
129 | error_code, trapnr)) | |
130 | return 0; | |
131 | } | |
79e21d65 | 132 | } else if (!user_mode(regs)) { |
81fd9c18 | 133 | if (fixup_exception(regs, trapnr, error_code, 0)) |
9a93848f PZ |
134 | return 0; |
135 | ||
9a93848f PZ |
136 | tsk->thread.error_code = error_code; |
137 | tsk->thread.trap_nr = trapnr; | |
138 | die(str, regs, error_code); | |
c416ddf5 | 139 | } |
1da177e4 | 140 | |
b5964405 | 141 | /* |
51e7dc70 | 142 | * We want error_code and trap_nr set for userspace faults and |
b5964405 IM |
143 | * kernelspace faults which result in die(), but not |
144 | * kernelspace faults which are fixed up. die() gives the | |
145 | * process no chance to handle the signal and notice the | |
146 | * kernel fault information, so that won't result in polluting | |
147 | * the information about previously queued, but not yet | |
be4c11af | 148 | * delivered, faults. See also exc_general_protection below. |
b5964405 IM |
149 | */ |
150 | tsk->thread.error_code = error_code; | |
51e7dc70 | 151 | tsk->thread.trap_nr = trapnr; |
d1895183 | 152 | |
c416ddf5 FW |
153 | return -1; |
154 | } | |
1da177e4 | 155 | |
6ace1098 EB |
156 | static void show_signal(struct task_struct *tsk, int signr, |
157 | const char *type, const char *desc, | |
158 | struct pt_regs *regs, long error_code) | |
159 | { | |
081f75bb AH |
160 | if (show_unhandled_signals && unhandled_signal(tsk, signr) && |
161 | printk_ratelimit()) { | |
6ace1098 EB |
162 | pr_info("%s[%d] %s%s ip:%lx sp:%lx error:%lx", |
163 | tsk->comm, task_pid_nr(tsk), type, desc, | |
c767a54b | 164 | regs->ip, regs->sp, error_code); |
1c99a687 | 165 | print_vma_addr(KERN_CONT " in ", regs->ip); |
c767a54b | 166 | pr_cont("\n"); |
081f75bb | 167 | } |
6ace1098 EB |
168 | } |
169 | ||
9326638c | 170 | static void |
c416ddf5 | 171 | do_trap(int trapnr, int signr, char *str, struct pt_regs *regs, |
164881b6 | 172 | long error_code, int sicode, void __user *addr) |
c416ddf5 FW |
173 | { |
174 | struct task_struct *tsk = current; | |
175 | ||
c416ddf5 FW |
176 | if (!do_trap_no_signal(tsk, trapnr, str, regs, error_code)) |
177 | return; | |
d1895183 | 178 | |
6ace1098 | 179 | show_signal(tsk, signr, "trap ", str, regs, error_code); |
081f75bb | 180 | |
164881b6 | 181 | if (!sicode) |
3cf5d076 | 182 | force_sig(signr); |
164881b6 | 183 | else |
2e1661d2 | 184 | force_sig_fault(signr, sicode, addr); |
1da177e4 | 185 | } |
9326638c | 186 | NOKPROBE_SYMBOL(do_trap); |
1da177e4 | 187 | |
dff0796e | 188 | static void do_error_trap(struct pt_regs *regs, long error_code, char *str, |
164881b6 | 189 | unsigned long trapnr, int signr, int sicode, void __user *addr) |
dff0796e | 190 | { |
5778077d | 191 | RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU"); |
02fdcd5e | 192 | |
b8347c21 AS |
193 | /* |
194 | * WARN*()s end up here; fix them up before we call the | |
195 | * notifier chain. | |
196 | */ | |
197 | if (!user_mode(regs) && fixup_bug(regs, trapnr)) | |
198 | return; | |
199 | ||
dff0796e ON |
200 | if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, signr) != |
201 | NOTIFY_STOP) { | |
d99e1bd1 | 202 | cond_local_irq_enable(regs); |
164881b6 | 203 | do_trap(trapnr, signr, str, regs, error_code, sicode, addr); |
ca4c6a98 | 204 | cond_local_irq_disable(regs); |
dff0796e | 205 | } |
dff0796e ON |
206 | } |
207 | ||
218e31b6 TG |
208 | /* |
209 | * Posix requires to provide the address of the faulting instruction for | |
210 | * SIGILL (#UD) and SIGFPE (#DE) in the si_addr member of siginfo_t. | |
211 | * | |
212 | * This address is usually regs->ip, but when an uprobe moved the code out | |
213 | * of line then regs->ip points to the XOL code which would confuse | |
214 | * anything which analyzes the fault address vs. the unmodified binary. If | |
215 | * a trap happened in XOL code then uprobe maps regs->ip back to the | |
216 | * original instruction address. | |
217 | */ | |
218 | static __always_inline void __user *error_get_trap_addr(struct pt_regs *regs) | |
219 | { | |
220 | return (void __user *)uprobe_get_trap_addr(regs); | |
221 | } | |
222 | ||
9d06c402 TG |
223 | DEFINE_IDTENTRY(exc_divide_error) |
224 | { | |
225 | do_error_trap(regs, 0, "divide_error", X86_TRAP_DE, SIGFPE, | |
226 | FPE_INTDIV, error_get_trap_addr(regs)); | |
227 | } | |
228 | ||
4b6b9111 TG |
229 | DEFINE_IDTENTRY(exc_overflow) |
230 | { | |
231 | do_error_trap(regs, 0, "overflow", X86_TRAP_OF, SIGSEGV, 0, NULL); | |
232 | } | |
233 | ||
49893c5c TG |
234 | #ifdef CONFIG_X86_F00F_BUG |
235 | void handle_invalid_op(struct pt_regs *regs) | |
236 | #else | |
237 | static inline void handle_invalid_op(struct pt_regs *regs) | |
238 | #endif | |
239 | { | |
240 | do_error_trap(regs, 0, "invalid opcode", X86_TRAP_UD, SIGILL, | |
241 | ILL_ILLOPN, error_get_trap_addr(regs)); | |
242 | } | |
243 | ||
244 | DEFINE_IDTENTRY(exc_invalid_op) | |
245 | { | |
246 | handle_invalid_op(regs); | |
247 | } | |
248 | ||
f95658fd TG |
249 | DEFINE_IDTENTRY(exc_coproc_segment_overrun) |
250 | { | |
251 | do_error_trap(regs, 0, "coprocessor segment overrun", | |
252 | X86_TRAP_OLD_MF, SIGFPE, 0, NULL); | |
253 | } | |
254 | ||
97b3d290 TG |
255 | DEFINE_IDTENTRY_ERRORCODE(exc_invalid_tss) |
256 | { | |
257 | do_error_trap(regs, error_code, "invalid TSS", X86_TRAP_TS, SIGSEGV, | |
258 | 0, NULL); | |
259 | } | |
260 | ||
99a3fb8d TG |
261 | DEFINE_IDTENTRY_ERRORCODE(exc_segment_not_present) |
262 | { | |
263 | do_error_trap(regs, error_code, "segment not present", X86_TRAP_NP, | |
264 | SIGBUS, 0, NULL); | |
265 | } | |
266 | ||
fd9689bf TG |
267 | DEFINE_IDTENTRY_ERRORCODE(exc_stack_segment) |
268 | { | |
269 | do_error_trap(regs, error_code, "stack segment", X86_TRAP_SS, SIGBUS, | |
270 | 0, NULL); | |
1da177e4 LT |
271 | } |
272 | ||
436608bb | 273 | DEFINE_IDTENTRY_ERRORCODE(exc_alignment_check) |
6650cdd9 PZI |
274 | { |
275 | char *str = "alignment check"; | |
276 | ||
6650cdd9 PZI |
277 | if (notify_die(DIE_TRAP, str, regs, error_code, X86_TRAP_AC, SIGBUS) == NOTIFY_STOP) |
278 | return; | |
279 | ||
280 | if (!user_mode(regs)) | |
281 | die("Split lock detected\n", regs, error_code); | |
282 | ||
283 | local_irq_enable(); | |
284 | ||
285 | if (handle_user_split_lock(regs, error_code)) | |
286 | return; | |
287 | ||
288 | do_trap(X86_TRAP_AC, SIGBUS, "alignment check", regs, | |
289 | error_code, BUS_ADRALN, NULL); | |
290 | } | |
291 | ||
e37e43a4 | 292 | #ifdef CONFIG_VMAP_STACK |
6271cfdf AL |
293 | __visible void __noreturn handle_stack_overflow(const char *message, |
294 | struct pt_regs *regs, | |
295 | unsigned long fault_address) | |
e37e43a4 AL |
296 | { |
297 | printk(KERN_EMERG "BUG: stack guard page was hit at %p (stack is %p..%p)\n", | |
298 | (void *)fault_address, current->stack, | |
299 | (char *)current->stack + THREAD_SIZE - 1); | |
300 | die(message, regs, 0); | |
301 | ||
302 | /* Be absolutely certain we don't return. */ | |
2022cceb | 303 | panic("%s", message); |
e37e43a4 AL |
304 | } |
305 | #endif | |
306 | ||
7d8d8cfd AL |
307 | /* |
308 | * Runs on an IST stack for x86_64 and on a special task stack for x86_32. | |
309 | * | |
310 | * On x86_64, this is more or less a normal kernel entry. Notwithstanding the | |
311 | * SDM's warnings about double faults being unrecoverable, returning works as | |
312 | * expected. Presumably what the SDM actually means is that the CPU may get | |
313 | * the register state wrong on entry, so returning could be a bad idea. | |
314 | * | |
315 | * Various CPU engineers have promised that double faults due to an IRET fault | |
316 | * while the stack is read-only are, in fact, recoverable. | |
317 | * | |
318 | * On x86_32, this is entered through a task gate, and regs are synthesized | |
319 | * from the TSS. Returning is, in principle, okay, but changes to regs will | |
320 | * be lost. If, for some reason, we need to return to a context with modified | |
321 | * regs, the shim code could be adjusted to synchronize the registers. | |
c29c775a TG |
322 | * |
323 | * The 32bit #DF shim provides CR2 already as an argument. On 64bit it needs | |
324 | * to be read before doing anything else. | |
7d8d8cfd | 325 | */ |
c29c775a | 326 | DEFINE_IDTENTRY_DF(exc_double_fault) |
081f75bb AH |
327 | { |
328 | static const char str[] = "double fault"; | |
329 | struct task_struct *tsk = current; | |
330 | ||
7102cb07 | 331 | #ifdef CONFIG_VMAP_STACK |
c29c775a TG |
332 | unsigned long address = read_cr2(); |
333 | #endif | |
334 | ||
af726f21 AL |
335 | #ifdef CONFIG_X86_ESPFIX64 |
336 | extern unsigned char native_irq_return_iret[]; | |
337 | ||
338 | /* | |
339 | * If IRET takes a non-IST fault on the espfix64 stack, then we | |
6d9256f0 AL |
340 | * end up promoting it to a doublefault. In that case, take |
341 | * advantage of the fact that we're not using the normal (TSS.sp0) | |
342 | * stack right now. We can write a fake #GP(0) frame at TSS.sp0 | |
343 | * and then modify our own IRET frame so that, when we return, | |
344 | * we land directly at the #GP(0) vector with the stack already | |
345 | * set up according to its expectations. | |
346 | * | |
347 | * The net result is that our #GP handler will think that we | |
348 | * entered from usermode with the bad user context. | |
95927475 | 349 | * |
0d00449c | 350 | * No need for nmi_enter() here because we don't use RCU. |
af726f21 | 351 | */ |
c739f930 | 352 | if (((long)regs->sp >> P4D_SHIFT) == ESPFIX_PGD_ENTRY && |
af726f21 AL |
353 | regs->cs == __KERNEL_CS && |
354 | regs->ip == (unsigned long)native_irq_return_iret) | |
355 | { | |
c482feef | 356 | struct pt_regs *gpregs = (struct pt_regs *)this_cpu_read(cpu_tss_rw.x86_tss.sp0) - 1; |
e9660391 | 357 | unsigned long *p = (unsigned long *)regs->sp; |
af726f21 | 358 | |
6d9256f0 AL |
359 | /* |
360 | * regs->sp points to the failing IRET frame on the | |
361 | * ESPFIX64 stack. Copy it to the entry stack. This fills | |
362 | * in gpregs->ss through gpregs->ip. | |
363 | * | |
364 | */ | |
e9660391 PZ |
365 | gpregs->ip = p[0]; |
366 | gpregs->cs = p[1]; | |
367 | gpregs->flags = p[2]; | |
368 | gpregs->sp = p[3]; | |
369 | gpregs->ss = p[4]; | |
6d9256f0 | 370 | gpregs->orig_ax = 0; /* Missing (lost) #GP error code */ |
af726f21 | 371 | |
6d9256f0 AL |
372 | /* |
373 | * Adjust our frame so that we return straight to the #GP | |
374 | * vector with the expected RSP value. This is safe because | |
375 | * we won't enable interupts or schedule before we invoke | |
376 | * general_protection, so nothing will clobber the stack | |
377 | * frame we just set up. | |
bd7b1f7c AL |
378 | * |
379 | * We will enter general_protection with kernel GSBASE, | |
380 | * which is what the stub expects, given that the faulting | |
381 | * RIP will be the IRET instruction. | |
6d9256f0 | 382 | */ |
be4c11af | 383 | regs->ip = (unsigned long)asm_exc_general_protection; |
6d9256f0 | 384 | regs->sp = (unsigned long)&gpregs->orig_ax; |
95927475 | 385 | |
af726f21 AL |
386 | return; |
387 | } | |
388 | #endif | |
389 | ||
0d00449c | 390 | nmi_enter(); |
c29c775a | 391 | instrumentation_begin(); |
c9408265 | 392 | notify_die(DIE_TRAP, str, regs, error_code, X86_TRAP_DF, SIGSEGV); |
081f75bb AH |
393 | |
394 | tsk->thread.error_code = error_code; | |
51e7dc70 | 395 | tsk->thread.trap_nr = X86_TRAP_DF; |
081f75bb | 396 | |
e37e43a4 AL |
397 | #ifdef CONFIG_VMAP_STACK |
398 | /* | |
399 | * If we overflow the stack into a guard page, the CPU will fail | |
400 | * to deliver #PF and will send #DF instead. Similarly, if we | |
401 | * take any non-IST exception while too close to the bottom of | |
402 | * the stack, the processor will get a page fault while | |
403 | * delivering the exception and will generate a double fault. | |
404 | * | |
405 | * According to the SDM (footnote in 6.15 under "Interrupt 14 - | |
406 | * Page-Fault Exception (#PF): | |
407 | * | |
408 | * Processors update CR2 whenever a page fault is detected. If a | |
409 | * second page fault occurs while an earlier page fault is being | |
6d9256f0 | 410 | * delivered, the faulting linear address of the second fault will |
e37e43a4 AL |
411 | * overwrite the contents of CR2 (replacing the previous |
412 | * address). These updates to CR2 occur even if the page fault | |
413 | * results in a double fault or occurs during the delivery of a | |
414 | * double fault. | |
415 | * | |
416 | * The logic below has a small possibility of incorrectly diagnosing | |
417 | * some errors as stack overflows. For example, if the IDT or GDT | |
418 | * gets corrupted such that #GP delivery fails due to a bad descriptor | |
419 | * causing #GP and we hit this condition while CR2 coincidentally | |
420 | * points to the stack guard page, we'll think we overflowed the | |
421 | * stack. Given that we're going to panic one way or another | |
422 | * if this happens, this isn't necessarily worth fixing. | |
423 | * | |
424 | * If necessary, we could improve the test by only diagnosing | |
425 | * a stack overflow if the saved RSP points within 47 bytes of | |
426 | * the bottom of the stack: if RSP == tsk_stack + 48 and we | |
427 | * take an exception, the stack is already aligned and there | |
428 | * will be enough room SS, RSP, RFLAGS, CS, RIP, and a | |
429 | * possible error code, so a stack overflow would *not* double | |
430 | * fault. With any less space left, exception delivery could | |
431 | * fail, and, as a practical matter, we've overflowed the | |
432 | * stack even if the actual trigger for the double fault was | |
433 | * something else. | |
434 | */ | |
c29c775a TG |
435 | if ((unsigned long)task_stack_page(tsk) - 1 - address < PAGE_SIZE) { |
436 | handle_stack_overflow("kernel stack overflow (double-fault)", | |
437 | regs, address); | |
438 | } | |
e37e43a4 AL |
439 | #endif |
440 | ||
93efbde2 | 441 | pr_emerg("PANIC: double fault, error_code: 0x%lx\n", error_code); |
0337b7eb | 442 | die("double fault", regs, error_code); |
93efbde2 | 443 | panic("Machine halted."); |
c29c775a | 444 | instrumentation_end(); |
081f75bb | 445 | } |
081f75bb | 446 | |
58d9c81f | 447 | DEFINE_IDTENTRY(exc_bounds) |
fe3d197f | 448 | { |
58d9c81f | 449 | if (notify_die(DIE_TRAP, "bounds", regs, 0, |
fe3d197f | 450 | X86_TRAP_BR, SIGSEGV) == NOTIFY_STOP) |
8c84014f | 451 | return; |
d99e1bd1 | 452 | cond_local_irq_enable(regs); |
fe3d197f | 453 | |
f39b6f0e | 454 | if (!user_mode(regs)) |
58d9c81f | 455 | die("bounds", regs, 0); |
fe3d197f | 456 | |
58d9c81f | 457 | do_trap(X86_TRAP_BR, SIGSEGV, "bounds", regs, 0, 0, NULL); |
ca4c6a98 TG |
458 | |
459 | cond_local_irq_disable(regs); | |
fe3d197f DH |
460 | } |
461 | ||
59c1dcbe JH |
462 | enum kernel_gp_hint { |
463 | GP_NO_HINT, | |
464 | GP_NON_CANONICAL, | |
465 | GP_CANONICAL | |
466 | }; | |
467 | ||
468 | /* | |
469 | * When an uncaught #GP occurs, try to determine the memory address accessed by | |
470 | * the instruction and return that address to the caller. Also, try to figure | |
471 | * out whether any part of the access to that address was non-canonical. | |
472 | */ | |
473 | static enum kernel_gp_hint get_kernel_gp_address(struct pt_regs *regs, | |
474 | unsigned long *addr) | |
1da177e4 | 475 | { |
59c1dcbe JH |
476 | u8 insn_buf[MAX_INSN_SIZE]; |
477 | struct insn insn; | |
478 | ||
479 | if (probe_kernel_read(insn_buf, (void *)regs->ip, MAX_INSN_SIZE)) | |
480 | return GP_NO_HINT; | |
481 | ||
482 | kernel_insn_init(&insn, insn_buf, MAX_INSN_SIZE); | |
483 | insn_get_modrm(&insn); | |
484 | insn_get_sib(&insn); | |
485 | ||
486 | *addr = (unsigned long)insn_get_addr_ref(&insn, regs); | |
487 | if (*addr == -1UL) | |
488 | return GP_NO_HINT; | |
489 | ||
490 | #ifdef CONFIG_X86_64 | |
491 | /* | |
492 | * Check that: | |
493 | * - the operand is not in the kernel half | |
494 | * - the last byte of the operand is not in the user canonical half | |
495 | */ | |
496 | if (*addr < ~__VIRTUAL_MASK && | |
497 | *addr + insn.opnd_bytes - 1 > __VIRTUAL_MASK) | |
498 | return GP_NON_CANONICAL; | |
499 | #endif | |
500 | ||
501 | return GP_CANONICAL; | |
502 | } | |
503 | ||
504 | #define GPFSTR "general protection fault" | |
505 | ||
be4c11af | 506 | DEFINE_IDTENTRY_ERRORCODE(exc_general_protection) |
1da177e4 | 507 | { |
59c1dcbe | 508 | char desc[sizeof(GPFSTR) + 50 + 2*sizeof(unsigned long) + 1] = GPFSTR; |
36209766 | 509 | enum kernel_gp_hint hint = GP_NO_HINT; |
13485ab5 | 510 | struct task_struct *tsk; |
36209766 BP |
511 | unsigned long gp_addr; |
512 | int ret; | |
b5964405 | 513 | |
d99e1bd1 | 514 | cond_local_irq_enable(regs); |
c6df0d71 | 515 | |
6fc9dc81 RN |
516 | if (static_cpu_has(X86_FEATURE_UMIP)) { |
517 | if (user_mode(regs) && fixup_umip_exception(regs)) | |
ca4c6a98 | 518 | goto exit; |
6fc9dc81 RN |
519 | } |
520 | ||
d74ef111 | 521 | if (v8086_mode(regs)) { |
ef3f6288 FW |
522 | local_irq_enable(); |
523 | handle_vm86_fault((struct kernel_vm86_regs *) regs, error_code); | |
ca4c6a98 | 524 | local_irq_disable(); |
8c84014f | 525 | return; |
ef3f6288 | 526 | } |
1da177e4 | 527 | |
13485ab5 | 528 | tsk = current; |
ef3f6288 | 529 | |
36209766 | 530 | if (user_mode(regs)) { |
ef3f6288 FW |
531 | tsk->thread.error_code = error_code; |
532 | tsk->thread.trap_nr = X86_TRAP_GP; | |
76dee4a7 | 533 | |
36209766 BP |
534 | show_signal(tsk, SIGSEGV, "", desc, regs, error_code); |
535 | force_sig(SIGSEGV); | |
ca4c6a98 | 536 | goto exit; |
ef3f6288 | 537 | } |
1da177e4 | 538 | |
36209766 | 539 | if (fixup_exception(regs, X86_TRAP_GP, error_code, 0)) |
ca4c6a98 | 540 | goto exit; |
59c1dcbe | 541 | |
13485ab5 | 542 | tsk->thread.error_code = error_code; |
51e7dc70 | 543 | tsk->thread.trap_nr = X86_TRAP_GP; |
b5964405 | 544 | |
36209766 BP |
545 | /* |
546 | * To be potentially processing a kprobe fault and to trust the result | |
547 | * from kprobe_running(), we have to be non-preemptible. | |
548 | */ | |
549 | if (!preemptible() && | |
550 | kprobe_running() && | |
551 | kprobe_fault_handler(regs, X86_TRAP_GP)) | |
ca4c6a98 | 552 | goto exit; |
aa49f204 | 553 | |
36209766 BP |
554 | ret = notify_die(DIE_GPF, desc, regs, error_code, X86_TRAP_GP, SIGSEGV); |
555 | if (ret == NOTIFY_STOP) | |
ca4c6a98 | 556 | goto exit; |
1da177e4 | 557 | |
36209766 BP |
558 | if (error_code) |
559 | snprintf(desc, sizeof(desc), "segment-related " GPFSTR); | |
560 | else | |
561 | hint = get_kernel_gp_address(regs, &gp_addr); | |
562 | ||
563 | if (hint != GP_NO_HINT) | |
564 | snprintf(desc, sizeof(desc), GPFSTR ", %s 0x%lx", | |
565 | (hint == GP_NON_CANONICAL) ? "probably for non-canonical address" | |
566 | : "maybe for address", | |
567 | gp_addr); | |
568 | ||
569 | /* | |
570 | * KASAN is interested only in the non-canonical case, clear it | |
571 | * otherwise. | |
572 | */ | |
573 | if (hint != GP_NON_CANONICAL) | |
574 | gp_addr = 0; | |
b5964405 | 575 | |
36209766 | 576 | die_addr(desc, regs, error_code, gp_addr); |
abd4f750 | 577 | |
ca4c6a98 TG |
578 | exit: |
579 | cond_local_irq_disable(regs); | |
1da177e4 LT |
580 | } |
581 | ||
21e28290 PZ |
582 | static bool do_int3(struct pt_regs *regs) |
583 | { | |
584 | int res; | |
585 | ||
586 | #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP | |
587 | if (kgdb_ll_trap(DIE_INT3, "int3", regs, 0, X86_TRAP_BP, | |
588 | SIGTRAP) == NOTIFY_STOP) | |
589 | return true; | |
590 | #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */ | |
591 | ||
592 | #ifdef CONFIG_KPROBES | |
593 | if (kprobe_int3_handler(regs)) | |
594 | return true; | |
595 | #endif | |
596 | res = notify_die(DIE_INT3, "int3", regs, 0, X86_TRAP_BP, SIGTRAP); | |
597 | ||
598 | return res == NOTIFY_STOP; | |
599 | } | |
600 | ||
601 | static void do_int3_user(struct pt_regs *regs) | |
602 | { | |
603 | if (do_int3(regs)) | |
604 | return; | |
605 | ||
606 | cond_local_irq_enable(regs); | |
607 | do_trap(X86_TRAP_BP, SIGTRAP, "int3", regs, 0, 0, NULL); | |
608 | cond_local_irq_disable(regs); | |
609 | } | |
610 | ||
8edd7e37 | 611 | DEFINE_IDTENTRY_RAW(exc_int3) |
1da177e4 | 612 | { |
f64366ef PZ |
613 | /* |
614 | * poke_int3_handler() is completely self contained code; it does (and | |
615 | * must) *NOT* call out to anything, lest it hits upon yet another | |
616 | * INT3. | |
617 | */ | |
17f41571 JK |
618 | if (poke_int3_handler(regs)) |
619 | return; | |
620 | ||
d8ba61ba | 621 | /* |
fa95d7dc | 622 | * idtentry_enter_user() uses static_branch_{,un}likely() and therefore |
8edd7e37 TG |
623 | * can trigger INT3, hence poke_int3_handler() must be done |
624 | * before. If the entry came from kernel mode, then use nmi_enter() | |
625 | * because the INT3 could have been hit in any context including | |
626 | * NMI. | |
d8ba61ba | 627 | */ |
21e28290 | 628 | if (user_mode(regs)) { |
fa95d7dc | 629 | idtentry_enter_user(regs); |
21e28290 PZ |
630 | instrumentation_begin(); |
631 | do_int3_user(regs); | |
632 | instrumentation_end(); | |
fa95d7dc | 633 | idtentry_exit_user(regs); |
21e28290 PZ |
634 | } else { |
635 | nmi_enter(); | |
636 | instrumentation_begin(); | |
3ffdfdce | 637 | trace_hardirqs_off_prepare(); |
21e28290 PZ |
638 | if (!do_int3(regs)) |
639 | die("int3", regs, 0); | |
3ffdfdce TG |
640 | if (regs->flags & X86_EFLAGS_IF) |
641 | trace_hardirqs_on_prepare(); | |
21e28290 | 642 | instrumentation_end(); |
0d00449c | 643 | nmi_exit(); |
21e28290 | 644 | } |
1da177e4 | 645 | } |
1da177e4 | 646 | |
081f75bb | 647 | #ifdef CONFIG_X86_64 |
bd8b96df | 648 | /* |
7f2590a1 AL |
649 | * Help handler running on a per-cpu (IST or entry trampoline) stack |
650 | * to switch to the normal thread stack if the interrupted code was in | |
651 | * user mode. The actual stack switch is done in entry_64.S | |
bd8b96df | 652 | */ |
daf7a697 | 653 | asmlinkage __visible noinstr struct pt_regs *sync_regs(struct pt_regs *eregs) |
081f75bb | 654 | { |
7f2590a1 AL |
655 | struct pt_regs *regs = (struct pt_regs *)this_cpu_read(cpu_current_top_of_stack) - 1; |
656 | if (regs != eregs) | |
657 | *regs = *eregs; | |
081f75bb AH |
658 | return regs; |
659 | } | |
b645af2d AL |
660 | |
661 | struct bad_iret_stack { | |
662 | void *error_entry_ret; | |
663 | struct pt_regs regs; | |
664 | }; | |
665 | ||
d73a3329 | 666 | asmlinkage __visible noinstr |
b645af2d AL |
667 | struct bad_iret_stack *fixup_bad_iret(struct bad_iret_stack *s) |
668 | { | |
669 | /* | |
670 | * This is called from entry_64.S early in handling a fault | |
671 | * caused by a bad iret to user mode. To handle the fault | |
7f2590a1 AL |
672 | * correctly, we want to move our stack frame to where it would |
673 | * be had we entered directly on the entry stack (rather than | |
674 | * just below the IRET frame) and we want to pretend that the | |
675 | * exception came from the IRET target. | |
b645af2d | 676 | */ |
d73a3329 TG |
677 | struct bad_iret_stack tmp, *new_stack = |
678 | (struct bad_iret_stack *)__this_cpu_read(cpu_tss_rw.x86_tss.sp0) - 1; | |
b645af2d | 679 | |
d73a3329 TG |
680 | /* Copy the IRET target to the temporary storage. */ |
681 | memcpy(&tmp.regs.ip, (void *)s->regs.sp, 5*8); | |
b645af2d AL |
682 | |
683 | /* Copy the remainder of the stack from the current stack. */ | |
d73a3329 TG |
684 | memcpy(&tmp, s, offsetof(struct bad_iret_stack, regs.ip)); |
685 | ||
686 | /* Update the entry stack */ | |
687 | memcpy(new_stack, &tmp, sizeof(tmp)); | |
b645af2d | 688 | |
f39b6f0e | 689 | BUG_ON(!user_mode(&new_stack->regs)); |
b645af2d AL |
690 | return new_stack; |
691 | } | |
081f75bb AH |
692 | #endif |
693 | ||
f2b37575 AL |
694 | static bool is_sysenter_singlestep(struct pt_regs *regs) |
695 | { | |
696 | /* | |
697 | * We don't try for precision here. If we're anywhere in the region of | |
698 | * code that can be single-stepped in the SYSENTER entry path, then | |
699 | * assume that this is a useless single-step trap due to SYSENTER | |
700 | * being invoked with TF set. (We don't know in advance exactly | |
701 | * which instructions will be hit because BTF could plausibly | |
702 | * be set.) | |
703 | */ | |
704 | #ifdef CONFIG_X86_32 | |
705 | return (regs->ip - (unsigned long)__begin_SYSENTER_singlestep_region) < | |
706 | (unsigned long)__end_SYSENTER_singlestep_region - | |
707 | (unsigned long)__begin_SYSENTER_singlestep_region; | |
708 | #elif defined(CONFIG_IA32_EMULATION) | |
709 | return (regs->ip - (unsigned long)entry_SYSENTER_compat) < | |
710 | (unsigned long)__end_entry_SYSENTER_compat - | |
711 | (unsigned long)entry_SYSENTER_compat; | |
712 | #else | |
713 | return false; | |
714 | #endif | |
715 | } | |
716 | ||
9f58fdde PZ |
717 | static __always_inline void debug_enter(unsigned long *dr6, unsigned long *dr7) |
718 | { | |
719 | /* | |
720 | * Disable breakpoints during exception handling; recursive exceptions | |
721 | * are exceedingly 'fun'. | |
722 | * | |
723 | * Since this function is NOKPROBE, and that also applies to | |
724 | * HW_BREAKPOINT_X, we can't hit a breakpoint before this (XXX except a | |
725 | * HW_BREAKPOINT_W on our stack) | |
726 | * | |
727 | * Entry text is excluded for HW_BP_X and cpu_entry_area, which | |
728 | * includes the entry stack is excluded for everything. | |
729 | */ | |
730 | get_debugreg(*dr7, 7); | |
731 | set_debugreg(0, 7); | |
732 | ||
733 | /* | |
734 | * Ensure the compiler doesn't lower the above statements into | |
735 | * the critical section; disabling breakpoints late would not | |
736 | * be good. | |
737 | */ | |
738 | barrier(); | |
739 | ||
740 | /* | |
741 | * The Intel SDM says: | |
742 | * | |
743 | * Certain debug exceptions may clear bits 0-3. The remaining | |
744 | * contents of the DR6 register are never cleared by the | |
745 | * processor. To avoid confusion in identifying debug | |
746 | * exceptions, debug handlers should clear the register before | |
747 | * returning to the interrupted task. | |
748 | * | |
749 | * Keep it simple: clear DR6 immediately. | |
750 | */ | |
751 | get_debugreg(*dr6, 6); | |
752 | set_debugreg(0, 6); | |
753 | /* Filter out all the reserved bits which are preset to 1 */ | |
754 | *dr6 &= ~DR6_RESERVED; | |
755 | } | |
756 | ||
757 | static __always_inline void debug_exit(unsigned long dr7) | |
758 | { | |
759 | /* | |
760 | * Ensure the compiler doesn't raise this statement into | |
761 | * the critical section; enabling breakpoints early would | |
762 | * not be good. | |
763 | */ | |
764 | barrier(); | |
765 | set_debugreg(dr7, 7); | |
766 | } | |
767 | ||
1da177e4 LT |
768 | /* |
769 | * Our handling of the processor debug registers is non-trivial. | |
770 | * We do not clear them on entry and exit from the kernel. Therefore | |
771 | * it is possible to get a watchpoint trap here from inside the kernel. | |
772 | * However, the code in ./ptrace.c has ensured that the user can | |
773 | * only set watchpoints on userspace addresses. Therefore the in-kernel | |
774 | * watchpoint trap can only occur in code which is reading/writing | |
775 | * from user space. Such code must not hold kernel locks (since it | |
776 | * can equally take a page fault), therefore it is safe to call | |
777 | * force_sig_info even though that claims and releases locks. | |
b5964405 | 778 | * |
1da177e4 LT |
779 | * Code in ./signal.c ensures that the debug control register |
780 | * is restored before we deliver any signal, and therefore that | |
781 | * user code runs with the correct debug control register even though | |
782 | * we clear it here. | |
783 | * | |
784 | * Being careful here means that we don't have to be as careful in a | |
785 | * lot of more complicated places (task switching can be a bit lazy | |
786 | * about restoring all the debug state, and ptrace doesn't have to | |
787 | * find every occurrence of the TF bit that could be saved away even | |
788 | * by user code) | |
c1d518c8 AH |
789 | * |
790 | * May run on IST stack. | |
1da177e4 | 791 | */ |
9347f413 TG |
792 | static void noinstr handle_debug(struct pt_regs *regs, unsigned long dr6, |
793 | bool user_icebp) | |
1da177e4 | 794 | { |
1da177e4 | 795 | struct task_struct *tsk = current; |
da654b74 | 796 | int si_code; |
1da177e4 | 797 | |
08d68323 P |
798 | /* Store the virtualized DR6 value */ |
799 | tsk->thread.debugreg6 = dr6; | |
800 | ||
75347bb2 | 801 | instrumentation_begin(); |
6f6343f5 | 802 | #ifdef CONFIG_KPROBES |
75347bb2 TG |
803 | if (kprobe_debug_handler(regs)) { |
804 | instrumentation_end(); | |
4c0dcd83 | 805 | return; |
75347bb2 | 806 | } |
6f6343f5 MH |
807 | #endif |
808 | ||
2bbc68f8 | 809 | if (notify_die(DIE_DEBUG, "debug", regs, (long)&dr6, 0, |
75347bb2 TG |
810 | SIGTRAP) == NOTIFY_STOP) { |
811 | instrumentation_end(); | |
4c0dcd83 | 812 | return; |
75347bb2 | 813 | } |
3d2a71a5 | 814 | |
42181186 SR |
815 | /* |
816 | * Let others (NMI) know that the debug stack is in use | |
817 | * as we may switch to the interrupt stack. | |
818 | */ | |
819 | debug_stack_usage_inc(); | |
820 | ||
1da177e4 | 821 | /* It's safe to allow irq's after DR6 has been saved */ |
d99e1bd1 | 822 | cond_local_irq_enable(regs); |
1da177e4 | 823 | |
d74ef111 | 824 | if (v8086_mode(regs)) { |
2bbc68f8 TG |
825 | handle_vm86_trap((struct kernel_vm86_regs *) regs, 0, |
826 | X86_TRAP_DB); | |
9347f413 | 827 | goto out; |
1da177e4 LT |
828 | } |
829 | ||
f2b37575 AL |
830 | if (WARN_ON_ONCE((dr6 & DR_STEP) && !user_mode(regs))) { |
831 | /* | |
832 | * Historical junk that used to handle SYSENTER single-stepping. | |
833 | * This should be unreachable now. If we survive for a while | |
834 | * without anyone hitting this warning, we'll turn this into | |
835 | * an oops. | |
836 | */ | |
08d68323 P |
837 | tsk->thread.debugreg6 &= ~DR_STEP; |
838 | set_tsk_thread_flag(tsk, TIF_SINGLESTEP); | |
839 | regs->flags &= ~X86_EFLAGS_TF; | |
1da177e4 | 840 | } |
9347f413 | 841 | |
08d68323 | 842 | si_code = get_si_code(tsk->thread.debugreg6); |
a1e80faf | 843 | if (tsk->thread.debugreg6 & (DR_STEP | DR_TRAP_BITS) || user_icebp) |
2bbc68f8 | 844 | send_sigtrap(regs, 0, si_code); |
9347f413 TG |
845 | |
846 | out: | |
d99e1bd1 | 847 | cond_local_irq_disable(regs); |
42181186 | 848 | debug_stack_usage_dec(); |
75347bb2 | 849 | instrumentation_end(); |
4c0dcd83 TG |
850 | } |
851 | ||
852 | static __always_inline void exc_debug_kernel(struct pt_regs *regs, | |
853 | unsigned long dr6) | |
854 | { | |
855 | nmi_enter(); | |
3ffdfdce TG |
856 | instrumentation_begin(); |
857 | trace_hardirqs_off_prepare(); | |
858 | instrumentation_end(); | |
859 | ||
9347f413 TG |
860 | /* |
861 | * The SDM says "The processor clears the BTF flag when it | |
862 | * generates a debug exception." Clear TIF_BLOCKSTEP to keep | |
863 | * TIF_BLOCKSTEP in sync with the hardware BTF flag. | |
864 | */ | |
865 | clear_thread_flag(TIF_BLOCKSTEP); | |
866 | ||
867 | /* | |
868 | * Catch SYSENTER with TF set and clear DR_STEP. If this hit a | |
869 | * watchpoint at the same time then that will still be handled. | |
870 | */ | |
871 | if ((dr6 & DR_STEP) && is_sysenter_singlestep(regs)) | |
872 | dr6 &= ~DR_STEP; | |
873 | ||
874 | /* | |
875 | * If DR6 is zero, no point in trying to handle it. The kernel is | |
876 | * not using INT1. | |
877 | */ | |
878 | if (dr6) | |
879 | handle_debug(regs, dr6, false); | |
880 | ||
3ffdfdce TG |
881 | instrumentation_begin(); |
882 | if (regs->flags & X86_EFLAGS_IF) | |
883 | trace_hardirqs_on_prepare(); | |
884 | instrumentation_end(); | |
4c0dcd83 TG |
885 | nmi_exit(); |
886 | } | |
887 | ||
888 | static __always_inline void exc_debug_user(struct pt_regs *regs, | |
889 | unsigned long dr6) | |
890 | { | |
fa95d7dc | 891 | idtentry_enter_user(regs); |
9347f413 TG |
892 | clear_thread_flag(TIF_BLOCKSTEP); |
893 | ||
894 | /* | |
895 | * If dr6 has no reason to give us about the origin of this trap, | |
896 | * then it's very likely the result of an icebp/int01 trap. | |
897 | * User wants a sigtrap for that. | |
898 | */ | |
899 | handle_debug(regs, dr6, !dr6); | |
fa95d7dc | 900 | idtentry_exit_user(regs); |
4c0dcd83 TG |
901 | } |
902 | ||
903 | #ifdef CONFIG_X86_64 | |
904 | /* IST stack entry */ | |
905 | DEFINE_IDTENTRY_DEBUG(exc_debug) | |
906 | { | |
907 | unsigned long dr6, dr7; | |
908 | ||
909 | debug_enter(&dr6, &dr7); | |
910 | exc_debug_kernel(regs, dr6); | |
911 | debug_exit(dr7); | |
912 | } | |
913 | ||
914 | /* User entry, runs on regular task stack */ | |
915 | DEFINE_IDTENTRY_DEBUG_USER(exc_debug) | |
916 | { | |
917 | unsigned long dr6, dr7; | |
918 | ||
919 | debug_enter(&dr6, &dr7); | |
920 | exc_debug_user(regs, dr6); | |
921 | debug_exit(dr7); | |
922 | } | |
923 | #else | |
924 | /* 32 bit does not have separate entry points. */ | |
925 | DEFINE_IDTENTRY_DEBUG(exc_debug) | |
926 | { | |
927 | unsigned long dr6, dr7; | |
928 | ||
929 | debug_enter(&dr6, &dr7); | |
1da177e4 | 930 | |
2bbc68f8 | 931 | if (user_mode(regs)) |
4c0dcd83 | 932 | exc_debug_user(regs, dr6); |
2bbc68f8 | 933 | else |
4c0dcd83 TG |
934 | exc_debug_kernel(regs, dr6); |
935 | ||
9f58fdde | 936 | debug_exit(dr7); |
1da177e4 | 937 | } |
4c0dcd83 | 938 | #endif |
1da177e4 LT |
939 | |
940 | /* | |
941 | * Note that we play around with the 'TS' bit in an attempt to get | |
942 | * the correct behaviour even in the presence of the asynchronous | |
943 | * IRQ13 behaviour | |
944 | */ | |
48227e21 | 945 | static void math_error(struct pt_regs *regs, int trapnr) |
1da177e4 | 946 | { |
e2e75c91 | 947 | struct task_struct *task = current; |
e1cebad4 | 948 | struct fpu *fpu = &task->thread.fpu; |
0a996c1a | 949 | int si_code; |
c9408265 KC |
950 | char *str = (trapnr == X86_TRAP_MF) ? "fpu exception" : |
951 | "simd exception"; | |
e2e75c91 | 952 | |
d99e1bd1 | 953 | cond_local_irq_enable(regs); |
e2e75c91 | 954 | |
e1cebad4 | 955 | if (!user_mode(regs)) { |
48227e21 | 956 | if (fixup_exception(regs, trapnr, 0, 0)) |
ca4c6a98 | 957 | goto exit; |
3ae6295c | 958 | |
48227e21 | 959 | task->thread.error_code = 0; |
3ae6295c SL |
960 | task->thread.trap_nr = trapnr; |
961 | ||
48227e21 TG |
962 | if (notify_die(DIE_TRAP, str, regs, 0, trapnr, |
963 | SIGFPE) != NOTIFY_STOP) | |
964 | die(str, regs, 0); | |
ca4c6a98 | 965 | goto exit; |
e2e75c91 | 966 | } |
1da177e4 LT |
967 | |
968 | /* | |
969 | * Save the info for the exception handler and clear the error. | |
970 | */ | |
e1cebad4 IM |
971 | fpu__save(fpu); |
972 | ||
973 | task->thread.trap_nr = trapnr; | |
48227e21 | 974 | task->thread.error_code = 0; |
adf77bac | 975 | |
0a996c1a | 976 | si_code = fpu__exception_code(fpu, trapnr); |
e1cebad4 | 977 | /* Retry when we get spurious exceptions: */ |
0a996c1a | 978 | if (!si_code) |
ca4c6a98 | 979 | goto exit; |
e1cebad4 | 980 | |
0a996c1a | 981 | force_sig_fault(SIGFPE, si_code, |
2e1661d2 | 982 | (void __user *)uprobe_get_trap_addr(regs)); |
ca4c6a98 TG |
983 | exit: |
984 | cond_local_irq_disable(regs); | |
1da177e4 LT |
985 | } |
986 | ||
14a8bd2a | 987 | DEFINE_IDTENTRY(exc_coprocessor_error) |
1da177e4 | 988 | { |
48227e21 | 989 | math_error(regs, X86_TRAP_MF); |
1da177e4 LT |
990 | } |
991 | ||
48227e21 | 992 | DEFINE_IDTENTRY(exc_simd_coprocessor_error) |
1da177e4 | 993 | { |
48227e21 TG |
994 | if (IS_ENABLED(CONFIG_X86_INVD_BUG)) { |
995 | /* AMD 486 bug: INVD in CPL 0 raises #XF instead of #GP */ | |
996 | if (!static_cpu_has(X86_FEATURE_XMM)) { | |
997 | __exc_general_protection(regs, 0); | |
998 | return; | |
999 | } | |
1000 | } | |
1001 | math_error(regs, X86_TRAP_XF); | |
1da177e4 LT |
1002 | } |
1003 | ||
dad7106f | 1004 | DEFINE_IDTENTRY(exc_spurious_interrupt_bug) |
1da177e4 | 1005 | { |
d244d0e1 TG |
1006 | /* |
1007 | * This addresses a Pentium Pro Erratum: | |
1008 | * | |
1009 | * PROBLEM: If the APIC subsystem is configured in mixed mode with | |
1010 | * Virtual Wire mode implemented through the local APIC, an | |
1011 | * interrupt vector of 0Fh (Intel reserved encoding) may be | |
1012 | * generated by the local APIC (Int 15). This vector may be | |
1013 | * generated upon receipt of a spurious interrupt (an interrupt | |
1014 | * which is removed before the system receives the INTA sequence) | |
1015 | * instead of the programmed 8259 spurious interrupt vector. | |
1016 | * | |
1017 | * IMPLICATION: The spurious interrupt vector programmed in the | |
1018 | * 8259 is normally handled by an operating system's spurious | |
1019 | * interrupt handler. However, a vector of 0Fh is unknown to some | |
1020 | * operating systems, which would crash if this erratum occurred. | |
1021 | * | |
1022 | * In theory this could be limited to 32bit, but the handler is not | |
1023 | * hurting and who knows which other CPUs suffer from this. | |
1024 | */ | |
081f75bb AH |
1025 | } |
1026 | ||
866ae2cc | 1027 | DEFINE_IDTENTRY(exc_device_not_available) |
7643e9b9 | 1028 | { |
ee35b9b9 | 1029 | unsigned long cr0 = read_cr0(); |
bef8b6da | 1030 | |
a334fe43 | 1031 | #ifdef CONFIG_MATH_EMULATION |
ee35b9b9 | 1032 | if (!boot_cpu_has(X86_FEATURE_FPU) && (cr0 & X86_CR0_EM)) { |
d315760f TH |
1033 | struct math_emu_info info = { }; |
1034 | ||
d99e1bd1 | 1035 | cond_local_irq_enable(regs); |
d315760f | 1036 | |
aa78bcfa | 1037 | info.regs = regs; |
d315760f | 1038 | math_emulate(&info); |
ca4c6a98 TG |
1039 | |
1040 | cond_local_irq_disable(regs); | |
a334fe43 | 1041 | return; |
7643e9b9 | 1042 | } |
a334fe43 | 1043 | #endif |
bef8b6da AL |
1044 | |
1045 | /* This should not happen. */ | |
bef8b6da AL |
1046 | if (WARN(cr0 & X86_CR0_TS, "CR0.TS was set")) { |
1047 | /* Try to fix it up and carry on. */ | |
1048 | write_cr0(cr0 & ~X86_CR0_TS); | |
1049 | } else { | |
1050 | /* | |
1051 | * Something terrible happened, and we're better off trying | |
1052 | * to kill the task than getting stuck in a never-ending | |
1053 | * loop of #NM faults. | |
1054 | */ | |
866ae2cc | 1055 | die("unexpected #NM exception", regs, 0); |
bef8b6da | 1056 | } |
7643e9b9 AH |
1057 | } |
1058 | ||
081f75bb | 1059 | #ifdef CONFIG_X86_32 |
d7729050 | 1060 | DEFINE_IDTENTRY_SW(iret_error) |
f8e0870f | 1061 | { |
f8e0870f | 1062 | local_irq_enable(); |
d7729050 | 1063 | if (notify_die(DIE_TRAP, "iret exception", regs, 0, |
6ba3c97a | 1064 | X86_TRAP_IRET, SIGILL) != NOTIFY_STOP) { |
d7729050 | 1065 | do_trap(X86_TRAP_IRET, SIGILL, "iret exception", regs, 0, |
164881b6 | 1066 | ILL_BADSTK, (void __user *)NULL); |
6ba3c97a | 1067 | } |
ca4c6a98 | 1068 | local_irq_disable(); |
f8e0870f | 1069 | } |
081f75bb | 1070 | #endif |
f8e0870f | 1071 | |
1da177e4 LT |
1072 | void __init trap_init(void) |
1073 | { | |
40e7f949 AL |
1074 | /* Init cpu_entry_area before IST entries are set up */ |
1075 | setup_cpu_entry_areas(); | |
1076 | ||
b70543a0 | 1077 | idt_setup_traps(); |
bb3f0b59 | 1078 | |
4eefbe79 KC |
1079 | /* |
1080 | * Set the IDT descriptor to a fixed read-only location, so that the | |
1081 | * "sidt" instruction will not leak the location of the kernel, and | |
1082 | * to defend the IDT against arbitrary memory write vulnerabilities. | |
1083 | * It will be reloaded in cpu_init() */ | |
92a0f81d TG |
1084 | cea_set_pte(CPU_ENTRY_AREA_RO_IDT_VADDR, __pa_symbol(idt_table), |
1085 | PAGE_KERNEL_RO); | |
1086 | idt_descr.address = CPU_ENTRY_AREA_RO_IDT; | |
4eefbe79 | 1087 | |
1da177e4 | 1088 | /* |
b5964405 | 1089 | * Should be a barrier for any external CPU state: |
1da177e4 LT |
1090 | */ |
1091 | cpu_init(); | |
1092 | ||
90f6225f | 1093 | idt_setup_ist_traps(); |
b4d83270 | 1094 | |
0a30908b | 1095 | idt_setup_debugidt_traps(); |
1da177e4 | 1096 | } |