Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * linux/arch/x86-64/kernel/time.c | |
3 | * | |
4 | * "High Precision Event Timer" based timekeeping. | |
5 | * | |
6 | * Copyright (c) 1991,1992,1995 Linus Torvalds | |
7 | * Copyright (c) 1994 Alan Modra | |
8 | * Copyright (c) 1995 Markus Kuhn | |
9 | * Copyright (c) 1996 Ingo Molnar | |
10 | * Copyright (c) 1998 Andrea Arcangeli | |
2f82bde4 | 11 | * Copyright (c) 2002,2006 Vojtech Pavlik |
1da177e4 LT |
12 | * Copyright (c) 2003 Andi Kleen |
13 | * RTC support code taken from arch/i386/kernel/timers/time_hpet.c | |
14 | */ | |
15 | ||
16 | #include <linux/kernel.h> | |
17 | #include <linux/sched.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/mc146818rtc.h> | |
1da177e4 LT |
21 | #include <linux/time.h> |
22 | #include <linux/ioport.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/device.h> | |
25 | #include <linux/sysdev.h> | |
26 | #include <linux/bcd.h> | |
a670fad0 VP |
27 | #include <linux/notifier.h> |
28 | #include <linux/cpu.h> | |
1da177e4 | 29 | #include <linux/kallsyms.h> |
312df5f1 | 30 | #include <linux/acpi.h> |
8d916406 | 31 | #ifdef CONFIG_ACPI |
312df5f1 | 32 | #include <acpi/achware.h> /* for PM timer frequency */ |
0e5f61b0 | 33 | #include <acpi/acpi_bus.h> |
8d916406 | 34 | #endif |
1da177e4 | 35 | #include <asm/8253pit.h> |
28318daf | 36 | #include <asm/i8253.h> |
1da177e4 LT |
37 | #include <asm/pgtable.h> |
38 | #include <asm/vsyscall.h> | |
39 | #include <asm/timex.h> | |
40 | #include <asm/proto.h> | |
41 | #include <asm/hpet.h> | |
42 | #include <asm/sections.h> | |
1da177e4 | 43 | #include <linux/hpet.h> |
1da177e4 | 44 | #include <asm/apic.h> |
c37e7bb5 | 45 | #include <asm/hpet.h> |
803d80f6 | 46 | #include <asm/mpspec.h> |
6b37f5a2 | 47 | #include <asm/nmi.h> |
2aae950b | 48 | #include <asm/vgtod.h> |
1da177e4 | 49 | |
a670fad0 | 50 | static char *timename = NULL; |
e8b91777 | 51 | |
1da177e4 | 52 | DEFINE_SPINLOCK(rtc_lock); |
2ee60e17 | 53 | EXPORT_SYMBOL(rtc_lock); |
1da177e4 | 54 | DEFINE_SPINLOCK(i8253_lock); |
28318daf | 55 | EXPORT_SYMBOL(i8253_lock); |
1da177e4 | 56 | |
1da177e4 | 57 | volatile unsigned long __jiffies __section_jiffies = INITIAL_JIFFIES; |
1da177e4 | 58 | |
1da177e4 LT |
59 | unsigned long profile_pc(struct pt_regs *regs) |
60 | { | |
61 | unsigned long pc = instruction_pointer(regs); | |
62 | ||
31679f38 AK |
63 | /* Assume the lock function has either no stack frame or a copy |
64 | of eflags from PUSHF | |
65 | Eflags always has bits 22 and up cleared unlike kernel addresses. */ | |
d5a26017 | 66 | if (!user_mode(regs) && in_lock_functions(pc)) { |
31679f38 AK |
67 | unsigned long *sp = (unsigned long *)regs->rsp; |
68 | if (sp[0] >> 22) | |
69 | return sp[0]; | |
70 | if (sp[1] >> 22) | |
71 | return sp[1]; | |
1da177e4 LT |
72 | } |
73 | return pc; | |
74 | } | |
75 | EXPORT_SYMBOL(profile_pc); | |
76 | ||
77 | /* | |
78 | * In order to set the CMOS clock precisely, set_rtc_mmss has to be called 500 | |
79 | * ms after the second nowtime has started, because when nowtime is written | |
80 | * into the registers of the CMOS clock, it will jump to the next second | |
81 | * precisely 500 ms later. Check the Motorola MC146818A or Dallas DS12887 data | |
82 | * sheet for details. | |
83 | */ | |
84 | ||
af74522a | 85 | static int set_rtc_mmss(unsigned long nowtime) |
1da177e4 | 86 | { |
af74522a | 87 | int retval = 0; |
1da177e4 LT |
88 | int real_seconds, real_minutes, cmos_minutes; |
89 | unsigned char control, freq_select; | |
90 | ||
91 | /* | |
92 | * IRQs are disabled when we're called from the timer interrupt, | |
93 | * no need for spin_lock_irqsave() | |
94 | */ | |
95 | ||
96 | spin_lock(&rtc_lock); | |
97 | ||
98 | /* | |
99 | * Tell the clock it's being set and stop it. | |
100 | */ | |
101 | ||
102 | control = CMOS_READ(RTC_CONTROL); | |
103 | CMOS_WRITE(control | RTC_SET, RTC_CONTROL); | |
104 | ||
105 | freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
106 | CMOS_WRITE(freq_select | RTC_DIV_RESET2, RTC_FREQ_SELECT); | |
107 | ||
108 | cmos_minutes = CMOS_READ(RTC_MINUTES); | |
109 | BCD_TO_BIN(cmos_minutes); | |
110 | ||
111 | /* | |
112 | * since we're only adjusting minutes and seconds, don't interfere with hour | |
113 | * overflow. This avoids messing with unknown time zones but requires your RTC | |
114 | * not to be off by more than 15 minutes. Since we're calling it only when | |
115 | * our clock is externally synchronized using NTP, this shouldn't be a problem. | |
116 | */ | |
117 | ||
118 | real_seconds = nowtime % 60; | |
119 | real_minutes = nowtime / 60; | |
120 | if (((abs(real_minutes - cmos_minutes) + 15) / 30) & 1) | |
121 | real_minutes += 30; /* correct for half hour time zone */ | |
122 | real_minutes %= 60; | |
123 | ||
1da177e4 LT |
124 | if (abs(real_minutes - cmos_minutes) >= 30) { |
125 | printk(KERN_WARNING "time.c: can't update CMOS clock " | |
126 | "from %d to %d\n", cmos_minutes, real_minutes); | |
af74522a | 127 | retval = -1; |
28456ede | 128 | } else { |
0b91317e AK |
129 | BIN_TO_BCD(real_seconds); |
130 | BIN_TO_BCD(real_minutes); | |
1da177e4 LT |
131 | CMOS_WRITE(real_seconds, RTC_SECONDS); |
132 | CMOS_WRITE(real_minutes, RTC_MINUTES); | |
133 | } | |
134 | ||
135 | /* | |
136 | * The following flags have to be released exactly in this order, otherwise the | |
137 | * DS12887 (popular MC146818A clone with integrated battery and quartz) will | |
138 | * not reset the oscillator and will not update precisely 500 ms later. You | |
139 | * won't find this mentioned in the Dallas Semiconductor data sheets, but who | |
140 | * believes data sheets anyway ... -- Markus Kuhn | |
141 | */ | |
142 | ||
143 | CMOS_WRITE(control, RTC_CONTROL); | |
144 | CMOS_WRITE(freq_select, RTC_FREQ_SELECT); | |
145 | ||
146 | spin_unlock(&rtc_lock); | |
af74522a TG |
147 | |
148 | return retval; | |
1da177e4 LT |
149 | } |
150 | ||
af74522a TG |
151 | int update_persistent_clock(struct timespec now) |
152 | { | |
153 | return set_rtc_mmss(now.tv_sec); | |
154 | } | |
1da177e4 | 155 | |
7d12e780 | 156 | void main_timer_handler(void) |
1da177e4 | 157 | { |
1da177e4 LT |
158 | /* |
159 | * Here we are in the timer irq handler. We have irqs locally disabled (so we | |
160 | * don't need spin_lock_irqsave()) but we don't know if the timer_bh is running | |
161 | * on the other CPU, so we need a lock. We also need to lock the vsyscall | |
162 | * variables, because both do_timer() and us change them -arca+vojtech | |
163 | */ | |
164 | ||
165 | write_seqlock(&xtime_lock); | |
166 | ||
1da177e4 LT |
167 | /* |
168 | * Do the timer stuff. | |
169 | */ | |
170 | ||
1489939f | 171 | do_timer(1); |
1da177e4 | 172 | #ifndef CONFIG_SMP |
7d12e780 | 173 | update_process_times(user_mode(get_irq_regs())); |
1da177e4 LT |
174 | #endif |
175 | ||
176 | /* | |
177 | * In the SMP case we use the local APIC timer interrupt to do the profiling, | |
178 | * except when we simulate SMP mode on a uniprocessor system, in that case we | |
179 | * have to call the local interrupt handler. | |
180 | */ | |
181 | ||
1da177e4 | 182 | if (!using_apic_timer) |
7d12e780 | 183 | smp_local_timer_interrupt(); |
1da177e4 | 184 | |
1da177e4 | 185 | write_sequnlock(&xtime_lock); |
73dea47f | 186 | } |
1da177e4 | 187 | |
7d12e780 | 188 | static irqreturn_t timer_interrupt(int irq, void *dev_id) |
73dea47f AK |
189 | { |
190 | if (apic_runs_main_timer > 1) | |
191 | return IRQ_HANDLED; | |
7d12e780 | 192 | main_timer_handler(); |
d25bf7e5 VP |
193 | if (using_apic_timer) |
194 | smp_send_timer_broadcast_ipi(); | |
1da177e4 LT |
195 | return IRQ_HANDLED; |
196 | } | |
197 | ||
ef81ab2c | 198 | unsigned long read_persistent_clock(void) |
1da177e4 | 199 | { |
641f71f5 | 200 | unsigned int year, mon, day, hour, min, sec; |
1da177e4 | 201 | unsigned long flags; |
ad71860a | 202 | unsigned century = 0; |
1da177e4 | 203 | |
1da177e4 LT |
204 | spin_lock_irqsave(&rtc_lock, flags); |
205 | ||
641f71f5 MM |
206 | do { |
207 | sec = CMOS_READ(RTC_SECONDS); | |
208 | min = CMOS_READ(RTC_MINUTES); | |
209 | hour = CMOS_READ(RTC_HOURS); | |
210 | day = CMOS_READ(RTC_DAY_OF_MONTH); | |
211 | mon = CMOS_READ(RTC_MONTH); | |
212 | year = CMOS_READ(RTC_YEAR); | |
6954bee8 | 213 | #ifdef CONFIG_ACPI |
ad71860a AS |
214 | if (acpi_gbl_FADT.header.revision >= FADT2_REVISION_ID && |
215 | acpi_gbl_FADT.century) | |
216 | century = CMOS_READ(acpi_gbl_FADT.century); | |
6954bee8 | 217 | #endif |
641f71f5 | 218 | } while (sec != CMOS_READ(RTC_SECONDS)); |
6954bee8 | 219 | |
1da177e4 LT |
220 | spin_unlock_irqrestore(&rtc_lock, flags); |
221 | ||
0b91317e AK |
222 | /* |
223 | * We know that x86-64 always uses BCD format, no need to check the | |
224 | * config register. | |
2618f86e | 225 | */ |
1da177e4 | 226 | |
0b91317e AK |
227 | BCD_TO_BIN(sec); |
228 | BCD_TO_BIN(min); | |
229 | BCD_TO_BIN(hour); | |
230 | BCD_TO_BIN(day); | |
231 | BCD_TO_BIN(mon); | |
232 | BCD_TO_BIN(year); | |
1da177e4 | 233 | |
ad71860a AS |
234 | if (century) { |
235 | BCD_TO_BIN(century); | |
236 | year += century * 100; | |
237 | printk(KERN_INFO "Extended CMOS year: %d\n", century * 100); | |
2618f86e | 238 | } else { |
6954bee8 AK |
239 | /* |
240 | * x86-64 systems only exists since 2002. | |
241 | * This will work up to Dec 31, 2100 | |
2618f86e | 242 | */ |
6954bee8 AK |
243 | year += 2000; |
244 | } | |
1da177e4 LT |
245 | |
246 | return mktime(year, mon, day, hour, min, sec); | |
247 | } | |
248 | ||
6b37f5a2 JR |
249 | /* calibrate_cpu is used on systems with fixed rate TSCs to determine |
250 | * processor frequency */ | |
251 | #define TICK_COUNT 100000000 | |
252 | static unsigned int __init tsc_calibrate_cpu_khz(void) | |
253 | { | |
2618f86e TG |
254 | int tsc_start, tsc_now; |
255 | int i, no_ctr_free; | |
256 | unsigned long evntsel3 = 0, pmc3 = 0, pmc_now = 0; | |
257 | unsigned long flags; | |
258 | ||
259 | for (i = 0; i < 4; i++) | |
260 | if (avail_to_resrv_perfctr_nmi_bit(i)) | |
261 | break; | |
262 | no_ctr_free = (i == 4); | |
263 | if (no_ctr_free) { | |
264 | i = 3; | |
265 | rdmsrl(MSR_K7_EVNTSEL3, evntsel3); | |
266 | wrmsrl(MSR_K7_EVNTSEL3, 0); | |
267 | rdmsrl(MSR_K7_PERFCTR3, pmc3); | |
268 | } else { | |
269 | reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i); | |
270 | reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i); | |
271 | } | |
272 | local_irq_save(flags); | |
273 | /* start meauring cycles, incrementing from 0 */ | |
274 | wrmsrl(MSR_K7_PERFCTR0 + i, 0); | |
275 | wrmsrl(MSR_K7_EVNTSEL0 + i, 1 << 22 | 3 << 16 | 0x76); | |
276 | rdtscl(tsc_start); | |
277 | do { | |
278 | rdmsrl(MSR_K7_PERFCTR0 + i, pmc_now); | |
279 | tsc_now = get_cycles_sync(); | |
280 | } while ((tsc_now - tsc_start) < TICK_COUNT); | |
281 | ||
282 | local_irq_restore(flags); | |
283 | if (no_ctr_free) { | |
284 | wrmsrl(MSR_K7_EVNTSEL3, 0); | |
285 | wrmsrl(MSR_K7_PERFCTR3, pmc3); | |
286 | wrmsrl(MSR_K7_EVNTSEL3, evntsel3); | |
287 | } else { | |
288 | release_perfctr_nmi(MSR_K7_PERFCTR0 + i); | |
289 | release_evntsel_nmi(MSR_K7_EVNTSEL0 + i); | |
290 | } | |
291 | ||
292 | return pmc_now * tsc_khz / (tsc_now - tsc_start); | |
6b37f5a2 | 293 | } |
1da177e4 | 294 | |
73dea47f AK |
295 | #define PIT_MODE 0x43 |
296 | #define PIT_CH0 0x40 | |
297 | ||
141f9cfe | 298 | static void __pit_init(int val, u8 mode) |
1da177e4 LT |
299 | { |
300 | unsigned long flags; | |
301 | ||
302 | spin_lock_irqsave(&i8253_lock, flags); | |
73dea47f AK |
303 | outb_p(mode, PIT_MODE); |
304 | outb_p(val & 0xff, PIT_CH0); /* LSB */ | |
305 | outb_p(val >> 8, PIT_CH0); /* MSB */ | |
1da177e4 LT |
306 | spin_unlock_irqrestore(&i8253_lock, flags); |
307 | } | |
308 | ||
73dea47f AK |
309 | void __init pit_init(void) |
310 | { | |
311 | __pit_init(LATCH, 0x34); /* binary, mode 2, LSB/MSB, ch 0 */ | |
312 | } | |
313 | ||
141f9cfe | 314 | void pit_stop_interrupt(void) |
73dea47f AK |
315 | { |
316 | __pit_init(0, 0x30); /* mode 0 */ | |
317 | } | |
318 | ||
141f9cfe | 319 | void stop_timer_interrupt(void) |
73dea47f AK |
320 | { |
321 | char *name; | |
2d0c87c3 | 322 | if (hpet_address) { |
73dea47f AK |
323 | name = "HPET"; |
324 | hpet_timer_stop_set_go(0); | |
325 | } else { | |
326 | name = "PIT"; | |
327 | pit_stop_interrupt(); | |
328 | } | |
329 | printk(KERN_INFO "timer: %s interrupt stopped.\n", name); | |
330 | } | |
331 | ||
1da177e4 | 332 | static struct irqaction irq0 = { |
e6d828f4 | 333 | .handler = timer_interrupt, |
5fa3a246 | 334 | .flags = IRQF_DISABLED | IRQF_IRQPOLL | IRQF_NOBALANCING, |
e6d828f4 | 335 | .mask = CPU_MASK_NONE, |
2618f86e | 336 | .name = "timer" |
1da177e4 LT |
337 | }; |
338 | ||
a670fad0 VP |
339 | void __init time_init(void) |
340 | { | |
1da177e4 | 341 | if (nohpet) |
2d0c87c3 | 342 | hpet_address = 0; |
1da177e4 | 343 | |
1489939f | 344 | if (hpet_arch_init()) |
2d0c87c3 | 345 | hpet_address = 0; |
a3a00751 | 346 | |
347 | if (hpet_use_timer) { | |
b20367a6 | 348 | /* set tick_nsec to use the proper rate for HPET */ |
2618f86e | 349 | tick_nsec = TICK_NSEC_HPET; |
1da177e4 LT |
350 | timename = "HPET"; |
351 | } else { | |
352 | pit_init(); | |
1da177e4 LT |
353 | timename = "PIT"; |
354 | } | |
355 | ||
d371698e TG |
356 | tsc_calibrate(); |
357 | ||
6b37f5a2 JR |
358 | cpu_khz = tsc_khz; |
359 | if (cpu_has(&boot_cpu_data, X86_FEATURE_CONSTANT_TSC) && | |
360 | boot_cpu_data.x86_vendor == X86_VENDOR_AMD && | |
361 | boot_cpu_data.x86 == 16) | |
362 | cpu_khz = tsc_calibrate_cpu_khz(); | |
363 | ||
312df5f1 | 364 | if (unsynchronized_tsc()) |
5a90cf20 | 365 | mark_tsc_unstable("TSCs unsynchronized"); |
a670fad0 | 366 | |
2d0c87c3 | 367 | if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP)) |
c08c8205 VP |
368 | vgetcpu_mode = VGETCPU_RDTSCP; |
369 | else | |
370 | vgetcpu_mode = VGETCPU_LSL; | |
371 | ||
6b37f5a2 | 372 | set_cyc2ns_scale(tsc_khz); |
a670fad0 VP |
373 | printk(KERN_INFO "time.c: Detected %d.%03d MHz processor.\n", |
374 | cpu_khz / 1000, cpu_khz % 1000); | |
6bb74df4 | 375 | init_tsc_clocksource(); |
376 | ||
1489939f | 377 | setup_irq(0, &irq0); |
1da177e4 LT |
378 | } |
379 | ||
0b91317e AK |
380 | /* |
381 | * sysfs support for the timer. | |
382 | */ | |
383 | ||
0b9c33a7 | 384 | static int timer_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 | 385 | { |
1da177e4 LT |
386 | return 0; |
387 | } | |
388 | ||
389 | static int timer_resume(struct sys_device *dev) | |
390 | { | |
2d0c87c3 | 391 | if (hpet_address) |
1da177e4 LT |
392 | hpet_reenable(); |
393 | else | |
394 | i8254_timer_resume(); | |
1da177e4 LT |
395 | return 0; |
396 | } | |
397 | ||
398 | static struct sysdev_class timer_sysclass = { | |
399 | .resume = timer_resume, | |
400 | .suspend = timer_suspend, | |
401 | set_kset_name("timer"), | |
402 | }; | |
403 | ||
405ae7d3 | 404 | /* XXX this sysfs stuff should probably go elsewhere later -john */ |
1da177e4 LT |
405 | static struct sys_device device_timer = { |
406 | .id = 0, | |
407 | .cls = &timer_sysclass, | |
408 | }; | |
409 | ||
410 | static int time_init_device(void) | |
411 | { | |
412 | int error = sysdev_class_register(&timer_sysclass); | |
413 | if (!error) | |
414 | error = sysdev_register(&device_timer); | |
415 | return error; | |
416 | } | |
417 | ||
418 | device_initcall(time_init_device); |