[linux-2.6-block.git] / arch / x86 / kernel / suspend_64.c

/*
 * Suspend support specific for i386.
 *
 * Distribute under GPLv2
 *
 * Copyright (c) 2002 Pavel Machek <pavel@suse.cz>
 * Copyright (c) 2001 Patrick Mochel <mochel@osdl.org>
 */

#include <linux/smp.h>
#include <linux/suspend.h>
#include <asm/proto.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/mtrr.h>

/* References to section boundaries */
extern const void __nosave_begin, __nosave_end;

static void fix_processor_context(void);

struct saved_context saved_context;

/**
 *	__save_processor_state - save CPU registers before creating a
 *		hibernation image and before restoring the memory state from it
 *	@ctxt - structure to store the registers contents in
 *
 *	NOTE: If there is a CPU register the modification of which by the
 *	boot kernel (ie. the kernel used for loading the hibernation image)
 *	might affect the operations of the restored target kernel (ie. the one
 *	saved in the hibernation image), then its contents must be saved by this
 *	function.  In other words, if kernel A is hibernated and different
 *	kernel B is used for loading the hibernation image into memory, the
 *	kernel A's __save_processor_state() function must save all registers
 *	needed by kernel A, so that it can operate correctly after the resume
 *	regardless of what kernel B does in the meantime.
 */
static void __save_processor_state(struct saved_context *ctxt)
{
	kernel_fpu_begin();

	/*
	 * descriptor tables
	 */
	store_gdt((struct desc_ptr *)&ctxt->gdt_limit);
	store_idt((struct desc_ptr *)&ctxt->idt_limit);
	store_tr(ctxt->tr);

	/* XMM0..XMM15 should be handled by kernel_fpu_begin(). */
	/*
	 * segment registers
	 */
	asm volatile ("movw %%ds, %0" : "=m" (ctxt->ds));
	asm volatile ("movw %%es, %0" : "=m" (ctxt->es));
	asm volatile ("movw %%fs, %0" : "=m" (ctxt->fs));
	asm volatile ("movw %%gs, %0" : "=m" (ctxt->gs));
	asm volatile ("movw %%ss, %0" : "=m" (ctxt->ss));

	rdmsrl(MSR_FS_BASE, ctxt->fs_base);
	rdmsrl(MSR_GS_BASE, ctxt->gs_base);
	rdmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
	mtrr_save_fixed_ranges(NULL);

	/*
	 * control registers 
	 */
	rdmsrl(MSR_EFER, ctxt->efer);
	ctxt->cr0 = read_cr0();
	ctxt->cr2 = read_cr2();
	ctxt->cr3 = read_cr3();
	ctxt->cr4 = read_cr4();
	ctxt->cr8 = read_cr8();
}

void save_processor_state(void)
{
	__save_processor_state(&saved_context);
}

static void do_fpu_end(void)
{
	/*
	 * Restore FPU regs if necessary
	 */
	kernel_fpu_end();
}

/**
 *	__restore_processor_state - restore the contents of CPU registers saved
 *		by __save_processor_state()
 *	@ctxt - structure to load the registers contents from
 */
static void __restore_processor_state(struct saved_context *ctxt)
{
	/*
	 * control registers
	 */
	wrmsrl(MSR_EFER, ctxt->efer);
	write_cr8(ctxt->cr8);
	write_cr4(ctxt->cr4);
	write_cr3(ctxt->cr3);
	write_cr2(ctxt->cr2);
	write_cr0(ctxt->cr0);

	/*
	 * now restore the descriptor tables to their proper values
	 * ltr is done i fix_processor_context().
	 */
	load_gdt((const struct desc_ptr *)&ctxt->gdt_limit);
	load_idt((const struct desc_ptr *)&ctxt->idt_limit);


	/*
	 * segment registers
	 */
	asm volatile ("movw %0, %%ds" :: "r" (ctxt->ds));
	asm volatile ("movw %0, %%es" :: "r" (ctxt->es));
	asm volatile ("movw %0, %%fs" :: "r" (ctxt->fs));
	load_gs_index(ctxt->gs);
	asm volatile ("movw %0, %%ss" :: "r" (ctxt->ss));

	wrmsrl(MSR_FS_BASE, ctxt->fs_base);
	wrmsrl(MSR_GS_BASE, ctxt->gs_base);
	wrmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);

	fix_processor_context();

	do_fpu_end();
	mtrr_ap_init();
}

void restore_processor_state(void)
{
	__restore_processor_state(&saved_context);
}

static void fix_processor_context(void)
{
	int cpu = smp_processor_id();
	struct tss_struct *t = &per_cpu(init_tss, cpu);

	/*
	 * This just modifies memory; should not be necessary. But... This
	 * is necessary, because 386 hardware has concept of busy TSS or some
	 * similar stupidity.
	 */
	set_tss_desc(cpu, t);

	get_cpu_gdt_table(cpu)[GDT_ENTRY_TSS].type = 9;

	syscall_init();                         /* This sets MSR_*STAR and related */
	load_TR_desc();				/* This does ltr */
	load_LDT(&current->active_mm->context);	/* This does lldt */

	/*
	 * Now maybe reload the debug registers
	 */
	if (current->thread.debugreg7){
                loaddebug(&current->thread, 0);
                loaddebug(&current->thread, 1);
                loaddebug(&current->thread, 2);
                loaddebug(&current->thread, 3);
                /* no 4 and 5 */
                loaddebug(&current->thread, 6);
                loaddebug(&current->thread, 7);
	}
}

#ifdef CONFIG_HIBERNATION
/* Defined in arch/x86_64/kernel/suspend_asm.S */
extern int restore_image(void);

/*
 * Address to jump to in the last phase of restore in order to get to the image
 * kernel's text (this value is passed in the image header).
 */
unsigned long restore_jump_address;

/*
 * Value of the cr3 register from before the hibernation (this value is passed
 * in the image header).
 */
unsigned long restore_cr3;

pgd_t *temp_level4_pgt;

void *relocated_restore_code;

static int res_phys_pud_init(pud_t *pud, unsigned long address, unsigned long end)
{
	long i, j;

	i = pud_index(address);
	pud = pud + i;
	for (; i < PTRS_PER_PUD; pud++, i++) {
		unsigned long paddr;
		pmd_t *pmd;

		paddr = address + i*PUD_SIZE;
		if (paddr >= end)
			break;

		pmd = (pmd_t *)get_safe_page(GFP_ATOMIC);
		if (!pmd)
			return -ENOMEM;
		set_pud(pud, __pud(__pa(pmd) | _KERNPG_TABLE));
		for (j = 0; j < PTRS_PER_PMD; pmd++, j++, paddr += PMD_SIZE) {
			unsigned long pe;

			if (paddr >= end)
				break;
			pe = __PAGE_KERNEL_LARGE_EXEC | paddr;
			pe &= __supported_pte_mask;
			set_pmd(pmd, __pmd(pe));
		}
	}
	return 0;
}

static int set_up_temporary_mappings(void)
{
	unsigned long start, end, next;
	int error;

	temp_level4_pgt = (pgd_t *)get_safe_page(GFP_ATOMIC);
	if (!temp_level4_pgt)
		return -ENOMEM;

	/* It is safe to reuse the original kernel mapping */
	set_pgd(temp_level4_pgt + pgd_index(__START_KERNEL_map),
		init_level4_pgt[pgd_index(__START_KERNEL_map)]);

	/* Set up the direct mapping from scratch */
	start = (unsigned long)pfn_to_kaddr(0);
	end = (unsigned long)pfn_to_kaddr(end_pfn);

	for (; start < end; start = next) {
		pud_t *pud = (pud_t *)get_safe_page(GFP_ATOMIC);
		if (!pud)
			return -ENOMEM;
		next = start + PGDIR_SIZE;
		if (next > end)
			next = end;
		if ((error = res_phys_pud_init(pud, __pa(start), __pa(next))))
			return error;
		set_pgd(temp_level4_pgt + pgd_index(start),
			mk_kernel_pgd(__pa(pud)));
	}
	return 0;
}

int swsusp_arch_resume(void)
{
	int error;

	/* We have got enough memory and from now on we cannot recover */
	if ((error = set_up_temporary_mappings()))
		return error;

	relocated_restore_code = (void *)get_safe_page(GFP_ATOMIC);
	if (!relocated_restore_code)
		return -ENOMEM;
	memcpy(relocated_restore_code, &core_restore_code,
	       &restore_registers - &core_restore_code);

	restore_image();
	return 0;
}

/*
 *	pfn_is_nosave - check if given pfn is in the 'nosave' section
 */

int pfn_is_nosave(unsigned long pfn)
{
	unsigned long nosave_begin_pfn = __pa_symbol(&__nosave_begin) >> PAGE_SHIFT;
	unsigned long nosave_end_pfn = PAGE_ALIGN(__pa_symbol(&__nosave_end)) >> PAGE_SHIFT;
	return (pfn >= nosave_begin_pfn) && (pfn < nosave_end_pfn);
}

struct restore_data_record {
	unsigned long jump_address;
	unsigned long cr3;
	unsigned long magic;
};

#define RESTORE_MAGIC	0x0123456789ABCDEFUL

/**
 *	arch_hibernation_header_save - populate the architecture specific part
 *		of a hibernation image header
 *	@addr: address to save the data at
 */
int arch_hibernation_header_save(void *addr, unsigned int max_size)
{
	struct restore_data_record *rdr = addr;

	if (max_size < sizeof(struct restore_data_record))
		return -EOVERFLOW;
	rdr->jump_address = restore_jump_address;
	rdr->cr3 = restore_cr3;
	rdr->magic = RESTORE_MAGIC;
	return 0;
}

/**
 *	arch_hibernation_header_restore - read the architecture specific data
 *		from the hibernation image header
 *	@addr: address to read the data from
 */
int arch_hibernation_header_restore(void *addr)
{
	struct restore_data_record *rdr = addr;

	restore_jump_address = rdr->jump_address;
	restore_cr3 = rdr->cr3;
	return (rdr->magic == RESTORE_MAGIC) ? 0 : -EINVAL;
}
#endif /* CONFIG_HIBERNATION */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Suspend support specific for i386.
	3	*
	4	* Distribute under GPLv2
	5	*
	6	* Copyright (c) 2002 Pavel Machek <pavel@suse.cz>
	7	* Copyright (c) 2001 Patrick Mochel <mochel@osdl.org>
	8	*/
	9
55679edb	10	#include <linux/smp.h>
1da177e4	11	#include <linux/suspend.h>
1da177e4	12	#include <asm/proto.h>
3dd08325 RW	13	#include <asm/page.h>
3dd08325 RW	14	#include <asm/pgtable.h>
3ebad590	15	#include <asm/mtrr.h>
1da177e4	16
49c3df6a VG	17	/* References to section boundaries */
	18	extern const void __nosave_begin, __nosave_end;
	19
cae45957 JB	20	static void fix_processor_context(void);
cae45957 JB	21
1da177e4 LT	22	struct saved_context saved_context;
1da177e4 LT	23
5c9c9bec RW	24	/**
	25	* __save_processor_state - save CPU registers before creating a
	26	* hibernation image and before restoring the memory state from it
	27	* @ctxt - structure to store the registers contents in
	28	*
	29	* NOTE: If there is a CPU register the modification of which by the
	30	* boot kernel (ie. the kernel used for loading the hibernation image)
	31	* might affect the operations of the restored target kernel (ie. the one
	32	* saved in the hibernation image), then its contents must be saved by this
	33	* function. In other words, if kernel A is hibernated and different
	34	* kernel B is used for loading the hibernation image into memory, the
	35	* kernel A's __save_processor_state() function must save all registers
	36	* needed by kernel A, so that it can operate correctly after the resume
	37	* regardless of what kernel B does in the meantime.
	38	*/
cae45957	39	static void __save_processor_state(struct saved_context *ctxt)
1da177e4 LT	40	{
	41	kernel_fpu_begin();
	42
	43	/*
	44	* descriptor tables
	45	*/
9d1c6e7c GOC	46	store_gdt((struct desc_ptr *)&ctxt->gdt_limit);
	47	store_idt((struct desc_ptr *)&ctxt->idt_limit);
	48	store_tr(ctxt->tr);
1da177e4 LT	49
1da177e4 LT	50	/* XMM0..XMM15 should be handled by kernel_fpu_begin(). */
1da177e4 LT	51	/*
	52	* segment registers
	53	*/
	54	asm volatile ("movw %%ds, %0" : "=m" (ctxt->ds));
	55	asm volatile ("movw %%es, %0" : "=m" (ctxt->es));
	56	asm volatile ("movw %%fs, %0" : "=m" (ctxt->fs));
	57	asm volatile ("movw %%gs, %0" : "=m" (ctxt->gs));
	58	asm volatile ("movw %%ss, %0" : "=m" (ctxt->ss));
	59
	60	rdmsrl(MSR_FS_BASE, ctxt->fs_base);
	61	rdmsrl(MSR_GS_BASE, ctxt->gs_base);
	62	rdmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
3ebad590	63	mtrr_save_fixed_ranges(NULL);
1da177e4 LT	64
	65	/*
	66	* control registers
	67	*/
3c321bce	68	rdmsrl(MSR_EFER, ctxt->efer);
f51c9452 GOC	69	ctxt->cr0 = read_cr0();
	70	ctxt->cr2 = read_cr2();
	71	ctxt->cr3 = read_cr3();
	72	ctxt->cr4 = read_cr4();
	73	ctxt->cr8 = read_cr8();
1da177e4 LT	74	}
	75
	76	void save_processor_state(void)
	77	{
	78	__save_processor_state(&saved_context);
	79	}
	80
08967f94	81	static void do_fpu_end(void)
1da177e4	82	{
08967f94 SL	83	/*
	84	* Restore FPU regs if necessary
	85	*/
	86	kernel_fpu_end();
1da177e4 LT	87	}
1da177e4 LT	88
5c9c9bec RW	89	/**
	90	* __restore_processor_state - restore the contents of CPU registers saved
	91	* by __save_processor_state()
	92	* @ctxt - structure to load the registers contents from
	93	*/
cae45957	94	static void __restore_processor_state(struct saved_context *ctxt)
1da177e4 LT	95	{
	96	/*
	97	* control registers
	98	*/
3c321bce	99	wrmsrl(MSR_EFER, ctxt->efer);
f51c9452 GOC	100	write_cr8(ctxt->cr8);
	101	write_cr4(ctxt->cr4);
	102	write_cr3(ctxt->cr3);
	103	write_cr2(ctxt->cr2);
	104	write_cr0(ctxt->cr0);
1da177e4	105
8d783b3e PM	106	/*
	107	* now restore the descriptor tables to their proper values
	108	* ltr is done i fix_processor_context().
	109	*/
9d1c6e7c GOC	110	load_gdt((const struct desc_ptr *)&ctxt->gdt_limit);
	111	load_idt((const struct desc_ptr *)&ctxt->idt_limit);
	112
8d783b3e	113
1da177e4 LT	114	/*
	115	* segment registers
	116	*/
	117	asm volatile ("movw %0, %%ds" :: "r" (ctxt->ds));
	118	asm volatile ("movw %0, %%es" :: "r" (ctxt->es));
	119	asm volatile ("movw %0, %%fs" :: "r" (ctxt->fs));
	120	load_gs_index(ctxt->gs);
	121	asm volatile ("movw %0, %%ss" :: "r" (ctxt->ss));
	122
	123	wrmsrl(MSR_FS_BASE, ctxt->fs_base);
	124	wrmsrl(MSR_GS_BASE, ctxt->gs_base);
	125	wrmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
	126
1da177e4 LT	127	fix_processor_context();
	128
	129	do_fpu_end();
3b520b23	130	mtrr_ap_init();
1da177e4 LT	131	}
	132
	133	void restore_processor_state(void)
	134	{
	135	__restore_processor_state(&saved_context);
	136	}
	137
cae45957	138	static void fix_processor_context(void)
1da177e4 LT	139	{
	140	int cpu = smp_processor_id();
	141	struct tss_struct *t = &per_cpu(init_tss, cpu);
	142
17b7a89c BP	143	/*
	144	* This just modifies memory; should not be necessary. But... This
	145	* is necessary, because 386 hardware has concept of busy TSS or some
	146	* similar stupidity.
	147	*/
	148	set_tss_desc(cpu, t);
1da177e4	149
f6dc247c	150	get_cpu_gdt_table(cpu)[GDT_ENTRY_TSS].type = 9;
1da177e4 LT	151
	152	syscall_init(); /* This sets MSR_STAR and related /
	153	load_TR_desc(); /* This does ltr */
	154	load_LDT(&current->active_mm->context); /* This does lldt */
	155
	156	/*
	157	* Now maybe reload the debug registers
	158	*/
	159	if (current->thread.debugreg7){
	160	loaddebug(&current->thread, 0);
	161	loaddebug(&current->thread, 1);
	162	loaddebug(&current->thread, 2);
	163	loaddebug(&current->thread, 3);
	164	/* no 4 and 5 */
	165	loaddebug(&current->thread, 6);
	166	loaddebug(&current->thread, 7);
	167	}
1da177e4 LT	168	}
1da177e4 LT	169
b0cb1a19	170	#ifdef CONFIG_HIBERNATION
3dd08325 RW	171	/* Defined in arch/x86_64/kernel/suspend_asm.S */
3dd08325 RW	172	extern int restore_image(void);
1da177e4	173
d158cbdf RW	174	/*
	175	* Address to jump to in the last phase of restore in order to get to the image
	176	* kernel's text (this value is passed in the image header).
	177	*/
	178	unsigned long restore_jump_address;
	179
c30bb68c RW	180	/*
	181	* Value of the cr3 register from before the hibernation (this value is passed
	182	* in the image header).
	183	*/
	184	unsigned long restore_cr3;
	185
3dd08325 RW	186	pgd_t *temp_level4_pgt;
3dd08325 RW	187
d158cbdf RW	188	void *relocated_restore_code;
d158cbdf RW	189
2c1b4a5c	190	static int res_phys_pud_init(pud_t *pud, unsigned long address, unsigned long end)
3dd08325 RW	191	{
	192	long i, j;
	193
	194	i = pud_index(address);
	195	pud = pud + i;
	196	for (; i < PTRS_PER_PUD; pud++, i++) {
	197	unsigned long paddr;
	198	pmd_t *pmd;
	199
	200	paddr = address + i*PUD_SIZE;
	201	if (paddr >= end)
	202	break;
	203
2c1b4a5c RW	204	pmd = (pmd_t *)get_safe_page(GFP_ATOMIC);
	205	if (!pmd)
	206	return -ENOMEM;
3dd08325 RW	207	set_pud(pud, __pud(__pa(pmd) \| _KERNPG_TABLE));
	208	for (j = 0; j < PTRS_PER_PMD; pmd++, j++, paddr += PMD_SIZE) {
	209	unsigned long pe;
	210
	211	if (paddr >= end)
	212	break;
d158cbdf	213	pe = __PAGE_KERNEL_LARGE_EXEC \| paddr;
3dd08325 RW	214	pe &= __supported_pte_mask;
	215	set_pmd(pmd, __pmd(pe));
	216	}
	217	}
2c1b4a5c	218	return 0;
3dd08325 RW	219	}
3dd08325 RW	220
2c1b4a5c	221	static int set_up_temporary_mappings(void)
3dd08325 RW	222	{
3dd08325 RW	223	unsigned long start, end, next;
2c1b4a5c	224	int error;
3dd08325	225
2c1b4a5c RW	226	temp_level4_pgt = (pgd_t *)get_safe_page(GFP_ATOMIC);
	227	if (!temp_level4_pgt)
	228	return -ENOMEM;
3dd08325	229
5867a78f AM	230	/* It is safe to reuse the original kernel mapping */
	231	set_pgd(temp_level4_pgt + pgd_index(__START_KERNEL_map),
	232	init_level4_pgt[pgd_index(__START_KERNEL_map)]);
	233
3dd08325 RW	234	/* Set up the direct mapping from scratch */
	235	start = (unsigned long)pfn_to_kaddr(0);
	236	end = (unsigned long)pfn_to_kaddr(end_pfn);
	237
	238	for (; start < end; start = next) {
5867a78f	239	pud_t pud = (pud_t )get_safe_page(GFP_ATOMIC);
2c1b4a5c RW	240	if (!pud)
2c1b4a5c RW	241	return -ENOMEM;
3dd08325 RW	242	next = start + PGDIR_SIZE;
	243	if (next > end)
	244	next = end;
2c1b4a5c RW	245	if ((error = res_phys_pud_init(pud, __pa(start), __pa(next))))
2c1b4a5c RW	246	return error;
3dd08325 RW	247	set_pgd(temp_level4_pgt + pgd_index(start),
	248	mk_kernel_pgd(__pa(pud)));
	249	}
5867a78f	250	return 0;
3dd08325 RW	251	}
	252
	253	int swsusp_arch_resume(void)
	254	{
2c1b4a5c	255	int error;
3dd08325	256
3dd08325	257	/* We have got enough memory and from now on we cannot recover */
2c1b4a5c RW	258	if ((error = set_up_temporary_mappings()))
2c1b4a5c RW	259	return error;
d158cbdf RW	260
	261	relocated_restore_code = (void *)get_safe_page(GFP_ATOMIC);
	262	if (!relocated_restore_code)
	263	return -ENOMEM;
	264	memcpy(relocated_restore_code, &core_restore_code,
	265	&restore_registers - &core_restore_code);
	266
3dd08325 RW	267	restore_image();
	268	return 0;
	269	}
49c3df6a VG	270
	271	/*
	272	* pfn_is_nosave - check if given pfn is in the 'nosave' section
	273	*/
	274
	275	int pfn_is_nosave(unsigned long pfn)
	276	{
	277	unsigned long nosave_begin_pfn = __pa_symbol(&__nosave_begin) >> PAGE_SHIFT;
	278	unsigned long nosave_end_pfn = PAGE_ALIGN(__pa_symbol(&__nosave_end)) >> PAGE_SHIFT;
	279	return (pfn >= nosave_begin_pfn) && (pfn < nosave_end_pfn);
	280	}
d158cbdf RW	281
	282	struct restore_data_record {
	283	unsigned long jump_address;
c30bb68c RW	284	unsigned long cr3;
c30bb68c RW	285	unsigned long magic;
d158cbdf RW	286	};
	287
	288	#define RESTORE_MAGIC 0x0123456789ABCDEFUL
	289
	290	/**
	291	* arch_hibernation_header_save - populate the architecture specific part
	292	* of a hibernation image header
	293	* @addr: address to save the data at
	294	*/
	295	int arch_hibernation_header_save(void *addr, unsigned int max_size)
	296	{
	297	struct restore_data_record *rdr = addr;
	298
	299	if (max_size < sizeof(struct restore_data_record))
	300	return -EOVERFLOW;
	301	rdr->jump_address = restore_jump_address;
c30bb68c RW	302	rdr->cr3 = restore_cr3;
c30bb68c RW	303	rdr->magic = RESTORE_MAGIC;
d158cbdf RW	304	return 0;
	305	}
	306
	307	/**
	308	* arch_hibernation_header_restore - read the architecture specific data
	309	* from the hibernation image header
	310	* @addr: address to read the data from
	311	*/
	312	int arch_hibernation_header_restore(void *addr)
	313	{
	314	struct restore_data_record *rdr = addr;
	315
	316	restore_jump_address = rdr->jump_address;
c30bb68c RW	317	restore_cr3 = rdr->cr3;
c30bb68c RW	318	return (rdr->magic == RESTORE_MAGIC) ? 0 : -EINVAL;
d158cbdf	319	}
b0cb1a19	320	#endif /* CONFIG_HIBERNATION */