Commit | Line | Data |
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1da177e4 | 1 | /* |
835c34a1 | 2 | * IBM Summit-Specific Code |
1da177e4 LT |
3 | * |
4 | * Written By: Matthew Dobson, IBM Corporation | |
5 | * | |
6 | * Copyright (c) 2003 IBM Corp. | |
7 | * | |
8 | * All rights reserved. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or (at | |
13 | * your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, but | |
16 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
18 | * NON INFRINGEMENT. See the GNU General Public License for more | |
19 | * details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | * | |
25 | * Send feedback to <colpatch@us.ibm.com> | |
26 | * | |
27 | */ | |
28 | ||
29 | #include <linux/mm.h> | |
30 | #include <linux/init.h> | |
31 | #include <asm/io.h> | |
356fa0c6 | 32 | #include <asm/bios_ebda.h> |
b11b867f IM |
33 | |
34 | /* | |
35 | * APIC driver for the IBM "Summit" chipset. | |
36 | */ | |
37 | #define APIC_DEFINITION 1 | |
38 | #include <linux/threads.h> | |
39 | #include <linux/cpumask.h> | |
40 | #include <asm/mpspec.h> | |
41 | #include <asm/apic.h> | |
42 | #include <asm/smp.h> | |
43 | #include <asm/genapic.h> | |
44 | #include <asm/fixmap.h> | |
45 | #include <asm/apicdef.h> | |
43f39890 | 46 | #include <asm/ipi.h> |
b11b867f IM |
47 | #include <linux/kernel.h> |
48 | #include <linux/string.h> | |
49 | #include <linux/init.h> | |
50 | #include <linux/gfp.h> | |
51 | #include <linux/smp.h> | |
52 | ||
53 | static inline unsigned summit_get_apic_id(unsigned long x) | |
54 | { | |
55 | return (x >> 24) & 0xFF; | |
56 | } | |
57 | ||
b11b867f IM |
58 | static inline void summit_send_IPI_mask(const cpumask_t *mask, int vector) |
59 | { | |
43f39890 | 60 | default_send_IPI_mask_sequence_logical(mask, vector); |
b11b867f IM |
61 | } |
62 | ||
63 | static inline void summit_send_IPI_allbutself(int vector) | |
64 | { | |
65 | cpumask_t mask = cpu_online_map; | |
66 | cpu_clear(smp_processor_id(), mask); | |
67 | ||
68 | if (!cpus_empty(mask)) | |
69 | summit_send_IPI_mask(&mask, vector); | |
70 | } | |
71 | ||
72 | static inline void summit_send_IPI_all(int vector) | |
73 | { | |
74 | summit_send_IPI_mask(&cpu_online_map, vector); | |
75 | } | |
76 | ||
77 | #include <asm/tsc.h> | |
78 | ||
79 | extern int use_cyclone; | |
80 | ||
81 | #ifdef CONFIG_X86_SUMMIT_NUMA | |
82 | extern void setup_summit(void); | |
83 | #else | |
84 | #define setup_summit() {} | |
85 | #endif | |
86 | ||
87 | static inline int | |
88 | summit_mps_oem_check(struct mpc_table *mpc, char *oem, char *productid) | |
89 | { | |
90 | if (!strncmp(oem, "IBM ENSW", 8) && | |
91 | (!strncmp(productid, "VIGIL SMP", 9) | |
92 | || !strncmp(productid, "EXA", 3) | |
93 | || !strncmp(productid, "RUTHLESS SMP", 12))){ | |
94 | mark_tsc_unstable("Summit based system"); | |
95 | use_cyclone = 1; /*enable cyclone-timer*/ | |
96 | setup_summit(); | |
97 | return 1; | |
98 | } | |
99 | return 0; | |
100 | } | |
101 | ||
102 | /* Hook from generic ACPI tables.c */ | |
103 | static inline int summit_acpi_madt_oem_check(char *oem_id, char *oem_table_id) | |
104 | { | |
105 | if (!strncmp(oem_id, "IBM", 3) && | |
106 | (!strncmp(oem_table_id, "SERVIGIL", 8) | |
107 | || !strncmp(oem_table_id, "EXA", 3))){ | |
108 | mark_tsc_unstable("Summit based system"); | |
109 | use_cyclone = 1; /*enable cyclone-timer*/ | |
110 | setup_summit(); | |
111 | return 1; | |
112 | } | |
113 | return 0; | |
114 | } | |
115 | ||
116 | struct rio_table_hdr { | |
117 | unsigned char version; /* Version number of this data structure */ | |
118 | /* Version 3 adds chassis_num & WP_index */ | |
119 | unsigned char num_scal_dev; /* # of Scalability devices (Twisters for Vigil) */ | |
120 | unsigned char num_rio_dev; /* # of RIO I/O devices (Cyclones and Winnipegs) */ | |
121 | } __attribute__((packed)); | |
122 | ||
123 | struct scal_detail { | |
124 | unsigned char node_id; /* Scalability Node ID */ | |
125 | unsigned long CBAR; /* Address of 1MB register space */ | |
126 | unsigned char port0node; /* Node ID port connected to: 0xFF=None */ | |
127 | unsigned char port0port; /* Port num port connected to: 0,1,2, or 0xFF=None */ | |
128 | unsigned char port1node; /* Node ID port connected to: 0xFF = None */ | |
129 | unsigned char port1port; /* Port num port connected to: 0,1,2, or 0xFF=None */ | |
130 | unsigned char port2node; /* Node ID port connected to: 0xFF = None */ | |
131 | unsigned char port2port; /* Port num port connected to: 0,1,2, or 0xFF=None */ | |
132 | unsigned char chassis_num; /* 1 based Chassis number (1 = boot node) */ | |
133 | } __attribute__((packed)); | |
134 | ||
135 | struct rio_detail { | |
136 | unsigned char node_id; /* RIO Node ID */ | |
137 | unsigned long BBAR; /* Address of 1MB register space */ | |
138 | unsigned char type; /* Type of device */ | |
139 | unsigned char owner_id; /* For WPEG: Node ID of Cyclone that owns this WPEG*/ | |
140 | /* For CYC: Node ID of Twister that owns this CYC */ | |
141 | unsigned char port0node; /* Node ID port connected to: 0xFF=None */ | |
142 | unsigned char port0port; /* Port num port connected to: 0,1,2, or 0xFF=None */ | |
143 | unsigned char port1node; /* Node ID port connected to: 0xFF=None */ | |
144 | unsigned char port1port; /* Port num port connected to: 0,1,2, or 0xFF=None */ | |
145 | unsigned char first_slot; /* For WPEG: Lowest slot number below this WPEG */ | |
146 | /* For CYC: 0 */ | |
147 | unsigned char status; /* For WPEG: Bit 0 = 1 : the XAPIC is used */ | |
148 | /* = 0 : the XAPIC is not used, ie:*/ | |
149 | /* ints fwded to another XAPIC */ | |
150 | /* Bits1:7 Reserved */ | |
151 | /* For CYC: Bits0:7 Reserved */ | |
152 | unsigned char WP_index; /* For WPEG: WPEG instance index - lower ones have */ | |
153 | /* lower slot numbers/PCI bus numbers */ | |
154 | /* For CYC: No meaning */ | |
155 | unsigned char chassis_num; /* 1 based Chassis number */ | |
156 | /* For LookOut WPEGs this field indicates the */ | |
157 | /* Expansion Chassis #, enumerated from Boot */ | |
158 | /* Node WPEG external port, then Boot Node CYC */ | |
159 | /* external port, then Next Vigil chassis WPEG */ | |
160 | /* external port, etc. */ | |
161 | /* Shared Lookouts have only 1 chassis number (the */ | |
162 | /* first one assigned) */ | |
163 | } __attribute__((packed)); | |
164 | ||
165 | ||
166 | typedef enum { | |
167 | CompatTwister = 0, /* Compatibility Twister */ | |
168 | AltTwister = 1, /* Alternate Twister of internal 8-way */ | |
169 | CompatCyclone = 2, /* Compatibility Cyclone */ | |
170 | AltCyclone = 3, /* Alternate Cyclone of internal 8-way */ | |
171 | CompatWPEG = 4, /* Compatibility WPEG */ | |
172 | AltWPEG = 5, /* Second Planar WPEG */ | |
173 | LookOutAWPEG = 6, /* LookOut WPEG */ | |
174 | LookOutBWPEG = 7, /* LookOut WPEG */ | |
175 | } node_type; | |
176 | ||
177 | static inline int is_WPEG(struct rio_detail *rio){ | |
178 | return (rio->type == CompatWPEG || rio->type == AltWPEG || | |
179 | rio->type == LookOutAWPEG || rio->type == LookOutBWPEG); | |
180 | } | |
181 | ||
182 | ||
183 | /* In clustered mode, the high nibble of APIC ID is a cluster number. | |
184 | * The low nibble is a 4-bit bitmap. */ | |
185 | #define XAPIC_DEST_CPUS_SHIFT 4 | |
186 | #define XAPIC_DEST_CPUS_MASK ((1u << XAPIC_DEST_CPUS_SHIFT) - 1) | |
187 | #define XAPIC_DEST_CLUSTER_MASK (XAPIC_DEST_CPUS_MASK << XAPIC_DEST_CPUS_SHIFT) | |
188 | ||
189 | #define SUMMIT_APIC_DFR_VALUE (APIC_DFR_CLUSTER) | |
190 | ||
191 | static inline const cpumask_t *summit_target_cpus(void) | |
192 | { | |
193 | /* CPU_MASK_ALL (0xff) has undefined behaviour with | |
194 | * dest_LowestPrio mode logical clustered apic interrupt routing | |
195 | * Just start on cpu 0. IRQ balancing will spread load | |
196 | */ | |
197 | return &cpumask_of_cpu(0); | |
198 | } | |
199 | ||
200 | static inline unsigned long | |
201 | summit_check_apicid_used(physid_mask_t bitmap, int apicid) | |
202 | { | |
203 | return 0; | |
204 | } | |
205 | ||
206 | /* we don't use the phys_cpu_present_map to indicate apicid presence */ | |
207 | static inline unsigned long summit_check_apicid_present(int bit) | |
208 | { | |
209 | return 1; | |
210 | } | |
211 | ||
212 | #define apicid_cluster(apicid) ((apicid) & XAPIC_DEST_CLUSTER_MASK) | |
213 | ||
214 | extern u8 cpu_2_logical_apicid[]; | |
215 | ||
216 | static inline void summit_init_apic_ldr(void) | |
217 | { | |
218 | unsigned long val, id; | |
219 | int count = 0; | |
220 | u8 my_id = (u8)hard_smp_processor_id(); | |
221 | u8 my_cluster = (u8)apicid_cluster(my_id); | |
222 | #ifdef CONFIG_SMP | |
223 | u8 lid; | |
224 | int i; | |
225 | ||
226 | /* Create logical APIC IDs by counting CPUs already in cluster. */ | |
227 | for (count = 0, i = nr_cpu_ids; --i >= 0; ) { | |
228 | lid = cpu_2_logical_apicid[i]; | |
229 | if (lid != BAD_APICID && apicid_cluster(lid) == my_cluster) | |
230 | ++count; | |
231 | } | |
232 | #endif | |
233 | /* We only have a 4 wide bitmap in cluster mode. If a deranged | |
234 | * BIOS puts 5 CPUs in one APIC cluster, we're hosed. */ | |
235 | BUG_ON(count >= XAPIC_DEST_CPUS_SHIFT); | |
236 | id = my_cluster | (1UL << count); | |
237 | apic_write(APIC_DFR, SUMMIT_APIC_DFR_VALUE); | |
238 | val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; | |
239 | val |= SET_APIC_LOGICAL_ID(id); | |
240 | apic_write(APIC_LDR, val); | |
241 | } | |
242 | ||
243 | static inline int summit_apic_id_registered(void) | |
244 | { | |
245 | return 1; | |
246 | } | |
247 | ||
248 | static inline void summit_setup_apic_routing(void) | |
249 | { | |
250 | printk("Enabling APIC mode: Summit. Using %d I/O APICs\n", | |
251 | nr_ioapics); | |
252 | } | |
253 | ||
254 | static inline int summit_apicid_to_node(int logical_apicid) | |
255 | { | |
256 | #ifdef CONFIG_SMP | |
257 | return apicid_2_node[hard_smp_processor_id()]; | |
258 | #else | |
259 | return 0; | |
260 | #endif | |
261 | } | |
262 | ||
263 | /* Mapping from cpu number to logical apicid */ | |
264 | static inline int summit_cpu_to_logical_apicid(int cpu) | |
265 | { | |
266 | #ifdef CONFIG_SMP | |
267 | if (cpu >= nr_cpu_ids) | |
268 | return BAD_APICID; | |
269 | return (int)cpu_2_logical_apicid[cpu]; | |
270 | #else | |
271 | return logical_smp_processor_id(); | |
272 | #endif | |
273 | } | |
274 | ||
275 | static inline int summit_cpu_present_to_apicid(int mps_cpu) | |
276 | { | |
277 | if (mps_cpu < nr_cpu_ids) | |
278 | return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu); | |
279 | else | |
280 | return BAD_APICID; | |
281 | } | |
282 | ||
283 | static inline physid_mask_t | |
284 | summit_ioapic_phys_id_map(physid_mask_t phys_id_map) | |
285 | { | |
286 | /* For clustered we don't have a good way to do this yet - hack */ | |
287 | return physids_promote(0x0F); | |
288 | } | |
289 | ||
290 | static inline physid_mask_t summit_apicid_to_cpu_present(int apicid) | |
291 | { | |
292 | return physid_mask_of_physid(0); | |
293 | } | |
294 | ||
295 | static inline void summit_setup_portio_remap(void) | |
296 | { | |
297 | } | |
298 | ||
299 | static inline int summit_check_phys_apicid_present(int boot_cpu_physical_apicid) | |
300 | { | |
301 | return 1; | |
302 | } | |
303 | ||
304 | static inline unsigned int summit_cpu_mask_to_apicid(const cpumask_t *cpumask) | |
305 | { | |
306 | int cpus_found = 0; | |
307 | int num_bits_set; | |
308 | int apicid; | |
309 | int cpu; | |
310 | ||
311 | num_bits_set = cpus_weight(*cpumask); | |
312 | /* Return id to all */ | |
313 | if (num_bits_set >= nr_cpu_ids) | |
314 | return 0xFF; | |
315 | /* | |
316 | * The cpus in the mask must all be on the apic cluster. If are not | |
317 | * on the same apicid cluster return default value of target_cpus(): | |
318 | */ | |
319 | cpu = first_cpu(*cpumask); | |
320 | apicid = summit_cpu_to_logical_apicid(cpu); | |
321 | ||
322 | while (cpus_found < num_bits_set) { | |
323 | if (cpu_isset(cpu, *cpumask)) { | |
324 | int new_apicid = summit_cpu_to_logical_apicid(cpu); | |
325 | ||
326 | if (apicid_cluster(apicid) != | |
327 | apicid_cluster(new_apicid)) { | |
328 | printk ("%s: Not a valid mask!\n", __func__); | |
329 | ||
330 | return 0xFF; | |
331 | } | |
332 | apicid = apicid | new_apicid; | |
333 | cpus_found++; | |
334 | } | |
335 | cpu++; | |
336 | } | |
337 | return apicid; | |
338 | } | |
339 | ||
340 | static inline unsigned int | |
341 | summit_cpu_mask_to_apicid_and(const struct cpumask *inmask, | |
342 | const struct cpumask *andmask) | |
343 | { | |
344 | int apicid = summit_cpu_to_logical_apicid(0); | |
345 | cpumask_var_t cpumask; | |
346 | ||
347 | if (!alloc_cpumask_var(&cpumask, GFP_ATOMIC)) | |
348 | return apicid; | |
349 | ||
350 | cpumask_and(cpumask, inmask, andmask); | |
351 | cpumask_and(cpumask, cpumask, cpu_online_mask); | |
352 | apicid = summit_cpu_mask_to_apicid(cpumask); | |
353 | ||
354 | free_cpumask_var(cpumask); | |
355 | ||
356 | return apicid; | |
357 | } | |
358 | ||
359 | /* | |
360 | * cpuid returns the value latched in the HW at reset, not the APIC ID | |
361 | * register's value. For any box whose BIOS changes APIC IDs, like | |
362 | * clustered APIC systems, we must use hard_smp_processor_id. | |
363 | * | |
364 | * See Intel's IA-32 SW Dev's Manual Vol2 under CPUID. | |
365 | */ | |
366 | static inline int summit_phys_pkg_id(int cpuid_apic, int index_msb) | |
367 | { | |
368 | return hard_smp_processor_id() >> index_msb; | |
369 | } | |
370 | ||
371 | static int probe_summit(void) | |
372 | { | |
373 | /* probed later in mptable/ACPI hooks */ | |
374 | return 0; | |
375 | } | |
376 | ||
377 | static void summit_vector_allocation_domain(int cpu, cpumask_t *retmask) | |
378 | { | |
379 | /* Careful. Some cpus do not strictly honor the set of cpus | |
380 | * specified in the interrupt destination when using lowest | |
381 | * priority interrupt delivery mode. | |
382 | * | |
383 | * In particular there was a hyperthreading cpu observed to | |
384 | * deliver interrupts to the wrong hyperthread when only one | |
385 | * hyperthread was specified in the interrupt desitination. | |
386 | */ | |
387 | *retmask = (cpumask_t){ { [0] = APIC_ALL_CPUS, } }; | |
388 | } | |
1da177e4 | 389 | |
7c20dcc5 | 390 | #ifdef CONFIG_X86_SUMMIT_NUMA |
1da177e4 LT |
391 | static struct rio_table_hdr *rio_table_hdr __initdata; |
392 | static struct scal_detail *scal_devs[MAX_NUMNODES] __initdata; | |
393 | static struct rio_detail *rio_devs[MAX_NUMNODES*4] __initdata; | |
394 | ||
d49c4288 | 395 | #ifndef CONFIG_X86_NUMAQ |
037cab07 | 396 | static int mp_bus_id_to_node[MAX_MP_BUSSES] __initdata; |
d49c4288 | 397 | #endif |
037cab07 | 398 | |
1da177e4 LT |
399 | static int __init setup_pci_node_map_for_wpeg(int wpeg_num, int last_bus) |
400 | { | |
401 | int twister = 0, node = 0; | |
402 | int i, bus, num_buses; | |
403 | ||
60e11746 PC |
404 | for (i = 0; i < rio_table_hdr->num_rio_dev; i++) { |
405 | if (rio_devs[i]->node_id == rio_devs[wpeg_num]->owner_id) { | |
1da177e4 LT |
406 | twister = rio_devs[i]->owner_id; |
407 | break; | |
408 | } | |
409 | } | |
60e11746 | 410 | if (i == rio_table_hdr->num_rio_dev) { |
77bf90ed | 411 | printk(KERN_ERR "%s: Couldn't find owner Cyclone for Winnipeg!\n", __func__); |
1da177e4 LT |
412 | return last_bus; |
413 | } | |
414 | ||
60e11746 PC |
415 | for (i = 0; i < rio_table_hdr->num_scal_dev; i++) { |
416 | if (scal_devs[i]->node_id == twister) { | |
1da177e4 LT |
417 | node = scal_devs[i]->node_id; |
418 | break; | |
419 | } | |
420 | } | |
60e11746 | 421 | if (i == rio_table_hdr->num_scal_dev) { |
77bf90ed | 422 | printk(KERN_ERR "%s: Couldn't find owner Twister for Cyclone!\n", __func__); |
1da177e4 LT |
423 | return last_bus; |
424 | } | |
425 | ||
60e11746 | 426 | switch (rio_devs[wpeg_num]->type) { |
1da177e4 | 427 | case CompatWPEG: |
60e11746 PC |
428 | /* |
429 | * The Compatibility Winnipeg controls the 2 legacy buses, | |
1da177e4 LT |
430 | * the 66MHz PCI bus [2 slots] and the 2 "extra" buses in case |
431 | * a PCI-PCI bridge card is used in either slot: total 5 buses. | |
432 | */ | |
433 | num_buses = 5; | |
434 | break; | |
435 | case AltWPEG: | |
60e11746 PC |
436 | /* |
437 | * The Alternate Winnipeg controls the 2 133MHz buses [1 slot | |
1da177e4 LT |
438 | * each], their 2 "extra" buses, the 100MHz bus [2 slots] and |
439 | * the "extra" buses for each of those slots: total 7 buses. | |
440 | */ | |
441 | num_buses = 7; | |
442 | break; | |
443 | case LookOutAWPEG: | |
444 | case LookOutBWPEG: | |
60e11746 PC |
445 | /* |
446 | * A Lookout Winnipeg controls 3 100MHz buses [2 slots each] | |
1da177e4 LT |
447 | * & the "extra" buses for each of those slots: total 9 buses. |
448 | */ | |
449 | num_buses = 9; | |
450 | break; | |
451 | default: | |
77bf90ed | 452 | printk(KERN_INFO "%s: Unsupported Winnipeg type!\n", __func__); |
1da177e4 LT |
453 | return last_bus; |
454 | } | |
455 | ||
60e11746 | 456 | for (bus = last_bus; bus < last_bus + num_buses; bus++) |
1da177e4 LT |
457 | mp_bus_id_to_node[bus] = node; |
458 | return bus; | |
459 | } | |
460 | ||
461 | static int __init build_detail_arrays(void) | |
462 | { | |
463 | unsigned long ptr; | |
464 | int i, scal_detail_size, rio_detail_size; | |
465 | ||
60e11746 | 466 | if (rio_table_hdr->num_scal_dev > MAX_NUMNODES) { |
77bf90ed | 467 | printk(KERN_WARNING "%s: MAX_NUMNODES too low! Defined as %d, but system has %d nodes.\n", __func__, MAX_NUMNODES, rio_table_hdr->num_scal_dev); |
1da177e4 LT |
468 | return 0; |
469 | } | |
470 | ||
60e11746 | 471 | switch (rio_table_hdr->version) { |
1da177e4 | 472 | default: |
77bf90ed | 473 | printk(KERN_WARNING "%s: Invalid Rio Grande Table Version: %d\n", __func__, rio_table_hdr->version); |
1da177e4 LT |
474 | return 0; |
475 | case 2: | |
476 | scal_detail_size = 11; | |
477 | rio_detail_size = 13; | |
478 | break; | |
479 | case 3: | |
480 | scal_detail_size = 12; | |
481 | rio_detail_size = 15; | |
482 | break; | |
483 | } | |
484 | ||
485 | ptr = (unsigned long)rio_table_hdr + 3; | |
60e11746 | 486 | for (i = 0; i < rio_table_hdr->num_scal_dev; i++, ptr += scal_detail_size) |
1da177e4 LT |
487 | scal_devs[i] = (struct scal_detail *)ptr; |
488 | ||
60e11746 | 489 | for (i = 0; i < rio_table_hdr->num_rio_dev; i++, ptr += rio_detail_size) |
1da177e4 LT |
490 | rio_devs[i] = (struct rio_detail *)ptr; |
491 | ||
492 | return 1; | |
493 | } | |
494 | ||
495 | void __init setup_summit(void) | |
496 | { | |
497 | unsigned long ptr; | |
498 | unsigned short offset; | |
499 | int i, next_wpeg, next_bus = 0; | |
500 | ||
501 | /* The pointer to the EBDA is stored in the word @ phys 0x40E(40:0E) */ | |
356fa0c6 AM |
502 | ptr = get_bios_ebda(); |
503 | ptr = (unsigned long)phys_to_virt(ptr); | |
1da177e4 LT |
504 | |
505 | rio_table_hdr = NULL; | |
506 | offset = 0x180; | |
60e11746 | 507 | while (offset) { |
1da177e4 | 508 | /* The block id is stored in the 2nd word */ |
60e11746 | 509 | if (*((unsigned short *)(ptr + offset + 2)) == 0x4752) { |
1da177e4 LT |
510 | /* set the pointer past the offset & block id */ |
511 | rio_table_hdr = (struct rio_table_hdr *)(ptr + offset + 4); | |
512 | break; | |
513 | } | |
514 | /* The next offset is stored in the 1st word. 0 means no more */ | |
515 | offset = *((unsigned short *)(ptr + offset)); | |
516 | } | |
60e11746 | 517 | if (!rio_table_hdr) { |
77bf90ed | 518 | printk(KERN_ERR "%s: Unable to locate Rio Grande Table in EBDA - bailing!\n", __func__); |
1da177e4 LT |
519 | return; |
520 | } | |
521 | ||
522 | if (!build_detail_arrays()) | |
523 | return; | |
524 | ||
525 | /* The first Winnipeg we're looking for has an index of 0 */ | |
526 | next_wpeg = 0; | |
527 | do { | |
60e11746 PC |
528 | for (i = 0; i < rio_table_hdr->num_rio_dev; i++) { |
529 | if (is_WPEG(rio_devs[i]) && rio_devs[i]->WP_index == next_wpeg) { | |
1da177e4 LT |
530 | /* It's the Winnipeg we're looking for! */ |
531 | next_bus = setup_pci_node_map_for_wpeg(i, next_bus); | |
532 | next_wpeg++; | |
533 | break; | |
534 | } | |
535 | } | |
536 | /* | |
537 | * If we go through all Rio devices and don't find one with | |
538 | * the next index, it means we've found all the Winnipegs, | |
539 | * and thus all the PCI buses. | |
540 | */ | |
541 | if (i == rio_table_hdr->num_rio_dev) | |
542 | next_wpeg = 0; | |
543 | } while (next_wpeg != 0); | |
544 | } | |
7c20dcc5 | 545 | #endif |
b11b867f IM |
546 | |
547 | struct genapic apic_summit = { | |
548 | ||
549 | .name = "summit", | |
550 | .probe = probe_summit, | |
551 | .acpi_madt_oem_check = summit_acpi_madt_oem_check, | |
552 | .apic_id_registered = summit_apic_id_registered, | |
553 | ||
554 | .irq_delivery_mode = dest_LowestPrio, | |
555 | /* logical delivery broadcast to all CPUs: */ | |
556 | .irq_dest_mode = 1, | |
557 | ||
558 | .target_cpus = summit_target_cpus, | |
559 | .disable_esr = 1, | |
560 | .dest_logical = APIC_DEST_LOGICAL, | |
561 | .check_apicid_used = summit_check_apicid_used, | |
562 | .check_apicid_present = summit_check_apicid_present, | |
563 | ||
564 | .vector_allocation_domain = summit_vector_allocation_domain, | |
565 | .init_apic_ldr = summit_init_apic_ldr, | |
566 | ||
567 | .ioapic_phys_id_map = summit_ioapic_phys_id_map, | |
568 | .setup_apic_routing = summit_setup_apic_routing, | |
569 | .multi_timer_check = NULL, | |
570 | .apicid_to_node = summit_apicid_to_node, | |
571 | .cpu_to_logical_apicid = summit_cpu_to_logical_apicid, | |
572 | .cpu_present_to_apicid = summit_cpu_present_to_apicid, | |
573 | .apicid_to_cpu_present = summit_apicid_to_cpu_present, | |
574 | .setup_portio_remap = NULL, | |
575 | .check_phys_apicid_present = summit_check_phys_apicid_present, | |
576 | .enable_apic_mode = NULL, | |
577 | .phys_pkg_id = summit_phys_pkg_id, | |
578 | .mps_oem_check = summit_mps_oem_check, | |
579 | ||
580 | .get_apic_id = summit_get_apic_id, | |
581 | .set_apic_id = NULL, | |
582 | .apic_id_mask = 0xFF << 24, | |
583 | ||
584 | .cpu_mask_to_apicid = summit_cpu_mask_to_apicid, | |
585 | .cpu_mask_to_apicid_and = summit_cpu_mask_to_apicid_and, | |
586 | ||
587 | .send_IPI_mask = summit_send_IPI_mask, | |
588 | .send_IPI_mask_allbutself = NULL, | |
589 | .send_IPI_allbutself = summit_send_IPI_allbutself, | |
590 | .send_IPI_all = summit_send_IPI_all, | |
6b64ee02 | 591 | .send_IPI_self = default_send_IPI_self, |
b11b867f IM |
592 | |
593 | .wakeup_cpu = NULL, | |
594 | .trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW, | |
595 | .trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH, | |
596 | ||
597 | .wait_for_init_deassert = default_wait_for_init_deassert, | |
598 | ||
599 | .smp_callin_clear_local_apic = NULL, | |
600 | .store_NMI_vector = NULL, | |
601 | .inquire_remote_apic = default_inquire_remote_apic, | |
c1eeb2de YL |
602 | |
603 | .read = native_apic_mem_read, | |
604 | .write = native_apic_mem_write, | |
605 | .icr_read = native_apic_icr_read, | |
606 | .icr_write = native_apic_icr_write, | |
607 | .wait_icr_idle = native_apic_wait_icr_idle, | |
608 | .safe_wait_icr_idle = native_safe_apic_wait_icr_idle, | |
b11b867f | 609 | }; |