Commit | Line | Data |
---|---|---|
4cedb334 GOC |
1 | /* |
2 | * x86 SMP booting functions | |
3 | * | |
87c6fe26 | 4 | * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> |
4cedb334 GOC |
5 | * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com> |
6 | * Copyright 2001 Andi Kleen, SuSE Labs. | |
7 | * | |
8 | * Much of the core SMP work is based on previous work by Thomas Radke, to | |
9 | * whom a great many thanks are extended. | |
10 | * | |
11 | * Thanks to Intel for making available several different Pentium, | |
12 | * Pentium Pro and Pentium-II/Xeon MP machines. | |
13 | * Original development of Linux SMP code supported by Caldera. | |
14 | * | |
15 | * This code is released under the GNU General Public License version 2 or | |
16 | * later. | |
17 | * | |
18 | * Fixes | |
19 | * Felix Koop : NR_CPUS used properly | |
20 | * Jose Renau : Handle single CPU case. | |
21 | * Alan Cox : By repeated request 8) - Total BogoMIPS report. | |
22 | * Greg Wright : Fix for kernel stacks panic. | |
23 | * Erich Boleyn : MP v1.4 and additional changes. | |
24 | * Matthias Sattler : Changes for 2.1 kernel map. | |
25 | * Michel Lespinasse : Changes for 2.1 kernel map. | |
26 | * Michael Chastain : Change trampoline.S to gnu as. | |
27 | * Alan Cox : Dumb bug: 'B' step PPro's are fine | |
28 | * Ingo Molnar : Added APIC timers, based on code | |
29 | * from Jose Renau | |
30 | * Ingo Molnar : various cleanups and rewrites | |
31 | * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. | |
32 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs | |
33 | * Andi Kleen : Changed for SMP boot into long mode. | |
34 | * Martin J. Bligh : Added support for multi-quad systems | |
35 | * Dave Jones : Report invalid combinations of Athlon CPUs. | |
36 | * Rusty Russell : Hacked into shape for new "hotplug" boot process. | |
37 | * Andi Kleen : Converted to new state machine. | |
38 | * Ashok Raj : CPU hotplug support | |
39 | * Glauber Costa : i386 and x86_64 integration | |
40 | */ | |
41 | ||
68a1c3f8 GC |
42 | #include <linux/init.h> |
43 | #include <linux/smp.h> | |
a355352b | 44 | #include <linux/module.h> |
70708a18 | 45 | #include <linux/sched.h> |
69c18c15 | 46 | #include <linux/percpu.h> |
91718e8d | 47 | #include <linux/bootmem.h> |
cb3c8b90 GOC |
48 | #include <linux/err.h> |
49 | #include <linux/nmi.h> | |
69c18c15 | 50 | |
8aef135c | 51 | #include <asm/acpi.h> |
cb3c8b90 | 52 | #include <asm/desc.h> |
69c18c15 GC |
53 | #include <asm/nmi.h> |
54 | #include <asm/irq.h> | |
07bbc16a | 55 | #include <asm/idle.h> |
e44b7b75 | 56 | #include <asm/trampoline.h> |
69c18c15 GC |
57 | #include <asm/cpu.h> |
58 | #include <asm/numa.h> | |
cb3c8b90 GOC |
59 | #include <asm/pgtable.h> |
60 | #include <asm/tlbflush.h> | |
61 | #include <asm/mtrr.h> | |
bbc2ff6a | 62 | #include <asm/vmi.h> |
34d05591 | 63 | #include <asm/genapic.h> |
569712b2 | 64 | #include <asm/setup.h> |
bdbcdd48 | 65 | #include <asm/uv/uv.h> |
cb3c8b90 | 66 | #include <linux/mc146818rtc.h> |
68a1c3f8 | 67 | |
f6bc4029 | 68 | #include <mach_apic.h> |
cb3c8b90 GOC |
69 | #include <mach_wakecpu.h> |
70 | #include <smpboot_hooks.h> | |
71 | ||
16ecf7a4 | 72 | #ifdef CONFIG_X86_32 |
4cedb334 | 73 | u8 apicid_2_node[MAX_APICID]; |
61165d7a | 74 | static int low_mappings; |
acbb6734 GOC |
75 | #endif |
76 | ||
a8db8453 GOC |
77 | /* State of each CPU */ |
78 | DEFINE_PER_CPU(int, cpu_state) = { 0 }; | |
79 | ||
cb3c8b90 GOC |
80 | /* Store all idle threads, this can be reused instead of creating |
81 | * a new thread. Also avoids complicated thread destroy functionality | |
82 | * for idle threads. | |
83 | */ | |
84 | #ifdef CONFIG_HOTPLUG_CPU | |
85 | /* | |
86 | * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is | |
87 | * removed after init for !CONFIG_HOTPLUG_CPU. | |
88 | */ | |
89 | static DEFINE_PER_CPU(struct task_struct *, idle_thread_array); | |
90 | #define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x)) | |
91 | #define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p)) | |
92 | #else | |
f86c9985 | 93 | static struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ; |
cb3c8b90 GOC |
94 | #define get_idle_for_cpu(x) (idle_thread_array[(x)]) |
95 | #define set_idle_for_cpu(x, p) (idle_thread_array[(x)] = (p)) | |
96 | #endif | |
f6bc4029 | 97 | |
a355352b GC |
98 | /* Number of siblings per CPU package */ |
99 | int smp_num_siblings = 1; | |
100 | EXPORT_SYMBOL(smp_num_siblings); | |
101 | ||
102 | /* Last level cache ID of each logical CPU */ | |
103 | DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID; | |
104 | ||
a355352b GC |
105 | /* representing HT siblings of each logical CPU */ |
106 | DEFINE_PER_CPU(cpumask_t, cpu_sibling_map); | |
107 | EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); | |
108 | ||
109 | /* representing HT and core siblings of each logical CPU */ | |
110 | DEFINE_PER_CPU(cpumask_t, cpu_core_map); | |
111 | EXPORT_PER_CPU_SYMBOL(cpu_core_map); | |
112 | ||
113 | /* Per CPU bogomips and other parameters */ | |
114 | DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); | |
115 | EXPORT_PER_CPU_SYMBOL(cpu_info); | |
768d9505 | 116 | |
cb3c8b90 GOC |
117 | static atomic_t init_deasserted; |
118 | ||
8aef135c | 119 | |
1d89a7f0 | 120 | /* Set if we find a B stepping CPU */ |
f86c9985 | 121 | static int __cpuinitdata smp_b_stepping; |
1d89a7f0 | 122 | |
7cc3959e GOC |
123 | #if defined(CONFIG_NUMA) && defined(CONFIG_X86_32) |
124 | ||
125 | /* which logical CPUs are on which nodes */ | |
126 | cpumask_t node_to_cpumask_map[MAX_NUMNODES] __read_mostly = | |
127 | { [0 ... MAX_NUMNODES-1] = CPU_MASK_NONE }; | |
128 | EXPORT_SYMBOL(node_to_cpumask_map); | |
129 | /* which node each logical CPU is on */ | |
130 | int cpu_to_node_map[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 }; | |
131 | EXPORT_SYMBOL(cpu_to_node_map); | |
132 | ||
133 | /* set up a mapping between cpu and node. */ | |
134 | static void map_cpu_to_node(int cpu, int node) | |
135 | { | |
136 | printk(KERN_INFO "Mapping cpu %d to node %d\n", cpu, node); | |
c2d1cec1 | 137 | cpumask_set_cpu(cpu, &node_to_cpumask_map[node]); |
7cc3959e GOC |
138 | cpu_to_node_map[cpu] = node; |
139 | } | |
140 | ||
141 | /* undo a mapping between cpu and node. */ | |
142 | static void unmap_cpu_to_node(int cpu) | |
143 | { | |
144 | int node; | |
145 | ||
146 | printk(KERN_INFO "Unmapping cpu %d from all nodes\n", cpu); | |
147 | for (node = 0; node < MAX_NUMNODES; node++) | |
c2d1cec1 | 148 | cpumask_clear_cpu(cpu, &node_to_cpumask_map[node]); |
7cc3959e GOC |
149 | cpu_to_node_map[cpu] = 0; |
150 | } | |
151 | #else /* !(CONFIG_NUMA && CONFIG_X86_32) */ | |
152 | #define map_cpu_to_node(cpu, node) ({}) | |
153 | #define unmap_cpu_to_node(cpu) ({}) | |
154 | #endif | |
155 | ||
156 | #ifdef CONFIG_X86_32 | |
1b374e4d SS |
157 | static int boot_cpu_logical_apicid; |
158 | ||
7cc3959e GOC |
159 | u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly = |
160 | { [0 ... NR_CPUS-1] = BAD_APICID }; | |
161 | ||
a4928cff | 162 | static void map_cpu_to_logical_apicid(void) |
7cc3959e GOC |
163 | { |
164 | int cpu = smp_processor_id(); | |
165 | int apicid = logical_smp_processor_id(); | |
166 | int node = apicid_to_node(apicid); | |
167 | ||
168 | if (!node_online(node)) | |
169 | node = first_online_node; | |
170 | ||
171 | cpu_2_logical_apicid[cpu] = apicid; | |
172 | map_cpu_to_node(cpu, node); | |
173 | } | |
174 | ||
1481a3dd | 175 | void numa_remove_cpu(int cpu) |
7cc3959e GOC |
176 | { |
177 | cpu_2_logical_apicid[cpu] = BAD_APICID; | |
178 | unmap_cpu_to_node(cpu); | |
179 | } | |
180 | #else | |
7cc3959e GOC |
181 | #define map_cpu_to_logical_apicid() do {} while (0) |
182 | #endif | |
183 | ||
cb3c8b90 GOC |
184 | /* |
185 | * Report back to the Boot Processor. | |
186 | * Running on AP. | |
187 | */ | |
a4928cff | 188 | static void __cpuinit smp_callin(void) |
cb3c8b90 GOC |
189 | { |
190 | int cpuid, phys_id; | |
191 | unsigned long timeout; | |
192 | ||
193 | /* | |
194 | * If waken up by an INIT in an 82489DX configuration | |
195 | * we may get here before an INIT-deassert IPI reaches | |
196 | * our local APIC. We have to wait for the IPI or we'll | |
197 | * lock up on an APIC access. | |
198 | */ | |
199 | wait_for_init_deassert(&init_deasserted); | |
200 | ||
201 | /* | |
202 | * (This works even if the APIC is not enabled.) | |
203 | */ | |
4c9961d5 | 204 | phys_id = read_apic_id(); |
cb3c8b90 | 205 | cpuid = smp_processor_id(); |
c2d1cec1 | 206 | if (cpumask_test_cpu(cpuid, cpu_callin_mask)) { |
cb3c8b90 GOC |
207 | panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__, |
208 | phys_id, cpuid); | |
209 | } | |
cfc1b9a6 | 210 | pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); |
cb3c8b90 GOC |
211 | |
212 | /* | |
213 | * STARTUP IPIs are fragile beasts as they might sometimes | |
214 | * trigger some glue motherboard logic. Complete APIC bus | |
215 | * silence for 1 second, this overestimates the time the | |
216 | * boot CPU is spending to send the up to 2 STARTUP IPIs | |
217 | * by a factor of two. This should be enough. | |
218 | */ | |
219 | ||
220 | /* | |
221 | * Waiting 2s total for startup (udelay is not yet working) | |
222 | */ | |
223 | timeout = jiffies + 2*HZ; | |
224 | while (time_before(jiffies, timeout)) { | |
225 | /* | |
226 | * Has the boot CPU finished it's STARTUP sequence? | |
227 | */ | |
c2d1cec1 | 228 | if (cpumask_test_cpu(cpuid, cpu_callout_mask)) |
cb3c8b90 GOC |
229 | break; |
230 | cpu_relax(); | |
231 | } | |
232 | ||
233 | if (!time_before(jiffies, timeout)) { | |
234 | panic("%s: CPU%d started up but did not get a callout!\n", | |
235 | __func__, cpuid); | |
236 | } | |
237 | ||
238 | /* | |
239 | * the boot CPU has finished the init stage and is spinning | |
240 | * on callin_map until we finish. We are free to set up this | |
241 | * CPU, first the APIC. (this is probably redundant on most | |
242 | * boards) | |
243 | */ | |
244 | ||
cfc1b9a6 | 245 | pr_debug("CALLIN, before setup_local_APIC().\n"); |
cb3c8b90 GOC |
246 | smp_callin_clear_local_apic(); |
247 | setup_local_APIC(); | |
248 | end_local_APIC_setup(); | |
249 | map_cpu_to_logical_apicid(); | |
250 | ||
e545a614 | 251 | notify_cpu_starting(cpuid); |
cb3c8b90 GOC |
252 | /* |
253 | * Get our bogomips. | |
254 | * | |
255 | * Need to enable IRQs because it can take longer and then | |
256 | * the NMI watchdog might kill us. | |
257 | */ | |
258 | local_irq_enable(); | |
259 | calibrate_delay(); | |
260 | local_irq_disable(); | |
cfc1b9a6 | 261 | pr_debug("Stack at about %p\n", &cpuid); |
cb3c8b90 GOC |
262 | |
263 | /* | |
264 | * Save our processor parameters | |
265 | */ | |
266 | smp_store_cpu_info(cpuid); | |
267 | ||
268 | /* | |
269 | * Allow the master to continue. | |
270 | */ | |
c2d1cec1 | 271 | cpumask_set_cpu(cpuid, cpu_callin_mask); |
cb3c8b90 GOC |
272 | } |
273 | ||
25ddbb18 AK |
274 | static int __cpuinitdata unsafe_smp; |
275 | ||
bbc2ff6a GOC |
276 | /* |
277 | * Activate a secondary processor. | |
278 | */ | |
0ca59dd9 | 279 | notrace static void __cpuinit start_secondary(void *unused) |
bbc2ff6a GOC |
280 | { |
281 | /* | |
282 | * Don't put *anything* before cpu_init(), SMP booting is too | |
283 | * fragile that we want to limit the things done here to the | |
284 | * most necessary things. | |
285 | */ | |
bbc2ff6a | 286 | vmi_bringup(); |
bbc2ff6a GOC |
287 | cpu_init(); |
288 | preempt_disable(); | |
289 | smp_callin(); | |
290 | ||
291 | /* otherwise gcc will move up smp_processor_id before the cpu_init */ | |
292 | barrier(); | |
293 | /* | |
294 | * Check TSC synchronization with the BP: | |
295 | */ | |
296 | check_tsc_sync_target(); | |
297 | ||
298 | if (nmi_watchdog == NMI_IO_APIC) { | |
299 | disable_8259A_irq(0); | |
300 | enable_NMI_through_LVT0(); | |
301 | enable_8259A_irq(0); | |
302 | } | |
303 | ||
61165d7a HD |
304 | #ifdef CONFIG_X86_32 |
305 | while (low_mappings) | |
306 | cpu_relax(); | |
307 | __flush_tlb_all(); | |
308 | #endif | |
309 | ||
bbc2ff6a GOC |
310 | /* This must be done before setting cpu_online_map */ |
311 | set_cpu_sibling_map(raw_smp_processor_id()); | |
312 | wmb(); | |
313 | ||
314 | /* | |
315 | * We need to hold call_lock, so there is no inconsistency | |
316 | * between the time smp_call_function() determines number of | |
317 | * IPI recipients, and the time when the determination is made | |
318 | * for which cpus receive the IPI. Holding this | |
319 | * lock helps us to not include this cpu in a currently in progress | |
320 | * smp_call_function(). | |
d388e5fd EB |
321 | * |
322 | * We need to hold vector_lock so there the set of online cpus | |
323 | * does not change while we are assigning vectors to cpus. Holding | |
324 | * this lock ensures we don't half assign or remove an irq from a cpu. | |
bbc2ff6a | 325 | */ |
0cefa5b9 | 326 | ipi_call_lock(); |
d388e5fd EB |
327 | lock_vector_lock(); |
328 | __setup_vector_irq(smp_processor_id()); | |
c2d1cec1 | 329 | set_cpu_online(smp_processor_id(), true); |
d388e5fd | 330 | unlock_vector_lock(); |
0cefa5b9 | 331 | ipi_call_unlock(); |
bbc2ff6a GOC |
332 | per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; |
333 | ||
0cefa5b9 MS |
334 | /* enable local interrupts */ |
335 | local_irq_enable(); | |
336 | ||
bbc2ff6a GOC |
337 | setup_secondary_clock(); |
338 | ||
339 | wmb(); | |
340 | cpu_idle(); | |
341 | } | |
342 | ||
1d89a7f0 GOC |
343 | static void __cpuinit smp_apply_quirks(struct cpuinfo_x86 *c) |
344 | { | |
1d89a7f0 GOC |
345 | /* |
346 | * Mask B, Pentium, but not Pentium MMX | |
347 | */ | |
348 | if (c->x86_vendor == X86_VENDOR_INTEL && | |
349 | c->x86 == 5 && | |
350 | c->x86_mask >= 1 && c->x86_mask <= 4 && | |
351 | c->x86_model <= 3) | |
352 | /* | |
353 | * Remember we have B step Pentia with bugs | |
354 | */ | |
355 | smp_b_stepping = 1; | |
356 | ||
357 | /* | |
358 | * Certain Athlons might work (for various values of 'work') in SMP | |
359 | * but they are not certified as MP capable. | |
360 | */ | |
361 | if ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6)) { | |
362 | ||
363 | if (num_possible_cpus() == 1) | |
364 | goto valid_k7; | |
365 | ||
366 | /* Athlon 660/661 is valid. */ | |
367 | if ((c->x86_model == 6) && ((c->x86_mask == 0) || | |
368 | (c->x86_mask == 1))) | |
369 | goto valid_k7; | |
370 | ||
371 | /* Duron 670 is valid */ | |
372 | if ((c->x86_model == 7) && (c->x86_mask == 0)) | |
373 | goto valid_k7; | |
374 | ||
375 | /* | |
376 | * Athlon 662, Duron 671, and Athlon >model 7 have capability | |
377 | * bit. It's worth noting that the A5 stepping (662) of some | |
378 | * Athlon XP's have the MP bit set. | |
379 | * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for | |
380 | * more. | |
381 | */ | |
382 | if (((c->x86_model == 6) && (c->x86_mask >= 2)) || | |
383 | ((c->x86_model == 7) && (c->x86_mask >= 1)) || | |
384 | (c->x86_model > 7)) | |
385 | if (cpu_has_mp) | |
386 | goto valid_k7; | |
387 | ||
388 | /* If we get here, not a certified SMP capable AMD system. */ | |
25ddbb18 | 389 | unsafe_smp = 1; |
1d89a7f0 GOC |
390 | } |
391 | ||
392 | valid_k7: | |
393 | ; | |
1d89a7f0 GOC |
394 | } |
395 | ||
a4928cff | 396 | static void __cpuinit smp_checks(void) |
693d4b8a GOC |
397 | { |
398 | if (smp_b_stepping) | |
399 | printk(KERN_WARNING "WARNING: SMP operation may be unreliable" | |
400 | "with B stepping processors.\n"); | |
401 | ||
402 | /* | |
403 | * Don't taint if we are running SMP kernel on a single non-MP | |
404 | * approved Athlon | |
405 | */ | |
25ddbb18 AK |
406 | if (unsafe_smp && num_online_cpus() > 1) { |
407 | printk(KERN_INFO "WARNING: This combination of AMD" | |
408 | "processors is not suitable for SMP.\n"); | |
409 | add_taint(TAINT_UNSAFE_SMP); | |
693d4b8a GOC |
410 | } |
411 | } | |
412 | ||
1d89a7f0 GOC |
413 | /* |
414 | * The bootstrap kernel entry code has set these up. Save them for | |
415 | * a given CPU | |
416 | */ | |
417 | ||
418 | void __cpuinit smp_store_cpu_info(int id) | |
419 | { | |
420 | struct cpuinfo_x86 *c = &cpu_data(id); | |
421 | ||
422 | *c = boot_cpu_data; | |
423 | c->cpu_index = id; | |
424 | if (id != 0) | |
425 | identify_secondary_cpu(c); | |
426 | smp_apply_quirks(c); | |
427 | } | |
428 | ||
429 | ||
768d9505 GC |
430 | void __cpuinit set_cpu_sibling_map(int cpu) |
431 | { | |
432 | int i; | |
433 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
434 | ||
c2d1cec1 | 435 | cpumask_set_cpu(cpu, cpu_sibling_setup_mask); |
768d9505 GC |
436 | |
437 | if (smp_num_siblings > 1) { | |
c2d1cec1 MT |
438 | for_each_cpu(i, cpu_sibling_setup_mask) { |
439 | struct cpuinfo_x86 *o = &cpu_data(i); | |
440 | ||
441 | if (c->phys_proc_id == o->phys_proc_id && | |
442 | c->cpu_core_id == o->cpu_core_id) { | |
443 | cpumask_set_cpu(i, cpu_sibling_mask(cpu)); | |
444 | cpumask_set_cpu(cpu, cpu_sibling_mask(i)); | |
445 | cpumask_set_cpu(i, cpu_core_mask(cpu)); | |
446 | cpumask_set_cpu(cpu, cpu_core_mask(i)); | |
447 | cpumask_set_cpu(i, &c->llc_shared_map); | |
448 | cpumask_set_cpu(cpu, &o->llc_shared_map); | |
768d9505 GC |
449 | } |
450 | } | |
451 | } else { | |
c2d1cec1 | 452 | cpumask_set_cpu(cpu, cpu_sibling_mask(cpu)); |
768d9505 GC |
453 | } |
454 | ||
c2d1cec1 | 455 | cpumask_set_cpu(cpu, &c->llc_shared_map); |
768d9505 GC |
456 | |
457 | if (current_cpu_data.x86_max_cores == 1) { | |
c2d1cec1 | 458 | cpumask_copy(cpu_core_mask(cpu), cpu_sibling_mask(cpu)); |
768d9505 GC |
459 | c->booted_cores = 1; |
460 | return; | |
461 | } | |
462 | ||
c2d1cec1 | 463 | for_each_cpu(i, cpu_sibling_setup_mask) { |
768d9505 GC |
464 | if (per_cpu(cpu_llc_id, cpu) != BAD_APICID && |
465 | per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) { | |
c2d1cec1 MT |
466 | cpumask_set_cpu(i, &c->llc_shared_map); |
467 | cpumask_set_cpu(cpu, &cpu_data(i).llc_shared_map); | |
768d9505 GC |
468 | } |
469 | if (c->phys_proc_id == cpu_data(i).phys_proc_id) { | |
c2d1cec1 MT |
470 | cpumask_set_cpu(i, cpu_core_mask(cpu)); |
471 | cpumask_set_cpu(cpu, cpu_core_mask(i)); | |
768d9505 GC |
472 | /* |
473 | * Does this new cpu bringup a new core? | |
474 | */ | |
c2d1cec1 | 475 | if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) { |
768d9505 GC |
476 | /* |
477 | * for each core in package, increment | |
478 | * the booted_cores for this new cpu | |
479 | */ | |
c2d1cec1 | 480 | if (cpumask_first(cpu_sibling_mask(i)) == i) |
768d9505 GC |
481 | c->booted_cores++; |
482 | /* | |
483 | * increment the core count for all | |
484 | * the other cpus in this package | |
485 | */ | |
486 | if (i != cpu) | |
487 | cpu_data(i).booted_cores++; | |
488 | } else if (i != cpu && !c->booted_cores) | |
489 | c->booted_cores = cpu_data(i).booted_cores; | |
490 | } | |
491 | } | |
492 | } | |
493 | ||
70708a18 | 494 | /* maps the cpu to the sched domain representing multi-core */ |
030bb203 | 495 | const struct cpumask *cpu_coregroup_mask(int cpu) |
70708a18 GC |
496 | { |
497 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
498 | /* | |
499 | * For perf, we return last level cache shared map. | |
500 | * And for power savings, we return cpu_core_map | |
501 | */ | |
502 | if (sched_mc_power_savings || sched_smt_power_savings) | |
c2d1cec1 | 503 | return cpu_core_mask(cpu); |
70708a18 | 504 | else |
030bb203 RR |
505 | return &c->llc_shared_map; |
506 | } | |
507 | ||
508 | cpumask_t cpu_coregroup_map(int cpu) | |
509 | { | |
510 | return *cpu_coregroup_mask(cpu); | |
70708a18 GC |
511 | } |
512 | ||
a4928cff | 513 | static void impress_friends(void) |
904541e2 GOC |
514 | { |
515 | int cpu; | |
516 | unsigned long bogosum = 0; | |
517 | /* | |
518 | * Allow the user to impress friends. | |
519 | */ | |
cfc1b9a6 | 520 | pr_debug("Before bogomips.\n"); |
904541e2 | 521 | for_each_possible_cpu(cpu) |
c2d1cec1 | 522 | if (cpumask_test_cpu(cpu, cpu_callout_mask)) |
904541e2 GOC |
523 | bogosum += cpu_data(cpu).loops_per_jiffy; |
524 | printk(KERN_INFO | |
525 | "Total of %d processors activated (%lu.%02lu BogoMIPS).\n", | |
f68e00a3 | 526 | num_online_cpus(), |
904541e2 GOC |
527 | bogosum/(500000/HZ), |
528 | (bogosum/(5000/HZ))%100); | |
529 | ||
cfc1b9a6 | 530 | pr_debug("Before bogocount - setting activated=1.\n"); |
904541e2 GOC |
531 | } |
532 | ||
569712b2 | 533 | void __inquire_remote_apic(int apicid) |
cb3c8b90 GOC |
534 | { |
535 | unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; | |
536 | char *names[] = { "ID", "VERSION", "SPIV" }; | |
537 | int timeout; | |
538 | u32 status; | |
539 | ||
823b259b | 540 | printk(KERN_INFO "Inquiring remote APIC 0x%x...\n", apicid); |
cb3c8b90 GOC |
541 | |
542 | for (i = 0; i < ARRAY_SIZE(regs); i++) { | |
823b259b | 543 | printk(KERN_INFO "... APIC 0x%x %s: ", apicid, names[i]); |
cb3c8b90 GOC |
544 | |
545 | /* | |
546 | * Wait for idle. | |
547 | */ | |
548 | status = safe_apic_wait_icr_idle(); | |
549 | if (status) | |
550 | printk(KERN_CONT | |
551 | "a previous APIC delivery may have failed\n"); | |
552 | ||
1b374e4d | 553 | apic_icr_write(APIC_DM_REMRD | regs[i], apicid); |
cb3c8b90 GOC |
554 | |
555 | timeout = 0; | |
556 | do { | |
557 | udelay(100); | |
558 | status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; | |
559 | } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); | |
560 | ||
561 | switch (status) { | |
562 | case APIC_ICR_RR_VALID: | |
563 | status = apic_read(APIC_RRR); | |
564 | printk(KERN_CONT "%08x\n", status); | |
565 | break; | |
566 | default: | |
567 | printk(KERN_CONT "failed\n"); | |
568 | } | |
569 | } | |
570 | } | |
571 | ||
cb3c8b90 GOC |
572 | /* |
573 | * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal | |
574 | * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this | |
575 | * won't ... remember to clear down the APIC, etc later. | |
576 | */ | |
569712b2 YL |
577 | int __devinit |
578 | wakeup_secondary_cpu_via_nmi(int logical_apicid, unsigned long start_eip) | |
cb3c8b90 GOC |
579 | { |
580 | unsigned long send_status, accept_status = 0; | |
581 | int maxlvt; | |
582 | ||
583 | /* Target chip */ | |
cb3c8b90 GOC |
584 | /* Boot on the stack */ |
585 | /* Kick the second */ | |
0b06e734 | 586 | apic_icr_write(APIC_DM_NMI | apic->apic_destination_logical, logical_apicid); |
cb3c8b90 | 587 | |
cfc1b9a6 | 588 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
589 | send_status = safe_apic_wait_icr_idle(); |
590 | ||
591 | /* | |
592 | * Give the other CPU some time to accept the IPI. | |
593 | */ | |
594 | udelay(200); | |
569712b2 | 595 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { |
59ef48a5 CG |
596 | maxlvt = lapic_get_maxlvt(); |
597 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
598 | apic_write(APIC_ESR, 0); | |
599 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
600 | } | |
cfc1b9a6 | 601 | pr_debug("NMI sent.\n"); |
cb3c8b90 GOC |
602 | |
603 | if (send_status) | |
604 | printk(KERN_ERR "APIC never delivered???\n"); | |
605 | if (accept_status) | |
606 | printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); | |
607 | ||
608 | return (send_status | accept_status); | |
609 | } | |
cb3c8b90 | 610 | |
54ac14a8 | 611 | int __devinit |
569712b2 | 612 | wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) |
cb3c8b90 GOC |
613 | { |
614 | unsigned long send_status, accept_status = 0; | |
615 | int maxlvt, num_starts, j; | |
616 | ||
34d05591 JS |
617 | if (get_uv_system_type() == UV_NON_UNIQUE_APIC) { |
618 | send_status = uv_wakeup_secondary(phys_apicid, start_eip); | |
619 | atomic_set(&init_deasserted, 1); | |
620 | return send_status; | |
621 | } | |
622 | ||
593f4a78 MR |
623 | maxlvt = lapic_get_maxlvt(); |
624 | ||
cb3c8b90 GOC |
625 | /* |
626 | * Be paranoid about clearing APIC errors. | |
627 | */ | |
628 | if (APIC_INTEGRATED(apic_version[phys_apicid])) { | |
593f4a78 MR |
629 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
630 | apic_write(APIC_ESR, 0); | |
cb3c8b90 GOC |
631 | apic_read(APIC_ESR); |
632 | } | |
633 | ||
cfc1b9a6 | 634 | pr_debug("Asserting INIT.\n"); |
cb3c8b90 GOC |
635 | |
636 | /* | |
637 | * Turn INIT on target chip | |
638 | */ | |
cb3c8b90 GOC |
639 | /* |
640 | * Send IPI | |
641 | */ | |
1b374e4d SS |
642 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, |
643 | phys_apicid); | |
cb3c8b90 | 644 | |
cfc1b9a6 | 645 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
646 | send_status = safe_apic_wait_icr_idle(); |
647 | ||
648 | mdelay(10); | |
649 | ||
cfc1b9a6 | 650 | pr_debug("Deasserting INIT.\n"); |
cb3c8b90 GOC |
651 | |
652 | /* Target chip */ | |
cb3c8b90 | 653 | /* Send IPI */ |
1b374e4d | 654 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); |
cb3c8b90 | 655 | |
cfc1b9a6 | 656 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
657 | send_status = safe_apic_wait_icr_idle(); |
658 | ||
659 | mb(); | |
660 | atomic_set(&init_deasserted, 1); | |
661 | ||
662 | /* | |
663 | * Should we send STARTUP IPIs ? | |
664 | * | |
665 | * Determine this based on the APIC version. | |
666 | * If we don't have an integrated APIC, don't send the STARTUP IPIs. | |
667 | */ | |
668 | if (APIC_INTEGRATED(apic_version[phys_apicid])) | |
669 | num_starts = 2; | |
670 | else | |
671 | num_starts = 0; | |
672 | ||
673 | /* | |
674 | * Paravirt / VMI wants a startup IPI hook here to set up the | |
675 | * target processor state. | |
676 | */ | |
677 | startup_ipi_hook(phys_apicid, (unsigned long) start_secondary, | |
cb3c8b90 | 678 | (unsigned long)stack_start.sp); |
cb3c8b90 GOC |
679 | |
680 | /* | |
681 | * Run STARTUP IPI loop. | |
682 | */ | |
cfc1b9a6 | 683 | pr_debug("#startup loops: %d.\n", num_starts); |
cb3c8b90 | 684 | |
cb3c8b90 | 685 | for (j = 1; j <= num_starts; j++) { |
cfc1b9a6 | 686 | pr_debug("Sending STARTUP #%d.\n", j); |
593f4a78 MR |
687 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
688 | apic_write(APIC_ESR, 0); | |
cb3c8b90 | 689 | apic_read(APIC_ESR); |
cfc1b9a6 | 690 | pr_debug("After apic_write.\n"); |
cb3c8b90 GOC |
691 | |
692 | /* | |
693 | * STARTUP IPI | |
694 | */ | |
695 | ||
696 | /* Target chip */ | |
cb3c8b90 GOC |
697 | /* Boot on the stack */ |
698 | /* Kick the second */ | |
1b374e4d SS |
699 | apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), |
700 | phys_apicid); | |
cb3c8b90 GOC |
701 | |
702 | /* | |
703 | * Give the other CPU some time to accept the IPI. | |
704 | */ | |
705 | udelay(300); | |
706 | ||
cfc1b9a6 | 707 | pr_debug("Startup point 1.\n"); |
cb3c8b90 | 708 | |
cfc1b9a6 | 709 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
710 | send_status = safe_apic_wait_icr_idle(); |
711 | ||
712 | /* | |
713 | * Give the other CPU some time to accept the IPI. | |
714 | */ | |
715 | udelay(200); | |
593f4a78 | 716 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
cb3c8b90 | 717 | apic_write(APIC_ESR, 0); |
cb3c8b90 GOC |
718 | accept_status = (apic_read(APIC_ESR) & 0xEF); |
719 | if (send_status || accept_status) | |
720 | break; | |
721 | } | |
cfc1b9a6 | 722 | pr_debug("After Startup.\n"); |
cb3c8b90 GOC |
723 | |
724 | if (send_status) | |
725 | printk(KERN_ERR "APIC never delivered???\n"); | |
726 | if (accept_status) | |
727 | printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); | |
728 | ||
729 | return (send_status | accept_status); | |
730 | } | |
cb3c8b90 GOC |
731 | |
732 | struct create_idle { | |
733 | struct work_struct work; | |
734 | struct task_struct *idle; | |
735 | struct completion done; | |
736 | int cpu; | |
737 | }; | |
738 | ||
739 | static void __cpuinit do_fork_idle(struct work_struct *work) | |
740 | { | |
741 | struct create_idle *c_idle = | |
742 | container_of(work, struct create_idle, work); | |
743 | ||
744 | c_idle->idle = fork_idle(c_idle->cpu); | |
745 | complete(&c_idle->done); | |
746 | } | |
747 | ||
748 | static int __cpuinit do_boot_cpu(int apicid, int cpu) | |
749 | /* | |
750 | * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad | |
751 | * (ie clustered apic addressing mode), this is a LOGICAL apic ID. | |
752 | * Returns zero if CPU booted OK, else error code from wakeup_secondary_cpu. | |
753 | */ | |
754 | { | |
755 | unsigned long boot_error = 0; | |
756 | int timeout; | |
757 | unsigned long start_ip; | |
758 | unsigned short nmi_high = 0, nmi_low = 0; | |
759 | struct create_idle c_idle = { | |
760 | .cpu = cpu, | |
761 | .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done), | |
762 | }; | |
763 | INIT_WORK(&c_idle.work, do_fork_idle); | |
cb3c8b90 | 764 | |
cb3c8b90 GOC |
765 | alternatives_smp_switch(1); |
766 | ||
767 | c_idle.idle = get_idle_for_cpu(cpu); | |
768 | ||
769 | /* | |
770 | * We can't use kernel_thread since we must avoid to | |
771 | * reschedule the child. | |
772 | */ | |
773 | if (c_idle.idle) { | |
774 | c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *) | |
775 | (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1); | |
776 | init_idle(c_idle.idle, cpu); | |
777 | goto do_rest; | |
778 | } | |
779 | ||
780 | if (!keventd_up() || current_is_keventd()) | |
781 | c_idle.work.func(&c_idle.work); | |
782 | else { | |
783 | schedule_work(&c_idle.work); | |
784 | wait_for_completion(&c_idle.done); | |
785 | } | |
786 | ||
787 | if (IS_ERR(c_idle.idle)) { | |
788 | printk("failed fork for CPU %d\n", cpu); | |
789 | return PTR_ERR(c_idle.idle); | |
790 | } | |
791 | ||
792 | set_idle_for_cpu(cpu, c_idle.idle); | |
793 | do_rest: | |
cb3c8b90 | 794 | per_cpu(current_task, cpu) = c_idle.idle; |
c6f5e0ac | 795 | #ifdef CONFIG_X86_32 |
cb3c8b90 | 796 | /* Stack for startup_32 can be just as for start_secondary onwards */ |
cb3c8b90 GOC |
797 | irq_ctx_init(cpu); |
798 | #else | |
cb3c8b90 | 799 | clear_tsk_thread_flag(c_idle.idle, TIF_FORK); |
004aa322 | 800 | initial_gs = per_cpu_offset(cpu); |
9af45651 BG |
801 | per_cpu(kernel_stack, cpu) = |
802 | (unsigned long)task_stack_page(c_idle.idle) - | |
803 | KERNEL_STACK_OFFSET + THREAD_SIZE; | |
cb3c8b90 | 804 | #endif |
a939098a | 805 | early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); |
3e970473 | 806 | initial_code = (unsigned long)start_secondary; |
9cf4f298 | 807 | stack_start.sp = (void *) c_idle.idle->thread.sp; |
cb3c8b90 GOC |
808 | |
809 | /* start_ip had better be page-aligned! */ | |
810 | start_ip = setup_trampoline(); | |
811 | ||
812 | /* So we see what's up */ | |
823b259b | 813 | printk(KERN_INFO "Booting processor %d APIC 0x%x ip 0x%lx\n", |
cb3c8b90 GOC |
814 | cpu, apicid, start_ip); |
815 | ||
816 | /* | |
817 | * This grunge runs the startup process for | |
818 | * the targeted processor. | |
819 | */ | |
820 | ||
821 | atomic_set(&init_deasserted, 0); | |
822 | ||
34d05591 | 823 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
cb3c8b90 | 824 | |
cfc1b9a6 | 825 | pr_debug("Setting warm reset code and vector.\n"); |
cb3c8b90 | 826 | |
34d05591 JS |
827 | store_NMI_vector(&nmi_high, &nmi_low); |
828 | ||
829 | smpboot_setup_warm_reset_vector(start_ip); | |
830 | /* | |
831 | * Be paranoid about clearing APIC errors. | |
db96b0a0 CG |
832 | */ |
833 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | |
834 | apic_write(APIC_ESR, 0); | |
835 | apic_read(APIC_ESR); | |
836 | } | |
34d05591 | 837 | } |
cb3c8b90 | 838 | |
cb3c8b90 GOC |
839 | /* |
840 | * Starting actual IPI sequence... | |
841 | */ | |
842 | boot_error = wakeup_secondary_cpu(apicid, start_ip); | |
843 | ||
844 | if (!boot_error) { | |
845 | /* | |
846 | * allow APs to start initializing. | |
847 | */ | |
cfc1b9a6 | 848 | pr_debug("Before Callout %d.\n", cpu); |
c2d1cec1 | 849 | cpumask_set_cpu(cpu, cpu_callout_mask); |
cfc1b9a6 | 850 | pr_debug("After Callout %d.\n", cpu); |
cb3c8b90 GOC |
851 | |
852 | /* | |
853 | * Wait 5s total for a response | |
854 | */ | |
855 | for (timeout = 0; timeout < 50000; timeout++) { | |
c2d1cec1 | 856 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) |
cb3c8b90 GOC |
857 | break; /* It has booted */ |
858 | udelay(100); | |
859 | } | |
860 | ||
c2d1cec1 | 861 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) { |
cb3c8b90 | 862 | /* number CPUs logically, starting from 1 (BSP is 0) */ |
cfc1b9a6 | 863 | pr_debug("OK.\n"); |
cb3c8b90 GOC |
864 | printk(KERN_INFO "CPU%d: ", cpu); |
865 | print_cpu_info(&cpu_data(cpu)); | |
cfc1b9a6 | 866 | pr_debug("CPU has booted.\n"); |
cb3c8b90 GOC |
867 | } else { |
868 | boot_error = 1; | |
869 | if (*((volatile unsigned char *)trampoline_base) | |
870 | == 0xA5) | |
871 | /* trampoline started but...? */ | |
872 | printk(KERN_ERR "Stuck ??\n"); | |
873 | else | |
874 | /* trampoline code not run */ | |
875 | printk(KERN_ERR "Not responding.\n"); | |
34d05591 JS |
876 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) |
877 | inquire_remote_apic(apicid); | |
cb3c8b90 GOC |
878 | } |
879 | } | |
1a51e3a0 | 880 | |
cb3c8b90 GOC |
881 | if (boot_error) { |
882 | /* Try to put things back the way they were before ... */ | |
23ca4bba | 883 | numa_remove_cpu(cpu); /* was set by numa_add_cpu */ |
c2d1cec1 MT |
884 | |
885 | /* was set by do_boot_cpu() */ | |
886 | cpumask_clear_cpu(cpu, cpu_callout_mask); | |
887 | ||
888 | /* was set by cpu_init() */ | |
889 | cpumask_clear_cpu(cpu, cpu_initialized_mask); | |
890 | ||
891 | set_cpu_present(cpu, false); | |
cb3c8b90 GOC |
892 | per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID; |
893 | } | |
894 | ||
895 | /* mark "stuck" area as not stuck */ | |
896 | *((volatile unsigned long *)trampoline_base) = 0; | |
897 | ||
63d38198 AK |
898 | /* |
899 | * Cleanup possible dangling ends... | |
900 | */ | |
901 | smpboot_restore_warm_reset_vector(); | |
902 | ||
cb3c8b90 GOC |
903 | return boot_error; |
904 | } | |
905 | ||
906 | int __cpuinit native_cpu_up(unsigned int cpu) | |
907 | { | |
908 | int apicid = cpu_present_to_apicid(cpu); | |
909 | unsigned long flags; | |
910 | int err; | |
911 | ||
912 | WARN_ON(irqs_disabled()); | |
913 | ||
cfc1b9a6 | 914 | pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); |
cb3c8b90 GOC |
915 | |
916 | if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid || | |
917 | !physid_isset(apicid, phys_cpu_present_map)) { | |
918 | printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu); | |
919 | return -EINVAL; | |
920 | } | |
921 | ||
922 | /* | |
923 | * Already booted CPU? | |
924 | */ | |
c2d1cec1 | 925 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) { |
cfc1b9a6 | 926 | pr_debug("do_boot_cpu %d Already started\n", cpu); |
cb3c8b90 GOC |
927 | return -ENOSYS; |
928 | } | |
929 | ||
930 | /* | |
931 | * Save current MTRR state in case it was changed since early boot | |
932 | * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: | |
933 | */ | |
934 | mtrr_save_state(); | |
935 | ||
936 | per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; | |
937 | ||
938 | #ifdef CONFIG_X86_32 | |
939 | /* init low mem mapping */ | |
68db065c | 940 | clone_pgd_range(swapper_pg_dir, swapper_pg_dir + KERNEL_PGD_BOUNDARY, |
61165d7a | 941 | min_t(unsigned long, KERNEL_PGD_PTRS, KERNEL_PGD_BOUNDARY)); |
cb3c8b90 | 942 | flush_tlb_all(); |
61165d7a | 943 | low_mappings = 1; |
cb3c8b90 GOC |
944 | |
945 | err = do_boot_cpu(apicid, cpu); | |
61165d7a HD |
946 | |
947 | zap_low_mappings(); | |
948 | low_mappings = 0; | |
949 | #else | |
950 | err = do_boot_cpu(apicid, cpu); | |
951 | #endif | |
952 | if (err) { | |
cfc1b9a6 | 953 | pr_debug("do_boot_cpu failed %d\n", err); |
61165d7a | 954 | return -EIO; |
cb3c8b90 GOC |
955 | } |
956 | ||
957 | /* | |
958 | * Check TSC synchronization with the AP (keep irqs disabled | |
959 | * while doing so): | |
960 | */ | |
961 | local_irq_save(flags); | |
962 | check_tsc_sync_source(cpu); | |
963 | local_irq_restore(flags); | |
964 | ||
7c04e64a | 965 | while (!cpu_online(cpu)) { |
cb3c8b90 GOC |
966 | cpu_relax(); |
967 | touch_nmi_watchdog(); | |
968 | } | |
969 | ||
970 | return 0; | |
971 | } | |
972 | ||
8aef135c GOC |
973 | /* |
974 | * Fall back to non SMP mode after errors. | |
975 | * | |
976 | * RED-PEN audit/test this more. I bet there is more state messed up here. | |
977 | */ | |
978 | static __init void disable_smp(void) | |
979 | { | |
c2d1cec1 MT |
980 | /* use the read/write pointers to the present and possible maps */ |
981 | cpumask_copy(&cpu_present_map, cpumask_of(0)); | |
982 | cpumask_copy(&cpu_possible_map, cpumask_of(0)); | |
8aef135c | 983 | smpboot_clear_io_apic_irqs(); |
0f385d1d | 984 | |
8aef135c | 985 | if (smp_found_config) |
b6df1b8b | 986 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
8aef135c | 987 | else |
b6df1b8b | 988 | physid_set_mask_of_physid(0, &phys_cpu_present_map); |
8aef135c | 989 | map_cpu_to_logical_apicid(); |
c2d1cec1 MT |
990 | cpumask_set_cpu(0, cpu_sibling_mask(0)); |
991 | cpumask_set_cpu(0, cpu_core_mask(0)); | |
8aef135c GOC |
992 | } |
993 | ||
994 | /* | |
995 | * Various sanity checks. | |
996 | */ | |
997 | static int __init smp_sanity_check(unsigned max_cpus) | |
998 | { | |
ac23d4ee | 999 | preempt_disable(); |
a58f03b0 YL |
1000 | |
1001 | #if defined(CONFIG_X86_PC) && defined(CONFIG_X86_32) | |
1002 | if (def_to_bigsmp && nr_cpu_ids > 8) { | |
1003 | unsigned int cpu; | |
1004 | unsigned nr; | |
1005 | ||
1006 | printk(KERN_WARNING | |
1007 | "More than 8 CPUs detected - skipping them.\n" | |
1008 | "Use CONFIG_X86_GENERICARCH and CONFIG_X86_BIGSMP.\n"); | |
1009 | ||
1010 | nr = 0; | |
1011 | for_each_present_cpu(cpu) { | |
1012 | if (nr >= 8) | |
c2d1cec1 | 1013 | set_cpu_present(cpu, false); |
a58f03b0 YL |
1014 | nr++; |
1015 | } | |
1016 | ||
1017 | nr = 0; | |
1018 | for_each_possible_cpu(cpu) { | |
1019 | if (nr >= 8) | |
c2d1cec1 | 1020 | set_cpu_possible(cpu, false); |
a58f03b0 YL |
1021 | nr++; |
1022 | } | |
1023 | ||
1024 | nr_cpu_ids = 8; | |
1025 | } | |
1026 | #endif | |
1027 | ||
8aef135c | 1028 | if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { |
55c395b4 MT |
1029 | printk(KERN_WARNING |
1030 | "weird, boot CPU (#%d) not listed by the BIOS.\n", | |
1031 | hard_smp_processor_id()); | |
1032 | ||
8aef135c GOC |
1033 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); |
1034 | } | |
1035 | ||
1036 | /* | |
1037 | * If we couldn't find an SMP configuration at boot time, | |
1038 | * get out of here now! | |
1039 | */ | |
1040 | if (!smp_found_config && !acpi_lapic) { | |
ac23d4ee | 1041 | preempt_enable(); |
8aef135c GOC |
1042 | printk(KERN_NOTICE "SMP motherboard not detected.\n"); |
1043 | disable_smp(); | |
1044 | if (APIC_init_uniprocessor()) | |
1045 | printk(KERN_NOTICE "Local APIC not detected." | |
1046 | " Using dummy APIC emulation.\n"); | |
1047 | return -1; | |
1048 | } | |
1049 | ||
1050 | /* | |
1051 | * Should not be necessary because the MP table should list the boot | |
1052 | * CPU too, but we do it for the sake of robustness anyway. | |
1053 | */ | |
1054 | if (!check_phys_apicid_present(boot_cpu_physical_apicid)) { | |
1055 | printk(KERN_NOTICE | |
1056 | "weird, boot CPU (#%d) not listed by the BIOS.\n", | |
1057 | boot_cpu_physical_apicid); | |
1058 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); | |
1059 | } | |
ac23d4ee | 1060 | preempt_enable(); |
8aef135c GOC |
1061 | |
1062 | /* | |
1063 | * If we couldn't find a local APIC, then get out of here now! | |
1064 | */ | |
1065 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && | |
1066 | !cpu_has_apic) { | |
1067 | printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n", | |
1068 | boot_cpu_physical_apicid); | |
1069 | printk(KERN_ERR "... forcing use of dummy APIC emulation." | |
1070 | "(tell your hw vendor)\n"); | |
1071 | smpboot_clear_io_apic(); | |
f1182638 | 1072 | disable_ioapic_setup(); |
8aef135c GOC |
1073 | return -1; |
1074 | } | |
1075 | ||
1076 | verify_local_APIC(); | |
1077 | ||
1078 | /* | |
1079 | * If SMP should be disabled, then really disable it! | |
1080 | */ | |
1081 | if (!max_cpus) { | |
73d08e63 | 1082 | printk(KERN_INFO "SMP mode deactivated.\n"); |
8aef135c | 1083 | smpboot_clear_io_apic(); |
d54db1ac MR |
1084 | |
1085 | localise_nmi_watchdog(); | |
1086 | ||
e90955c2 | 1087 | connect_bsp_APIC(); |
e90955c2 JB |
1088 | setup_local_APIC(); |
1089 | end_local_APIC_setup(); | |
8aef135c GOC |
1090 | return -1; |
1091 | } | |
1092 | ||
1093 | return 0; | |
1094 | } | |
1095 | ||
1096 | static void __init smp_cpu_index_default(void) | |
1097 | { | |
1098 | int i; | |
1099 | struct cpuinfo_x86 *c; | |
1100 | ||
7c04e64a | 1101 | for_each_possible_cpu(i) { |
8aef135c GOC |
1102 | c = &cpu_data(i); |
1103 | /* mark all to hotplug */ | |
9628937d | 1104 | c->cpu_index = nr_cpu_ids; |
8aef135c GOC |
1105 | } |
1106 | } | |
1107 | ||
1108 | /* | |
1109 | * Prepare for SMP bootup. The MP table or ACPI has been read | |
1110 | * earlier. Just do some sanity checking here and enable APIC mode. | |
1111 | */ | |
1112 | void __init native_smp_prepare_cpus(unsigned int max_cpus) | |
1113 | { | |
deef3250 | 1114 | preempt_disable(); |
8aef135c GOC |
1115 | smp_cpu_index_default(); |
1116 | current_cpu_data = boot_cpu_data; | |
c2d1cec1 | 1117 | cpumask_copy(cpu_callin_mask, cpumask_of(0)); |
8aef135c GOC |
1118 | mb(); |
1119 | /* | |
1120 | * Setup boot CPU information | |
1121 | */ | |
1122 | smp_store_cpu_info(0); /* Final full version of the data */ | |
1b374e4d | 1123 | #ifdef CONFIG_X86_32 |
8aef135c | 1124 | boot_cpu_logical_apicid = logical_smp_processor_id(); |
1b374e4d | 1125 | #endif |
8aef135c GOC |
1126 | current_thread_info()->cpu = 0; /* needed? */ |
1127 | set_cpu_sibling_map(0); | |
1128 | ||
6e1cb38a SS |
1129 | #ifdef CONFIG_X86_64 |
1130 | enable_IR_x2apic(); | |
1131 | setup_apic_routing(); | |
1132 | #endif | |
1133 | ||
8aef135c GOC |
1134 | if (smp_sanity_check(max_cpus) < 0) { |
1135 | printk(KERN_INFO "SMP disabled\n"); | |
1136 | disable_smp(); | |
deef3250 | 1137 | goto out; |
8aef135c GOC |
1138 | } |
1139 | ||
ac23d4ee | 1140 | preempt_disable(); |
4c9961d5 | 1141 | if (read_apic_id() != boot_cpu_physical_apicid) { |
8aef135c | 1142 | panic("Boot APIC ID in local APIC unexpected (%d vs %d)", |
4c9961d5 | 1143 | read_apic_id(), boot_cpu_physical_apicid); |
8aef135c GOC |
1144 | /* Or can we switch back to PIC here? */ |
1145 | } | |
ac23d4ee | 1146 | preempt_enable(); |
8aef135c | 1147 | |
8aef135c | 1148 | connect_bsp_APIC(); |
b5841765 | 1149 | |
8aef135c GOC |
1150 | /* |
1151 | * Switch from PIC to APIC mode. | |
1152 | */ | |
1153 | setup_local_APIC(); | |
1154 | ||
1155 | #ifdef CONFIG_X86_64 | |
1156 | /* | |
1157 | * Enable IO APIC before setting up error vector | |
1158 | */ | |
1159 | if (!skip_ioapic_setup && nr_ioapics) | |
1160 | enable_IO_APIC(); | |
1161 | #endif | |
1162 | end_local_APIC_setup(); | |
1163 | ||
1164 | map_cpu_to_logical_apicid(); | |
1165 | ||
1166 | setup_portio_remap(); | |
1167 | ||
1168 | smpboot_setup_io_apic(); | |
1169 | /* | |
1170 | * Set up local APIC timer on boot CPU. | |
1171 | */ | |
1172 | ||
1173 | printk(KERN_INFO "CPU%d: ", 0); | |
1174 | print_cpu_info(&cpu_data(0)); | |
1175 | setup_boot_clock(); | |
c4bd1fda MS |
1176 | |
1177 | if (is_uv_system()) | |
1178 | uv_system_init(); | |
deef3250 IM |
1179 | out: |
1180 | preempt_enable(); | |
8aef135c | 1181 | } |
a8db8453 GOC |
1182 | /* |
1183 | * Early setup to make printk work. | |
1184 | */ | |
1185 | void __init native_smp_prepare_boot_cpu(void) | |
1186 | { | |
1187 | int me = smp_processor_id(); | |
a939098a | 1188 | switch_to_new_gdt(); |
c2d1cec1 MT |
1189 | /* already set me in cpu_online_mask in boot_cpu_init() */ |
1190 | cpumask_set_cpu(me, cpu_callout_mask); | |
a8db8453 GOC |
1191 | per_cpu(cpu_state, me) = CPU_ONLINE; |
1192 | } | |
1193 | ||
83f7eb9c GOC |
1194 | void __init native_smp_cpus_done(unsigned int max_cpus) |
1195 | { | |
cfc1b9a6 | 1196 | pr_debug("Boot done.\n"); |
83f7eb9c GOC |
1197 | |
1198 | impress_friends(); | |
1199 | smp_checks(); | |
1200 | #ifdef CONFIG_X86_IO_APIC | |
1201 | setup_ioapic_dest(); | |
1202 | #endif | |
1203 | check_nmi_watchdog(); | |
83f7eb9c GOC |
1204 | } |
1205 | ||
3b11ce7f MT |
1206 | static int __initdata setup_possible_cpus = -1; |
1207 | static int __init _setup_possible_cpus(char *str) | |
1208 | { | |
1209 | get_option(&str, &setup_possible_cpus); | |
1210 | return 0; | |
1211 | } | |
1212 | early_param("possible_cpus", _setup_possible_cpus); | |
1213 | ||
1214 | ||
68a1c3f8 GC |
1215 | /* |
1216 | * cpu_possible_map should be static, it cannot change as cpu's | |
1217 | * are onlined, or offlined. The reason is per-cpu data-structures | |
1218 | * are allocated by some modules at init time, and dont expect to | |
1219 | * do this dynamically on cpu arrival/departure. | |
1220 | * cpu_present_map on the other hand can change dynamically. | |
1221 | * In case when cpu_hotplug is not compiled, then we resort to current | |
1222 | * behaviour, which is cpu_possible == cpu_present. | |
1223 | * - Ashok Raj | |
1224 | * | |
1225 | * Three ways to find out the number of additional hotplug CPUs: | |
1226 | * - If the BIOS specified disabled CPUs in ACPI/mptables use that. | |
3b11ce7f | 1227 | * - The user can overwrite it with possible_cpus=NUM |
68a1c3f8 GC |
1228 | * - Otherwise don't reserve additional CPUs. |
1229 | * We do this because additional CPUs waste a lot of memory. | |
1230 | * -AK | |
1231 | */ | |
1232 | __init void prefill_possible_map(void) | |
1233 | { | |
cb48bb59 | 1234 | int i, possible; |
68a1c3f8 | 1235 | |
329513a3 YL |
1236 | /* no processor from mptable or madt */ |
1237 | if (!num_processors) | |
1238 | num_processors = 1; | |
1239 | ||
3b11ce7f MT |
1240 | if (setup_possible_cpus == -1) |
1241 | possible = num_processors + disabled_cpus; | |
1242 | else | |
1243 | possible = setup_possible_cpus; | |
1244 | ||
730cf272 MT |
1245 | total_cpus = max_t(int, possible, num_processors + disabled_cpus); |
1246 | ||
3b11ce7f MT |
1247 | if (possible > CONFIG_NR_CPUS) { |
1248 | printk(KERN_WARNING | |
1249 | "%d Processors exceeds NR_CPUS limit of %d\n", | |
1250 | possible, CONFIG_NR_CPUS); | |
1251 | possible = CONFIG_NR_CPUS; | |
1252 | } | |
68a1c3f8 GC |
1253 | |
1254 | printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n", | |
1255 | possible, max_t(int, possible - num_processors, 0)); | |
1256 | ||
1257 | for (i = 0; i < possible; i++) | |
c2d1cec1 | 1258 | set_cpu_possible(i, true); |
3461b0af MT |
1259 | |
1260 | nr_cpu_ids = possible; | |
68a1c3f8 | 1261 | } |
69c18c15 | 1262 | |
14adf855 CE |
1263 | #ifdef CONFIG_HOTPLUG_CPU |
1264 | ||
1265 | static void remove_siblinginfo(int cpu) | |
1266 | { | |
1267 | int sibling; | |
1268 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
1269 | ||
c2d1cec1 MT |
1270 | for_each_cpu(sibling, cpu_core_mask(cpu)) { |
1271 | cpumask_clear_cpu(cpu, cpu_core_mask(sibling)); | |
14adf855 CE |
1272 | /*/ |
1273 | * last thread sibling in this cpu core going down | |
1274 | */ | |
c2d1cec1 | 1275 | if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) |
14adf855 CE |
1276 | cpu_data(sibling).booted_cores--; |
1277 | } | |
1278 | ||
c2d1cec1 MT |
1279 | for_each_cpu(sibling, cpu_sibling_mask(cpu)) |
1280 | cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling)); | |
1281 | cpumask_clear(cpu_sibling_mask(cpu)); | |
1282 | cpumask_clear(cpu_core_mask(cpu)); | |
14adf855 CE |
1283 | c->phys_proc_id = 0; |
1284 | c->cpu_core_id = 0; | |
c2d1cec1 | 1285 | cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); |
14adf855 CE |
1286 | } |
1287 | ||
69c18c15 GC |
1288 | static void __ref remove_cpu_from_maps(int cpu) |
1289 | { | |
c2d1cec1 MT |
1290 | set_cpu_online(cpu, false); |
1291 | cpumask_clear_cpu(cpu, cpu_callout_mask); | |
1292 | cpumask_clear_cpu(cpu, cpu_callin_mask); | |
69c18c15 | 1293 | /* was set by cpu_init() */ |
c2d1cec1 | 1294 | cpumask_clear_cpu(cpu, cpu_initialized_mask); |
23ca4bba | 1295 | numa_remove_cpu(cpu); |
69c18c15 GC |
1296 | } |
1297 | ||
8227dce7 | 1298 | void cpu_disable_common(void) |
69c18c15 GC |
1299 | { |
1300 | int cpu = smp_processor_id(); | |
69c18c15 GC |
1301 | /* |
1302 | * HACK: | |
1303 | * Allow any queued timer interrupts to get serviced | |
1304 | * This is only a temporary solution until we cleanup | |
1305 | * fixup_irqs as we do for IA64. | |
1306 | */ | |
1307 | local_irq_enable(); | |
1308 | mdelay(1); | |
1309 | ||
1310 | local_irq_disable(); | |
1311 | remove_siblinginfo(cpu); | |
1312 | ||
1313 | /* It's now safe to remove this processor from the online map */ | |
d388e5fd | 1314 | lock_vector_lock(); |
69c18c15 | 1315 | remove_cpu_from_maps(cpu); |
d388e5fd | 1316 | unlock_vector_lock(); |
d7b381bb | 1317 | fixup_irqs(); |
8227dce7 AN |
1318 | } |
1319 | ||
1320 | int native_cpu_disable(void) | |
1321 | { | |
1322 | int cpu = smp_processor_id(); | |
1323 | ||
1324 | /* | |
1325 | * Perhaps use cpufreq to drop frequency, but that could go | |
1326 | * into generic code. | |
1327 | * | |
1328 | * We won't take down the boot processor on i386 due to some | |
1329 | * interrupts only being able to be serviced by the BSP. | |
1330 | * Especially so if we're not using an IOAPIC -zwane | |
1331 | */ | |
1332 | if (cpu == 0) | |
1333 | return -EBUSY; | |
1334 | ||
1335 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
1336 | stop_apic_nmi_watchdog(NULL); | |
1337 | clear_local_APIC(); | |
1338 | ||
1339 | cpu_disable_common(); | |
69c18c15 GC |
1340 | return 0; |
1341 | } | |
1342 | ||
93be71b6 | 1343 | void native_cpu_die(unsigned int cpu) |
69c18c15 GC |
1344 | { |
1345 | /* We don't do anything here: idle task is faking death itself. */ | |
1346 | unsigned int i; | |
1347 | ||
1348 | for (i = 0; i < 10; i++) { | |
1349 | /* They ack this in play_dead by setting CPU_DEAD */ | |
1350 | if (per_cpu(cpu_state, cpu) == CPU_DEAD) { | |
1351 | printk(KERN_INFO "CPU %d is now offline\n", cpu); | |
1352 | if (1 == num_online_cpus()) | |
1353 | alternatives_smp_switch(0); | |
1354 | return; | |
1355 | } | |
1356 | msleep(100); | |
1357 | } | |
1358 | printk(KERN_ERR "CPU %u didn't die...\n", cpu); | |
1359 | } | |
a21f5d88 AN |
1360 | |
1361 | void play_dead_common(void) | |
1362 | { | |
1363 | idle_task_exit(); | |
1364 | reset_lazy_tlbstate(); | |
1365 | irq_ctx_exit(raw_smp_processor_id()); | |
07bbc16a | 1366 | c1e_remove_cpu(raw_smp_processor_id()); |
a21f5d88 AN |
1367 | |
1368 | mb(); | |
1369 | /* Ack it */ | |
1370 | __get_cpu_var(cpu_state) = CPU_DEAD; | |
1371 | ||
1372 | /* | |
1373 | * With physical CPU hotplug, we should halt the cpu | |
1374 | */ | |
1375 | local_irq_disable(); | |
1376 | } | |
1377 | ||
1378 | void native_play_dead(void) | |
1379 | { | |
1380 | play_dead_common(); | |
1381 | wbinvd_halt(); | |
1382 | } | |
1383 | ||
69c18c15 | 1384 | #else /* ... !CONFIG_HOTPLUG_CPU */ |
93be71b6 | 1385 | int native_cpu_disable(void) |
69c18c15 GC |
1386 | { |
1387 | return -ENOSYS; | |
1388 | } | |
1389 | ||
93be71b6 | 1390 | void native_cpu_die(unsigned int cpu) |
69c18c15 GC |
1391 | { |
1392 | /* We said "no" in __cpu_disable */ | |
1393 | BUG(); | |
1394 | } | |
a21f5d88 AN |
1395 | |
1396 | void native_play_dead(void) | |
1397 | { | |
1398 | BUG(); | |
1399 | } | |
1400 | ||
68a1c3f8 | 1401 | #endif |