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9ff554e9 | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
0941ecb5 GC |
2 | /* |
3 | * Intel SMP support routines. | |
4 | * | |
87c6fe26 | 5 | * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> |
8f47e163 | 6 | * (c) 1998-99, 2000, 2009 Ingo Molnar <mingo@redhat.com> |
0941ecb5 GC |
7 | * (c) 2002,2003 Andi Kleen, SuSE Labs. |
8 | * | |
9 | * i386 and x86_64 integration by Glauber Costa <gcosta@redhat.com> | |
0941ecb5 GC |
10 | */ |
11 | ||
f9e47a12 GC |
12 | #include <linux/init.h> |
13 | ||
14 | #include <linux/mm.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/spinlock.h> | |
69c60c88 | 17 | #include <linux/export.h> |
f9e47a12 GC |
18 | #include <linux/kernel_stat.h> |
19 | #include <linux/mc146818rtc.h> | |
20 | #include <linux/cache.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/cpu.h> | |
5a0e3ad6 | 23 | #include <linux/gfp.h> |
d7893093 | 24 | #include <linux/kexec.h> |
f9e47a12 GC |
25 | |
26 | #include <asm/mtrr.h> | |
27 | #include <asm/tlbflush.h> | |
28 | #include <asm/mmu_context.h> | |
29 | #include <asm/proto.h> | |
7b6aa335 | 30 | #include <asm/apic.h> |
1f5e7eb7 | 31 | #include <asm/cpu.h> |
582f9191 | 32 | #include <asm/idtentry.h> |
7d007d21 | 33 | #include <asm/nmi.h> |
8838eb6c | 34 | #include <asm/mce.h> |
cf910e83 | 35 | #include <asm/trace/irq_vectors.h> |
0ee59413 | 36 | #include <asm/kexec.h> |
a2b07fa7 | 37 | #include <asm/reboot.h> |
0ee59413 | 38 | |
0941ecb5 GC |
39 | /* |
40 | * Some notes on x86 processor bugs affecting SMP operation: | |
41 | * | |
42 | * Pentium, Pentium Pro, II, III (and all CPUs) have bugs. | |
43 | * The Linux implications for SMP are handled as follows: | |
44 | * | |
45 | * Pentium III / [Xeon] | |
46 | * None of the E1AP-E3AP errata are visible to the user. | |
47 | * | |
48 | * E1AP. see PII A1AP | |
49 | * E2AP. see PII A2AP | |
50 | * E3AP. see PII A3AP | |
51 | * | |
52 | * Pentium II / [Xeon] | |
53 | * None of the A1AP-A3AP errata are visible to the user. | |
54 | * | |
55 | * A1AP. see PPro 1AP | |
56 | * A2AP. see PPro 2AP | |
57 | * A3AP. see PPro 7AP | |
58 | * | |
59 | * Pentium Pro | |
60 | * None of 1AP-9AP errata are visible to the normal user, | |
61 | * except occasional delivery of 'spurious interrupt' as trap #15. | |
62 | * This is very rare and a non-problem. | |
63 | * | |
64 | * 1AP. Linux maps APIC as non-cacheable | |
65 | * 2AP. worked around in hardware | |
66 | * 3AP. fixed in C0 and above steppings microcode update. | |
67 | * Linux does not use excessive STARTUP_IPIs. | |
68 | * 4AP. worked around in hardware | |
69 | * 5AP. symmetric IO mode (normal Linux operation) not affected. | |
70 | * 'noapic' mode has vector 0xf filled out properly. | |
71 | * 6AP. 'noapic' mode might be affected - fixed in later steppings | |
d9f6e12f | 72 | * 7AP. We do not assume writes to the LVT deasserting IRQs |
0941ecb5 GC |
73 | * 8AP. We do not enable low power mode (deep sleep) during MP bootup |
74 | * 9AP. We do not use mixed mode | |
75 | * | |
76 | * Pentium | |
77 | * There is a marginal case where REP MOVS on 100MHz SMP | |
78 | * machines with B stepping processors can fail. XXX should provide | |
79 | * an L1cache=Writethrough or L1cache=off option. | |
80 | * | |
81 | * B stepping CPUs may hang. There are hardware work arounds | |
82 | * for this. We warn about it in case your board doesn't have the work | |
83 | * arounds. Basically that's so I can tell anyone with a B stepping | |
84 | * CPU and SMP problems "tough". | |
85 | * | |
86 | * Specific items [From Pentium Processor Specification Update] | |
87 | * | |
88 | * 1AP. Linux doesn't use remote read | |
89 | * 2AP. Linux doesn't trust APIC errors | |
90 | * 3AP. We work around this | |
91 | * 4AP. Linux never generated 3 interrupts of the same priority | |
92 | * to cause a lost local interrupt. | |
93 | * 5AP. Remote read is never used | |
94 | * 6AP. not affected - worked around in hardware | |
95 | * 7AP. not affected - worked around in hardware | |
96 | * 8AP. worked around in hardware - we get explicit CS errors if not | |
97 | * 9AP. only 'noapic' mode affected. Might generate spurious | |
98 | * interrupts, we log only the first one and count the | |
99 | * rest silently. | |
100 | * 10AP. not affected - worked around in hardware | |
101 | * 11AP. Linux reads the APIC between writes to avoid this, as per | |
102 | * the documentation. Make sure you preserve this as it affects | |
103 | * the C stepping chips too. | |
104 | * 12AP. not affected - worked around in hardware | |
105 | * 13AP. not affected - worked around in hardware | |
106 | * 14AP. we always deassert INIT during bootup | |
107 | * 15AP. not affected - worked around in hardware | |
108 | * 16AP. not affected - worked around in hardware | |
109 | * 17AP. not affected - worked around in hardware | |
110 | * 18AP. not affected - worked around in hardware | |
111 | * 19AP. not affected - worked around in BIOS | |
112 | * | |
113 | * If this sounds worrying believe me these bugs are either ___RARE___, | |
114 | * or are signal timing bugs worked around in hardware and there's | |
115 | * about nothing of note with C stepping upwards. | |
116 | */ | |
f9e47a12 | 117 | |
7d007d21 | 118 | static atomic_t stopping_cpu = ATOMIC_INIT(-1); |
3aac27ab | 119 | static bool smp_no_nmi_ipi = false; |
7d007d21 | 120 | |
7d007d21 DZ |
121 | static int smp_stop_nmi_callback(unsigned int val, struct pt_regs *regs) |
122 | { | |
123 | /* We are registered on stopping cpu too, avoid spurious NMI */ | |
124 | if (raw_smp_processor_id() == atomic_read(&stopping_cpu)) | |
125 | return NMI_HANDLED; | |
126 | ||
a2b07fa7 | 127 | cpu_emergency_disable_virtualization(); |
7d007d21 DZ |
128 | stop_this_cpu(NULL); |
129 | ||
130 | return NMI_HANDLED; | |
131 | } | |
132 | ||
f9e47a12 | 133 | /* |
fbe1bf1e | 134 | * this function calls the 'stop' function on all other CPUs in the system. |
f9e47a12 | 135 | */ |
582f9191 | 136 | DEFINE_IDTENTRY_SYSVEC(sysvec_reboot) |
4ef702c1 | 137 | { |
670c04ad | 138 | apic_eoi(); |
a2b07fa7 | 139 | cpu_emergency_disable_virtualization(); |
4ef702c1 | 140 | stop_this_cpu(NULL); |
4ef702c1 AK |
141 | } |
142 | ||
747d5a1b GH |
143 | static int register_stop_handler(void) |
144 | { | |
145 | return register_nmi_handler(NMI_LOCAL, smp_stop_nmi_callback, | |
146 | NMI_FLAG_FIRST, "smp_stop"); | |
147 | } | |
148 | ||
5d2b86d9 | 149 | static void native_stop_other_cpus(int wait) |
f9e47a12 | 150 | { |
9e9d673b | 151 | unsigned int old_cpu, this_cpu; |
1f5e7eb7 | 152 | unsigned long flags, timeout; |
f9e47a12 GC |
153 | |
154 | if (reboot_force) | |
155 | return; | |
156 | ||
1f5e7eb7 | 157 | /* Only proceed if this is the first CPU to reach this code */ |
9e9d673b | 158 | old_cpu = -1; |
9d1c8f21 | 159 | this_cpu = smp_processor_id(); |
9e9d673b | 160 | if (!atomic_try_cmpxchg(&stopping_cpu, &old_cpu, this_cpu)) |
1f5e7eb7 | 161 | return; |
7d007d21 | 162 | |
d7893093 TG |
163 | /* For kexec, ensure that offline CPUs are out of MWAIT and in HLT */ |
164 | if (kexec_in_progress) | |
165 | smp_kick_mwait_play_dead(); | |
7d007d21 DZ |
166 | |
167 | /* | |
1f5e7eb7 TG |
168 | * 1) Send an IPI on the reboot vector to all other CPUs. |
169 | * | |
170 | * The other CPUs should react on it after leaving critical | |
171 | * sections and re-enabling interrupts. They might still hold | |
172 | * locks, but there is nothing which can be done about that. | |
173 | * | |
174 | * 2) Wait for all other CPUs to report that they reached the | |
175 | * HLT loop in stop_this_cpu() | |
176 | * | |
fbe1bf1e LT |
177 | * 3) If #2 timed out send an NMI to the CPUs which did not |
178 | * yet report | |
1f5e7eb7 | 179 | * |
fbe1bf1e | 180 | * 4) Wait for all other CPUs to report that they reached the |
1f5e7eb7 TG |
181 | * HLT loop in stop_this_cpu() |
182 | * | |
fbe1bf1e | 183 | * #3 can obviously race against a CPU reaching the HLT loop late. |
1f5e7eb7 TG |
184 | * That CPU will have reported already and the "have all CPUs |
185 | * reached HLT" condition will be true despite the fact that the | |
186 | * other CPU is still handling the NMI. Again, there is no | |
187 | * protection against that as "disabled" APICs still respond to | |
188 | * NMIs. | |
4ef702c1 | 189 | */ |
1f5e7eb7 | 190 | cpumask_copy(&cpus_stop_mask, cpu_online_mask); |
9d1c8f21 | 191 | cpumask_clear_cpu(this_cpu, &cpus_stop_mask); |
7d007d21 | 192 | |
1f5e7eb7 | 193 | if (!cpumask_empty(&cpus_stop_mask)) { |
22ca7ee9 | 194 | apic_send_IPI_allbutself(REBOOT_VECTOR); |
4ef702c1 | 195 | |
76fac077 | 196 | /* |
747d5a1b GH |
197 | * Don't wait longer than a second for IPI completion. The |
198 | * wait request is not checked here because that would | |
fbe1bf1e | 199 | * prevent an NMI shutdown attempt in case that not all |
747d5a1b | 200 | * CPUs reach shutdown state. |
76fac077 AK |
201 | */ |
202 | timeout = USEC_PER_SEC; | |
1f5e7eb7 | 203 | while (!cpumask_empty(&cpus_stop_mask) && timeout--) |
4ef702c1 AK |
204 | udelay(1); |
205 | } | |
7d007d21 | 206 | |
fbe1bf1e | 207 | /* if the REBOOT_VECTOR didn't work, try with the NMI */ |
1f5e7eb7 | 208 | if (!cpumask_empty(&cpus_stop_mask)) { |
747d5a1b GH |
209 | /* |
210 | * If NMI IPI is enabled, try to register the stop handler | |
211 | * and send the IPI. In any case try to wait for the other | |
212 | * CPUs to stop. | |
213 | */ | |
214 | if (!smp_no_nmi_ipi && !register_stop_handler()) { | |
9d1c8f21 UB |
215 | unsigned int cpu; |
216 | ||
747d5a1b | 217 | pr_emerg("Shutting down cpus with NMI\n"); |
7d007d21 | 218 | |
1f5e7eb7 | 219 | for_each_cpu(cpu, &cpus_stop_mask) |
28b82352 | 220 | __apic_send_IPI(cpu, NMI_VECTOR); |
747d5a1b | 221 | } |
7d007d21 | 222 | /* |
747d5a1b | 223 | * Don't wait longer than 10 ms if the caller didn't |
163b0991 | 224 | * request it. If wait is true, the machine hangs here if |
747d5a1b | 225 | * one or more CPUs do not reach shutdown state. |
7d007d21 DZ |
226 | */ |
227 | timeout = USEC_PER_MSEC * 10; | |
1f5e7eb7 | 228 | while (!cpumask_empty(&cpus_stop_mask) && (wait || timeout--)) |
7d007d21 DZ |
229 | udelay(1); |
230 | } | |
4ef702c1 | 231 | |
f9e47a12 | 232 | local_irq_save(flags); |
f9e47a12 | 233 | disable_local_APIC(); |
8838eb6c | 234 | mcheck_cpu_clear(this_cpu_ptr(&cpu_info)); |
f9e47a12 | 235 | local_irq_restore(flags); |
1f5e7eb7 TG |
236 | |
237 | /* | |
238 | * Ensure that the cpus_stop_mask cache lines are invalidated on | |
239 | * the other CPUs. See comment vs. SME in stop_this_cpu(). | |
240 | */ | |
241 | cpumask_clear(&cpus_stop_mask); | |
f9e47a12 GC |
242 | } |
243 | ||
244 | /* | |
3cd788c1 | 245 | * Reschedule call back. KVM uses this interrupt to force a cpu out of |
13cad985 | 246 | * guest mode. |
f9e47a12 | 247 | */ |
13cad985 | 248 | DEFINE_IDTENTRY_SYSVEC_SIMPLE(sysvec_reschedule_ipi) |
eddc0e92 | 249 | { |
670c04ad | 250 | apic_eoi(); |
13cad985 | 251 | trace_reschedule_entry(RESCHEDULE_VECTOR); |
85b77cdd TG |
252 | inc_irq_stat(irq_resched_count); |
253 | scheduler_ipi(); | |
13cad985 | 254 | trace_reschedule_exit(RESCHEDULE_VECTOR); |
3b16cf87 | 255 | } |
f9e47a12 | 256 | |
582f9191 | 257 | DEFINE_IDTENTRY_SYSVEC(sysvec_call_function) |
cf910e83 | 258 | { |
670c04ad | 259 | apic_eoi(); |
cf910e83 | 260 | trace_call_function_entry(CALL_FUNCTION_VECTOR); |
915b0d01 | 261 | inc_irq_stat(irq_call_count); |
85b77cdd TG |
262 | generic_smp_call_function_interrupt(); |
263 | trace_call_function_exit(CALL_FUNCTION_VECTOR); | |
f9e47a12 GC |
264 | } |
265 | ||
582f9191 | 266 | DEFINE_IDTENTRY_SYSVEC(sysvec_call_function_single) |
cf910e83 | 267 | { |
670c04ad | 268 | apic_eoi(); |
cf910e83 | 269 | trace_call_function_single_entry(CALL_FUNCTION_SINGLE_VECTOR); |
85b77cdd TG |
270 | inc_irq_stat(irq_call_count); |
271 | generic_smp_call_function_single_interrupt(); | |
cf910e83 | 272 | trace_call_function_single_exit(CALL_FUNCTION_SINGLE_VECTOR); |
cf910e83 SA |
273 | } |
274 | ||
bda62633 DZ |
275 | static int __init nonmi_ipi_setup(char *str) |
276 | { | |
3aac27ab DZ |
277 | smp_no_nmi_ipi = true; |
278 | return 1; | |
bda62633 DZ |
279 | } |
280 | ||
281 | __setup("nonmi_ipi", nonmi_ipi_setup); | |
282 | ||
f9e47a12 | 283 | struct smp_ops smp_ops = { |
b9b34f24 CG |
284 | .smp_prepare_boot_cpu = native_smp_prepare_boot_cpu, |
285 | .smp_prepare_cpus = native_smp_prepare_cpus, | |
286 | .smp_cpus_done = native_smp_cpus_done, | |
f9e47a12 | 287 | |
5d2b86d9 | 288 | .stop_other_cpus = native_stop_other_cpus, |
a4eeb217 | 289 | #if defined(CONFIG_CRASH_DUMP) |
0ee59413 HK |
290 | .crash_stop_other_cpus = kdump_nmi_shootdown_cpus, |
291 | #endif | |
b9b34f24 | 292 | .smp_send_reschedule = native_smp_send_reschedule, |
3b16cf87 | 293 | |
8b5a0f95 | 294 | .kick_ap_alive = native_kick_ap, |
b9b34f24 CG |
295 | .cpu_disable = native_cpu_disable, |
296 | .play_dead = native_play_dead, | |
93be71b6 | 297 | |
b9b34f24 | 298 | .send_call_func_ipi = native_send_call_func_ipi, |
3b16cf87 | 299 | .send_call_func_single_ipi = native_send_call_func_single_ipi, |
f9e47a12 GC |
300 | }; |
301 | EXPORT_SYMBOL_GPL(smp_ops); |