Commit | Line | Data |
---|---|---|
0941ecb5 GC |
1 | /* |
2 | * Intel SMP support routines. | |
3 | * | |
87c6fe26 | 4 | * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> |
8f47e163 | 5 | * (c) 1998-99, 2000, 2009 Ingo Molnar <mingo@redhat.com> |
0941ecb5 GC |
6 | * (c) 2002,2003 Andi Kleen, SuSE Labs. |
7 | * | |
8 | * i386 and x86_64 integration by Glauber Costa <gcosta@redhat.com> | |
9 | * | |
10 | * This code is released under the GNU General Public License version 2 or | |
11 | * later. | |
12 | */ | |
13 | ||
f9e47a12 GC |
14 | #include <linux/init.h> |
15 | ||
16 | #include <linux/mm.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/spinlock.h> | |
69c60c88 | 19 | #include <linux/export.h> |
f9e47a12 GC |
20 | #include <linux/kernel_stat.h> |
21 | #include <linux/mc146818rtc.h> | |
22 | #include <linux/cache.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/cpu.h> | |
5a0e3ad6 | 25 | #include <linux/gfp.h> |
f9e47a12 GC |
26 | |
27 | #include <asm/mtrr.h> | |
28 | #include <asm/tlbflush.h> | |
29 | #include <asm/mmu_context.h> | |
30 | #include <asm/proto.h> | |
7b6aa335 | 31 | #include <asm/apic.h> |
7d007d21 | 32 | #include <asm/nmi.h> |
8838eb6c | 33 | #include <asm/mce.h> |
cf910e83 | 34 | #include <asm/trace/irq_vectors.h> |
0941ecb5 GC |
35 | /* |
36 | * Some notes on x86 processor bugs affecting SMP operation: | |
37 | * | |
38 | * Pentium, Pentium Pro, II, III (and all CPUs) have bugs. | |
39 | * The Linux implications for SMP are handled as follows: | |
40 | * | |
41 | * Pentium III / [Xeon] | |
42 | * None of the E1AP-E3AP errata are visible to the user. | |
43 | * | |
44 | * E1AP. see PII A1AP | |
45 | * E2AP. see PII A2AP | |
46 | * E3AP. see PII A3AP | |
47 | * | |
48 | * Pentium II / [Xeon] | |
49 | * None of the A1AP-A3AP errata are visible to the user. | |
50 | * | |
51 | * A1AP. see PPro 1AP | |
52 | * A2AP. see PPro 2AP | |
53 | * A3AP. see PPro 7AP | |
54 | * | |
55 | * Pentium Pro | |
56 | * None of 1AP-9AP errata are visible to the normal user, | |
57 | * except occasional delivery of 'spurious interrupt' as trap #15. | |
58 | * This is very rare and a non-problem. | |
59 | * | |
60 | * 1AP. Linux maps APIC as non-cacheable | |
61 | * 2AP. worked around in hardware | |
62 | * 3AP. fixed in C0 and above steppings microcode update. | |
63 | * Linux does not use excessive STARTUP_IPIs. | |
64 | * 4AP. worked around in hardware | |
65 | * 5AP. symmetric IO mode (normal Linux operation) not affected. | |
66 | * 'noapic' mode has vector 0xf filled out properly. | |
67 | * 6AP. 'noapic' mode might be affected - fixed in later steppings | |
68 | * 7AP. We do not assume writes to the LVT deassering IRQs | |
69 | * 8AP. We do not enable low power mode (deep sleep) during MP bootup | |
70 | * 9AP. We do not use mixed mode | |
71 | * | |
72 | * Pentium | |
73 | * There is a marginal case where REP MOVS on 100MHz SMP | |
74 | * machines with B stepping processors can fail. XXX should provide | |
75 | * an L1cache=Writethrough or L1cache=off option. | |
76 | * | |
77 | * B stepping CPUs may hang. There are hardware work arounds | |
78 | * for this. We warn about it in case your board doesn't have the work | |
79 | * arounds. Basically that's so I can tell anyone with a B stepping | |
80 | * CPU and SMP problems "tough". | |
81 | * | |
82 | * Specific items [From Pentium Processor Specification Update] | |
83 | * | |
84 | * 1AP. Linux doesn't use remote read | |
85 | * 2AP. Linux doesn't trust APIC errors | |
86 | * 3AP. We work around this | |
87 | * 4AP. Linux never generated 3 interrupts of the same priority | |
88 | * to cause a lost local interrupt. | |
89 | * 5AP. Remote read is never used | |
90 | * 6AP. not affected - worked around in hardware | |
91 | * 7AP. not affected - worked around in hardware | |
92 | * 8AP. worked around in hardware - we get explicit CS errors if not | |
93 | * 9AP. only 'noapic' mode affected. Might generate spurious | |
94 | * interrupts, we log only the first one and count the | |
95 | * rest silently. | |
96 | * 10AP. not affected - worked around in hardware | |
97 | * 11AP. Linux reads the APIC between writes to avoid this, as per | |
98 | * the documentation. Make sure you preserve this as it affects | |
99 | * the C stepping chips too. | |
100 | * 12AP. not affected - worked around in hardware | |
101 | * 13AP. not affected - worked around in hardware | |
102 | * 14AP. we always deassert INIT during bootup | |
103 | * 15AP. not affected - worked around in hardware | |
104 | * 16AP. not affected - worked around in hardware | |
105 | * 17AP. not affected - worked around in hardware | |
106 | * 18AP. not affected - worked around in hardware | |
107 | * 19AP. not affected - worked around in BIOS | |
108 | * | |
109 | * If this sounds worrying believe me these bugs are either ___RARE___, | |
110 | * or are signal timing bugs worked around in hardware and there's | |
111 | * about nothing of note with C stepping upwards. | |
112 | */ | |
f9e47a12 | 113 | |
7d007d21 | 114 | static atomic_t stopping_cpu = ATOMIC_INIT(-1); |
3aac27ab | 115 | static bool smp_no_nmi_ipi = false; |
7d007d21 | 116 | |
539da787 LT |
117 | /* |
118 | * Helper wrapper: not all apic definitions support sending to | |
119 | * a single CPU, so we fall back to sending to a mask. | |
120 | */ | |
121 | static void send_IPI_cpu(int cpu, int vector) | |
122 | { | |
123 | if (apic->send_IPI) | |
124 | apic->send_IPI(cpu, vector); | |
125 | else | |
126 | apic->send_IPI_mask(cpumask_of(cpu), vector); | |
127 | } | |
128 | ||
f9e47a12 GC |
129 | /* |
130 | * this function sends a 'reschedule' IPI to another CPU. | |
131 | * it goes straight through and wastes no time serializing | |
132 | * anything. Worst case is that we lose a reschedule ... | |
133 | */ | |
134 | static void native_smp_send_reschedule(int cpu) | |
135 | { | |
f6940101 GS |
136 | if (unlikely(cpu_is_offline(cpu))) { |
137 | WARN_ON(1); | |
138 | return; | |
139 | } | |
539da787 | 140 | send_IPI_cpu(cpu, RESCHEDULE_VECTOR); |
f9e47a12 GC |
141 | } |
142 | ||
3b16cf87 | 143 | void native_send_call_func_single_ipi(int cpu) |
f9e47a12 | 144 | { |
539da787 | 145 | send_IPI_cpu(cpu, CALL_FUNCTION_SINGLE_VECTOR); |
f9e47a12 GC |
146 | } |
147 | ||
bcda016e | 148 | void native_send_call_func_ipi(const struct cpumask *mask) |
f9e47a12 | 149 | { |
c2d1cec1 | 150 | cpumask_var_t allbutself; |
f9e47a12 | 151 | |
c2d1cec1 | 152 | if (!alloc_cpumask_var(&allbutself, GFP_ATOMIC)) { |
dac5f412 | 153 | apic->send_IPI_mask(mask, CALL_FUNCTION_VECTOR); |
c2d1cec1 MT |
154 | return; |
155 | } | |
f9e47a12 | 156 | |
c2d1cec1 MT |
157 | cpumask_copy(allbutself, cpu_online_mask); |
158 | cpumask_clear_cpu(smp_processor_id(), allbutself); | |
159 | ||
160 | if (cpumask_equal(mask, allbutself) && | |
161 | cpumask_equal(cpu_online_mask, cpu_callout_mask)) | |
dac5f412 | 162 | apic->send_IPI_allbutself(CALL_FUNCTION_VECTOR); |
f9e47a12 | 163 | else |
dac5f412 | 164 | apic->send_IPI_mask(mask, CALL_FUNCTION_VECTOR); |
c2d1cec1 MT |
165 | |
166 | free_cpumask_var(allbutself); | |
f9e47a12 GC |
167 | } |
168 | ||
7d007d21 DZ |
169 | static int smp_stop_nmi_callback(unsigned int val, struct pt_regs *regs) |
170 | { | |
171 | /* We are registered on stopping cpu too, avoid spurious NMI */ | |
172 | if (raw_smp_processor_id() == atomic_read(&stopping_cpu)) | |
173 | return NMI_HANDLED; | |
174 | ||
175 | stop_this_cpu(NULL); | |
176 | ||
177 | return NMI_HANDLED; | |
178 | } | |
179 | ||
f9e47a12 GC |
180 | /* |
181 | * this function calls the 'stop' function on all other CPUs in the system. | |
182 | */ | |
183 | ||
2605fc21 | 184 | asmlinkage __visible void smp_reboot_interrupt(void) |
4ef702c1 | 185 | { |
6dc17876 | 186 | ipi_entering_ack_irq(); |
4ef702c1 AK |
187 | stop_this_cpu(NULL); |
188 | irq_exit(); | |
189 | } | |
190 | ||
5d2b86d9 | 191 | static void native_stop_other_cpus(int wait) |
f9e47a12 | 192 | { |
f9e47a12 | 193 | unsigned long flags; |
76fac077 | 194 | unsigned long timeout; |
f9e47a12 GC |
195 | |
196 | if (reboot_force) | |
197 | return; | |
198 | ||
4ef702c1 AK |
199 | /* |
200 | * Use an own vector here because smp_call_function | |
201 | * does lots of things not suitable in a panic situation. | |
7d007d21 DZ |
202 | */ |
203 | ||
204 | /* | |
205 | * We start by using the REBOOT_VECTOR irq. | |
206 | * The irq is treated as a sync point to allow critical | |
207 | * regions of code on other cpus to release their spin locks | |
208 | * and re-enable irqs. Jumping straight to an NMI might | |
209 | * accidentally cause deadlocks with further shutdown/panic | |
210 | * code. By syncing, we give the cpus up to one second to | |
211 | * finish their work before we force them off with the NMI. | |
4ef702c1 AK |
212 | */ |
213 | if (num_online_cpus() > 1) { | |
7d007d21 DZ |
214 | /* did someone beat us here? */ |
215 | if (atomic_cmpxchg(&stopping_cpu, -1, safe_smp_processor_id()) != -1) | |
216 | return; | |
217 | ||
218 | /* sync above data before sending IRQ */ | |
219 | wmb(); | |
220 | ||
4ef702c1 AK |
221 | apic->send_IPI_allbutself(REBOOT_VECTOR); |
222 | ||
76fac077 AK |
223 | /* |
224 | * Don't wait longer than a second if the caller | |
225 | * didn't ask us to wait. | |
226 | */ | |
227 | timeout = USEC_PER_SEC; | |
228 | while (num_online_cpus() > 1 && (wait || timeout--)) | |
4ef702c1 AK |
229 | udelay(1); |
230 | } | |
7d007d21 DZ |
231 | |
232 | /* if the REBOOT_VECTOR didn't work, try with the NMI */ | |
3aac27ab | 233 | if ((num_online_cpus() > 1) && (!smp_no_nmi_ipi)) { |
7d007d21 DZ |
234 | if (register_nmi_handler(NMI_LOCAL, smp_stop_nmi_callback, |
235 | NMI_FLAG_FIRST, "smp_stop")) | |
236 | /* Note: we ignore failures here */ | |
237 | /* Hope the REBOOT_IRQ is good enough */ | |
238 | goto finish; | |
239 | ||
240 | /* sync above data before sending IRQ */ | |
241 | wmb(); | |
242 | ||
243 | pr_emerg("Shutting down cpus with NMI\n"); | |
244 | ||
245 | apic->send_IPI_allbutself(NMI_VECTOR); | |
246 | ||
247 | /* | |
248 | * Don't wait longer than a 10 ms if the caller | |
249 | * didn't ask us to wait. | |
250 | */ | |
251 | timeout = USEC_PER_MSEC * 10; | |
252 | while (num_online_cpus() > 1 && (wait || timeout--)) | |
253 | udelay(1); | |
254 | } | |
4ef702c1 | 255 | |
7d007d21 | 256 | finish: |
f9e47a12 | 257 | local_irq_save(flags); |
f9e47a12 | 258 | disable_local_APIC(); |
8838eb6c | 259 | mcheck_cpu_clear(this_cpu_ptr(&cpu_info)); |
f9e47a12 GC |
260 | local_irq_restore(flags); |
261 | } | |
262 | ||
263 | /* | |
184748cc | 264 | * Reschedule call back. |
f9e47a12 | 265 | */ |
eddc0e92 | 266 | static inline void __smp_reschedule_interrupt(void) |
f9e47a12 | 267 | { |
915b0d01 | 268 | inc_irq_stat(irq_resched_count); |
184748cc | 269 | scheduler_ipi(); |
eddc0e92 SA |
270 | } |
271 | ||
1d9090e2 | 272 | __visible void smp_reschedule_interrupt(struct pt_regs *regs) |
eddc0e92 SA |
273 | { |
274 | ack_APIC_irq(); | |
275 | __smp_reschedule_interrupt(); | |
32f88400 MT |
276 | /* |
277 | * KVM uses this interrupt to force a cpu out of guest mode | |
278 | */ | |
f9e47a12 GC |
279 | } |
280 | ||
1d9090e2 | 281 | __visible void smp_trace_reschedule_interrupt(struct pt_regs *regs) |
4787c368 SA |
282 | { |
283 | /* | |
284 | * Need to call irq_enter() before calling the trace point. | |
285 | * __smp_reschedule_interrupt() calls irq_enter/exit() too (in | |
286 | * scheduler_ipi(). This is OK, since those functions are allowed | |
287 | * to nest. | |
288 | */ | |
6dc17876 | 289 | ipi_entering_ack_irq(); |
cf910e83 SA |
290 | trace_reschedule_entry(RESCHEDULE_VECTOR); |
291 | __smp_reschedule_interrupt(); | |
292 | trace_reschedule_exit(RESCHEDULE_VECTOR); | |
4787c368 | 293 | exiting_irq(); |
cf910e83 SA |
294 | /* |
295 | * KVM uses this interrupt to force a cpu out of guest mode | |
296 | */ | |
297 | } | |
298 | ||
eddc0e92 SA |
299 | static inline void __smp_call_function_interrupt(void) |
300 | { | |
3b16cf87 | 301 | generic_smp_call_function_interrupt(); |
915b0d01 | 302 | inc_irq_stat(irq_call_count); |
3b16cf87 | 303 | } |
f9e47a12 | 304 | |
1d9090e2 | 305 | __visible void smp_call_function_interrupt(struct pt_regs *regs) |
eddc0e92 | 306 | { |
6dc17876 | 307 | ipi_entering_ack_irq(); |
eddc0e92 SA |
308 | __smp_call_function_interrupt(); |
309 | exiting_irq(); | |
310 | } | |
311 | ||
1d9090e2 | 312 | __visible void smp_trace_call_function_interrupt(struct pt_regs *regs) |
cf910e83 | 313 | { |
6dc17876 | 314 | ipi_entering_ack_irq(); |
cf910e83 SA |
315 | trace_call_function_entry(CALL_FUNCTION_VECTOR); |
316 | __smp_call_function_interrupt(); | |
317 | trace_call_function_exit(CALL_FUNCTION_VECTOR); | |
318 | exiting_irq(); | |
319 | } | |
320 | ||
eddc0e92 | 321 | static inline void __smp_call_function_single_interrupt(void) |
3b16cf87 | 322 | { |
3b16cf87 | 323 | generic_smp_call_function_single_interrupt(); |
915b0d01 | 324 | inc_irq_stat(irq_call_count); |
eddc0e92 SA |
325 | } |
326 | ||
1d9090e2 | 327 | __visible void smp_call_function_single_interrupt(struct pt_regs *regs) |
eddc0e92 | 328 | { |
6dc17876 | 329 | ipi_entering_ack_irq(); |
eddc0e92 SA |
330 | __smp_call_function_single_interrupt(); |
331 | exiting_irq(); | |
f9e47a12 GC |
332 | } |
333 | ||
1d9090e2 | 334 | __visible void smp_trace_call_function_single_interrupt(struct pt_regs *regs) |
cf910e83 | 335 | { |
6dc17876 | 336 | ipi_entering_ack_irq(); |
cf910e83 SA |
337 | trace_call_function_single_entry(CALL_FUNCTION_SINGLE_VECTOR); |
338 | __smp_call_function_single_interrupt(); | |
339 | trace_call_function_single_exit(CALL_FUNCTION_SINGLE_VECTOR); | |
340 | exiting_irq(); | |
341 | } | |
342 | ||
bda62633 DZ |
343 | static int __init nonmi_ipi_setup(char *str) |
344 | { | |
3aac27ab DZ |
345 | smp_no_nmi_ipi = true; |
346 | return 1; | |
bda62633 DZ |
347 | } |
348 | ||
349 | __setup("nonmi_ipi", nonmi_ipi_setup); | |
350 | ||
f9e47a12 | 351 | struct smp_ops smp_ops = { |
b9b34f24 CG |
352 | .smp_prepare_boot_cpu = native_smp_prepare_boot_cpu, |
353 | .smp_prepare_cpus = native_smp_prepare_cpus, | |
354 | .smp_cpus_done = native_smp_cpus_done, | |
f9e47a12 | 355 | |
5d2b86d9 | 356 | .stop_other_cpus = native_stop_other_cpus, |
b9b34f24 | 357 | .smp_send_reschedule = native_smp_send_reschedule, |
3b16cf87 | 358 | |
b9b34f24 CG |
359 | .cpu_up = native_cpu_up, |
360 | .cpu_die = native_cpu_die, | |
361 | .cpu_disable = native_cpu_disable, | |
362 | .play_dead = native_play_dead, | |
93be71b6 | 363 | |
b9b34f24 | 364 | .send_call_func_ipi = native_send_call_func_ipi, |
3b16cf87 | 365 | .send_call_func_single_ipi = native_send_call_func_single_ipi, |
f9e47a12 GC |
366 | }; |
367 | EXPORT_SYMBOL_GPL(smp_ops); |