Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * X86-64 specific CPU setup. | |
3 | * Copyright (C) 1995 Linus Torvalds | |
4 | * Copyright 2001, 2002, 2003 SuSE Labs / Andi Kleen. | |
5 | * See setup.c for older changelog. | |
1da177e4 | 6 | */ |
1da177e4 LT |
7 | #include <linux/init.h> |
8 | #include <linux/kernel.h> | |
9 | #include <linux/sched.h> | |
10 | #include <linux/string.h> | |
11 | #include <linux/bootmem.h> | |
12 | #include <linux/bitops.h> | |
a940199f | 13 | #include <linux/module.h> |
1da177e4 LT |
14 | #include <asm/pda.h> |
15 | #include <asm/pgtable.h> | |
16 | #include <asm/processor.h> | |
17 | #include <asm/desc.h> | |
18 | #include <asm/atomic.h> | |
19 | #include <asm/mmu_context.h> | |
20 | #include <asm/smp.h> | |
21 | #include <asm/i387.h> | |
22 | #include <asm/percpu.h> | |
1da177e4 | 23 | #include <asm/proto.h> |
a940199f | 24 | #include <asm/sections.h> |
30c82645 | 25 | #include <asm/setup.h> |
1da177e4 | 26 | |
6d7d7433 | 27 | #ifndef CONFIG_DEBUG_BOOT_PARAMS |
30c82645 | 28 | struct boot_params __initdata boot_params; |
6d7d7433 HY |
29 | #else |
30 | struct boot_params boot_params; | |
31 | #endif | |
1da177e4 | 32 | |
e6982c67 | 33 | cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE; |
1da177e4 | 34 | |
365ba917 | 35 | struct x8664_pda *_cpu_pda[NR_CPUS] __read_mostly; |
2ee60e17 | 36 | EXPORT_SYMBOL(_cpu_pda); |
365ba917 | 37 | struct x8664_pda boot_cpu_pda[NR_CPUS] __cacheline_aligned; |
1da177e4 | 38 | |
e57113bc | 39 | struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table }; |
1da177e4 LT |
40 | |
41 | char boot_cpu_stack[IRQSTACKSIZE] __attribute__((section(".bss.page_aligned"))); | |
42 | ||
6c231b7b | 43 | unsigned long __supported_pte_mask __read_mostly = ~0UL; |
e68decb5 GOC |
44 | EXPORT_SYMBOL_GPL(__supported_pte_mask); |
45 | ||
142a64a6 | 46 | static int do_not_nx __cpuinitdata = 0; |
1da177e4 LT |
47 | |
48 | /* noexec=on|off | |
49 | Control non executable mappings for 64bit processes. | |
50 | ||
51 | on Enable(default) | |
52 | off Disable | |
53 | */ | |
2c8c0e6b | 54 | static int __init nonx_setup(char *str) |
1da177e4 | 55 | { |
2c8c0e6b AK |
56 | if (!str) |
57 | return -EINVAL; | |
1da177e4 LT |
58 | if (!strncmp(str, "on", 2)) { |
59 | __supported_pte_mask |= _PAGE_NX; | |
60 | do_not_nx = 0; | |
61 | } else if (!strncmp(str, "off", 3)) { | |
62 | do_not_nx = 1; | |
63 | __supported_pte_mask &= ~_PAGE_NX; | |
64 | } | |
2c8c0e6b | 65 | return 0; |
1da177e4 | 66 | } |
2c8c0e6b | 67 | early_param("noexec", nonx_setup); |
1da177e4 | 68 | |
7682968b | 69 | int force_personality32 = 0; |
1da177e4 LT |
70 | |
71 | /* noexec32=on|off | |
72 | Control non executable heap for 32bit processes. | |
73 | To control the stack too use noexec=off | |
74 | ||
75 | on PROT_READ does not imply PROT_EXEC for 32bit processes | |
76 | off PROT_READ implies PROT_EXEC (default) | |
77 | */ | |
78 | static int __init nonx32_setup(char *str) | |
79 | { | |
80 | if (!strcmp(str, "on")) | |
81 | force_personality32 &= ~READ_IMPLIES_EXEC; | |
82 | else if (!strcmp(str, "off")) | |
83 | force_personality32 |= READ_IMPLIES_EXEC; | |
9b41046c | 84 | return 1; |
1da177e4 LT |
85 | } |
86 | __setup("noexec32=", nonx32_setup); | |
87 | ||
1da177e4 LT |
88 | void pda_init(int cpu) |
89 | { | |
df79efde | 90 | struct x8664_pda *pda = cpu_pda(cpu); |
1da177e4 LT |
91 | |
92 | /* Setup up data that may be needed in __get_free_pages early */ | |
93 | asm volatile("movl %0,%%fs ; movl %0,%%gs" :: "r" (0)); | |
53ee11ae AK |
94 | /* Memory clobbers used to order PDA accessed */ |
95 | mb(); | |
df79efde | 96 | wrmsrl(MSR_GS_BASE, pda); |
53ee11ae | 97 | mb(); |
1da177e4 | 98 | |
1da177e4 LT |
99 | pda->cpunumber = cpu; |
100 | pda->irqcount = -1; | |
101 | pda->kernelstack = | |
102 | (unsigned long)stack_thread_info() - PDA_STACKOFFSET + THREAD_SIZE; | |
103 | pda->active_mm = &init_mm; | |
104 | pda->mmu_state = 0; | |
105 | ||
106 | if (cpu == 0) { | |
107 | /* others are initialized in smpboot.c */ | |
108 | pda->pcurrent = &init_task; | |
109 | pda->irqstackptr = boot_cpu_stack; | |
110 | } else { | |
111 | pda->irqstackptr = (char *) | |
112 | __get_free_pages(GFP_ATOMIC, IRQSTACK_ORDER); | |
113 | if (!pda->irqstackptr) | |
114 | panic("cannot allocate irqstack for cpu %d", cpu); | |
115 | } | |
116 | ||
1da177e4 LT |
117 | |
118 | pda->irqstackptr += IRQSTACKSIZE-64; | |
119 | } | |
120 | ||
ab26a20b | 121 | char boot_exception_stacks[(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ] |
1da177e4 LT |
122 | __attribute__((section(".bss.page_aligned"))); |
123 | ||
75154f40 AK |
124 | extern asmlinkage void ignore_sysret(void); |
125 | ||
1da177e4 LT |
126 | /* May not be marked __init: used by software suspend */ |
127 | void syscall_init(void) | |
128 | { | |
129 | /* | |
130 | * LSTAR and STAR live in a bit strange symbiosis. | |
131 | * They both write to the same internal register. STAR allows to set CS/DS | |
132 | * but only a 32bit target. LSTAR sets the 64bit rip. | |
133 | */ | |
134 | wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32); | |
135 | wrmsrl(MSR_LSTAR, system_call); | |
75154f40 | 136 | wrmsrl(MSR_CSTAR, ignore_sysret); |
1da177e4 LT |
137 | |
138 | #ifdef CONFIG_IA32_EMULATION | |
139 | syscall32_cpu_init (); | |
140 | #endif | |
141 | ||
142 | /* Flags to clear on syscall */ | |
a46ff73d RM |
143 | wrmsrl(MSR_SYSCALL_MASK, |
144 | X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL); | |
1da177e4 LT |
145 | } |
146 | ||
e6982c67 | 147 | void __cpuinit check_efer(void) |
1da177e4 LT |
148 | { |
149 | unsigned long efer; | |
150 | ||
151 | rdmsrl(MSR_EFER, efer); | |
152 | if (!(efer & EFER_NX) || do_not_nx) { | |
153 | __supported_pte_mask &= ~_PAGE_NX; | |
154 | } | |
155 | } | |
156 | ||
658fdbef AK |
157 | unsigned long kernel_eflags; |
158 | ||
77788878 HS |
159 | /* |
160 | * Copies of the original ist values from the tss are only accessed during | |
161 | * debugging, no special alignment required. | |
162 | */ | |
163 | DEFINE_PER_CPU(struct orig_ist, orig_ist); | |
164 | ||
1da177e4 LT |
165 | /* |
166 | * cpu_init() initializes state that is per-CPU. Some data is already | |
167 | * initialized (naturally) in the bootstrap process, such as the GDT | |
168 | * and IDT. We reload them nevertheless, this function acts as a | |
169 | * 'CPU state barrier', nothing should get across. | |
170 | * A lot of state is already set up in PDA init. | |
171 | */ | |
e6982c67 | 172 | void __cpuinit cpu_init (void) |
1da177e4 | 173 | { |
1da177e4 | 174 | int cpu = stack_smp_processor_id(); |
1da177e4 | 175 | struct tss_struct *t = &per_cpu(init_tss, cpu); |
01ebb77b | 176 | struct orig_ist *orig_ist = &per_cpu(orig_ist, cpu); |
1da177e4 LT |
177 | unsigned long v; |
178 | char *estacks = NULL; | |
179 | struct task_struct *me; | |
180 | int i; | |
181 | ||
182 | /* CPU 0 is initialised in head64.c */ | |
183 | if (cpu != 0) { | |
184 | pda_init(cpu); | |
185 | } else | |
186 | estacks = boot_exception_stacks; | |
187 | ||
188 | me = current; | |
189 | ||
190 | if (cpu_test_and_set(cpu, cpu_initialized)) | |
191 | panic("CPU#%d already initialized!\n", cpu); | |
192 | ||
193 | printk("Initializing CPU#%d\n", cpu); | |
194 | ||
a940199f | 195 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); |
1da177e4 LT |
196 | |
197 | /* | |
198 | * Initialize the per-CPU GDT with the boot GDT, | |
199 | * and set up the GDT descriptor: | |
200 | */ | |
c11efdf9 | 201 | if (cpu) |
f6dc247c | 202 | memcpy(get_cpu_gdt_table(cpu), cpu_gdt_table, GDT_SIZE); |
1da177e4 LT |
203 | |
204 | cpu_gdt_descr[cpu].size = GDT_SIZE; | |
9d1c6e7c GOC |
205 | load_gdt((const struct desc_ptr *)&cpu_gdt_descr[cpu]); |
206 | load_idt((const struct desc_ptr *)&idt_descr); | |
1da177e4 | 207 | |
c11efdf9 | 208 | memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); |
1da177e4 LT |
209 | syscall_init(); |
210 | ||
211 | wrmsrl(MSR_FS_BASE, 0); | |
212 | wrmsrl(MSR_KERNEL_GS_BASE, 0); | |
213 | barrier(); | |
214 | ||
215 | check_efer(); | |
216 | ||
217 | /* | |
218 | * set up and load the per-CPU TSS | |
219 | */ | |
220 | for (v = 0; v < N_EXCEPTION_STACKS; v++) { | |
f5741644 KO |
221 | static const unsigned int order[N_EXCEPTION_STACKS] = { |
222 | [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STACK_ORDER, | |
223 | [DEBUG_STACK - 1] = DEBUG_STACK_ORDER | |
224 | }; | |
1da177e4 | 225 | if (cpu) { |
b556b35e | 226 | estacks = (char *)__get_free_pages(GFP_ATOMIC, order[v]); |
1da177e4 LT |
227 | if (!estacks) |
228 | panic("Cannot allocate exception stack %ld %d\n", | |
229 | v, cpu); | |
230 | } | |
f5741644 | 231 | estacks += PAGE_SIZE << order[v]; |
ca241c75 | 232 | orig_ist->ist[v] = t->x86_tss.ist[v] = (unsigned long)estacks; |
1da177e4 LT |
233 | } |
234 | ||
ca241c75 | 235 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); |
1da177e4 LT |
236 | /* |
237 | * <= is required because the CPU will access up to | |
238 | * 8 bits beyond the end of the IO permission bitmap. | |
239 | */ | |
240 | for (i = 0; i <= IO_BITMAP_LONGS; i++) | |
241 | t->io_bitmap[i] = ~0UL; | |
242 | ||
243 | atomic_inc(&init_mm.mm_count); | |
244 | me->active_mm = &init_mm; | |
245 | if (me->mm) | |
246 | BUG(); | |
247 | enter_lazy_tlb(&init_mm, me); | |
248 | ||
249 | set_tss_desc(cpu, t); | |
250 | load_TR_desc(); | |
251 | load_LDT(&init_mm.context); | |
252 | ||
253 | /* | |
254 | * Clear all 6 debug registers: | |
255 | */ | |
256 | ||
2b514e74 JB |
257 | set_debugreg(0UL, 0); |
258 | set_debugreg(0UL, 1); | |
259 | set_debugreg(0UL, 2); | |
260 | set_debugreg(0UL, 3); | |
261 | set_debugreg(0UL, 6); | |
262 | set_debugreg(0UL, 7); | |
1da177e4 LT |
263 | |
264 | fpu_init(); | |
658fdbef AK |
265 | |
266 | raw_local_save_flags(kernel_eflags); | |
1da177e4 | 267 | } |