Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * This file contains work-arounds for x86 and x86_64 platform bugs. | |
3 | */ | |
1da177e4 LT |
4 | #include <linux/pci.h> |
5 | #include <linux/irq.h> | |
6 | ||
d54bd57d VP |
7 | #include <asm/hpet.h> |
8 | ||
1da177e4 LT |
9 | #if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_SMP) && defined(CONFIG_PCI) |
10 | ||
a86f34b4 | 11 | static void __devinit quirk_intel_irqbalance(struct pci_dev *dev) |
1da177e4 LT |
12 | { |
13 | u8 config, rev; | |
9585ca02 | 14 | u16 word; |
1da177e4 LT |
15 | |
16 | /* BIOS may enable hardware IRQ balancing for | |
17 | * E7520/E7320/E7525(revision ID 0x9 and below) | |
18 | * based platforms. | |
19 | * Disable SW irqbalance/affinity on those platforms. | |
20 | */ | |
a86f34b4 | 21 | pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev); |
1da177e4 LT |
22 | if (rev > 0x9) |
23 | return; | |
24 | ||
a86f34b4 AM |
25 | /* enable access to config space*/ |
26 | pci_read_config_byte(dev, 0xf4, &config); | |
27 | pci_write_config_byte(dev, 0xf4, config|0x2); | |
1da177e4 | 28 | |
9585ca02 MW |
29 | /* |
30 | * read xTPR register. We may not have a pci_dev for device 8 | |
31 | * because it might be hidden until the above write. | |
32 | */ | |
33 | pci_bus_read_config_word(dev->bus, PCI_DEVFN(8, 0), 0x4c, &word); | |
1da177e4 LT |
34 | |
35 | if (!(word & (1 << 13))) { | |
9ed88554 | 36 | dev_info(&dev->dev, "Intel E7520/7320/7525 detected; " |
37 | "disabling irq balancing and affinity\n"); | |
1da177e4 LT |
38 | noirqdebug_setup(""); |
39 | #ifdef CONFIG_PROC_FS | |
40 | no_irq_affinity = 1; | |
41 | #endif | |
42 | } | |
43 | ||
a86f34b4 | 44 | /* put back the original value for config space*/ |
da9bb1d2 | 45 | if (!(config & 0x2)) |
a86f34b4 | 46 | pci_write_config_byte(dev, 0xf4, config); |
1da177e4 | 47 | } |
76492237 TG |
48 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, |
49 | quirk_intel_irqbalance); | |
50 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, | |
51 | quirk_intel_irqbalance); | |
52 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, | |
53 | quirk_intel_irqbalance); | |
1da177e4 | 54 | #endif |
d54bd57d VP |
55 | |
56 | #if defined(CONFIG_HPET_TIMER) | |
57 | unsigned long force_hpet_address; | |
58 | ||
bfe0c1cc VP |
59 | static enum { |
60 | NONE_FORCE_HPET_RESUME, | |
61 | OLD_ICH_FORCE_HPET_RESUME, | |
b196884e | 62 | ICH_FORCE_HPET_RESUME, |
d79a5f80 CC |
63 | VT8237_FORCE_HPET_RESUME, |
64 | NVIDIA_FORCE_HPET_RESUME, | |
e8aa4667 | 65 | ATI_FORCE_HPET_RESUME, |
bfe0c1cc VP |
66 | } force_hpet_resume_type; |
67 | ||
d54bd57d VP |
68 | static void __iomem *rcba_base; |
69 | ||
bfe0c1cc | 70 | static void ich_force_hpet_resume(void) |
d54bd57d VP |
71 | { |
72 | u32 val; | |
73 | ||
74 | if (!force_hpet_address) | |
75 | return; | |
76 | ||
8c5dfd25 | 77 | BUG_ON(rcba_base == NULL); |
d54bd57d VP |
78 | |
79 | /* read the Function Disable register, dword mode only */ | |
80 | val = readl(rcba_base + 0x3404); | |
81 | if (!(val & 0x80)) { | |
82 | /* HPET disabled in HPTC. Trying to enable */ | |
83 | writel(val | 0x80, rcba_base + 0x3404); | |
84 | } | |
85 | ||
86 | val = readl(rcba_base + 0x3404); | |
87 | if (!(val & 0x80)) | |
88 | BUG(); | |
89 | else | |
90 | printk(KERN_DEBUG "Force enabled HPET at resume\n"); | |
91 | ||
92 | return; | |
93 | } | |
94 | ||
95 | static void ich_force_enable_hpet(struct pci_dev *dev) | |
96 | { | |
97 | u32 val; | |
98 | u32 uninitialized_var(rcba); | |
99 | int err = 0; | |
100 | ||
101 | if (hpet_address || force_hpet_address) | |
102 | return; | |
103 | ||
104 | pci_read_config_dword(dev, 0xF0, &rcba); | |
105 | rcba &= 0xFFFFC000; | |
106 | if (rcba == 0) { | |
9ed88554 | 107 | dev_printk(KERN_DEBUG, &dev->dev, "RCBA disabled; " |
108 | "cannot force enable HPET\n"); | |
d54bd57d VP |
109 | return; |
110 | } | |
111 | ||
112 | /* use bits 31:14, 16 kB aligned */ | |
113 | rcba_base = ioremap_nocache(rcba, 0x4000); | |
114 | if (rcba_base == NULL) { | |
9ed88554 | 115 | dev_printk(KERN_DEBUG, &dev->dev, "ioremap failed; " |
116 | "cannot force enable HPET\n"); | |
d54bd57d VP |
117 | return; |
118 | } | |
119 | ||
120 | /* read the Function Disable register, dword mode only */ | |
121 | val = readl(rcba_base + 0x3404); | |
122 | ||
123 | if (val & 0x80) { | |
124 | /* HPET is enabled in HPTC. Just not reported by BIOS */ | |
125 | val = val & 0x3; | |
126 | force_hpet_address = 0xFED00000 | (val << 12); | |
9ed88554 | 127 | dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at " |
128 | "0x%lx\n", force_hpet_address); | |
d54bd57d VP |
129 | iounmap(rcba_base); |
130 | return; | |
131 | } | |
132 | ||
133 | /* HPET disabled in HPTC. Trying to enable */ | |
134 | writel(val | 0x80, rcba_base + 0x3404); | |
135 | ||
136 | val = readl(rcba_base + 0x3404); | |
137 | if (!(val & 0x80)) { | |
138 | err = 1; | |
139 | } else { | |
140 | val = val & 0x3; | |
141 | force_hpet_address = 0xFED00000 | (val << 12); | |
142 | } | |
143 | ||
144 | if (err) { | |
145 | force_hpet_address = 0; | |
146 | iounmap(rcba_base); | |
9ed88554 | 147 | dev_printk(KERN_DEBUG, &dev->dev, |
148 | "Failed to force enable HPET\n"); | |
d54bd57d | 149 | } else { |
bfe0c1cc | 150 | force_hpet_resume_type = ICH_FORCE_HPET_RESUME; |
9ed88554 | 151 | dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at " |
152 | "0x%lx\n", force_hpet_address); | |
d54bd57d VP |
153 | } |
154 | } | |
155 | ||
156 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, | |
76492237 | 157 | ich_force_enable_hpet); |
74e411cb KO |
158 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, |
159 | ich_force_enable_hpet); | |
d54bd57d | 160 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, |
76492237 | 161 | ich_force_enable_hpet); |
ed6fb174 | 162 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, |
76492237 | 163 | ich_force_enable_hpet); |
d54bd57d | 164 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, |
76492237 | 165 | ich_force_enable_hpet); |
d54bd57d | 166 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, |
76492237 | 167 | ich_force_enable_hpet); |
d54bd57d | 168 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, |
76492237 | 169 | ich_force_enable_hpet); |
bacbe999 JK |
170 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, |
171 | ich_force_enable_hpet); | |
dff244af AJS |
172 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, |
173 | ich_force_enable_hpet); | |
42bb8cc5 AK |
174 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x3a16, /* ICH10 */ |
175 | ich_force_enable_hpet); | |
bfe0c1cc VP |
176 | |
177 | static struct pci_dev *cached_dev; | |
178 | ||
7c4728f4 TG |
179 | static void hpet_print_force_info(void) |
180 | { | |
181 | printk(KERN_INFO "HPET not enabled in BIOS. " | |
182 | "You might try hpet=force boot option\n"); | |
183 | } | |
184 | ||
bfe0c1cc VP |
185 | static void old_ich_force_hpet_resume(void) |
186 | { | |
187 | u32 val; | |
188 | u32 uninitialized_var(gen_cntl); | |
189 | ||
190 | if (!force_hpet_address || !cached_dev) | |
191 | return; | |
192 | ||
193 | pci_read_config_dword(cached_dev, 0xD0, &gen_cntl); | |
194 | gen_cntl &= (~(0x7 << 15)); | |
195 | gen_cntl |= (0x4 << 15); | |
196 | ||
197 | pci_write_config_dword(cached_dev, 0xD0, gen_cntl); | |
198 | pci_read_config_dword(cached_dev, 0xD0, &gen_cntl); | |
199 | val = gen_cntl >> 15; | |
200 | val &= 0x7; | |
201 | if (val == 0x4) | |
202 | printk(KERN_DEBUG "Force enabled HPET at resume\n"); | |
203 | else | |
204 | BUG(); | |
205 | } | |
206 | ||
207 | static void old_ich_force_enable_hpet(struct pci_dev *dev) | |
208 | { | |
209 | u32 val; | |
210 | u32 uninitialized_var(gen_cntl); | |
211 | ||
212 | if (hpet_address || force_hpet_address) | |
213 | return; | |
214 | ||
215 | pci_read_config_dword(dev, 0xD0, &gen_cntl); | |
216 | /* | |
217 | * Bit 17 is HPET enable bit. | |
218 | * Bit 16:15 control the HPET base address. | |
219 | */ | |
220 | val = gen_cntl >> 15; | |
221 | val &= 0x7; | |
222 | if (val & 0x4) { | |
223 | val &= 0x3; | |
224 | force_hpet_address = 0xFED00000 | (val << 12); | |
9ed88554 | 225 | dev_printk(KERN_DEBUG, &dev->dev, "HPET at 0x%lx\n", |
226 | force_hpet_address); | |
bfe0c1cc VP |
227 | return; |
228 | } | |
229 | ||
230 | /* | |
231 | * HPET is disabled. Trying enabling at FED00000 and check | |
232 | * whether it sticks | |
233 | */ | |
234 | gen_cntl &= (~(0x7 << 15)); | |
235 | gen_cntl |= (0x4 << 15); | |
236 | pci_write_config_dword(dev, 0xD0, gen_cntl); | |
237 | ||
238 | pci_read_config_dword(dev, 0xD0, &gen_cntl); | |
239 | ||
240 | val = gen_cntl >> 15; | |
241 | val &= 0x7; | |
242 | if (val & 0x4) { | |
243 | /* HPET is enabled in HPTC. Just not reported by BIOS */ | |
244 | val &= 0x3; | |
245 | force_hpet_address = 0xFED00000 | (val << 12); | |
9ed88554 | 246 | dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at " |
247 | "0x%lx\n", force_hpet_address); | |
32a2da64 | 248 | cached_dev = dev; |
bfe0c1cc VP |
249 | force_hpet_resume_type = OLD_ICH_FORCE_HPET_RESUME; |
250 | return; | |
251 | } | |
252 | ||
9ed88554 | 253 | dev_printk(KERN_DEBUG, &dev->dev, "Failed to force enable HPET\n"); |
bfe0c1cc VP |
254 | } |
255 | ||
158ad326 US |
256 | /* |
257 | * Undocumented chipset features. Make sure that the user enforced | |
258 | * this. | |
259 | */ | |
260 | static void old_ich_force_enable_hpet_user(struct pci_dev *dev) | |
261 | { | |
262 | if (hpet_force_user) | |
263 | old_ich_force_enable_hpet(dev); | |
264 | } | |
265 | ||
4c2a997c JB |
266 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, |
267 | old_ich_force_enable_hpet_user); | |
158ad326 US |
268 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, |
269 | old_ich_force_enable_hpet_user); | |
270 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, | |
271 | old_ich_force_enable_hpet_user); | |
272 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, | |
273 | old_ich_force_enable_hpet_user); | |
274 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, | |
275 | old_ich_force_enable_hpet_user); | |
bfe0c1cc | 276 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, |
76492237 | 277 | old_ich_force_enable_hpet); |
bfe0c1cc | 278 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_12, |
76492237 | 279 | old_ich_force_enable_hpet); |
bfe0c1cc | 280 | |
b196884e US |
281 | |
282 | static void vt8237_force_hpet_resume(void) | |
283 | { | |
284 | u32 val; | |
285 | ||
286 | if (!force_hpet_address || !cached_dev) | |
287 | return; | |
288 | ||
289 | val = 0xfed00000 | 0x80; | |
290 | pci_write_config_dword(cached_dev, 0x68, val); | |
291 | ||
292 | pci_read_config_dword(cached_dev, 0x68, &val); | |
293 | if (val & 0x80) | |
294 | printk(KERN_DEBUG "Force enabled HPET at resume\n"); | |
295 | else | |
296 | BUG(); | |
297 | } | |
298 | ||
299 | static void vt8237_force_enable_hpet(struct pci_dev *dev) | |
300 | { | |
301 | u32 uninitialized_var(val); | |
302 | ||
7c4728f4 TG |
303 | if (hpet_address || force_hpet_address) |
304 | return; | |
305 | ||
306 | if (!hpet_force_user) { | |
307 | hpet_print_force_info(); | |
b196884e | 308 | return; |
7c4728f4 | 309 | } |
b196884e US |
310 | |
311 | pci_read_config_dword(dev, 0x68, &val); | |
312 | /* | |
313 | * Bit 7 is HPET enable bit. | |
314 | * Bit 31:10 is HPET base address (contrary to what datasheet claims) | |
315 | */ | |
316 | if (val & 0x80) { | |
317 | force_hpet_address = (val & ~0x3ff); | |
9ed88554 | 318 | dev_printk(KERN_DEBUG, &dev->dev, "HPET at 0x%lx\n", |
319 | force_hpet_address); | |
b196884e US |
320 | return; |
321 | } | |
322 | ||
323 | /* | |
324 | * HPET is disabled. Trying enabling at FED00000 and check | |
325 | * whether it sticks | |
326 | */ | |
327 | val = 0xfed00000 | 0x80; | |
328 | pci_write_config_dword(dev, 0x68, val); | |
329 | ||
330 | pci_read_config_dword(dev, 0x68, &val); | |
331 | if (val & 0x80) { | |
332 | force_hpet_address = (val & ~0x3ff); | |
9ed88554 | 333 | dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at " |
334 | "0x%lx\n", force_hpet_address); | |
b196884e US |
335 | cached_dev = dev; |
336 | force_hpet_resume_type = VT8237_FORCE_HPET_RESUME; | |
337 | return; | |
338 | } | |
339 | ||
9ed88554 | 340 | dev_printk(KERN_DEBUG, &dev->dev, "Failed to force enable HPET\n"); |
b196884e US |
341 | } |
342 | ||
343 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, | |
344 | vt8237_force_enable_hpet); | |
345 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, | |
346 | vt8237_force_enable_hpet); | |
347 | ||
e8aa4667 AH |
348 | static void ati_force_hpet_resume(void) |
349 | { | |
350 | pci_write_config_dword(cached_dev, 0x14, 0xfed00000); | |
351 | printk(KERN_DEBUG "Force enabled HPET at resume\n"); | |
352 | } | |
353 | ||
e7250b8a AH |
354 | static u32 ati_ixp4x0_rev(struct pci_dev *dev) |
355 | { | |
356 | u32 d; | |
357 | u8 b; | |
358 | ||
359 | pci_read_config_byte(dev, 0xac, &b); | |
360 | b &= ~(1<<5); | |
361 | pci_write_config_byte(dev, 0xac, b); | |
362 | pci_read_config_dword(dev, 0x70, &d); | |
363 | d |= 1<<8; | |
364 | pci_write_config_dword(dev, 0x70, d); | |
365 | pci_read_config_dword(dev, 0x8, &d); | |
366 | d &= 0xff; | |
367 | dev_printk(KERN_DEBUG, &dev->dev, "SB4X0 revision 0x%x\n", d); | |
368 | return d; | |
369 | } | |
370 | ||
e8aa4667 AH |
371 | static void ati_force_enable_hpet(struct pci_dev *dev) |
372 | { | |
e7250b8a AH |
373 | u32 d, val; |
374 | u8 b; | |
e8aa4667 | 375 | |
7c4728f4 TG |
376 | if (hpet_address || force_hpet_address) |
377 | return; | |
378 | ||
379 | if (!hpet_force_user) { | |
380 | hpet_print_force_info(); | |
e8aa4667 | 381 | return; |
7c4728f4 | 382 | } |
e8aa4667 | 383 | |
e7250b8a AH |
384 | d = ati_ixp4x0_rev(dev); |
385 | if (d < 0x82) | |
386 | return; | |
387 | ||
388 | /* base address */ | |
e8aa4667 AH |
389 | pci_write_config_dword(dev, 0x14, 0xfed00000); |
390 | pci_read_config_dword(dev, 0x14, &val); | |
e7250b8a AH |
391 | |
392 | /* enable interrupt */ | |
393 | outb(0x72, 0xcd6); b = inb(0xcd7); | |
394 | b |= 0x1; | |
395 | outb(0x72, 0xcd6); outb(b, 0xcd7); | |
396 | outb(0x72, 0xcd6); b = inb(0xcd7); | |
397 | if (!(b & 0x1)) | |
398 | return; | |
399 | pci_read_config_dword(dev, 0x64, &d); | |
400 | d |= (1<<10); | |
401 | pci_write_config_dword(dev, 0x64, d); | |
402 | pci_read_config_dword(dev, 0x64, &d); | |
403 | if (!(d & (1<<10))) | |
404 | return; | |
405 | ||
e8aa4667 AH |
406 | force_hpet_address = val; |
407 | force_hpet_resume_type = ATI_FORCE_HPET_RESUME; | |
408 | dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at 0x%lx\n", | |
409 | force_hpet_address); | |
410 | cached_dev = dev; | |
e8aa4667 AH |
411 | } |
412 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS, | |
413 | ati_force_enable_hpet); | |
414 | ||
d79a5f80 CC |
415 | /* |
416 | * Undocumented chipset feature taken from LinuxBIOS. | |
417 | */ | |
418 | static void nvidia_force_hpet_resume(void) | |
419 | { | |
420 | pci_write_config_dword(cached_dev, 0x44, 0xfed00001); | |
421 | printk(KERN_DEBUG "Force enabled HPET at resume\n"); | |
422 | } | |
423 | ||
424 | static void nvidia_force_enable_hpet(struct pci_dev *dev) | |
425 | { | |
426 | u32 uninitialized_var(val); | |
427 | ||
7c4728f4 TG |
428 | if (hpet_address || force_hpet_address) |
429 | return; | |
430 | ||
431 | if (!hpet_force_user) { | |
432 | hpet_print_force_info(); | |
d79a5f80 | 433 | return; |
7c4728f4 | 434 | } |
d79a5f80 CC |
435 | |
436 | pci_write_config_dword(dev, 0x44, 0xfed00001); | |
437 | pci_read_config_dword(dev, 0x44, &val); | |
438 | force_hpet_address = val & 0xfffffffe; | |
439 | force_hpet_resume_type = NVIDIA_FORCE_HPET_RESUME; | |
9ed88554 | 440 | dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at 0x%lx\n", |
d79a5f80 CC |
441 | force_hpet_address); |
442 | cached_dev = dev; | |
443 | return; | |
444 | } | |
445 | ||
446 | /* ISA Bridges */ | |
447 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0050, | |
448 | nvidia_force_enable_hpet); | |
449 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0051, | |
450 | nvidia_force_enable_hpet); | |
b196884e | 451 | |
1b82ba6e | 452 | /* LPC bridges */ |
96bcf458 ZL |
453 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0260, |
454 | nvidia_force_enable_hpet); | |
1b82ba6e CC |
455 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0360, |
456 | nvidia_force_enable_hpet); | |
457 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0361, | |
458 | nvidia_force_enable_hpet); | |
459 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0362, | |
460 | nvidia_force_enable_hpet); | |
461 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0363, | |
462 | nvidia_force_enable_hpet); | |
463 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0364, | |
464 | nvidia_force_enable_hpet); | |
465 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0365, | |
466 | nvidia_force_enable_hpet); | |
467 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0366, | |
468 | nvidia_force_enable_hpet); | |
469 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0367, | |
470 | nvidia_force_enable_hpet); | |
471 | ||
bfe0c1cc VP |
472 | void force_hpet_resume(void) |
473 | { | |
474 | switch (force_hpet_resume_type) { | |
4a5a77d1 HH |
475 | case ICH_FORCE_HPET_RESUME: |
476 | ich_force_hpet_resume(); | |
477 | return; | |
478 | case OLD_ICH_FORCE_HPET_RESUME: | |
479 | old_ich_force_hpet_resume(); | |
480 | return; | |
481 | case VT8237_FORCE_HPET_RESUME: | |
482 | vt8237_force_hpet_resume(); | |
483 | return; | |
484 | case NVIDIA_FORCE_HPET_RESUME: | |
485 | nvidia_force_hpet_resume(); | |
486 | return; | |
e8aa4667 AH |
487 | case ATI_FORCE_HPET_RESUME: |
488 | ati_force_hpet_resume(); | |
489 | return; | |
4a5a77d1 | 490 | default: |
bfe0c1cc VP |
491 | break; |
492 | } | |
493 | } | |
73472a46 PV |
494 | |
495 | /* | |
496 | * HPET MSI on some boards (ATI SB700/SB800) has side effect on | |
497 | * floppy DMA. Disable HPET MSI on such platforms. | |
498 | */ | |
499 | static void force_disable_hpet_msi(struct pci_dev *unused) | |
500 | { | |
501 | hpet_msi_disable = 1; | |
502 | } | |
503 | ||
504 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, | |
505 | force_disable_hpet_msi); | |
506 | ||
9b94b3a1 AH |
507 | #endif |
508 | ||
509 | #if defined(CONFIG_PCI) && defined(CONFIG_NUMA) | |
510 | /* Set correct numa_node information for AMD NB functions */ | |
511 | static void __init quirk_amd_nb_node(struct pci_dev *dev) | |
512 | { | |
513 | struct pci_dev *nb_ht; | |
514 | unsigned int devfn; | |
303fc087 | 515 | u32 node; |
9b94b3a1 AH |
516 | u32 val; |
517 | ||
518 | devfn = PCI_DEVFN(PCI_SLOT(dev->devfn), 0); | |
519 | nb_ht = pci_get_slot(dev->bus, devfn); | |
520 | if (!nb_ht) | |
521 | return; | |
522 | ||
523 | pci_read_config_dword(nb_ht, 0x60, &val); | |
303fc087 PB |
524 | node = val & 7; |
525 | /* | |
526 | * Some hardware may return an invalid node ID, | |
527 | * so check it first: | |
528 | */ | |
529 | if (node_online(node)) | |
530 | set_dev_node(&dev->dev, node); | |
748df9a4 | 531 | pci_dev_put(nb_ht); |
9b94b3a1 | 532 | } |
bfe0c1cc | 533 | |
9b94b3a1 AH |
534 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB, |
535 | quirk_amd_nb_node); | |
536 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_ADDRMAP, | |
537 | quirk_amd_nb_node); | |
538 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MEMCTL, | |
539 | quirk_amd_nb_node); | |
540 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC, | |
541 | quirk_amd_nb_node); | |
542 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_HT, | |
543 | quirk_amd_nb_node); | |
544 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MAP, | |
545 | quirk_amd_nb_node); | |
546 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_DRAM, | |
547 | quirk_amd_nb_node); | |
548 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC, | |
549 | quirk_amd_nb_node); | |
550 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_LINK, | |
551 | quirk_amd_nb_node); | |
d54bd57d | 552 | #endif |