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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
c767a54b JP |
2 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
3 | ||
61c4628b SS |
4 | #include <linux/errno.h> |
5 | #include <linux/kernel.h> | |
6 | #include <linux/mm.h> | |
7 | #include <linux/smp.h> | |
389d1fb1 | 8 | #include <linux/prctl.h> |
61c4628b SS |
9 | #include <linux/slab.h> |
10 | #include <linux/sched.h> | |
4c822698 | 11 | #include <linux/sched/idle.h> |
b17b0153 | 12 | #include <linux/sched/debug.h> |
29930025 | 13 | #include <linux/sched/task.h> |
68db0cf1 | 14 | #include <linux/sched/task_stack.h> |
186f4360 PG |
15 | #include <linux/init.h> |
16 | #include <linux/export.h> | |
7f424a8b | 17 | #include <linux/pm.h> |
162a688e | 18 | #include <linux/tick.h> |
9d62dcdf | 19 | #include <linux/random.h> |
7c68af6e | 20 | #include <linux/user-return-notifier.h> |
814e2c84 AI |
21 | #include <linux/dmi.h> |
22 | #include <linux/utsname.h> | |
90e24014 | 23 | #include <linux/stackprotector.h> |
90e24014 | 24 | #include <linux/cpuidle.h> |
61613521 | 25 | #include <trace/events/power.h> |
24f1e32c | 26 | #include <linux/hw_breakpoint.h> |
93789b32 | 27 | #include <asm/cpu.h> |
d3ec5cae | 28 | #include <asm/apic.h> |
2c1b284e | 29 | #include <asm/syscalls.h> |
7c0f6ba6 | 30 | #include <linux/uaccess.h> |
b253149b | 31 | #include <asm/mwait.h> |
78f7f1e5 | 32 | #include <asm/fpu/internal.h> |
66cb5917 | 33 | #include <asm/debugreg.h> |
90e24014 | 34 | #include <asm/nmi.h> |
375074cc | 35 | #include <asm/tlbflush.h> |
8838eb6c | 36 | #include <asm/mce.h> |
9fda6a06 | 37 | #include <asm/vm86.h> |
7b32aead | 38 | #include <asm/switch_to.h> |
b7ffc44d | 39 | #include <asm/desc.h> |
e9ea1e7f | 40 | #include <asm/prctl.h> |
885f82bf | 41 | #include <asm/spec-ctrl.h> |
90e24014 | 42 | |
45046892 TG |
43 | /* |
44 | * per-CPU TSS segments. Threads are completely 'soft' on Linux, | |
45 | * no more per-task TSS's. The TSS size is kept cacheline-aligned | |
46 | * so they are allowed to end up in the .data..cacheline_aligned | |
47 | * section. Since TSS's are completely CPU-local, we want them | |
48 | * on exact cacheline boundaries, to eliminate cacheline ping-pong. | |
49 | */ | |
2fd9c41a | 50 | __visible DEFINE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw) = { |
d0a0de21 | 51 | .x86_tss = { |
20bb8344 AL |
52 | /* |
53 | * .sp0 is only used when entering ring 0 from a lower | |
54 | * privilege level. Since the init task never runs anything | |
55 | * but ring 0 code, there is no need for a valid value here. | |
56 | * Poison it. | |
57 | */ | |
58 | .sp0 = (1UL << (BITS_PER_LONG-1)) + 1, | |
9aaefe7b | 59 | |
9aaefe7b AL |
60 | /* |
61 | * .sp1 is cpu_current_top_of_stack. The init task never | |
62 | * runs user code, but cpu_current_top_of_stack should still | |
63 | * be well defined before the first context switch. | |
64 | */ | |
65 | .sp1 = TOP_OF_INIT_STACK, | |
9aaefe7b | 66 | |
d0a0de21 AL |
67 | #ifdef CONFIG_X86_32 |
68 | .ss0 = __KERNEL_DS, | |
69 | .ss1 = __KERNEL_CS, | |
70 | .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, | |
71 | #endif | |
72 | }, | |
73 | #ifdef CONFIG_X86_32 | |
74 | /* | |
75 | * Note that the .io_bitmap member must be extra-big. This is because | |
76 | * the CPU will access an additional byte beyond the end of the IO | |
77 | * permission bitmap. The extra byte must be all 1 bits, and must | |
78 | * be within the limit. | |
79 | */ | |
80 | .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, | |
81 | #endif | |
82 | }; | |
c482feef | 83 | EXPORT_PER_CPU_SYMBOL(cpu_tss_rw); |
45046892 | 84 | |
b7ceaec1 AL |
85 | DEFINE_PER_CPU(bool, __tss_limit_invalid); |
86 | EXPORT_PER_CPU_SYMBOL_GPL(__tss_limit_invalid); | |
b7ffc44d | 87 | |
55ccf3fe SS |
88 | /* |
89 | * this gets called so that we can store lazy state into memory and copy the | |
90 | * current task into the new thread. | |
91 | */ | |
61c4628b SS |
92 | int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) |
93 | { | |
5aaeb5c0 | 94 | memcpy(dst, src, arch_task_struct_size); |
2459ee86 AL |
95 | #ifdef CONFIG_VM86 |
96 | dst->thread.vm86 = NULL; | |
97 | #endif | |
f1853505 | 98 | |
c69e098b | 99 | return fpu__copy(&dst->thread.fpu, &src->thread.fpu); |
61c4628b | 100 | } |
7f424a8b | 101 | |
389d1fb1 JF |
102 | /* |
103 | * Free current thread data structures etc.. | |
104 | */ | |
e6464694 | 105 | void exit_thread(struct task_struct *tsk) |
389d1fb1 | 106 | { |
e6464694 | 107 | struct thread_struct *t = &tsk->thread; |
250981e6 | 108 | unsigned long *bp = t->io_bitmap_ptr; |
ca6787ba | 109 | struct fpu *fpu = &t->fpu; |
389d1fb1 | 110 | |
250981e6 | 111 | if (bp) { |
c482feef | 112 | struct tss_struct *tss = &per_cpu(cpu_tss_rw, get_cpu()); |
389d1fb1 | 113 | |
389d1fb1 JF |
114 | t->io_bitmap_ptr = NULL; |
115 | clear_thread_flag(TIF_IO_BITMAP); | |
116 | /* | |
117 | * Careful, clear this in the TSS too: | |
118 | */ | |
119 | memset(tss->io_bitmap, 0xff, t->io_bitmap_max); | |
120 | t->io_bitmap_max = 0; | |
121 | put_cpu(); | |
250981e6 | 122 | kfree(bp); |
389d1fb1 | 123 | } |
1dcc8d7b | 124 | |
9fda6a06 BG |
125 | free_vm86(t); |
126 | ||
50338615 | 127 | fpu__drop(fpu); |
389d1fb1 JF |
128 | } |
129 | ||
130 | void flush_thread(void) | |
131 | { | |
132 | struct task_struct *tsk = current; | |
133 | ||
24f1e32c | 134 | flush_ptrace_hw_breakpoint(tsk); |
389d1fb1 | 135 | memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array)); |
110d7f75 | 136 | |
04c8e01d | 137 | fpu__clear(&tsk->thread.fpu); |
389d1fb1 JF |
138 | } |
139 | ||
389d1fb1 JF |
140 | void disable_TSC(void) |
141 | { | |
142 | preempt_disable(); | |
143 | if (!test_and_set_thread_flag(TIF_NOTSC)) | |
144 | /* | |
145 | * Must flip the CPU state synchronously with | |
146 | * TIF_NOTSC in the current running context. | |
147 | */ | |
5a920155 | 148 | cr4_set_bits(X86_CR4_TSD); |
389d1fb1 JF |
149 | preempt_enable(); |
150 | } | |
151 | ||
389d1fb1 JF |
152 | static void enable_TSC(void) |
153 | { | |
154 | preempt_disable(); | |
155 | if (test_and_clear_thread_flag(TIF_NOTSC)) | |
156 | /* | |
157 | * Must flip the CPU state synchronously with | |
158 | * TIF_NOTSC in the current running context. | |
159 | */ | |
5a920155 | 160 | cr4_clear_bits(X86_CR4_TSD); |
389d1fb1 JF |
161 | preempt_enable(); |
162 | } | |
163 | ||
164 | int get_tsc_mode(unsigned long adr) | |
165 | { | |
166 | unsigned int val; | |
167 | ||
168 | if (test_thread_flag(TIF_NOTSC)) | |
169 | val = PR_TSC_SIGSEGV; | |
170 | else | |
171 | val = PR_TSC_ENABLE; | |
172 | ||
173 | return put_user(val, (unsigned int __user *)adr); | |
174 | } | |
175 | ||
176 | int set_tsc_mode(unsigned int val) | |
177 | { | |
178 | if (val == PR_TSC_SIGSEGV) | |
179 | disable_TSC(); | |
180 | else if (val == PR_TSC_ENABLE) | |
181 | enable_TSC(); | |
182 | else | |
183 | return -EINVAL; | |
184 | ||
185 | return 0; | |
186 | } | |
187 | ||
e9ea1e7f KH |
188 | DEFINE_PER_CPU(u64, msr_misc_features_shadow); |
189 | ||
190 | static void set_cpuid_faulting(bool on) | |
191 | { | |
192 | u64 msrval; | |
193 | ||
194 | msrval = this_cpu_read(msr_misc_features_shadow); | |
195 | msrval &= ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT; | |
196 | msrval |= (on << MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT); | |
197 | this_cpu_write(msr_misc_features_shadow, msrval); | |
198 | wrmsrl(MSR_MISC_FEATURES_ENABLES, msrval); | |
199 | } | |
200 | ||
201 | static void disable_cpuid(void) | |
202 | { | |
203 | preempt_disable(); | |
204 | if (!test_and_set_thread_flag(TIF_NOCPUID)) { | |
205 | /* | |
206 | * Must flip the CPU state synchronously with | |
207 | * TIF_NOCPUID in the current running context. | |
208 | */ | |
209 | set_cpuid_faulting(true); | |
210 | } | |
211 | preempt_enable(); | |
212 | } | |
213 | ||
214 | static void enable_cpuid(void) | |
215 | { | |
216 | preempt_disable(); | |
217 | if (test_and_clear_thread_flag(TIF_NOCPUID)) { | |
218 | /* | |
219 | * Must flip the CPU state synchronously with | |
220 | * TIF_NOCPUID in the current running context. | |
221 | */ | |
222 | set_cpuid_faulting(false); | |
223 | } | |
224 | preempt_enable(); | |
225 | } | |
226 | ||
227 | static int get_cpuid_mode(void) | |
228 | { | |
229 | return !test_thread_flag(TIF_NOCPUID); | |
230 | } | |
231 | ||
232 | static int set_cpuid_mode(struct task_struct *task, unsigned long cpuid_enabled) | |
233 | { | |
234 | if (!static_cpu_has(X86_FEATURE_CPUID_FAULT)) | |
235 | return -ENODEV; | |
236 | ||
237 | if (cpuid_enabled) | |
238 | enable_cpuid(); | |
239 | else | |
240 | disable_cpuid(); | |
241 | ||
242 | return 0; | |
243 | } | |
244 | ||
245 | /* | |
246 | * Called immediately after a successful exec. | |
247 | */ | |
248 | void arch_setup_new_exec(void) | |
249 | { | |
250 | /* If cpuid was previously disabled for this task, re-enable it. */ | |
251 | if (test_thread_flag(TIF_NOCPUID)) | |
252 | enable_cpuid(); | |
253 | } | |
254 | ||
af8b3cd3 KH |
255 | static inline void switch_to_bitmap(struct tss_struct *tss, |
256 | struct thread_struct *prev, | |
257 | struct thread_struct *next, | |
258 | unsigned long tifp, unsigned long tifn) | |
259 | { | |
260 | if (tifn & _TIF_IO_BITMAP) { | |
261 | /* | |
262 | * Copy the relevant range of the IO bitmap. | |
263 | * Normally this is 128 bytes or less: | |
264 | */ | |
265 | memcpy(tss->io_bitmap, next->io_bitmap_ptr, | |
266 | max(prev->io_bitmap_max, next->io_bitmap_max)); | |
267 | /* | |
268 | * Make sure that the TSS limit is correct for the CPU | |
269 | * to notice the IO bitmap. | |
270 | */ | |
271 | refresh_tss_limit(); | |
272 | } else if (tifp & _TIF_IO_BITMAP) { | |
273 | /* | |
274 | * Clear any possible leftover bits: | |
275 | */ | |
276 | memset(tss->io_bitmap, 0xff, prev->io_bitmap_max); | |
277 | } | |
278 | } | |
279 | ||
1f50ddb4 TG |
280 | #ifdef CONFIG_SMP |
281 | ||
282 | struct ssb_state { | |
283 | struct ssb_state *shared_state; | |
284 | raw_spinlock_t lock; | |
285 | unsigned int disable_state; | |
286 | unsigned long local_state; | |
287 | }; | |
288 | ||
289 | #define LSTATE_SSB 0 | |
290 | ||
291 | static DEFINE_PER_CPU(struct ssb_state, ssb_state); | |
292 | ||
293 | void speculative_store_bypass_ht_init(void) | |
885f82bf | 294 | { |
1f50ddb4 TG |
295 | struct ssb_state *st = this_cpu_ptr(&ssb_state); |
296 | unsigned int this_cpu = smp_processor_id(); | |
297 | unsigned int cpu; | |
298 | ||
299 | st->local_state = 0; | |
300 | ||
301 | /* | |
302 | * Shared state setup happens once on the first bringup | |
303 | * of the CPU. It's not destroyed on CPU hotunplug. | |
304 | */ | |
305 | if (st->shared_state) | |
306 | return; | |
307 | ||
308 | raw_spin_lock_init(&st->lock); | |
309 | ||
310 | /* | |
311 | * Go over HT siblings and check whether one of them has set up the | |
312 | * shared state pointer already. | |
313 | */ | |
314 | for_each_cpu(cpu, topology_sibling_cpumask(this_cpu)) { | |
315 | if (cpu == this_cpu) | |
316 | continue; | |
317 | ||
318 | if (!per_cpu(ssb_state, cpu).shared_state) | |
319 | continue; | |
320 | ||
321 | /* Link it to the state of the sibling: */ | |
322 | st->shared_state = per_cpu(ssb_state, cpu).shared_state; | |
323 | return; | |
324 | } | |
325 | ||
326 | /* | |
327 | * First HT sibling to come up on the core. Link shared state of | |
328 | * the first HT sibling to itself. The siblings on the same core | |
329 | * which come up later will see the shared state pointer and link | |
330 | * themself to the state of this CPU. | |
331 | */ | |
332 | st->shared_state = st; | |
333 | } | |
885f82bf | 334 | |
1f50ddb4 TG |
335 | /* |
336 | * Logic is: First HT sibling enables SSBD for both siblings in the core | |
337 | * and last sibling to disable it, disables it for the whole core. This how | |
338 | * MSR_SPEC_CTRL works in "hardware": | |
339 | * | |
340 | * CORE_SPEC_CTRL = THREAD0_SPEC_CTRL | THREAD1_SPEC_CTRL | |
341 | */ | |
342 | static __always_inline void amd_set_core_ssb_state(unsigned long tifn) | |
343 | { | |
344 | struct ssb_state *st = this_cpu_ptr(&ssb_state); | |
345 | u64 msr = x86_amd_ls_cfg_base; | |
346 | ||
347 | if (!static_cpu_has(X86_FEATURE_ZEN)) { | |
348 | msr |= ssbd_tif_to_amd_ls_cfg(tifn); | |
885f82bf | 349 | wrmsrl(MSR_AMD64_LS_CFG, msr); |
1f50ddb4 TG |
350 | return; |
351 | } | |
352 | ||
353 | if (tifn & _TIF_SSBD) { | |
354 | /* | |
355 | * Since this can race with prctl(), block reentry on the | |
356 | * same CPU. | |
357 | */ | |
358 | if (__test_and_set_bit(LSTATE_SSB, &st->local_state)) | |
359 | return; | |
360 | ||
361 | msr |= x86_amd_ls_cfg_ssbd_mask; | |
362 | ||
363 | raw_spin_lock(&st->shared_state->lock); | |
364 | /* First sibling enables SSBD: */ | |
365 | if (!st->shared_state->disable_state) | |
366 | wrmsrl(MSR_AMD64_LS_CFG, msr); | |
367 | st->shared_state->disable_state++; | |
368 | raw_spin_unlock(&st->shared_state->lock); | |
885f82bf | 369 | } else { |
1f50ddb4 TG |
370 | if (!__test_and_clear_bit(LSTATE_SSB, &st->local_state)) |
371 | return; | |
372 | ||
373 | raw_spin_lock(&st->shared_state->lock); | |
374 | st->shared_state->disable_state--; | |
375 | if (!st->shared_state->disable_state) | |
376 | wrmsrl(MSR_AMD64_LS_CFG, msr); | |
377 | raw_spin_unlock(&st->shared_state->lock); | |
885f82bf TG |
378 | } |
379 | } | |
1f50ddb4 TG |
380 | #else |
381 | static __always_inline void amd_set_core_ssb_state(unsigned long tifn) | |
382 | { | |
383 | u64 msr = x86_amd_ls_cfg_base | ssbd_tif_to_amd_ls_cfg(tifn); | |
384 | ||
385 | wrmsrl(MSR_AMD64_LS_CFG, msr); | |
386 | } | |
387 | #endif | |
388 | ||
11fb0683 TL |
389 | static __always_inline void amd_set_ssb_virt_state(unsigned long tifn) |
390 | { | |
391 | /* | |
392 | * SSBD has the same definition in SPEC_CTRL and VIRT_SPEC_CTRL, | |
393 | * so ssbd_tif_to_spec_ctrl() just works. | |
394 | */ | |
395 | wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, ssbd_tif_to_spec_ctrl(tifn)); | |
396 | } | |
397 | ||
01daf568 TC |
398 | /* |
399 | * Update the MSRs managing speculation control, during context switch. | |
400 | * | |
401 | * tifp: Previous task's thread flags | |
402 | * tifn: Next task's thread flags | |
403 | */ | |
404 | static __always_inline void __speculation_ctrl_update(unsigned long tifp, | |
405 | unsigned long tifn) | |
1f50ddb4 | 406 | { |
01daf568 TC |
407 | u64 msr = x86_spec_ctrl_base; |
408 | bool updmsr = false; | |
409 | ||
410 | /* If TIF_SSBD is different, select the proper mitigation method */ | |
411 | if ((tifp ^ tifn) & _TIF_SSBD) { | |
412 | if (static_cpu_has(X86_FEATURE_VIRT_SSBD)) { | |
413 | amd_set_ssb_virt_state(tifn); | |
414 | } else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD)) { | |
415 | amd_set_core_ssb_state(tifn); | |
416 | } else if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) || | |
417 | static_cpu_has(X86_FEATURE_AMD_SSBD)) { | |
418 | msr |= ssbd_tif_to_spec_ctrl(tifn); | |
419 | updmsr = true; | |
420 | } | |
421 | } | |
1f50ddb4 | 422 | |
01daf568 TC |
423 | if (updmsr) |
424 | wrmsrl(MSR_IA32_SPEC_CTRL, msr); | |
1f50ddb4 | 425 | } |
885f82bf | 426 | |
26c4d75b | 427 | void speculation_ctrl_update(unsigned long tif) |
885f82bf | 428 | { |
01daf568 | 429 | /* Forced update. Make sure all relevant TIF flags are different */ |
1f50ddb4 | 430 | preempt_disable(); |
01daf568 | 431 | __speculation_ctrl_update(~tif, tif); |
1f50ddb4 | 432 | preempt_enable(); |
885f82bf TG |
433 | } |
434 | ||
389d1fb1 JF |
435 | void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p, |
436 | struct tss_struct *tss) | |
437 | { | |
438 | struct thread_struct *prev, *next; | |
af8b3cd3 | 439 | unsigned long tifp, tifn; |
389d1fb1 JF |
440 | |
441 | prev = &prev_p->thread; | |
442 | next = &next_p->thread; | |
443 | ||
af8b3cd3 KH |
444 | tifn = READ_ONCE(task_thread_info(next_p)->flags); |
445 | tifp = READ_ONCE(task_thread_info(prev_p)->flags); | |
446 | switch_to_bitmap(tss, prev, next, tifp, tifn); | |
447 | ||
448 | propagate_user_return_notify(prev_p, next_p); | |
449 | ||
b9894a2f KH |
450 | if ((tifp & _TIF_BLOCKSTEP || tifn & _TIF_BLOCKSTEP) && |
451 | arch_has_block_step()) { | |
452 | unsigned long debugctl, msk; | |
ea8e61b7 | 453 | |
b9894a2f | 454 | rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); |
ea8e61b7 | 455 | debugctl &= ~DEBUGCTLMSR_BTF; |
b9894a2f KH |
456 | msk = tifn & _TIF_BLOCKSTEP; |
457 | debugctl |= (msk >> TIF_BLOCKSTEP) << DEBUGCTLMSR_BTF_SHIFT; | |
458 | wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); | |
ea8e61b7 | 459 | } |
389d1fb1 | 460 | |
5a920155 | 461 | if ((tifp ^ tifn) & _TIF_NOTSC) |
9d0b6232 | 462 | cr4_toggle_bits_irqsoff(X86_CR4_TSD); |
e9ea1e7f KH |
463 | |
464 | if ((tifp ^ tifn) & _TIF_NOCPUID) | |
465 | set_cpuid_faulting(!!(tifn & _TIF_NOCPUID)); | |
885f82bf | 466 | |
01daf568 | 467 | __speculation_ctrl_update(tifp, tifn); |
389d1fb1 JF |
468 | } |
469 | ||
00dba564 TG |
470 | /* |
471 | * Idle related variables and functions | |
472 | */ | |
d1896049 | 473 | unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE; |
00dba564 TG |
474 | EXPORT_SYMBOL(boot_option_idle_override); |
475 | ||
a476bda3 | 476 | static void (*x86_idle)(void); |
00dba564 | 477 | |
90e24014 RW |
478 | #ifndef CONFIG_SMP |
479 | static inline void play_dead(void) | |
480 | { | |
481 | BUG(); | |
482 | } | |
483 | #endif | |
484 | ||
7d1a9417 TG |
485 | void arch_cpu_idle_enter(void) |
486 | { | |
6a369583 | 487 | tsc_verify_tsc_adjust(false); |
7d1a9417 | 488 | local_touch_nmi(); |
7d1a9417 | 489 | } |
90e24014 | 490 | |
7d1a9417 TG |
491 | void arch_cpu_idle_dead(void) |
492 | { | |
493 | play_dead(); | |
494 | } | |
90e24014 | 495 | |
7d1a9417 TG |
496 | /* |
497 | * Called from the generic idle code. | |
498 | */ | |
499 | void arch_cpu_idle(void) | |
500 | { | |
16f8b05a | 501 | x86_idle(); |
90e24014 RW |
502 | } |
503 | ||
00dba564 | 504 | /* |
7d1a9417 | 505 | * We use this if we don't have any better idle routine.. |
00dba564 | 506 | */ |
6727ad9e | 507 | void __cpuidle default_idle(void) |
00dba564 | 508 | { |
4d0e42cc | 509 | trace_cpu_idle_rcuidle(1, smp_processor_id()); |
7d1a9417 | 510 | safe_halt(); |
4d0e42cc | 511 | trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id()); |
00dba564 | 512 | } |
60b8b1de | 513 | #ifdef CONFIG_APM_MODULE |
00dba564 TG |
514 | EXPORT_SYMBOL(default_idle); |
515 | #endif | |
516 | ||
6a377ddc LB |
517 | #ifdef CONFIG_XEN |
518 | bool xen_set_default_idle(void) | |
e5fd47bf | 519 | { |
a476bda3 | 520 | bool ret = !!x86_idle; |
e5fd47bf | 521 | |
a476bda3 | 522 | x86_idle = default_idle; |
e5fd47bf KRW |
523 | |
524 | return ret; | |
525 | } | |
6a377ddc | 526 | #endif |
bba4ed01 | 527 | |
d3ec5cae IV |
528 | void stop_this_cpu(void *dummy) |
529 | { | |
530 | local_irq_disable(); | |
531 | /* | |
532 | * Remove this CPU: | |
533 | */ | |
4f062896 | 534 | set_cpu_online(smp_processor_id(), false); |
d3ec5cae | 535 | disable_local_APIC(); |
8838eb6c | 536 | mcheck_cpu_clear(this_cpu_ptr(&cpu_info)); |
d3ec5cae | 537 | |
f23d74f6 TL |
538 | /* |
539 | * Use wbinvd on processors that support SME. This provides support | |
540 | * for performing a successful kexec when going from SME inactive | |
541 | * to SME active (or vice-versa). The cache must be cleared so that | |
542 | * if there are entries with the same physical address, both with and | |
543 | * without the encryption bit, they don't race each other when flushed | |
544 | * and potentially end up with the wrong entry being committed to | |
545 | * memory. | |
546 | */ | |
547 | if (boot_cpu_has(X86_FEATURE_SME)) | |
548 | native_wbinvd(); | |
bba4ed01 TL |
549 | for (;;) { |
550 | /* | |
f23d74f6 TL |
551 | * Use native_halt() so that memory contents don't change |
552 | * (stack usage and variables) after possibly issuing the | |
553 | * native_wbinvd() above. | |
bba4ed01 | 554 | */ |
f23d74f6 | 555 | native_halt(); |
bba4ed01 | 556 | } |
7f424a8b PZ |
557 | } |
558 | ||
aa276e1c | 559 | /* |
07c94a38 BP |
560 | * AMD Erratum 400 aware idle routine. We handle it the same way as C3 power |
561 | * states (local apic timer and TSC stop). | |
aa276e1c | 562 | */ |
02c68a02 | 563 | static void amd_e400_idle(void) |
aa276e1c | 564 | { |
07c94a38 BP |
565 | /* |
566 | * We cannot use static_cpu_has_bug() here because X86_BUG_AMD_APIC_C1E | |
567 | * gets set after static_cpu_has() places have been converted via | |
568 | * alternatives. | |
569 | */ | |
570 | if (!boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) { | |
571 | default_idle(); | |
572 | return; | |
aa276e1c TG |
573 | } |
574 | ||
07c94a38 | 575 | tick_broadcast_enter(); |
aa276e1c | 576 | |
07c94a38 | 577 | default_idle(); |
0beefa20 | 578 | |
07c94a38 BP |
579 | /* |
580 | * The switch back from broadcast mode needs to be called with | |
581 | * interrupts disabled. | |
582 | */ | |
583 | local_irq_disable(); | |
584 | tick_broadcast_exit(); | |
585 | local_irq_enable(); | |
aa276e1c TG |
586 | } |
587 | ||
b253149b LB |
588 | /* |
589 | * Intel Core2 and older machines prefer MWAIT over HALT for C1. | |
590 | * We can't rely on cpuidle installing MWAIT, because it will not load | |
591 | * on systems that support only C1 -- so the boot default must be MWAIT. | |
592 | * | |
593 | * Some AMD machines are the opposite, they depend on using HALT. | |
594 | * | |
595 | * So for default C1, which is used during boot until cpuidle loads, | |
596 | * use MWAIT-C1 on Intel HW that has it, else use HALT. | |
597 | */ | |
598 | static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c) | |
599 | { | |
600 | if (c->x86_vendor != X86_VENDOR_INTEL) | |
601 | return 0; | |
602 | ||
08e237fa | 603 | if (!cpu_has(c, X86_FEATURE_MWAIT) || static_cpu_has_bug(X86_BUG_MONITOR)) |
b253149b LB |
604 | return 0; |
605 | ||
606 | return 1; | |
607 | } | |
608 | ||
609 | /* | |
0fb0328d HR |
610 | * MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT |
611 | * with interrupts enabled and no flags, which is backwards compatible with the | |
612 | * original MWAIT implementation. | |
b253149b | 613 | */ |
6727ad9e | 614 | static __cpuidle void mwait_idle(void) |
b253149b | 615 | { |
f8e617f4 | 616 | if (!current_set_polling_and_test()) { |
e43d0189 | 617 | trace_cpu_idle_rcuidle(1, smp_processor_id()); |
f8e617f4 | 618 | if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) { |
ca59809f | 619 | mb(); /* quirk */ |
b253149b | 620 | clflush((void *)¤t_thread_info()->flags); |
ca59809f | 621 | mb(); /* quirk */ |
f8e617f4 | 622 | } |
b253149b LB |
623 | |
624 | __monitor((void *)¤t_thread_info()->flags, 0, 0); | |
b253149b LB |
625 | if (!need_resched()) |
626 | __sti_mwait(0, 0); | |
627 | else | |
628 | local_irq_enable(); | |
e43d0189 | 629 | trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id()); |
f8e617f4 | 630 | } else { |
b253149b | 631 | local_irq_enable(); |
f8e617f4 MG |
632 | } |
633 | __current_clr_polling(); | |
b253149b LB |
634 | } |
635 | ||
148f9bb8 | 636 | void select_idle_routine(const struct cpuinfo_x86 *c) |
7f424a8b | 637 | { |
3e5095d1 | 638 | #ifdef CONFIG_SMP |
7d1a9417 | 639 | if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1) |
c767a54b | 640 | pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n"); |
7f424a8b | 641 | #endif |
7d1a9417 | 642 | if (x86_idle || boot_option_idle_override == IDLE_POLL) |
6ddd2a27 TG |
643 | return; |
644 | ||
3344ed30 | 645 | if (boot_cpu_has_bug(X86_BUG_AMD_E400)) { |
c767a54b | 646 | pr_info("using AMD E400 aware idle routine\n"); |
a476bda3 | 647 | x86_idle = amd_e400_idle; |
b253149b LB |
648 | } else if (prefer_mwait_c1_over_halt(c)) { |
649 | pr_info("using mwait in idle threads\n"); | |
650 | x86_idle = mwait_idle; | |
6ddd2a27 | 651 | } else |
a476bda3 | 652 | x86_idle = default_idle; |
7f424a8b PZ |
653 | } |
654 | ||
07c94a38 | 655 | void amd_e400_c1e_apic_setup(void) |
30e1e6d1 | 656 | { |
07c94a38 BP |
657 | if (boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) { |
658 | pr_info("Switch to broadcast mode on CPU%d\n", smp_processor_id()); | |
659 | local_irq_disable(); | |
660 | tick_broadcast_force(); | |
661 | local_irq_enable(); | |
662 | } | |
30e1e6d1 RR |
663 | } |
664 | ||
e7ff3a47 TG |
665 | void __init arch_post_acpi_subsys_init(void) |
666 | { | |
667 | u32 lo, hi; | |
668 | ||
669 | if (!boot_cpu_has_bug(X86_BUG_AMD_E400)) | |
670 | return; | |
671 | ||
672 | /* | |
673 | * AMD E400 detection needs to happen after ACPI has been enabled. If | |
674 | * the machine is affected K8_INTP_C1E_ACTIVE_MASK bits are set in | |
675 | * MSR_K8_INT_PENDING_MSG. | |
676 | */ | |
677 | rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi); | |
678 | if (!(lo & K8_INTP_C1E_ACTIVE_MASK)) | |
679 | return; | |
680 | ||
681 | boot_cpu_set_bug(X86_BUG_AMD_APIC_C1E); | |
682 | ||
683 | if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) | |
684 | mark_tsc_unstable("TSC halt in AMD C1E"); | |
685 | pr_info("System has AMD C1E enabled\n"); | |
686 | } | |
687 | ||
7f424a8b PZ |
688 | static int __init idle_setup(char *str) |
689 | { | |
ab6bc3e3 CG |
690 | if (!str) |
691 | return -EINVAL; | |
692 | ||
7f424a8b | 693 | if (!strcmp(str, "poll")) { |
c767a54b | 694 | pr_info("using polling idle threads\n"); |
d1896049 | 695 | boot_option_idle_override = IDLE_POLL; |
7d1a9417 | 696 | cpu_idle_poll_ctrl(true); |
d1896049 | 697 | } else if (!strcmp(str, "halt")) { |
c1e3b377 ZY |
698 | /* |
699 | * When the boot option of idle=halt is added, halt is | |
700 | * forced to be used for CPU idle. In such case CPU C2/C3 | |
701 | * won't be used again. | |
702 | * To continue to load the CPU idle driver, don't touch | |
703 | * the boot_option_idle_override. | |
704 | */ | |
a476bda3 | 705 | x86_idle = default_idle; |
d1896049 | 706 | boot_option_idle_override = IDLE_HALT; |
da5e09a1 ZY |
707 | } else if (!strcmp(str, "nomwait")) { |
708 | /* | |
709 | * If the boot option of "idle=nomwait" is added, | |
710 | * it means that mwait will be disabled for CPU C2/C3 | |
711 | * states. In such case it won't touch the variable | |
712 | * of boot_option_idle_override. | |
713 | */ | |
d1896049 | 714 | boot_option_idle_override = IDLE_NOMWAIT; |
c1e3b377 | 715 | } else |
7f424a8b PZ |
716 | return -1; |
717 | ||
7f424a8b PZ |
718 | return 0; |
719 | } | |
720 | early_param("idle", idle_setup); | |
721 | ||
9d62dcdf AW |
722 | unsigned long arch_align_stack(unsigned long sp) |
723 | { | |
724 | if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) | |
725 | sp -= get_random_int() % 8192; | |
726 | return sp & ~0xf; | |
727 | } | |
728 | ||
729 | unsigned long arch_randomize_brk(struct mm_struct *mm) | |
730 | { | |
9c6f0902 | 731 | return randomize_page(mm->brk, 0x02000000); |
9d62dcdf AW |
732 | } |
733 | ||
7ba78053 TG |
734 | /* |
735 | * Called from fs/proc with a reference on @p to find the function | |
736 | * which called into schedule(). This needs to be done carefully | |
737 | * because the task might wake up and we might look at a stack | |
738 | * changing under us. | |
739 | */ | |
740 | unsigned long get_wchan(struct task_struct *p) | |
741 | { | |
74327a3e | 742 | unsigned long start, bottom, top, sp, fp, ip, ret = 0; |
7ba78053 TG |
743 | int count = 0; |
744 | ||
745 | if (!p || p == current || p->state == TASK_RUNNING) | |
746 | return 0; | |
747 | ||
74327a3e AL |
748 | if (!try_get_task_stack(p)) |
749 | return 0; | |
750 | ||
7ba78053 TG |
751 | start = (unsigned long)task_stack_page(p); |
752 | if (!start) | |
74327a3e | 753 | goto out; |
7ba78053 TG |
754 | |
755 | /* | |
756 | * Layout of the stack page: | |
757 | * | |
758 | * ----------- topmax = start + THREAD_SIZE - sizeof(unsigned long) | |
759 | * PADDING | |
760 | * ----------- top = topmax - TOP_OF_KERNEL_STACK_PADDING | |
761 | * stack | |
15f4eae7 | 762 | * ----------- bottom = start |
7ba78053 TG |
763 | * |
764 | * The tasks stack pointer points at the location where the | |
765 | * framepointer is stored. The data on the stack is: | |
766 | * ... IP FP ... IP FP | |
767 | * | |
768 | * We need to read FP and IP, so we need to adjust the upper | |
769 | * bound by another unsigned long. | |
770 | */ | |
771 | top = start + THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; | |
772 | top -= 2 * sizeof(unsigned long); | |
15f4eae7 | 773 | bottom = start; |
7ba78053 TG |
774 | |
775 | sp = READ_ONCE(p->thread.sp); | |
776 | if (sp < bottom || sp > top) | |
74327a3e | 777 | goto out; |
7ba78053 | 778 | |
7b32aead | 779 | fp = READ_ONCE_NOCHECK(((struct inactive_task_frame *)sp)->bp); |
7ba78053 TG |
780 | do { |
781 | if (fp < bottom || fp > top) | |
74327a3e | 782 | goto out; |
f7d27c35 | 783 | ip = READ_ONCE_NOCHECK(*(unsigned long *)(fp + sizeof(unsigned long))); |
74327a3e AL |
784 | if (!in_sched_functions(ip)) { |
785 | ret = ip; | |
786 | goto out; | |
787 | } | |
f7d27c35 | 788 | fp = READ_ONCE_NOCHECK(*(unsigned long *)fp); |
7ba78053 | 789 | } while (count++ < 16 && p->state != TASK_RUNNING); |
74327a3e AL |
790 | |
791 | out: | |
792 | put_task_stack(p); | |
793 | return ret; | |
7ba78053 | 794 | } |
b0b9b014 KH |
795 | |
796 | long do_arch_prctl_common(struct task_struct *task, int option, | |
797 | unsigned long cpuid_enabled) | |
798 | { | |
e9ea1e7f KH |
799 | switch (option) { |
800 | case ARCH_GET_CPUID: | |
801 | return get_cpuid_mode(); | |
802 | case ARCH_SET_CPUID: | |
803 | return set_cpuid_mode(task, cpuid_enabled); | |
804 | } | |
805 | ||
b0b9b014 KH |
806 | return -EINVAL; |
807 | } |