Commit | Line | Data |
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61c4628b SS |
1 | #include <linux/errno.h> |
2 | #include <linux/kernel.h> | |
3 | #include <linux/mm.h> | |
4 | #include <linux/smp.h> | |
389d1fb1 | 5 | #include <linux/prctl.h> |
61c4628b SS |
6 | #include <linux/slab.h> |
7 | #include <linux/sched.h> | |
7f424a8b PZ |
8 | #include <linux/module.h> |
9 | #include <linux/pm.h> | |
aa276e1c | 10 | #include <linux/clockchips.h> |
9d62dcdf | 11 | #include <linux/random.h> |
7c68af6e | 12 | #include <linux/user-return-notifier.h> |
814e2c84 AI |
13 | #include <linux/dmi.h> |
14 | #include <linux/utsname.h> | |
61613521 | 15 | #include <trace/events/power.h> |
24f1e32c | 16 | #include <linux/hw_breakpoint.h> |
c1e3b377 | 17 | #include <asm/system.h> |
d3ec5cae | 18 | #include <asm/apic.h> |
2c1b284e | 19 | #include <asm/syscalls.h> |
389d1fb1 JF |
20 | #include <asm/idle.h> |
21 | #include <asm/uaccess.h> | |
22 | #include <asm/i387.h> | |
66cb5917 | 23 | #include <asm/debugreg.h> |
c1e3b377 | 24 | |
aa283f49 | 25 | struct kmem_cache *task_xstate_cachep; |
5ee481da | 26 | EXPORT_SYMBOL_GPL(task_xstate_cachep); |
61c4628b SS |
27 | |
28 | int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) | |
29 | { | |
86603283 AK |
30 | int ret; |
31 | ||
61c4628b | 32 | *dst = *src; |
86603283 AK |
33 | if (fpu_allocated(&src->thread.fpu)) { |
34 | memset(&dst->thread.fpu, 0, sizeof(dst->thread.fpu)); | |
35 | ret = fpu_alloc(&dst->thread.fpu); | |
36 | if (ret) | |
37 | return ret; | |
38 | fpu_copy(&dst->thread.fpu, &src->thread.fpu); | |
aa283f49 | 39 | } |
61c4628b SS |
40 | return 0; |
41 | } | |
42 | ||
aa283f49 | 43 | void free_thread_xstate(struct task_struct *tsk) |
61c4628b | 44 | { |
86603283 | 45 | fpu_free(&tsk->thread.fpu); |
aa283f49 SS |
46 | } |
47 | ||
aa283f49 SS |
48 | void free_thread_info(struct thread_info *ti) |
49 | { | |
50 | free_thread_xstate(ti->task); | |
1679f271 | 51 | free_pages((unsigned long)ti, get_order(THREAD_SIZE)); |
61c4628b SS |
52 | } |
53 | ||
54 | void arch_task_cache_init(void) | |
55 | { | |
56 | task_xstate_cachep = | |
57 | kmem_cache_create("task_xstate", xstate_size, | |
58 | __alignof__(union thread_xstate), | |
2dff4405 | 59 | SLAB_PANIC | SLAB_NOTRACK, NULL); |
61c4628b | 60 | } |
7f424a8b | 61 | |
389d1fb1 JF |
62 | /* |
63 | * Free current thread data structures etc.. | |
64 | */ | |
65 | void exit_thread(void) | |
66 | { | |
67 | struct task_struct *me = current; | |
68 | struct thread_struct *t = &me->thread; | |
250981e6 | 69 | unsigned long *bp = t->io_bitmap_ptr; |
389d1fb1 | 70 | |
250981e6 | 71 | if (bp) { |
389d1fb1 JF |
72 | struct tss_struct *tss = &per_cpu(init_tss, get_cpu()); |
73 | ||
389d1fb1 JF |
74 | t->io_bitmap_ptr = NULL; |
75 | clear_thread_flag(TIF_IO_BITMAP); | |
76 | /* | |
77 | * Careful, clear this in the TSS too: | |
78 | */ | |
79 | memset(tss->io_bitmap, 0xff, t->io_bitmap_max); | |
80 | t->io_bitmap_max = 0; | |
81 | put_cpu(); | |
250981e6 | 82 | kfree(bp); |
389d1fb1 | 83 | } |
389d1fb1 JF |
84 | } |
85 | ||
3bef4447 BG |
86 | void show_regs(struct pt_regs *regs) |
87 | { | |
88 | show_registers(regs); | |
9c0729dc | 89 | show_trace(NULL, regs, (unsigned long *)kernel_stack_pointer(regs)); |
3bef4447 BG |
90 | } |
91 | ||
814e2c84 AI |
92 | void show_regs_common(void) |
93 | { | |
a1884b8e | 94 | const char *board, *product; |
814e2c84 | 95 | |
a1884b8e | 96 | board = dmi_get_system_info(DMI_BOARD_NAME); |
814e2c84 AI |
97 | if (!board) |
98 | board = ""; | |
a1884b8e AI |
99 | product = dmi_get_system_info(DMI_PRODUCT_NAME); |
100 | if (!product) | |
101 | product = ""; | |
814e2c84 | 102 | |
d015a092 PE |
103 | printk(KERN_CONT "\n"); |
104 | printk(KERN_DEFAULT "Pid: %d, comm: %.20s %s %s %.*s %s/%s\n", | |
814e2c84 AI |
105 | current->pid, current->comm, print_tainted(), |
106 | init_utsname()->release, | |
107 | (int)strcspn(init_utsname()->version, " "), | |
a1884b8e | 108 | init_utsname()->version, board, product); |
814e2c84 AI |
109 | } |
110 | ||
389d1fb1 JF |
111 | void flush_thread(void) |
112 | { | |
113 | struct task_struct *tsk = current; | |
114 | ||
24f1e32c | 115 | flush_ptrace_hw_breakpoint(tsk); |
389d1fb1 JF |
116 | memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array)); |
117 | /* | |
118 | * Forget coprocessor state.. | |
119 | */ | |
120 | tsk->fpu_counter = 0; | |
121 | clear_fpu(tsk); | |
122 | clear_used_math(); | |
123 | } | |
124 | ||
125 | static void hard_disable_TSC(void) | |
126 | { | |
127 | write_cr4(read_cr4() | X86_CR4_TSD); | |
128 | } | |
129 | ||
130 | void disable_TSC(void) | |
131 | { | |
132 | preempt_disable(); | |
133 | if (!test_and_set_thread_flag(TIF_NOTSC)) | |
134 | /* | |
135 | * Must flip the CPU state synchronously with | |
136 | * TIF_NOTSC in the current running context. | |
137 | */ | |
138 | hard_disable_TSC(); | |
139 | preempt_enable(); | |
140 | } | |
141 | ||
142 | static void hard_enable_TSC(void) | |
143 | { | |
144 | write_cr4(read_cr4() & ~X86_CR4_TSD); | |
145 | } | |
146 | ||
147 | static void enable_TSC(void) | |
148 | { | |
149 | preempt_disable(); | |
150 | if (test_and_clear_thread_flag(TIF_NOTSC)) | |
151 | /* | |
152 | * Must flip the CPU state synchronously with | |
153 | * TIF_NOTSC in the current running context. | |
154 | */ | |
155 | hard_enable_TSC(); | |
156 | preempt_enable(); | |
157 | } | |
158 | ||
159 | int get_tsc_mode(unsigned long adr) | |
160 | { | |
161 | unsigned int val; | |
162 | ||
163 | if (test_thread_flag(TIF_NOTSC)) | |
164 | val = PR_TSC_SIGSEGV; | |
165 | else | |
166 | val = PR_TSC_ENABLE; | |
167 | ||
168 | return put_user(val, (unsigned int __user *)adr); | |
169 | } | |
170 | ||
171 | int set_tsc_mode(unsigned int val) | |
172 | { | |
173 | if (val == PR_TSC_SIGSEGV) | |
174 | disable_TSC(); | |
175 | else if (val == PR_TSC_ENABLE) | |
176 | enable_TSC(); | |
177 | else | |
178 | return -EINVAL; | |
179 | ||
180 | return 0; | |
181 | } | |
182 | ||
183 | void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p, | |
184 | struct tss_struct *tss) | |
185 | { | |
186 | struct thread_struct *prev, *next; | |
187 | ||
188 | prev = &prev_p->thread; | |
189 | next = &next_p->thread; | |
190 | ||
ea8e61b7 PZ |
191 | if (test_tsk_thread_flag(prev_p, TIF_BLOCKSTEP) ^ |
192 | test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) { | |
193 | unsigned long debugctl = get_debugctlmsr(); | |
194 | ||
195 | debugctl &= ~DEBUGCTLMSR_BTF; | |
196 | if (test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) | |
197 | debugctl |= DEBUGCTLMSR_BTF; | |
198 | ||
199 | update_debugctlmsr(debugctl); | |
200 | } | |
389d1fb1 | 201 | |
389d1fb1 JF |
202 | if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^ |
203 | test_tsk_thread_flag(next_p, TIF_NOTSC)) { | |
204 | /* prev and next are different */ | |
205 | if (test_tsk_thread_flag(next_p, TIF_NOTSC)) | |
206 | hard_disable_TSC(); | |
207 | else | |
208 | hard_enable_TSC(); | |
209 | } | |
210 | ||
211 | if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) { | |
212 | /* | |
213 | * Copy the relevant range of the IO bitmap. | |
214 | * Normally this is 128 bytes or less: | |
215 | */ | |
216 | memcpy(tss->io_bitmap, next->io_bitmap_ptr, | |
217 | max(prev->io_bitmap_max, next->io_bitmap_max)); | |
218 | } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) { | |
219 | /* | |
220 | * Clear any possible leftover bits: | |
221 | */ | |
222 | memset(tss->io_bitmap, 0xff, prev->io_bitmap_max); | |
223 | } | |
7c68af6e | 224 | propagate_user_return_notify(prev_p, next_p); |
389d1fb1 JF |
225 | } |
226 | ||
227 | int sys_fork(struct pt_regs *regs) | |
228 | { | |
229 | return do_fork(SIGCHLD, regs->sp, regs, 0, NULL, NULL); | |
230 | } | |
231 | ||
232 | /* | |
233 | * This is trivial, and on the face of it looks like it | |
234 | * could equally well be done in user mode. | |
235 | * | |
236 | * Not so, for quite unobvious reasons - register pressure. | |
237 | * In user mode vfork() cannot have a stack frame, and if | |
238 | * done by calling the "clone()" system call directly, you | |
239 | * do not have enough call-clobbered registers to hold all | |
240 | * the information you need. | |
241 | */ | |
242 | int sys_vfork(struct pt_regs *regs) | |
243 | { | |
244 | return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->sp, regs, 0, | |
245 | NULL, NULL); | |
246 | } | |
247 | ||
f839bbc5 BG |
248 | long |
249 | sys_clone(unsigned long clone_flags, unsigned long newsp, | |
250 | void __user *parent_tid, void __user *child_tid, struct pt_regs *regs) | |
251 | { | |
252 | if (!newsp) | |
253 | newsp = regs->sp; | |
254 | return do_fork(clone_flags, newsp, regs, 0, parent_tid, child_tid); | |
255 | } | |
256 | ||
df59e7bf BG |
257 | /* |
258 | * This gets run with %si containing the | |
259 | * function to call, and %di containing | |
260 | * the "args". | |
261 | */ | |
262 | extern void kernel_thread_helper(void); | |
263 | ||
264 | /* | |
265 | * Create a kernel thread | |
266 | */ | |
267 | int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags) | |
268 | { | |
269 | struct pt_regs regs; | |
270 | ||
271 | memset(®s, 0, sizeof(regs)); | |
272 | ||
273 | regs.si = (unsigned long) fn; | |
274 | regs.di = (unsigned long) arg; | |
275 | ||
276 | #ifdef CONFIG_X86_32 | |
277 | regs.ds = __USER_DS; | |
278 | regs.es = __USER_DS; | |
279 | regs.fs = __KERNEL_PERCPU; | |
280 | regs.gs = __KERNEL_STACK_CANARY; | |
864a0922 CG |
281 | #else |
282 | regs.ss = __KERNEL_DS; | |
df59e7bf BG |
283 | #endif |
284 | ||
285 | regs.orig_ax = -1; | |
286 | regs.ip = (unsigned long) kernel_thread_helper; | |
287 | regs.cs = __KERNEL_CS | get_kernel_rpl(); | |
288 | regs.flags = X86_EFLAGS_IF | 0x2; | |
289 | ||
290 | /* Ok, create the new process.. */ | |
291 | return do_fork(flags | CLONE_VM | CLONE_UNTRACED, 0, ®s, 0, NULL, NULL); | |
292 | } | |
293 | EXPORT_SYMBOL(kernel_thread); | |
389d1fb1 | 294 | |
11cf88bd BG |
295 | /* |
296 | * sys_execve() executes a new program. | |
297 | */ | |
d7627467 DH |
298 | long sys_execve(const char __user *name, |
299 | const char __user *const __user *argv, | |
300 | const char __user *const __user *envp, struct pt_regs *regs) | |
11cf88bd BG |
301 | { |
302 | long error; | |
303 | char *filename; | |
304 | ||
305 | filename = getname(name); | |
306 | error = PTR_ERR(filename); | |
307 | if (IS_ERR(filename)) | |
308 | return error; | |
309 | error = do_execve(filename, argv, envp, regs); | |
310 | ||
311 | #ifdef CONFIG_X86_32 | |
312 | if (error == 0) { | |
313 | /* Make sure we don't return using sysenter.. */ | |
314 | set_thread_flag(TIF_IRET); | |
315 | } | |
316 | #endif | |
317 | ||
318 | putname(filename); | |
319 | return error; | |
320 | } | |
389d1fb1 | 321 | |
00dba564 TG |
322 | /* |
323 | * Idle related variables and functions | |
324 | */ | |
d1896049 | 325 | unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE; |
00dba564 TG |
326 | EXPORT_SYMBOL(boot_option_idle_override); |
327 | ||
328 | /* | |
329 | * Powermanagement idle function, if any.. | |
330 | */ | |
331 | void (*pm_idle)(void); | |
332 | EXPORT_SYMBOL(pm_idle); | |
333 | ||
334 | #ifdef CONFIG_X86_32 | |
335 | /* | |
336 | * This halt magic was a workaround for ancient floppy DMA | |
337 | * wreckage. It should be safe to remove. | |
338 | */ | |
339 | static int hlt_counter; | |
340 | void disable_hlt(void) | |
341 | { | |
342 | hlt_counter++; | |
343 | } | |
344 | EXPORT_SYMBOL(disable_hlt); | |
345 | ||
346 | void enable_hlt(void) | |
347 | { | |
348 | hlt_counter--; | |
349 | } | |
350 | EXPORT_SYMBOL(enable_hlt); | |
351 | ||
352 | static inline int hlt_use_halt(void) | |
353 | { | |
354 | return (!hlt_counter && boot_cpu_data.hlt_works_ok); | |
355 | } | |
356 | #else | |
357 | static inline int hlt_use_halt(void) | |
358 | { | |
359 | return 1; | |
360 | } | |
361 | #endif | |
362 | ||
363 | /* | |
364 | * We use this if we don't have any better | |
365 | * idle routine.. | |
366 | */ | |
367 | void default_idle(void) | |
368 | { | |
369 | if (hlt_use_halt()) { | |
6f4f2723 | 370 | trace_power_start(POWER_CSTATE, 1, smp_processor_id()); |
25e41933 | 371 | trace_cpu_idle(1, smp_processor_id()); |
00dba564 TG |
372 | current_thread_info()->status &= ~TS_POLLING; |
373 | /* | |
374 | * TS_POLLING-cleared state must be visible before we | |
375 | * test NEED_RESCHED: | |
376 | */ | |
377 | smp_mb(); | |
378 | ||
379 | if (!need_resched()) | |
380 | safe_halt(); /* enables interrupts racelessly */ | |
381 | else | |
382 | local_irq_enable(); | |
383 | current_thread_info()->status |= TS_POLLING; | |
f77cfe4e TR |
384 | trace_power_end(smp_processor_id()); |
385 | trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id()); | |
00dba564 TG |
386 | } else { |
387 | local_irq_enable(); | |
388 | /* loop is done by the caller */ | |
389 | cpu_relax(); | |
390 | } | |
391 | } | |
392 | #ifdef CONFIG_APM_MODULE | |
393 | EXPORT_SYMBOL(default_idle); | |
394 | #endif | |
395 | ||
d3ec5cae IV |
396 | void stop_this_cpu(void *dummy) |
397 | { | |
398 | local_irq_disable(); | |
399 | /* | |
400 | * Remove this CPU: | |
401 | */ | |
4f062896 | 402 | set_cpu_online(smp_processor_id(), false); |
d3ec5cae IV |
403 | disable_local_APIC(); |
404 | ||
405 | for (;;) { | |
406 | if (hlt_works(smp_processor_id())) | |
407 | halt(); | |
408 | } | |
409 | } | |
410 | ||
7f424a8b PZ |
411 | static void do_nothing(void *unused) |
412 | { | |
413 | } | |
414 | ||
415 | /* | |
416 | * cpu_idle_wait - Used to ensure that all the CPUs discard old value of | |
417 | * pm_idle and update to new pm_idle value. Required while changing pm_idle | |
418 | * handler on SMP systems. | |
419 | * | |
420 | * Caller must have changed pm_idle to the new value before the call. Old | |
421 | * pm_idle value will not be used by any CPU after the return of this function. | |
422 | */ | |
423 | void cpu_idle_wait(void) | |
424 | { | |
425 | smp_mb(); | |
426 | /* kick all the CPUs so that they exit out of pm_idle */ | |
127a237a | 427 | smp_call_function(do_nothing, NULL, 1); |
7f424a8b PZ |
428 | } |
429 | EXPORT_SYMBOL_GPL(cpu_idle_wait); | |
430 | ||
431 | /* | |
432 | * This uses new MONITOR/MWAIT instructions on P4 processors with PNI, | |
433 | * which can obviate IPI to trigger checking of need_resched. | |
434 | * We execute MONITOR against need_resched and enter optimized wait state | |
435 | * through MWAIT. Whenever someone changes need_resched, we would be woken | |
436 | * up from MWAIT (without an IPI). | |
437 | * | |
438 | * New with Core Duo processors, MWAIT can take some hints based on CPU | |
439 | * capability. | |
440 | */ | |
441 | void mwait_idle_with_hints(unsigned long ax, unsigned long cx) | |
442 | { | |
443 | if (!need_resched()) { | |
7b543a53 | 444 | if (cpu_has(__this_cpu_ptr(&cpu_info), X86_FEATURE_CLFLUSH_MONITOR)) |
e736ad54 PV |
445 | clflush((void *)¤t_thread_info()->flags); |
446 | ||
7f424a8b PZ |
447 | __monitor((void *)¤t_thread_info()->flags, 0, 0); |
448 | smp_mb(); | |
449 | if (!need_resched()) | |
450 | __mwait(ax, cx); | |
451 | } | |
452 | } | |
453 | ||
454 | /* Default MONITOR/MWAIT with no hints, used for default C1 state */ | |
455 | static void mwait_idle(void) | |
456 | { | |
457 | if (!need_resched()) { | |
6f4f2723 | 458 | trace_power_start(POWER_CSTATE, 1, smp_processor_id()); |
25e41933 | 459 | trace_cpu_idle(1, smp_processor_id()); |
7b543a53 | 460 | if (cpu_has(__this_cpu_ptr(&cpu_info), X86_FEATURE_CLFLUSH_MONITOR)) |
e736ad54 PV |
461 | clflush((void *)¤t_thread_info()->flags); |
462 | ||
7f424a8b PZ |
463 | __monitor((void *)¤t_thread_info()->flags, 0, 0); |
464 | smp_mb(); | |
465 | if (!need_resched()) | |
466 | __sti_mwait(0, 0); | |
467 | else | |
468 | local_irq_enable(); | |
f77cfe4e TR |
469 | trace_power_end(smp_processor_id()); |
470 | trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id()); | |
7f424a8b PZ |
471 | } else |
472 | local_irq_enable(); | |
473 | } | |
474 | ||
7f424a8b PZ |
475 | /* |
476 | * On SMP it's slightly faster (but much more power-consuming!) | |
477 | * to poll the ->work.need_resched flag instead of waiting for the | |
478 | * cross-CPU IPI to arrive. Use this option with caution. | |
479 | */ | |
480 | static void poll_idle(void) | |
481 | { | |
6f4f2723 | 482 | trace_power_start(POWER_CSTATE, 0, smp_processor_id()); |
25e41933 | 483 | trace_cpu_idle(0, smp_processor_id()); |
7f424a8b | 484 | local_irq_enable(); |
2c7e9fd4 JK |
485 | while (!need_resched()) |
486 | cpu_relax(); | |
25e41933 TR |
487 | trace_power_end(smp_processor_id()); |
488 | trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id()); | |
7f424a8b PZ |
489 | } |
490 | ||
e9623b35 TG |
491 | /* |
492 | * mwait selection logic: | |
493 | * | |
494 | * It depends on the CPU. For AMD CPUs that support MWAIT this is | |
495 | * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings | |
496 | * then depend on a clock divisor and current Pstate of the core. If | |
497 | * all cores of a processor are in halt state (C1) the processor can | |
498 | * enter the C1E (C1 enhanced) state. If mwait is used this will never | |
499 | * happen. | |
500 | * | |
501 | * idle=mwait overrides this decision and forces the usage of mwait. | |
502 | */ | |
09fd4b4e TG |
503 | |
504 | #define MWAIT_INFO 0x05 | |
505 | #define MWAIT_ECX_EXTENDED_INFO 0x01 | |
506 | #define MWAIT_EDX_C1 0xf0 | |
507 | ||
e9623b35 TG |
508 | static int __cpuinit mwait_usable(const struct cpuinfo_x86 *c) |
509 | { | |
09fd4b4e TG |
510 | u32 eax, ebx, ecx, edx; |
511 | ||
d1896049 | 512 | if (boot_option_idle_override == IDLE_FORCE_MWAIT) |
e9623b35 TG |
513 | return 1; |
514 | ||
09fd4b4e TG |
515 | if (c->cpuid_level < MWAIT_INFO) |
516 | return 0; | |
517 | ||
518 | cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx); | |
519 | /* Check, whether EDX has extended info about MWAIT */ | |
520 | if (!(ecx & MWAIT_ECX_EXTENDED_INFO)) | |
521 | return 1; | |
522 | ||
523 | /* | |
524 | * edx enumeratios MONITOR/MWAIT extensions. Check, whether | |
525 | * C1 supports MWAIT | |
526 | */ | |
527 | return (edx & MWAIT_EDX_C1); | |
e9623b35 TG |
528 | } |
529 | ||
e8c534ec MS |
530 | bool c1e_detected; |
531 | EXPORT_SYMBOL(c1e_detected); | |
aa276e1c | 532 | |
bc9b83dd | 533 | static cpumask_var_t c1e_mask; |
4faac97d TG |
534 | |
535 | void c1e_remove_cpu(int cpu) | |
536 | { | |
30e1e6d1 RR |
537 | if (c1e_mask != NULL) |
538 | cpumask_clear_cpu(cpu, c1e_mask); | |
4faac97d TG |
539 | } |
540 | ||
aa276e1c TG |
541 | /* |
542 | * C1E aware idle routine. We check for C1E active in the interrupt | |
543 | * pending message MSR. If we detect C1E, then we handle it the same | |
544 | * way as C3 power states (local apic timer and TSC stop) | |
545 | */ | |
546 | static void c1e_idle(void) | |
547 | { | |
aa276e1c TG |
548 | if (need_resched()) |
549 | return; | |
550 | ||
551 | if (!c1e_detected) { | |
552 | u32 lo, hi; | |
553 | ||
554 | rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi); | |
e8c534ec | 555 | |
aa276e1c | 556 | if (lo & K8_INTP_C1E_ACTIVE_MASK) { |
e8c534ec | 557 | c1e_detected = true; |
40fb1715 | 558 | if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) |
09bfeea1 AH |
559 | mark_tsc_unstable("TSC halt in AMD C1E"); |
560 | printk(KERN_INFO "System has AMD C1E enabled\n"); | |
aa276e1c TG |
561 | } |
562 | } | |
563 | ||
564 | if (c1e_detected) { | |
565 | int cpu = smp_processor_id(); | |
566 | ||
bc9b83dd RR |
567 | if (!cpumask_test_cpu(cpu, c1e_mask)) { |
568 | cpumask_set_cpu(cpu, c1e_mask); | |
0beefa20 | 569 | /* |
f833bab8 | 570 | * Force broadcast so ACPI can not interfere. |
0beefa20 | 571 | */ |
aa276e1c TG |
572 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE, |
573 | &cpu); | |
574 | printk(KERN_INFO "Switch to broadcast mode on CPU%d\n", | |
575 | cpu); | |
576 | } | |
577 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu); | |
0beefa20 | 578 | |
aa276e1c | 579 | default_idle(); |
0beefa20 TG |
580 | |
581 | /* | |
582 | * The switch back from broadcast mode needs to be | |
583 | * called with interrupts disabled. | |
584 | */ | |
585 | local_irq_disable(); | |
586 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu); | |
587 | local_irq_enable(); | |
aa276e1c TG |
588 | } else |
589 | default_idle(); | |
590 | } | |
591 | ||
7f424a8b PZ |
592 | void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c) |
593 | { | |
3e5095d1 | 594 | #ifdef CONFIG_SMP |
7f424a8b | 595 | if (pm_idle == poll_idle && smp_num_siblings > 1) { |
d6dd6921 | 596 | printk_once(KERN_WARNING "WARNING: polling idle and HT enabled," |
7f424a8b PZ |
597 | " performance may degrade.\n"); |
598 | } | |
599 | #endif | |
6ddd2a27 TG |
600 | if (pm_idle) |
601 | return; | |
602 | ||
e9623b35 | 603 | if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) { |
7f424a8b | 604 | /* |
7f424a8b PZ |
605 | * One CPU supports mwait => All CPUs supports mwait |
606 | */ | |
6ddd2a27 TG |
607 | printk(KERN_INFO "using mwait in idle threads.\n"); |
608 | pm_idle = mwait_idle; | |
9d8888c2 HR |
609 | } else if (cpu_has_amd_erratum(amd_erratum_400)) { |
610 | /* E400: APIC timer interrupt does not wake up CPU from C1e */ | |
aa276e1c TG |
611 | printk(KERN_INFO "using C1E aware idle routine\n"); |
612 | pm_idle = c1e_idle; | |
6ddd2a27 TG |
613 | } else |
614 | pm_idle = default_idle; | |
7f424a8b PZ |
615 | } |
616 | ||
30e1e6d1 RR |
617 | void __init init_c1e_mask(void) |
618 | { | |
619 | /* If we're using c1e_idle, we need to allocate c1e_mask. */ | |
79f55997 LZ |
620 | if (pm_idle == c1e_idle) |
621 | zalloc_cpumask_var(&c1e_mask, GFP_KERNEL); | |
30e1e6d1 RR |
622 | } |
623 | ||
7f424a8b PZ |
624 | static int __init idle_setup(char *str) |
625 | { | |
ab6bc3e3 CG |
626 | if (!str) |
627 | return -EINVAL; | |
628 | ||
7f424a8b PZ |
629 | if (!strcmp(str, "poll")) { |
630 | printk("using polling idle threads.\n"); | |
631 | pm_idle = poll_idle; | |
d1896049 TR |
632 | boot_option_idle_override = IDLE_POLL; |
633 | } else if (!strcmp(str, "mwait")) { | |
634 | boot_option_idle_override = IDLE_FORCE_MWAIT; | |
635 | } else if (!strcmp(str, "halt")) { | |
c1e3b377 ZY |
636 | /* |
637 | * When the boot option of idle=halt is added, halt is | |
638 | * forced to be used for CPU idle. In such case CPU C2/C3 | |
639 | * won't be used again. | |
640 | * To continue to load the CPU idle driver, don't touch | |
641 | * the boot_option_idle_override. | |
642 | */ | |
643 | pm_idle = default_idle; | |
d1896049 | 644 | boot_option_idle_override = IDLE_HALT; |
da5e09a1 ZY |
645 | } else if (!strcmp(str, "nomwait")) { |
646 | /* | |
647 | * If the boot option of "idle=nomwait" is added, | |
648 | * it means that mwait will be disabled for CPU C2/C3 | |
649 | * states. In such case it won't touch the variable | |
650 | * of boot_option_idle_override. | |
651 | */ | |
d1896049 | 652 | boot_option_idle_override = IDLE_NOMWAIT; |
c1e3b377 | 653 | } else |
7f424a8b PZ |
654 | return -1; |
655 | ||
7f424a8b PZ |
656 | return 0; |
657 | } | |
658 | early_param("idle", idle_setup); | |
659 | ||
9d62dcdf AW |
660 | unsigned long arch_align_stack(unsigned long sp) |
661 | { | |
662 | if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) | |
663 | sp -= get_random_int() % 8192; | |
664 | return sp & ~0xf; | |
665 | } | |
666 | ||
667 | unsigned long arch_randomize_brk(struct mm_struct *mm) | |
668 | { | |
669 | unsigned long range_end = mm->brk + 0x02000000; | |
670 | return randomize_range(mm->brk, range_end, 0) ? : mm->brk; | |
671 | } | |
672 |