[linux-2.6-block.git] / arch / x86 / kernel / process.c

#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/smp.h>
#include <linux/slab.h>
#include <linux/sched.h>
#include <linux/module.h>
#include <linux/pm.h>
#include <linux/clockchips.h>
#include <asm/system.h>
#include <asm/apic.h>

unsigned long idle_halt;
EXPORT_SYMBOL(idle_halt);
unsigned long idle_nomwait;
EXPORT_SYMBOL(idle_nomwait);

struct kmem_cache *task_xstate_cachep;

int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
{
	*dst = *src;
	if (src->thread.xstate) {
		dst->thread.xstate = kmem_cache_alloc(task_xstate_cachep,
						      GFP_KERNEL);
		if (!dst->thread.xstate)
			return -ENOMEM;
		WARN_ON((unsigned long)dst->thread.xstate & 15);
		memcpy(dst->thread.xstate, src->thread.xstate, xstate_size);
	}
	return 0;
}

void free_thread_xstate(struct task_struct *tsk)
{
	if (tsk->thread.xstate) {
		kmem_cache_free(task_xstate_cachep, tsk->thread.xstate);
		tsk->thread.xstate = NULL;
	}
}

void free_thread_info(struct thread_info *ti)
{
	free_thread_xstate(ti->task);
	free_pages((unsigned long)ti, get_order(THREAD_SIZE));
}

void arch_task_cache_init(void)
{
        task_xstate_cachep =
        	kmem_cache_create("task_xstate", xstate_size,
				  __alignof__(union thread_xstate),
				  SLAB_PANIC, NULL);
}

/*
 * Idle related variables and functions
 */
unsigned long boot_option_idle_override = 0;
EXPORT_SYMBOL(boot_option_idle_override);

/*
 * Powermanagement idle function, if any..
 */
void (*pm_idle)(void);
EXPORT_SYMBOL(pm_idle);

#ifdef CONFIG_X86_32
/*
 * This halt magic was a workaround for ancient floppy DMA
 * wreckage. It should be safe to remove.
 */
static int hlt_counter;
void disable_hlt(void)
{
	hlt_counter++;
}
EXPORT_SYMBOL(disable_hlt);

void enable_hlt(void)
{
	hlt_counter--;
}
EXPORT_SYMBOL(enable_hlt);

static inline int hlt_use_halt(void)
{
	return (!hlt_counter && boot_cpu_data.hlt_works_ok);
}
#else
static inline int hlt_use_halt(void)
{
	return 1;
}
#endif

/*
 * We use this if we don't have any better
 * idle routine..
 */
void default_idle(void)
{
	if (hlt_use_halt()) {
		current_thread_info()->status &= ~TS_POLLING;
		/*
		 * TS_POLLING-cleared state must be visible before we
		 * test NEED_RESCHED:
		 */
		smp_mb();

		if (!need_resched())
			safe_halt();	/* enables interrupts racelessly */
		else
			local_irq_enable();
		current_thread_info()->status |= TS_POLLING;
	} else {
		local_irq_enable();
		/* loop is done by the caller */
		cpu_relax();
	}
}
#ifdef CONFIG_APM_MODULE
EXPORT_SYMBOL(default_idle);
#endif

void stop_this_cpu(void *dummy)
{
	local_irq_disable();
	/*
	 * Remove this CPU:
	 */
	cpu_clear(smp_processor_id(), cpu_online_map);
	disable_local_APIC();

	for (;;) {
		if (hlt_works(smp_processor_id()))
			halt();
	}
}

static void do_nothing(void *unused)
{
}

/*
 * cpu_idle_wait - Used to ensure that all the CPUs discard old value of
 * pm_idle and update to new pm_idle value. Required while changing pm_idle
 * handler on SMP systems.
 *
 * Caller must have changed pm_idle to the new value before the call. Old
 * pm_idle value will not be used by any CPU after the return of this function.
 */
void cpu_idle_wait(void)
{
	smp_mb();
	/* kick all the CPUs so that they exit out of pm_idle */
	smp_call_function(do_nothing, NULL, 1);
}
EXPORT_SYMBOL_GPL(cpu_idle_wait);

/*
 * This uses new MONITOR/MWAIT instructions on P4 processors with PNI,
 * which can obviate IPI to trigger checking of need_resched.
 * We execute MONITOR against need_resched and enter optimized wait state
 * through MWAIT. Whenever someone changes need_resched, we would be woken
 * up from MWAIT (without an IPI).
 *
 * New with Core Duo processors, MWAIT can take some hints based on CPU
 * capability.
 */
void mwait_idle_with_hints(unsigned long ax, unsigned long cx)
{
	if (!need_resched()) {
		__monitor((void *)&current_thread_info()->flags, 0, 0);
		smp_mb();
		if (!need_resched())
			__mwait(ax, cx);
	}
}

/* Default MONITOR/MWAIT with no hints, used for default C1 state */
static void mwait_idle(void)
{
	if (!need_resched()) {
		__monitor((void *)&current_thread_info()->flags, 0, 0);
		smp_mb();
		if (!need_resched())
			__sti_mwait(0, 0);
		else
			local_irq_enable();
	} else
		local_irq_enable();
}

/*
 * On SMP it's slightly faster (but much more power-consuming!)
 * to poll the ->work.need_resched flag instead of waiting for the
 * cross-CPU IPI to arrive. Use this option with caution.
 */
static void poll_idle(void)
{
	local_irq_enable();
	while (!need_resched())
		cpu_relax();
}

/*
 * mwait selection logic:
 *
 * It depends on the CPU. For AMD CPUs that support MWAIT this is
 * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings
 * then depend on a clock divisor and current Pstate of the core. If
 * all cores of a processor are in halt state (C1) the processor can
 * enter the C1E (C1 enhanced) state. If mwait is used this will never
 * happen.
 *
 * idle=mwait overrides this decision and forces the usage of mwait.
 */
static int __cpuinitdata force_mwait;

#define MWAIT_INFO			0x05
#define MWAIT_ECX_EXTENDED_INFO		0x01
#define MWAIT_EDX_C1			0xf0

static int __cpuinit mwait_usable(const struct cpuinfo_x86 *c)
{
	u32 eax, ebx, ecx, edx;

	if (force_mwait)
		return 1;

	if (c->cpuid_level < MWAIT_INFO)
		return 0;

	cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx);
	/* Check, whether EDX has extended info about MWAIT */
	if (!(ecx & MWAIT_ECX_EXTENDED_INFO))
		return 1;

	/*
	 * edx enumeratios MONITOR/MWAIT extensions. Check, whether
	 * C1  supports MWAIT
	 */
	return (edx & MWAIT_EDX_C1);
}

/*
 * Check for AMD CPUs, which have potentially C1E support
 */
static int __cpuinit check_c1e_idle(const struct cpuinfo_x86 *c)
{
	if (c->x86_vendor != X86_VENDOR_AMD)
		return 0;

	if (c->x86 < 0x0F)
		return 0;

	/* Family 0x0f models < rev F do not have C1E */
	if (c->x86 == 0x0f && c->x86_model < 0x40)
		return 0;

	return 1;
}

static cpumask_t c1e_mask = CPU_MASK_NONE;
static int c1e_detected;

void c1e_remove_cpu(int cpu)
{
	cpu_clear(cpu, c1e_mask);
}

/*
 * C1E aware idle routine. We check for C1E active in the interrupt
 * pending message MSR. If we detect C1E, then we handle it the same
 * way as C3 power states (local apic timer and TSC stop)
 */
static void c1e_idle(void)
{
	if (need_resched())
		return;

	if (!c1e_detected) {
		u32 lo, hi;

		rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
		if (lo & K8_INTP_C1E_ACTIVE_MASK) {
			c1e_detected = 1;
			if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
				mark_tsc_unstable("TSC halt in AMD C1E");
			printk(KERN_INFO "System has AMD C1E enabled\n");
			set_cpu_cap(&boot_cpu_data, X86_FEATURE_AMDC1E);
		}
	}

	if (c1e_detected) {
		int cpu = smp_processor_id();

		if (!cpu_isset(cpu, c1e_mask)) {
			cpu_set(cpu, c1e_mask);
			/*
			 * Force broadcast so ACPI can not interfere. Needs
			 * to run with interrupts enabled as it uses
			 * smp_function_call.
			 */
			local_irq_enable();
			clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
					   &cpu);
			printk(KERN_INFO "Switch to broadcast mode on CPU%d\n",
			       cpu);
			local_irq_disable();
		}
		clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);

		default_idle();

		/*
		 * The switch back from broadcast mode needs to be
		 * called with interrupts disabled.
		 */
		 local_irq_disable();
		 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
		 local_irq_enable();
	} else
		default_idle();
}

void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
{
#ifdef CONFIG_X86_SMP
	if (pm_idle == poll_idle && smp_num_siblings > 1) {
		printk(KERN_WARNING "WARNING: polling idle and HT enabled,"
			" performance may degrade.\n");
	}
#endif
	if (pm_idle)
		return;

	if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) {
		/*
		 * One CPU supports mwait => All CPUs supports mwait
		 */
		printk(KERN_INFO "using mwait in idle threads.\n");
		pm_idle = mwait_idle;
	} else if (check_c1e_idle(c)) {
		printk(KERN_INFO "using C1E aware idle routine\n");
		pm_idle = c1e_idle;
	} else
		pm_idle = default_idle;
}

static int __init idle_setup(char *str)
{
	if (!str)
		return -EINVAL;

	if (!strcmp(str, "poll")) {
		printk("using polling idle threads.\n");
		pm_idle = poll_idle;
	} else if (!strcmp(str, "mwait"))
		force_mwait = 1;
	else if (!strcmp(str, "halt")) {
		/*
		 * When the boot option of idle=halt is added, halt is
		 * forced to be used for CPU idle. In such case CPU C2/C3
		 * won't be used again.
		 * To continue to load the CPU idle driver, don't touch
		 * the boot_option_idle_override.
		 */
		pm_idle = default_idle;
		idle_halt = 1;
		return 0;
	} else if (!strcmp(str, "nomwait")) {
		/*
		 * If the boot option of "idle=nomwait" is added,
		 * it means that mwait will be disabled for CPU C2/C3
		 * states. In such case it won't touch the variable
		 * of boot_option_idle_override.
		 */
		idle_nomwait = 1;
		return 0;
	} else
		return -1;

	boot_option_idle_override = 1;
	return 0;
}
early_param("idle", idle_setup);
Commit	Line	Data
61c4628b SS	1	#include <linux/errno.h>
	2	#include <linux/kernel.h>
	3	#include <linux/mm.h>
	4	#include <linux/smp.h>
	5	#include <linux/slab.h>
	6	#include <linux/sched.h>
7f424a8b PZ	7	#include <linux/module.h>
7f424a8b PZ	8	#include <linux/pm.h>
aa276e1c	9	#include <linux/clockchips.h>
c1e3b377	10	#include <asm/system.h>
d3ec5cae	11	#include <asm/apic.h>
c1e3b377 ZY	12
	13	unsigned long idle_halt;
	14	EXPORT_SYMBOL(idle_halt);
da5e09a1 ZY	15	unsigned long idle_nomwait;
da5e09a1 ZY	16	EXPORT_SYMBOL(idle_nomwait);
61c4628b	17
aa283f49	18	struct kmem_cache *task_xstate_cachep;
61c4628b SS	19
	20	int arch_dup_task_struct(struct task_struct dst, struct task_struct src)
	21	{
	22	dst = src;
aa283f49 SS	23	if (src->thread.xstate) {
	24	dst->thread.xstate = kmem_cache_alloc(task_xstate_cachep,
	25	GFP_KERNEL);
	26	if (!dst->thread.xstate)
	27	return -ENOMEM;
	28	WARN_ON((unsigned long)dst->thread.xstate & 15);
	29	memcpy(dst->thread.xstate, src->thread.xstate, xstate_size);
	30	}
61c4628b SS	31	return 0;
	32	}
	33
aa283f49	34	void free_thread_xstate(struct task_struct *tsk)
61c4628b	35	{
aa283f49 SS	36	if (tsk->thread.xstate) {
	37	kmem_cache_free(task_xstate_cachep, tsk->thread.xstate);
	38	tsk->thread.xstate = NULL;
	39	}
	40	}
	41
aa283f49 SS	42	void free_thread_info(struct thread_info *ti)
	43	{
	44	free_thread_xstate(ti->task);
1679f271	45	free_pages((unsigned long)ti, get_order(THREAD_SIZE));
61c4628b SS	46	}
	47
	48	void arch_task_cache_init(void)
	49	{
	50	task_xstate_cachep =
	51	kmem_cache_create("task_xstate", xstate_size,
	52	__alignof__(union thread_xstate),
	53	SLAB_PANIC, NULL);
	54	}
7f424a8b	55
00dba564 TG	56	/*
	57	* Idle related variables and functions
	58	*/
	59	unsigned long boot_option_idle_override = 0;
	60	EXPORT_SYMBOL(boot_option_idle_override);
	61
	62	/*
	63	* Powermanagement idle function, if any..
	64	*/
	65	void (*pm_idle)(void);
	66	EXPORT_SYMBOL(pm_idle);
	67
	68	#ifdef CONFIG_X86_32
	69	/*
	70	* This halt magic was a workaround for ancient floppy DMA
	71	* wreckage. It should be safe to remove.
	72	*/
	73	static int hlt_counter;
	74	void disable_hlt(void)
	75	{
	76	hlt_counter++;
	77	}
	78	EXPORT_SYMBOL(disable_hlt);
	79
	80	void enable_hlt(void)
	81	{
	82	hlt_counter--;
	83	}
	84	EXPORT_SYMBOL(enable_hlt);
	85
	86	static inline int hlt_use_halt(void)
	87	{
	88	return (!hlt_counter && boot_cpu_data.hlt_works_ok);
	89	}
	90	#else
	91	static inline int hlt_use_halt(void)
	92	{
	93	return 1;
	94	}
	95	#endif
	96
	97	/*
	98	* We use this if we don't have any better
	99	* idle routine..
	100	*/
	101	void default_idle(void)
	102	{
	103	if (hlt_use_halt()) {
	104	current_thread_info()->status &= ~TS_POLLING;
	105	/*
	106	* TS_POLLING-cleared state must be visible before we
	107	* test NEED_RESCHED:
	108	*/
	109	smp_mb();
	110
	111	if (!need_resched())
	112	safe_halt(); /* enables interrupts racelessly */
	113	else
	114	local_irq_enable();
	115	current_thread_info()->status \|= TS_POLLING;
	116	} else {
	117	local_irq_enable();
	118	/* loop is done by the caller */
	119	cpu_relax();
120	}
121	}
122	#ifdef CONFIG_APM_MODULE
123	EXPORT_SYMBOL(default_idle);
124	#endif
125
d3ec5cae IV	126	void stop_this_cpu(void *dummy)
	127	{
	128	local_irq_disable();
	129	/*
	130	* Remove this CPU:
	131	*/
	132	cpu_clear(smp_processor_id(), cpu_online_map);
	133	disable_local_APIC();
	134
	135	for (;;) {
	136	if (hlt_works(smp_processor_id()))
	137	halt();
	138	}
	139	}
	140
7f424a8b PZ	141	static void do_nothing(void *unused)
	142	{
	143	}
	144
	145	/*
	146	* cpu_idle_wait - Used to ensure that all the CPUs discard old value of
	147	* pm_idle and update to new pm_idle value. Required while changing pm_idle
	148	* handler on SMP systems.
	149	*
	150	* Caller must have changed pm_idle to the new value before the call. Old
	151	* pm_idle value will not be used by any CPU after the return of this function.
	152	*/
	153	void cpu_idle_wait(void)
	154	{
	155	smp_mb();
	156	/* kick all the CPUs so that they exit out of pm_idle */
127a237a	157	smp_call_function(do_nothing, NULL, 1);
7f424a8b PZ	158	}
	159	EXPORT_SYMBOL_GPL(cpu_idle_wait);
	160
	161	/*
	162	* This uses new MONITOR/MWAIT instructions on P4 processors with PNI,
	163	* which can obviate IPI to trigger checking of need_resched.
	164	* We execute MONITOR against need_resched and enter optimized wait state
	165	* through MWAIT. Whenever someone changes need_resched, we would be woken
	166	* up from MWAIT (without an IPI).
	167	*
	168	* New with Core Duo processors, MWAIT can take some hints based on CPU
	169	* capability.
	170	*/
	171	void mwait_idle_with_hints(unsigned long ax, unsigned long cx)
	172	{
	173	if (!need_resched()) {
	174	__monitor((void *)&current_thread_info()->flags, 0, 0);
	175	smp_mb();
	176	if (!need_resched())
	177	__mwait(ax, cx);
	178	}
	179	}
	180
	181	/* Default MONITOR/MWAIT with no hints, used for default C1 state */
	182	static void mwait_idle(void)
	183	{
	184	if (!need_resched()) {
	185	__monitor((void *)&current_thread_info()->flags, 0, 0);
	186	smp_mb();
	187	if (!need_resched())
	188	__sti_mwait(0, 0);
	189	else
	190	local_irq_enable();
	191	} else
	192	local_irq_enable();
	193	}
	194
7f424a8b PZ	195	/*
	196	* On SMP it's slightly faster (but much more power-consuming!)
	197	* to poll the ->work.need_resched flag instead of waiting for the
	198	* cross-CPU IPI to arrive. Use this option with caution.
	199	*/
	200	static void poll_idle(void)
	201	{
	202	local_irq_enable();
2c7e9fd4 JK	203	while (!need_resched())
2c7e9fd4 JK	204	cpu_relax();
7f424a8b PZ	205	}
7f424a8b PZ	206
e9623b35 TG	207	/*
	208	* mwait selection logic:
	209	*
	210	* It depends on the CPU. For AMD CPUs that support MWAIT this is
	211	* wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings
	212	* then depend on a clock divisor and current Pstate of the core. If
	213	* all cores of a processor are in halt state (C1) the processor can
	214	* enter the C1E (C1 enhanced) state. If mwait is used this will never
	215	* happen.
	216	*
	217	* idle=mwait overrides this decision and forces the usage of mwait.
	218	*/
08ad8afa	219	static int __cpuinitdata force_mwait;
09fd4b4e TG	220
	221	#define MWAIT_INFO 0x05
	222	#define MWAIT_ECX_EXTENDED_INFO 0x01
	223	#define MWAIT_EDX_C1 0xf0
	224
e9623b35 TG	225	static int __cpuinit mwait_usable(const struct cpuinfo_x86 *c)
e9623b35 TG	226	{
09fd4b4e TG	227	u32 eax, ebx, ecx, edx;
09fd4b4e TG	228
e9623b35 TG	229	if (force_mwait)
	230	return 1;
	231
09fd4b4e TG	232	if (c->cpuid_level < MWAIT_INFO)
	233	return 0;
	234
	235	cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx);
	236	/* Check, whether EDX has extended info about MWAIT */
	237	if (!(ecx & MWAIT_ECX_EXTENDED_INFO))
	238	return 1;
	239
	240	/*
	241	* edx enumeratios MONITOR/MWAIT extensions. Check, whether
	242	* C1 supports MWAIT
	243	*/
	244	return (edx & MWAIT_EDX_C1);
e9623b35 TG	245	}
e9623b35 TG	246
aa276e1c TG	247	/*
	248	* Check for AMD CPUs, which have potentially C1E support
	249	*/
	250	static int __cpuinit check_c1e_idle(const struct cpuinfo_x86 *c)
	251	{
	252	if (c->x86_vendor != X86_VENDOR_AMD)
	253	return 0;
	254
	255	if (c->x86 < 0x0F)
	256	return 0;
	257
	258	/* Family 0x0f models < rev F do not have C1E */
	259	if (c->x86 == 0x0f && c->x86_model < 0x40)
	260	return 0;
	261
	262	return 1;
	263	}
	264
4faac97d TG	265	static cpumask_t c1e_mask = CPU_MASK_NONE;
	266	static int c1e_detected;
	267
	268	void c1e_remove_cpu(int cpu)
	269	{
	270	cpu_clear(cpu, c1e_mask);
	271	}
	272
aa276e1c TG	273	/*
	274	* C1E aware idle routine. We check for C1E active in the interrupt
	275	* pending message MSR. If we detect C1E, then we handle it the same
	276	* way as C3 power states (local apic timer and TSC stop)
	277	*/
	278	static void c1e_idle(void)
	279	{
aa276e1c TG	280	if (need_resched())
	281	return;
	282
	283	if (!c1e_detected) {
	284	u32 lo, hi;
	285
	286	rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
	287	if (lo & K8_INTP_C1E_ACTIVE_MASK) {
	288	c1e_detected = 1;
09bfeea1 AH	289	if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
	290	mark_tsc_unstable("TSC halt in AMD C1E");
	291	printk(KERN_INFO "System has AMD C1E enabled\n");
a8d68290	292	set_cpu_cap(&boot_cpu_data, X86_FEATURE_AMDC1E);
aa276e1c TG	293	}
	294	}
	295
	296	if (c1e_detected) {
	297	int cpu = smp_processor_id();
	298
	299	if (!cpu_isset(cpu, c1e_mask)) {
	300	cpu_set(cpu, c1e_mask);
0beefa20 TG	301	/*
	302	* Force broadcast so ACPI can not interfere. Needs
	303	* to run with interrupts enabled as it uses
	304	* smp_function_call.
	305	*/
	306	local_irq_enable();
aa276e1c TG	307	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
	308	&cpu);
	309	printk(KERN_INFO "Switch to broadcast mode on CPU%d\n",
	310	cpu);
0beefa20	311	local_irq_disable();
aa276e1c TG	312	}
aa276e1c TG	313	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
0beefa20	314
aa276e1c	315	default_idle();
0beefa20 TG	316
	317	/*
	318	* The switch back from broadcast mode needs to be
	319	* called with interrupts disabled.
	320	*/
	321	local_irq_disable();
	322	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
	323	local_irq_enable();
aa276e1c TG	324	} else
	325	default_idle();
	326	}
	327
7f424a8b PZ	328	void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
7f424a8b PZ	329	{
7f424a8b PZ	330	#ifdef CONFIG_X86_SMP
	331	if (pm_idle == poll_idle && smp_num_siblings > 1) {
	332	printk(KERN_WARNING "WARNING: polling idle and HT enabled,"
	333	" performance may degrade.\n");
	334	}
	335	#endif
6ddd2a27 TG	336	if (pm_idle)
	337	return;
	338
e9623b35	339	if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) {
7f424a8b	340	/*
7f424a8b PZ	341	* One CPU supports mwait => All CPUs supports mwait
7f424a8b PZ	342	*/
6ddd2a27 TG	343	printk(KERN_INFO "using mwait in idle threads.\n");
6ddd2a27 TG	344	pm_idle = mwait_idle;
aa276e1c TG	345	} else if (check_c1e_idle(c)) {
	346	printk(KERN_INFO "using C1E aware idle routine\n");
	347	pm_idle = c1e_idle;
6ddd2a27 TG	348	} else
6ddd2a27 TG	349	pm_idle = default_idle;
7f424a8b PZ	350	}
	351
	352	static int __init idle_setup(char *str)
	353	{
ab6bc3e3 CG	354	if (!str)
	355	return -EINVAL;
	356
7f424a8b PZ	357	if (!strcmp(str, "poll")) {
	358	printk("using polling idle threads.\n");
	359	pm_idle = poll_idle;
	360	} else if (!strcmp(str, "mwait"))
	361	force_mwait = 1;
c1e3b377 ZY	362	else if (!strcmp(str, "halt")) {
	363	/*
	364	* When the boot option of idle=halt is added, halt is
	365	* forced to be used for CPU idle. In such case CPU C2/C3
	366	* won't be used again.
	367	* To continue to load the CPU idle driver, don't touch
	368	* the boot_option_idle_override.
	369	*/
	370	pm_idle = default_idle;
	371	idle_halt = 1;
	372	return 0;
da5e09a1 ZY	373	} else if (!strcmp(str, "nomwait")) {
	374	/*
	375	* If the boot option of "idle=nomwait" is added,
	376	* it means that mwait will be disabled for CPU C2/C3
	377	* states. In such case it won't touch the variable
	378	* of boot_option_idle_override.
	379	*/
	380	idle_nomwait = 1;
	381	return 0;
c1e3b377	382	} else
7f424a8b PZ	383	return -1;
	384
	385	boot_option_idle_override = 1;
	386	return 0;
	387	}
	388	early_param("idle", idle_setup);
	389