Commit | Line | Data |
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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
c767a54b JP |
2 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
3 | ||
61c4628b SS |
4 | #include <linux/errno.h> |
5 | #include <linux/kernel.h> | |
6 | #include <linux/mm.h> | |
7 | #include <linux/smp.h> | |
389d1fb1 | 8 | #include <linux/prctl.h> |
61c4628b SS |
9 | #include <linux/slab.h> |
10 | #include <linux/sched.h> | |
4c822698 | 11 | #include <linux/sched/idle.h> |
b17b0153 | 12 | #include <linux/sched/debug.h> |
29930025 | 13 | #include <linux/sched/task.h> |
68db0cf1 | 14 | #include <linux/sched/task_stack.h> |
186f4360 PG |
15 | #include <linux/init.h> |
16 | #include <linux/export.h> | |
7f424a8b | 17 | #include <linux/pm.h> |
162a688e | 18 | #include <linux/tick.h> |
9d62dcdf | 19 | #include <linux/random.h> |
7c68af6e | 20 | #include <linux/user-return-notifier.h> |
814e2c84 AI |
21 | #include <linux/dmi.h> |
22 | #include <linux/utsname.h> | |
90e24014 | 23 | #include <linux/stackprotector.h> |
90e24014 | 24 | #include <linux/cpuidle.h> |
89f579ce YW |
25 | #include <linux/acpi.h> |
26 | #include <linux/elf-randomize.h> | |
61613521 | 27 | #include <trace/events/power.h> |
24f1e32c | 28 | #include <linux/hw_breakpoint.h> |
93789b32 | 29 | #include <asm/cpu.h> |
d3ec5cae | 30 | #include <asm/apic.h> |
7c0f6ba6 | 31 | #include <linux/uaccess.h> |
b253149b | 32 | #include <asm/mwait.h> |
63e81807 | 33 | #include <asm/fpu/sched.h> |
66cb5917 | 34 | #include <asm/debugreg.h> |
90e24014 | 35 | #include <asm/nmi.h> |
375074cc | 36 | #include <asm/tlbflush.h> |
8838eb6c | 37 | #include <asm/mce.h> |
9fda6a06 | 38 | #include <asm/vm86.h> |
7b32aead | 39 | #include <asm/switch_to.h> |
b7ffc44d | 40 | #include <asm/desc.h> |
e9ea1e7f | 41 | #include <asm/prctl.h> |
885f82bf | 42 | #include <asm/spec-ctrl.h> |
577d5cd7 | 43 | #include <asm/io_bitmap.h> |
89f579ce | 44 | #include <asm/proto.h> |
6f9885a3 | 45 | #include <asm/frame.h> |
90e24014 | 46 | |
ff16701a TG |
47 | #include "process.h" |
48 | ||
45046892 TG |
49 | /* |
50 | * per-CPU TSS segments. Threads are completely 'soft' on Linux, | |
51 | * no more per-task TSS's. The TSS size is kept cacheline-aligned | |
52 | * so they are allowed to end up in the .data..cacheline_aligned | |
53 | * section. Since TSS's are completely CPU-local, we want them | |
54 | * on exact cacheline boundaries, to eliminate cacheline ping-pong. | |
55 | */ | |
2fd9c41a | 56 | __visible DEFINE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw) = { |
d0a0de21 | 57 | .x86_tss = { |
20bb8344 AL |
58 | /* |
59 | * .sp0 is only used when entering ring 0 from a lower | |
60 | * privilege level. Since the init task never runs anything | |
61 | * but ring 0 code, there is no need for a valid value here. | |
62 | * Poison it. | |
63 | */ | |
64 | .sp0 = (1UL << (BITS_PER_LONG-1)) + 1, | |
9aaefe7b | 65 | |
1591584e | 66 | #ifdef CONFIG_X86_32 |
9aaefe7b | 67 | .sp1 = TOP_OF_INIT_STACK, |
9aaefe7b | 68 | |
d0a0de21 AL |
69 | .ss0 = __KERNEL_DS, |
70 | .ss1 = __KERNEL_CS, | |
d0a0de21 | 71 | #endif |
ecc7e37d | 72 | .io_bitmap_base = IO_BITMAP_OFFSET_INVALID, |
d0a0de21 | 73 | }, |
d0a0de21 | 74 | }; |
c482feef | 75 | EXPORT_PER_CPU_SYMBOL(cpu_tss_rw); |
45046892 | 76 | |
b7ceaec1 AL |
77 | DEFINE_PER_CPU(bool, __tss_limit_invalid); |
78 | EXPORT_PER_CPU_SYMBOL_GPL(__tss_limit_invalid); | |
b7ffc44d | 79 | |
55ccf3fe SS |
80 | /* |
81 | * this gets called so that we can store lazy state into memory and copy the | |
82 | * current task into the new thread. | |
83 | */ | |
61c4628b SS |
84 | int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) |
85 | { | |
5aaeb5c0 | 86 | memcpy(dst, src, arch_task_struct_size); |
2459ee86 AL |
87 | #ifdef CONFIG_VM86 |
88 | dst->thread.vm86 = NULL; | |
89 | #endif | |
f0cbc8b3 TG |
90 | /* Drop the copied pointer to current's fpstate */ |
91 | dst->thread.fpu.fpstate = NULL; | |
2d16a187 | 92 | return 0; |
61c4628b | 93 | } |
7f424a8b | 94 | |
389d1fb1 | 95 | /* |
4bfe6cce | 96 | * Free thread data structures etc.. |
389d1fb1 | 97 | */ |
e6464694 | 98 | void exit_thread(struct task_struct *tsk) |
389d1fb1 | 99 | { |
e6464694 | 100 | struct thread_struct *t = &tsk->thread; |
ca6787ba | 101 | struct fpu *fpu = &t->fpu; |
ea5f1cd7 TG |
102 | |
103 | if (test_thread_flag(TIF_IO_BITMAP)) | |
4bfe6cce | 104 | io_bitmap_exit(tsk); |
1dcc8d7b | 105 | |
9fda6a06 BG |
106 | free_vm86(t); |
107 | ||
50338615 | 108 | fpu__drop(fpu); |
389d1fb1 JF |
109 | } |
110 | ||
2fff071d TG |
111 | static int set_new_tls(struct task_struct *p, unsigned long tls) |
112 | { | |
113 | struct user_desc __user *utls = (struct user_desc __user *)tls; | |
114 | ||
115 | if (in_ia32_syscall()) | |
116 | return do_set_thread_area(p, -1, utls, 0); | |
117 | else | |
118 | return do_set_thread_area_64(p, ARCH_SET_FS, tls); | |
119 | } | |
120 | ||
714acdbd CB |
121 | int copy_thread(unsigned long clone_flags, unsigned long sp, unsigned long arg, |
122 | struct task_struct *p, unsigned long tls) | |
2fff071d TG |
123 | { |
124 | struct inactive_task_frame *frame; | |
125 | struct fork_frame *fork_frame; | |
126 | struct pt_regs *childregs; | |
4804e382 | 127 | int ret = 0; |
2fff071d TG |
128 | |
129 | childregs = task_pt_regs(p); | |
130 | fork_frame = container_of(childregs, struct fork_frame, regs); | |
131 | frame = &fork_frame->frame; | |
132 | ||
6f9885a3 | 133 | frame->bp = encode_frame_pointer(childregs); |
2fff071d TG |
134 | frame->ret_addr = (unsigned long) ret_from_fork; |
135 | p->thread.sp = (unsigned long) fork_frame; | |
577d5cd7 | 136 | p->thread.io_bitmap = NULL; |
2fff071d TG |
137 | memset(p->thread.ptrace_bps, 0, sizeof(p->thread.ptrace_bps)); |
138 | ||
139 | #ifdef CONFIG_X86_64 | |
005f141e CB |
140 | current_save_fsgs(); |
141 | p->thread.fsindex = current->thread.fsindex; | |
142 | p->thread.fsbase = current->thread.fsbase; | |
143 | p->thread.gsindex = current->thread.gsindex; | |
144 | p->thread.gsbase = current->thread.gsbase; | |
145 | ||
2fff071d TG |
146 | savesegment(es, p->thread.es); |
147 | savesegment(ds, p->thread.ds); | |
148 | #else | |
149 | p->thread.sp0 = (unsigned long) (childregs + 1); | |
150 | /* | |
151 | * Clear all status flags including IF and set fixed bit. 64bit | |
152 | * does not have this initialization as the frame does not contain | |
153 | * flags. The flags consistency (especially vs. AC) is there | |
154 | * ensured via objtool, which lacks 32bit support. | |
155 | */ | |
156 | frame->flags = X86_EFLAGS_FIXED; | |
157 | #endif | |
158 | ||
2d16a187 TG |
159 | fpu_clone(p); |
160 | ||
2fff071d | 161 | /* Kernel thread ? */ |
50b7b6f2 | 162 | if (unlikely(p->flags & PF_KTHREAD)) { |
9782a712 | 163 | p->thread.pkru = pkru_get_init_value(); |
2fff071d TG |
164 | memset(childregs, 0, sizeof(struct pt_regs)); |
165 | kthread_frame_init(frame, sp, arg); | |
166 | return 0; | |
167 | } | |
168 | ||
9782a712 DH |
169 | /* |
170 | * Clone current's PKRU value from hardware. tsk->thread.pkru | |
171 | * is only valid when scheduled out. | |
172 | */ | |
173 | p->thread.pkru = read_pkru(); | |
174 | ||
2fff071d TG |
175 | frame->bx = 0; |
176 | *childregs = *current_pt_regs(); | |
177 | childregs->ax = 0; | |
178 | if (sp) | |
179 | childregs->sp = sp; | |
180 | ||
181 | #ifdef CONFIG_X86_32 | |
182 | task_user_gs(p) = get_user_gs(current_pt_regs()); | |
183 | #endif | |
184 | ||
50b7b6f2 SM |
185 | if (unlikely(p->flags & PF_IO_WORKER)) { |
186 | /* | |
187 | * An IO thread is a user space thread, but it doesn't | |
188 | * return to ret_after_fork(). | |
189 | * | |
190 | * In order to indicate that to tools like gdb, | |
191 | * we reset the stack and instruction pointers. | |
192 | * | |
193 | * It does the same kernel frame setup to return to a kernel | |
194 | * function that a kernel thread does. | |
195 | */ | |
196 | childregs->sp = 0; | |
197 | childregs->ip = 0; | |
198 | kthread_frame_init(frame, sp, arg); | |
199 | return 0; | |
200 | } | |
201 | ||
2fff071d | 202 | /* Set a new TLS for the child thread? */ |
4804e382 | 203 | if (clone_flags & CLONE_SETTLS) |
2fff071d | 204 | ret = set_new_tls(p, tls); |
4804e382 TG |
205 | |
206 | if (!ret && unlikely(test_tsk_thread_flag(current, TIF_IO_BITMAP))) | |
207 | io_bitmap_share(p); | |
208 | ||
2fff071d TG |
209 | return ret; |
210 | } | |
211 | ||
33344368 AL |
212 | static void pkru_flush_thread(void) |
213 | { | |
214 | /* | |
215 | * If PKRU is enabled the default PKRU value has to be loaded into | |
216 | * the hardware right here (similar to context switch). | |
217 | */ | |
218 | pkru_write_default(); | |
219 | } | |
220 | ||
389d1fb1 JF |
221 | void flush_thread(void) |
222 | { | |
223 | struct task_struct *tsk = current; | |
224 | ||
24f1e32c | 225 | flush_ptrace_hw_breakpoint(tsk); |
389d1fb1 | 226 | memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array)); |
110d7f75 | 227 | |
e7ecad17 | 228 | fpu_flush_thread(); |
33344368 | 229 | pkru_flush_thread(); |
389d1fb1 JF |
230 | } |
231 | ||
389d1fb1 JF |
232 | void disable_TSC(void) |
233 | { | |
234 | preempt_disable(); | |
235 | if (!test_and_set_thread_flag(TIF_NOTSC)) | |
236 | /* | |
237 | * Must flip the CPU state synchronously with | |
238 | * TIF_NOTSC in the current running context. | |
239 | */ | |
5a920155 | 240 | cr4_set_bits(X86_CR4_TSD); |
389d1fb1 JF |
241 | preempt_enable(); |
242 | } | |
243 | ||
389d1fb1 JF |
244 | static void enable_TSC(void) |
245 | { | |
246 | preempt_disable(); | |
247 | if (test_and_clear_thread_flag(TIF_NOTSC)) | |
248 | /* | |
249 | * Must flip the CPU state synchronously with | |
250 | * TIF_NOTSC in the current running context. | |
251 | */ | |
5a920155 | 252 | cr4_clear_bits(X86_CR4_TSD); |
389d1fb1 JF |
253 | preempt_enable(); |
254 | } | |
255 | ||
256 | int get_tsc_mode(unsigned long adr) | |
257 | { | |
258 | unsigned int val; | |
259 | ||
260 | if (test_thread_flag(TIF_NOTSC)) | |
261 | val = PR_TSC_SIGSEGV; | |
262 | else | |
263 | val = PR_TSC_ENABLE; | |
264 | ||
265 | return put_user(val, (unsigned int __user *)adr); | |
266 | } | |
267 | ||
268 | int set_tsc_mode(unsigned int val) | |
269 | { | |
270 | if (val == PR_TSC_SIGSEGV) | |
271 | disable_TSC(); | |
272 | else if (val == PR_TSC_ENABLE) | |
273 | enable_TSC(); | |
274 | else | |
275 | return -EINVAL; | |
276 | ||
277 | return 0; | |
278 | } | |
279 | ||
e9ea1e7f KH |
280 | DEFINE_PER_CPU(u64, msr_misc_features_shadow); |
281 | ||
282 | static void set_cpuid_faulting(bool on) | |
283 | { | |
284 | u64 msrval; | |
285 | ||
286 | msrval = this_cpu_read(msr_misc_features_shadow); | |
287 | msrval &= ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT; | |
288 | msrval |= (on << MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT); | |
289 | this_cpu_write(msr_misc_features_shadow, msrval); | |
290 | wrmsrl(MSR_MISC_FEATURES_ENABLES, msrval); | |
291 | } | |
292 | ||
293 | static void disable_cpuid(void) | |
294 | { | |
295 | preempt_disable(); | |
296 | if (!test_and_set_thread_flag(TIF_NOCPUID)) { | |
297 | /* | |
298 | * Must flip the CPU state synchronously with | |
299 | * TIF_NOCPUID in the current running context. | |
300 | */ | |
301 | set_cpuid_faulting(true); | |
302 | } | |
303 | preempt_enable(); | |
304 | } | |
305 | ||
306 | static void enable_cpuid(void) | |
307 | { | |
308 | preempt_disable(); | |
309 | if (test_and_clear_thread_flag(TIF_NOCPUID)) { | |
310 | /* | |
311 | * Must flip the CPU state synchronously with | |
312 | * TIF_NOCPUID in the current running context. | |
313 | */ | |
314 | set_cpuid_faulting(false); | |
315 | } | |
316 | preempt_enable(); | |
317 | } | |
318 | ||
319 | static int get_cpuid_mode(void) | |
320 | { | |
321 | return !test_thread_flag(TIF_NOCPUID); | |
322 | } | |
323 | ||
324 | static int set_cpuid_mode(struct task_struct *task, unsigned long cpuid_enabled) | |
325 | { | |
67e87d43 | 326 | if (!boot_cpu_has(X86_FEATURE_CPUID_FAULT)) |
e9ea1e7f KH |
327 | return -ENODEV; |
328 | ||
329 | if (cpuid_enabled) | |
330 | enable_cpuid(); | |
331 | else | |
332 | disable_cpuid(); | |
333 | ||
334 | return 0; | |
335 | } | |
336 | ||
337 | /* | |
338 | * Called immediately after a successful exec. | |
339 | */ | |
340 | void arch_setup_new_exec(void) | |
341 | { | |
342 | /* If cpuid was previously disabled for this task, re-enable it. */ | |
343 | if (test_thread_flag(TIF_NOCPUID)) | |
344 | enable_cpuid(); | |
71368af9 WL |
345 | |
346 | /* | |
347 | * Don't inherit TIF_SSBD across exec boundary when | |
348 | * PR_SPEC_DISABLE_NOEXEC is used. | |
349 | */ | |
350 | if (test_thread_flag(TIF_SSBD) && | |
351 | task_spec_ssb_noexec(current)) { | |
352 | clear_thread_flag(TIF_SSBD); | |
353 | task_clear_spec_ssb_disable(current); | |
354 | task_clear_spec_ssb_noexec(current); | |
355 | speculation_ctrl_update(task_thread_info(current)->flags); | |
356 | } | |
e9ea1e7f KH |
357 | } |
358 | ||
111e7b15 | 359 | #ifdef CONFIG_X86_IOPL_IOPERM |
22fe5b04 TG |
360 | static inline void switch_to_bitmap(unsigned long tifp) |
361 | { | |
362 | /* | |
363 | * Invalidate I/O bitmap if the previous task used it. This prevents | |
364 | * any possible leakage of an active I/O bitmap. | |
365 | * | |
366 | * If the next task has an I/O bitmap it will handle it on exit to | |
367 | * user mode. | |
368 | */ | |
369 | if (tifp & _TIF_IO_BITMAP) | |
cadfad87 | 370 | tss_invalidate_io_bitmap(); |
22fe5b04 TG |
371 | } |
372 | ||
373 | static void tss_copy_io_bitmap(struct tss_struct *tss, struct io_bitmap *iobm) | |
060aa16f TG |
374 | { |
375 | /* | |
376 | * Copy at least the byte range of the incoming tasks bitmap which | |
377 | * covers the permitted I/O ports. | |
378 | * | |
379 | * If the previous task which used an I/O bitmap had more bits | |
380 | * permitted, then the copy needs to cover those as well so they | |
381 | * get turned off. | |
382 | */ | |
383 | memcpy(tss->io_bitmap.bitmap, iobm->bitmap, | |
384 | max(tss->io_bitmap.prev_max, iobm->max)); | |
385 | ||
386 | /* | |
387 | * Store the new max and the sequence number of this bitmap | |
388 | * and a pointer to the bitmap itself. | |
389 | */ | |
390 | tss->io_bitmap.prev_max = iobm->max; | |
391 | tss->io_bitmap.prev_sequence = iobm->sequence; | |
392 | } | |
393 | ||
22fe5b04 TG |
394 | /** |
395 | * tss_update_io_bitmap - Update I/O bitmap before exiting to usermode | |
396 | */ | |
99bcd4a6 | 397 | void native_tss_update_io_bitmap(void) |
af8b3cd3 | 398 | { |
ff16701a | 399 | struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw); |
7b0b8cfd | 400 | struct thread_struct *t = ¤t->thread; |
c8137ace | 401 | u16 *base = &tss->x86_tss.io_bitmap_base; |
ff16701a | 402 | |
7b0b8cfd | 403 | if (!test_thread_flag(TIF_IO_BITMAP)) { |
cadfad87 | 404 | native_tss_invalidate_io_bitmap(); |
7b0b8cfd BP |
405 | return; |
406 | } | |
407 | ||
408 | if (IS_ENABLED(CONFIG_X86_IOPL_IOPERM) && t->iopl_emul == 3) { | |
409 | *base = IO_BITMAP_OFFSET_VALID_ALL; | |
410 | } else { | |
411 | struct io_bitmap *iobm = t->io_bitmap; | |
412 | ||
af8b3cd3 | 413 | /* |
7b0b8cfd BP |
414 | * Only copy bitmap data when the sequence number differs. The |
415 | * update time is accounted to the incoming task. | |
af8b3cd3 | 416 | */ |
7b0b8cfd BP |
417 | if (tss->io_bitmap.prev_sequence != iobm->sequence) |
418 | tss_copy_io_bitmap(tss, iobm); | |
419 | ||
420 | /* Enable the bitmap */ | |
421 | *base = IO_BITMAP_OFFSET_VALID_MAP; | |
af8b3cd3 | 422 | } |
7b0b8cfd BP |
423 | |
424 | /* | |
425 | * Make sure that the TSS limit is covering the IO bitmap. It might have | |
426 | * been cut down by a VMEXIT to 0x67 which would cause a subsequent I/O | |
427 | * access from user space to trigger a #GP because tbe bitmap is outside | |
428 | * the TSS limit. | |
429 | */ | |
430 | refresh_tss_limit(); | |
af8b3cd3 | 431 | } |
111e7b15 TG |
432 | #else /* CONFIG_X86_IOPL_IOPERM */ |
433 | static inline void switch_to_bitmap(unsigned long tifp) { } | |
434 | #endif | |
af8b3cd3 | 435 | |
1f50ddb4 TG |
436 | #ifdef CONFIG_SMP |
437 | ||
438 | struct ssb_state { | |
439 | struct ssb_state *shared_state; | |
440 | raw_spinlock_t lock; | |
441 | unsigned int disable_state; | |
442 | unsigned long local_state; | |
443 | }; | |
444 | ||
445 | #define LSTATE_SSB 0 | |
446 | ||
447 | static DEFINE_PER_CPU(struct ssb_state, ssb_state); | |
448 | ||
449 | void speculative_store_bypass_ht_init(void) | |
885f82bf | 450 | { |
1f50ddb4 TG |
451 | struct ssb_state *st = this_cpu_ptr(&ssb_state); |
452 | unsigned int this_cpu = smp_processor_id(); | |
453 | unsigned int cpu; | |
454 | ||
455 | st->local_state = 0; | |
456 | ||
457 | /* | |
458 | * Shared state setup happens once on the first bringup | |
459 | * of the CPU. It's not destroyed on CPU hotunplug. | |
460 | */ | |
461 | if (st->shared_state) | |
462 | return; | |
463 | ||
464 | raw_spin_lock_init(&st->lock); | |
465 | ||
466 | /* | |
467 | * Go over HT siblings and check whether one of them has set up the | |
468 | * shared state pointer already. | |
469 | */ | |
470 | for_each_cpu(cpu, topology_sibling_cpumask(this_cpu)) { | |
471 | if (cpu == this_cpu) | |
472 | continue; | |
473 | ||
474 | if (!per_cpu(ssb_state, cpu).shared_state) | |
475 | continue; | |
476 | ||
477 | /* Link it to the state of the sibling: */ | |
478 | st->shared_state = per_cpu(ssb_state, cpu).shared_state; | |
479 | return; | |
480 | } | |
481 | ||
482 | /* | |
483 | * First HT sibling to come up on the core. Link shared state of | |
484 | * the first HT sibling to itself. The siblings on the same core | |
485 | * which come up later will see the shared state pointer and link | |
d9f6e12f | 486 | * themselves to the state of this CPU. |
1f50ddb4 TG |
487 | */ |
488 | st->shared_state = st; | |
489 | } | |
885f82bf | 490 | |
1f50ddb4 TG |
491 | /* |
492 | * Logic is: First HT sibling enables SSBD for both siblings in the core | |
493 | * and last sibling to disable it, disables it for the whole core. This how | |
494 | * MSR_SPEC_CTRL works in "hardware": | |
495 | * | |
496 | * CORE_SPEC_CTRL = THREAD0_SPEC_CTRL | THREAD1_SPEC_CTRL | |
497 | */ | |
498 | static __always_inline void amd_set_core_ssb_state(unsigned long tifn) | |
499 | { | |
500 | struct ssb_state *st = this_cpu_ptr(&ssb_state); | |
501 | u64 msr = x86_amd_ls_cfg_base; | |
502 | ||
503 | if (!static_cpu_has(X86_FEATURE_ZEN)) { | |
504 | msr |= ssbd_tif_to_amd_ls_cfg(tifn); | |
885f82bf | 505 | wrmsrl(MSR_AMD64_LS_CFG, msr); |
1f50ddb4 TG |
506 | return; |
507 | } | |
508 | ||
509 | if (tifn & _TIF_SSBD) { | |
510 | /* | |
511 | * Since this can race with prctl(), block reentry on the | |
512 | * same CPU. | |
513 | */ | |
514 | if (__test_and_set_bit(LSTATE_SSB, &st->local_state)) | |
515 | return; | |
516 | ||
517 | msr |= x86_amd_ls_cfg_ssbd_mask; | |
518 | ||
519 | raw_spin_lock(&st->shared_state->lock); | |
520 | /* First sibling enables SSBD: */ | |
521 | if (!st->shared_state->disable_state) | |
522 | wrmsrl(MSR_AMD64_LS_CFG, msr); | |
523 | st->shared_state->disable_state++; | |
524 | raw_spin_unlock(&st->shared_state->lock); | |
885f82bf | 525 | } else { |
1f50ddb4 TG |
526 | if (!__test_and_clear_bit(LSTATE_SSB, &st->local_state)) |
527 | return; | |
528 | ||
529 | raw_spin_lock(&st->shared_state->lock); | |
530 | st->shared_state->disable_state--; | |
531 | if (!st->shared_state->disable_state) | |
532 | wrmsrl(MSR_AMD64_LS_CFG, msr); | |
533 | raw_spin_unlock(&st->shared_state->lock); | |
885f82bf TG |
534 | } |
535 | } | |
1f50ddb4 TG |
536 | #else |
537 | static __always_inline void amd_set_core_ssb_state(unsigned long tifn) | |
538 | { | |
539 | u64 msr = x86_amd_ls_cfg_base | ssbd_tif_to_amd_ls_cfg(tifn); | |
540 | ||
541 | wrmsrl(MSR_AMD64_LS_CFG, msr); | |
542 | } | |
543 | #endif | |
544 | ||
11fb0683 TL |
545 | static __always_inline void amd_set_ssb_virt_state(unsigned long tifn) |
546 | { | |
547 | /* | |
548 | * SSBD has the same definition in SPEC_CTRL and VIRT_SPEC_CTRL, | |
549 | * so ssbd_tif_to_spec_ctrl() just works. | |
550 | */ | |
551 | wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, ssbd_tif_to_spec_ctrl(tifn)); | |
552 | } | |
553 | ||
01daf568 TC |
554 | /* |
555 | * Update the MSRs managing speculation control, during context switch. | |
556 | * | |
557 | * tifp: Previous task's thread flags | |
558 | * tifn: Next task's thread flags | |
559 | */ | |
560 | static __always_inline void __speculation_ctrl_update(unsigned long tifp, | |
561 | unsigned long tifn) | |
1f50ddb4 | 562 | { |
5bfbe3ad | 563 | unsigned long tif_diff = tifp ^ tifn; |
01daf568 TC |
564 | u64 msr = x86_spec_ctrl_base; |
565 | bool updmsr = false; | |
566 | ||
2f5fb193 TG |
567 | lockdep_assert_irqs_disabled(); |
568 | ||
dbbe2ad0 AS |
569 | /* Handle change of TIF_SSBD depending on the mitigation method. */ |
570 | if (static_cpu_has(X86_FEATURE_VIRT_SSBD)) { | |
571 | if (tif_diff & _TIF_SSBD) | |
01daf568 | 572 | amd_set_ssb_virt_state(tifn); |
dbbe2ad0 AS |
573 | } else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD)) { |
574 | if (tif_diff & _TIF_SSBD) | |
01daf568 | 575 | amd_set_core_ssb_state(tifn); |
dbbe2ad0 AS |
576 | } else if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) || |
577 | static_cpu_has(X86_FEATURE_AMD_SSBD)) { | |
578 | updmsr |= !!(tif_diff & _TIF_SSBD); | |
579 | msr |= ssbd_tif_to_spec_ctrl(tifn); | |
01daf568 | 580 | } |
1f50ddb4 | 581 | |
dbbe2ad0 | 582 | /* Only evaluate TIF_SPEC_IB if conditional STIBP is enabled. */ |
5bfbe3ad TC |
583 | if (IS_ENABLED(CONFIG_SMP) && |
584 | static_branch_unlikely(&switch_to_cond_stibp)) { | |
585 | updmsr |= !!(tif_diff & _TIF_SPEC_IB); | |
586 | msr |= stibp_tif_to_spec_ctrl(tifn); | |
587 | } | |
588 | ||
01daf568 TC |
589 | if (updmsr) |
590 | wrmsrl(MSR_IA32_SPEC_CTRL, msr); | |
1f50ddb4 TG |
591 | } |
592 | ||
6d991ba5 | 593 | static unsigned long speculation_ctrl_update_tif(struct task_struct *tsk) |
1f50ddb4 | 594 | { |
6d991ba5 TG |
595 | if (test_and_clear_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE)) { |
596 | if (task_spec_ssb_disable(tsk)) | |
597 | set_tsk_thread_flag(tsk, TIF_SSBD); | |
598 | else | |
599 | clear_tsk_thread_flag(tsk, TIF_SSBD); | |
9137bb27 TG |
600 | |
601 | if (task_spec_ib_disable(tsk)) | |
602 | set_tsk_thread_flag(tsk, TIF_SPEC_IB); | |
603 | else | |
604 | clear_tsk_thread_flag(tsk, TIF_SPEC_IB); | |
6d991ba5 TG |
605 | } |
606 | /* Return the updated threadinfo flags*/ | |
607 | return task_thread_info(tsk)->flags; | |
1f50ddb4 | 608 | } |
885f82bf | 609 | |
26c4d75b | 610 | void speculation_ctrl_update(unsigned long tif) |
885f82bf | 611 | { |
2f5fb193 TG |
612 | unsigned long flags; |
613 | ||
01daf568 | 614 | /* Forced update. Make sure all relevant TIF flags are different */ |
2f5fb193 | 615 | local_irq_save(flags); |
01daf568 | 616 | __speculation_ctrl_update(~tif, tif); |
2f5fb193 | 617 | local_irq_restore(flags); |
885f82bf TG |
618 | } |
619 | ||
6d991ba5 TG |
620 | /* Called from seccomp/prctl update */ |
621 | void speculation_ctrl_update_current(void) | |
622 | { | |
623 | preempt_disable(); | |
624 | speculation_ctrl_update(speculation_ctrl_update_tif(current)); | |
625 | preempt_enable(); | |
626 | } | |
627 | ||
d8f0b353 TG |
628 | static inline void cr4_toggle_bits_irqsoff(unsigned long mask) |
629 | { | |
630 | unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4); | |
631 | ||
632 | newval = cr4 ^ mask; | |
633 | if (newval != cr4) { | |
634 | this_cpu_write(cpu_tlbstate.cr4, newval); | |
635 | __write_cr4(newval); | |
636 | } | |
637 | } | |
638 | ||
ff16701a | 639 | void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p) |
389d1fb1 | 640 | { |
af8b3cd3 | 641 | unsigned long tifp, tifn; |
389d1fb1 | 642 | |
af8b3cd3 KH |
643 | tifn = READ_ONCE(task_thread_info(next_p)->flags); |
644 | tifp = READ_ONCE(task_thread_info(prev_p)->flags); | |
22fe5b04 TG |
645 | |
646 | switch_to_bitmap(tifp); | |
af8b3cd3 KH |
647 | |
648 | propagate_user_return_notify(prev_p, next_p); | |
649 | ||
b9894a2f KH |
650 | if ((tifp & _TIF_BLOCKSTEP || tifn & _TIF_BLOCKSTEP) && |
651 | arch_has_block_step()) { | |
652 | unsigned long debugctl, msk; | |
ea8e61b7 | 653 | |
b9894a2f | 654 | rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); |
ea8e61b7 | 655 | debugctl &= ~DEBUGCTLMSR_BTF; |
b9894a2f KH |
656 | msk = tifn & _TIF_BLOCKSTEP; |
657 | debugctl |= (msk >> TIF_BLOCKSTEP) << DEBUGCTLMSR_BTF_SHIFT; | |
658 | wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); | |
ea8e61b7 | 659 | } |
389d1fb1 | 660 | |
5a920155 | 661 | if ((tifp ^ tifn) & _TIF_NOTSC) |
9d0b6232 | 662 | cr4_toggle_bits_irqsoff(X86_CR4_TSD); |
e9ea1e7f KH |
663 | |
664 | if ((tifp ^ tifn) & _TIF_NOCPUID) | |
665 | set_cpuid_faulting(!!(tifn & _TIF_NOCPUID)); | |
885f82bf | 666 | |
6d991ba5 TG |
667 | if (likely(!((tifp | tifn) & _TIF_SPEC_FORCE_UPDATE))) { |
668 | __speculation_ctrl_update(tifp, tifn); | |
669 | } else { | |
670 | speculation_ctrl_update_tif(prev_p); | |
671 | tifn = speculation_ctrl_update_tif(next_p); | |
672 | ||
673 | /* Enforce MSR update to ensure consistent state */ | |
674 | __speculation_ctrl_update(~tifn, tifn); | |
675 | } | |
6650cdd9 PZI |
676 | |
677 | if ((tifp ^ tifn) & _TIF_SLD) | |
678 | switch_to_sld(tifn); | |
389d1fb1 JF |
679 | } |
680 | ||
00dba564 TG |
681 | /* |
682 | * Idle related variables and functions | |
683 | */ | |
d1896049 | 684 | unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE; |
00dba564 TG |
685 | EXPORT_SYMBOL(boot_option_idle_override); |
686 | ||
a476bda3 | 687 | static void (*x86_idle)(void); |
00dba564 | 688 | |
90e24014 RW |
689 | #ifndef CONFIG_SMP |
690 | static inline void play_dead(void) | |
691 | { | |
692 | BUG(); | |
693 | } | |
694 | #endif | |
695 | ||
7d1a9417 TG |
696 | void arch_cpu_idle_enter(void) |
697 | { | |
6a369583 | 698 | tsc_verify_tsc_adjust(false); |
7d1a9417 | 699 | local_touch_nmi(); |
7d1a9417 | 700 | } |
90e24014 | 701 | |
7d1a9417 TG |
702 | void arch_cpu_idle_dead(void) |
703 | { | |
704 | play_dead(); | |
705 | } | |
90e24014 | 706 | |
7d1a9417 TG |
707 | /* |
708 | * Called from the generic idle code. | |
709 | */ | |
710 | void arch_cpu_idle(void) | |
711 | { | |
16f8b05a | 712 | x86_idle(); |
90e24014 RW |
713 | } |
714 | ||
00dba564 | 715 | /* |
7d1a9417 | 716 | * We use this if we don't have any better idle routine.. |
00dba564 | 717 | */ |
6727ad9e | 718 | void __cpuidle default_idle(void) |
00dba564 | 719 | { |
58c644ba | 720 | raw_safe_halt(); |
00dba564 | 721 | } |
fa86ee90 | 722 | #if defined(CONFIG_APM_MODULE) || defined(CONFIG_HALTPOLL_CPUIDLE_MODULE) |
00dba564 TG |
723 | EXPORT_SYMBOL(default_idle); |
724 | #endif | |
725 | ||
6a377ddc LB |
726 | #ifdef CONFIG_XEN |
727 | bool xen_set_default_idle(void) | |
e5fd47bf | 728 | { |
a476bda3 | 729 | bool ret = !!x86_idle; |
e5fd47bf | 730 | |
a476bda3 | 731 | x86_idle = default_idle; |
e5fd47bf KRW |
732 | |
733 | return ret; | |
734 | } | |
6a377ddc | 735 | #endif |
bba4ed01 | 736 | |
d3ec5cae IV |
737 | void stop_this_cpu(void *dummy) |
738 | { | |
739 | local_irq_disable(); | |
740 | /* | |
741 | * Remove this CPU: | |
742 | */ | |
4f062896 | 743 | set_cpu_online(smp_processor_id(), false); |
d3ec5cae | 744 | disable_local_APIC(); |
8838eb6c | 745 | mcheck_cpu_clear(this_cpu_ptr(&cpu_info)); |
d3ec5cae | 746 | |
f23d74f6 TL |
747 | /* |
748 | * Use wbinvd on processors that support SME. This provides support | |
749 | * for performing a successful kexec when going from SME inactive | |
750 | * to SME active (or vice-versa). The cache must be cleared so that | |
751 | * if there are entries with the same physical address, both with and | |
752 | * without the encryption bit, they don't race each other when flushed | |
753 | * and potentially end up with the wrong entry being committed to | |
754 | * memory. | |
755 | */ | |
756 | if (boot_cpu_has(X86_FEATURE_SME)) | |
757 | native_wbinvd(); | |
bba4ed01 TL |
758 | for (;;) { |
759 | /* | |
f23d74f6 TL |
760 | * Use native_halt() so that memory contents don't change |
761 | * (stack usage and variables) after possibly issuing the | |
762 | * native_wbinvd() above. | |
bba4ed01 | 763 | */ |
f23d74f6 | 764 | native_halt(); |
bba4ed01 | 765 | } |
7f424a8b PZ |
766 | } |
767 | ||
aa276e1c | 768 | /* |
07c94a38 BP |
769 | * AMD Erratum 400 aware idle routine. We handle it the same way as C3 power |
770 | * states (local apic timer and TSC stop). | |
58c644ba PZ |
771 | * |
772 | * XXX this function is completely buggered vs RCU and tracing. | |
aa276e1c | 773 | */ |
02c68a02 | 774 | static void amd_e400_idle(void) |
aa276e1c | 775 | { |
07c94a38 BP |
776 | /* |
777 | * We cannot use static_cpu_has_bug() here because X86_BUG_AMD_APIC_C1E | |
778 | * gets set after static_cpu_has() places have been converted via | |
779 | * alternatives. | |
780 | */ | |
781 | if (!boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) { | |
782 | default_idle(); | |
783 | return; | |
aa276e1c TG |
784 | } |
785 | ||
07c94a38 | 786 | tick_broadcast_enter(); |
aa276e1c | 787 | |
07c94a38 | 788 | default_idle(); |
0beefa20 | 789 | |
07c94a38 BP |
790 | /* |
791 | * The switch back from broadcast mode needs to be called with | |
792 | * interrupts disabled. | |
793 | */ | |
58c644ba | 794 | raw_local_irq_disable(); |
07c94a38 | 795 | tick_broadcast_exit(); |
58c644ba | 796 | raw_local_irq_enable(); |
aa276e1c TG |
797 | } |
798 | ||
b253149b LB |
799 | /* |
800 | * Intel Core2 and older machines prefer MWAIT over HALT for C1. | |
801 | * We can't rely on cpuidle installing MWAIT, because it will not load | |
802 | * on systems that support only C1 -- so the boot default must be MWAIT. | |
803 | * | |
804 | * Some AMD machines are the opposite, they depend on using HALT. | |
805 | * | |
806 | * So for default C1, which is used during boot until cpuidle loads, | |
807 | * use MWAIT-C1 on Intel HW that has it, else use HALT. | |
808 | */ | |
809 | static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c) | |
810 | { | |
811 | if (c->x86_vendor != X86_VENDOR_INTEL) | |
812 | return 0; | |
813 | ||
67e87d43 | 814 | if (!cpu_has(c, X86_FEATURE_MWAIT) || boot_cpu_has_bug(X86_BUG_MONITOR)) |
b253149b LB |
815 | return 0; |
816 | ||
817 | return 1; | |
818 | } | |
819 | ||
820 | /* | |
0fb0328d HR |
821 | * MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT |
822 | * with interrupts enabled and no flags, which is backwards compatible with the | |
823 | * original MWAIT implementation. | |
b253149b | 824 | */ |
6727ad9e | 825 | static __cpuidle void mwait_idle(void) |
b253149b | 826 | { |
f8e617f4 MG |
827 | if (!current_set_polling_and_test()) { |
828 | if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) { | |
ca59809f | 829 | mb(); /* quirk */ |
b253149b | 830 | clflush((void *)¤t_thread_info()->flags); |
ca59809f | 831 | mb(); /* quirk */ |
f8e617f4 | 832 | } |
b253149b LB |
833 | |
834 | __monitor((void *)¤t_thread_info()->flags, 0, 0); | |
b253149b LB |
835 | if (!need_resched()) |
836 | __sti_mwait(0, 0); | |
837 | else | |
58c644ba | 838 | raw_local_irq_enable(); |
f8e617f4 | 839 | } else { |
58c644ba | 840 | raw_local_irq_enable(); |
f8e617f4 MG |
841 | } |
842 | __current_clr_polling(); | |
b253149b LB |
843 | } |
844 | ||
148f9bb8 | 845 | void select_idle_routine(const struct cpuinfo_x86 *c) |
7f424a8b | 846 | { |
3e5095d1 | 847 | #ifdef CONFIG_SMP |
7d1a9417 | 848 | if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1) |
c767a54b | 849 | pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n"); |
7f424a8b | 850 | #endif |
7d1a9417 | 851 | if (x86_idle || boot_option_idle_override == IDLE_POLL) |
6ddd2a27 TG |
852 | return; |
853 | ||
3344ed30 | 854 | if (boot_cpu_has_bug(X86_BUG_AMD_E400)) { |
c767a54b | 855 | pr_info("using AMD E400 aware idle routine\n"); |
a476bda3 | 856 | x86_idle = amd_e400_idle; |
b253149b LB |
857 | } else if (prefer_mwait_c1_over_halt(c)) { |
858 | pr_info("using mwait in idle threads\n"); | |
859 | x86_idle = mwait_idle; | |
6ddd2a27 | 860 | } else |
a476bda3 | 861 | x86_idle = default_idle; |
7f424a8b PZ |
862 | } |
863 | ||
07c94a38 | 864 | void amd_e400_c1e_apic_setup(void) |
30e1e6d1 | 865 | { |
07c94a38 BP |
866 | if (boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) { |
867 | pr_info("Switch to broadcast mode on CPU%d\n", smp_processor_id()); | |
868 | local_irq_disable(); | |
869 | tick_broadcast_force(); | |
870 | local_irq_enable(); | |
871 | } | |
30e1e6d1 RR |
872 | } |
873 | ||
e7ff3a47 TG |
874 | void __init arch_post_acpi_subsys_init(void) |
875 | { | |
876 | u32 lo, hi; | |
877 | ||
878 | if (!boot_cpu_has_bug(X86_BUG_AMD_E400)) | |
879 | return; | |
880 | ||
881 | /* | |
882 | * AMD E400 detection needs to happen after ACPI has been enabled. If | |
883 | * the machine is affected K8_INTP_C1E_ACTIVE_MASK bits are set in | |
884 | * MSR_K8_INT_PENDING_MSG. | |
885 | */ | |
886 | rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi); | |
887 | if (!(lo & K8_INTP_C1E_ACTIVE_MASK)) | |
888 | return; | |
889 | ||
890 | boot_cpu_set_bug(X86_BUG_AMD_APIC_C1E); | |
891 | ||
892 | if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) | |
893 | mark_tsc_unstable("TSC halt in AMD C1E"); | |
894 | pr_info("System has AMD C1E enabled\n"); | |
895 | } | |
896 | ||
7f424a8b PZ |
897 | static int __init idle_setup(char *str) |
898 | { | |
ab6bc3e3 CG |
899 | if (!str) |
900 | return -EINVAL; | |
901 | ||
7f424a8b | 902 | if (!strcmp(str, "poll")) { |
c767a54b | 903 | pr_info("using polling idle threads\n"); |
d1896049 | 904 | boot_option_idle_override = IDLE_POLL; |
7d1a9417 | 905 | cpu_idle_poll_ctrl(true); |
d1896049 | 906 | } else if (!strcmp(str, "halt")) { |
c1e3b377 ZY |
907 | /* |
908 | * When the boot option of idle=halt is added, halt is | |
909 | * forced to be used for CPU idle. In such case CPU C2/C3 | |
910 | * won't be used again. | |
911 | * To continue to load the CPU idle driver, don't touch | |
912 | * the boot_option_idle_override. | |
913 | */ | |
a476bda3 | 914 | x86_idle = default_idle; |
d1896049 | 915 | boot_option_idle_override = IDLE_HALT; |
da5e09a1 ZY |
916 | } else if (!strcmp(str, "nomwait")) { |
917 | /* | |
918 | * If the boot option of "idle=nomwait" is added, | |
919 | * it means that mwait will be disabled for CPU C2/C3 | |
920 | * states. In such case it won't touch the variable | |
921 | * of boot_option_idle_override. | |
922 | */ | |
d1896049 | 923 | boot_option_idle_override = IDLE_NOMWAIT; |
c1e3b377 | 924 | } else |
7f424a8b PZ |
925 | return -1; |
926 | ||
7f424a8b PZ |
927 | return 0; |
928 | } | |
929 | early_param("idle", idle_setup); | |
930 | ||
9d62dcdf AW |
931 | unsigned long arch_align_stack(unsigned long sp) |
932 | { | |
933 | if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) | |
934 | sp -= get_random_int() % 8192; | |
935 | return sp & ~0xf; | |
936 | } | |
937 | ||
938 | unsigned long arch_randomize_brk(struct mm_struct *mm) | |
939 | { | |
9c6f0902 | 940 | return randomize_page(mm->brk, 0x02000000); |
9d62dcdf AW |
941 | } |
942 | ||
7ba78053 TG |
943 | /* |
944 | * Called from fs/proc with a reference on @p to find the function | |
945 | * which called into schedule(). This needs to be done carefully | |
946 | * because the task might wake up and we might look at a stack | |
947 | * changing under us. | |
948 | */ | |
949 | unsigned long get_wchan(struct task_struct *p) | |
950 | { | |
74327a3e | 951 | unsigned long start, bottom, top, sp, fp, ip, ret = 0; |
7ba78053 TG |
952 | int count = 0; |
953 | ||
b03fbd4f | 954 | if (p == current || task_is_running(p)) |
7ba78053 TG |
955 | return 0; |
956 | ||
74327a3e AL |
957 | if (!try_get_task_stack(p)) |
958 | return 0; | |
959 | ||
7ba78053 TG |
960 | start = (unsigned long)task_stack_page(p); |
961 | if (!start) | |
74327a3e | 962 | goto out; |
7ba78053 TG |
963 | |
964 | /* | |
965 | * Layout of the stack page: | |
966 | * | |
967 | * ----------- topmax = start + THREAD_SIZE - sizeof(unsigned long) | |
968 | * PADDING | |
969 | * ----------- top = topmax - TOP_OF_KERNEL_STACK_PADDING | |
970 | * stack | |
15f4eae7 | 971 | * ----------- bottom = start |
7ba78053 TG |
972 | * |
973 | * The tasks stack pointer points at the location where the | |
974 | * framepointer is stored. The data on the stack is: | |
975 | * ... IP FP ... IP FP | |
976 | * | |
977 | * We need to read FP and IP, so we need to adjust the upper | |
978 | * bound by another unsigned long. | |
979 | */ | |
980 | top = start + THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; | |
981 | top -= 2 * sizeof(unsigned long); | |
15f4eae7 | 982 | bottom = start; |
7ba78053 TG |
983 | |
984 | sp = READ_ONCE(p->thread.sp); | |
985 | if (sp < bottom || sp > top) | |
74327a3e | 986 | goto out; |
7ba78053 | 987 | |
7b32aead | 988 | fp = READ_ONCE_NOCHECK(((struct inactive_task_frame *)sp)->bp); |
7ba78053 TG |
989 | do { |
990 | if (fp < bottom || fp > top) | |
74327a3e | 991 | goto out; |
f7d27c35 | 992 | ip = READ_ONCE_NOCHECK(*(unsigned long *)(fp + sizeof(unsigned long))); |
74327a3e AL |
993 | if (!in_sched_functions(ip)) { |
994 | ret = ip; | |
995 | goto out; | |
996 | } | |
f7d27c35 | 997 | fp = READ_ONCE_NOCHECK(*(unsigned long *)fp); |
b03fbd4f | 998 | } while (count++ < 16 && !task_is_running(p)); |
74327a3e AL |
999 | |
1000 | out: | |
1001 | put_task_stack(p); | |
1002 | return ret; | |
7ba78053 | 1003 | } |
b0b9b014 KH |
1004 | |
1005 | long do_arch_prctl_common(struct task_struct *task, int option, | |
1006 | unsigned long cpuid_enabled) | |
1007 | { | |
e9ea1e7f KH |
1008 | switch (option) { |
1009 | case ARCH_GET_CPUID: | |
1010 | return get_cpuid_mode(); | |
1011 | case ARCH_SET_CPUID: | |
1012 | return set_cpuid_mode(task, cpuid_enabled); | |
1013 | } | |
1014 | ||
b0b9b014 KH |
1015 | return -EINVAL; |
1016 | } |