Commit | Line | Data |
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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
c767a54b JP |
2 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
3 | ||
61c4628b SS |
4 | #include <linux/errno.h> |
5 | #include <linux/kernel.h> | |
6 | #include <linux/mm.h> | |
7 | #include <linux/smp.h> | |
389d1fb1 | 8 | #include <linux/prctl.h> |
61c4628b SS |
9 | #include <linux/slab.h> |
10 | #include <linux/sched.h> | |
4c822698 | 11 | #include <linux/sched/idle.h> |
b17b0153 | 12 | #include <linux/sched/debug.h> |
29930025 | 13 | #include <linux/sched/task.h> |
68db0cf1 | 14 | #include <linux/sched/task_stack.h> |
186f4360 PG |
15 | #include <linux/init.h> |
16 | #include <linux/export.h> | |
7f424a8b | 17 | #include <linux/pm.h> |
162a688e | 18 | #include <linux/tick.h> |
9d62dcdf | 19 | #include <linux/random.h> |
7c68af6e | 20 | #include <linux/user-return-notifier.h> |
814e2c84 AI |
21 | #include <linux/dmi.h> |
22 | #include <linux/utsname.h> | |
90e24014 | 23 | #include <linux/stackprotector.h> |
90e24014 | 24 | #include <linux/cpuidle.h> |
89f579ce YW |
25 | #include <linux/acpi.h> |
26 | #include <linux/elf-randomize.h> | |
61613521 | 27 | #include <trace/events/power.h> |
24f1e32c | 28 | #include <linux/hw_breakpoint.h> |
93789b32 | 29 | #include <asm/cpu.h> |
d3ec5cae | 30 | #include <asm/apic.h> |
7c0f6ba6 | 31 | #include <linux/uaccess.h> |
b253149b | 32 | #include <asm/mwait.h> |
78f7f1e5 | 33 | #include <asm/fpu/internal.h> |
66cb5917 | 34 | #include <asm/debugreg.h> |
90e24014 | 35 | #include <asm/nmi.h> |
375074cc | 36 | #include <asm/tlbflush.h> |
8838eb6c | 37 | #include <asm/mce.h> |
9fda6a06 | 38 | #include <asm/vm86.h> |
7b32aead | 39 | #include <asm/switch_to.h> |
b7ffc44d | 40 | #include <asm/desc.h> |
e9ea1e7f | 41 | #include <asm/prctl.h> |
885f82bf | 42 | #include <asm/spec-ctrl.h> |
577d5cd7 | 43 | #include <asm/io_bitmap.h> |
89f579ce | 44 | #include <asm/proto.h> |
6f9885a3 | 45 | #include <asm/frame.h> |
90e24014 | 46 | |
ff16701a TG |
47 | #include "process.h" |
48 | ||
45046892 TG |
49 | /* |
50 | * per-CPU TSS segments. Threads are completely 'soft' on Linux, | |
51 | * no more per-task TSS's. The TSS size is kept cacheline-aligned | |
52 | * so they are allowed to end up in the .data..cacheline_aligned | |
53 | * section. Since TSS's are completely CPU-local, we want them | |
54 | * on exact cacheline boundaries, to eliminate cacheline ping-pong. | |
55 | */ | |
2fd9c41a | 56 | __visible DEFINE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw) = { |
d0a0de21 | 57 | .x86_tss = { |
20bb8344 AL |
58 | /* |
59 | * .sp0 is only used when entering ring 0 from a lower | |
60 | * privilege level. Since the init task never runs anything | |
61 | * but ring 0 code, there is no need for a valid value here. | |
62 | * Poison it. | |
63 | */ | |
64 | .sp0 = (1UL << (BITS_PER_LONG-1)) + 1, | |
9aaefe7b | 65 | |
1591584e | 66 | #ifdef CONFIG_X86_32 |
9aaefe7b | 67 | .sp1 = TOP_OF_INIT_STACK, |
9aaefe7b | 68 | |
d0a0de21 AL |
69 | .ss0 = __KERNEL_DS, |
70 | .ss1 = __KERNEL_CS, | |
d0a0de21 | 71 | #endif |
ecc7e37d | 72 | .io_bitmap_base = IO_BITMAP_OFFSET_INVALID, |
d0a0de21 | 73 | }, |
d0a0de21 | 74 | }; |
c482feef | 75 | EXPORT_PER_CPU_SYMBOL(cpu_tss_rw); |
45046892 | 76 | |
b7ceaec1 AL |
77 | DEFINE_PER_CPU(bool, __tss_limit_invalid); |
78 | EXPORT_PER_CPU_SYMBOL_GPL(__tss_limit_invalid); | |
b7ffc44d | 79 | |
55ccf3fe SS |
80 | /* |
81 | * this gets called so that we can store lazy state into memory and copy the | |
82 | * current task into the new thread. | |
83 | */ | |
61c4628b SS |
84 | int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) |
85 | { | |
5aaeb5c0 | 86 | memcpy(dst, src, arch_task_struct_size); |
2459ee86 AL |
87 | #ifdef CONFIG_VM86 |
88 | dst->thread.vm86 = NULL; | |
89 | #endif | |
b2681e79 | 90 | return fpu_clone(dst); |
61c4628b | 91 | } |
7f424a8b | 92 | |
389d1fb1 | 93 | /* |
4bfe6cce | 94 | * Free thread data structures etc.. |
389d1fb1 | 95 | */ |
e6464694 | 96 | void exit_thread(struct task_struct *tsk) |
389d1fb1 | 97 | { |
e6464694 | 98 | struct thread_struct *t = &tsk->thread; |
ca6787ba | 99 | struct fpu *fpu = &t->fpu; |
ea5f1cd7 TG |
100 | |
101 | if (test_thread_flag(TIF_IO_BITMAP)) | |
4bfe6cce | 102 | io_bitmap_exit(tsk); |
1dcc8d7b | 103 | |
9fda6a06 BG |
104 | free_vm86(t); |
105 | ||
50338615 | 106 | fpu__drop(fpu); |
389d1fb1 JF |
107 | } |
108 | ||
2fff071d TG |
109 | static int set_new_tls(struct task_struct *p, unsigned long tls) |
110 | { | |
111 | struct user_desc __user *utls = (struct user_desc __user *)tls; | |
112 | ||
113 | if (in_ia32_syscall()) | |
114 | return do_set_thread_area(p, -1, utls, 0); | |
115 | else | |
116 | return do_set_thread_area_64(p, ARCH_SET_FS, tls); | |
117 | } | |
118 | ||
714acdbd CB |
119 | int copy_thread(unsigned long clone_flags, unsigned long sp, unsigned long arg, |
120 | struct task_struct *p, unsigned long tls) | |
2fff071d TG |
121 | { |
122 | struct inactive_task_frame *frame; | |
123 | struct fork_frame *fork_frame; | |
124 | struct pt_regs *childregs; | |
4804e382 | 125 | int ret = 0; |
2fff071d TG |
126 | |
127 | childregs = task_pt_regs(p); | |
128 | fork_frame = container_of(childregs, struct fork_frame, regs); | |
129 | frame = &fork_frame->frame; | |
130 | ||
6f9885a3 | 131 | frame->bp = encode_frame_pointer(childregs); |
2fff071d TG |
132 | frame->ret_addr = (unsigned long) ret_from_fork; |
133 | p->thread.sp = (unsigned long) fork_frame; | |
577d5cd7 | 134 | p->thread.io_bitmap = NULL; |
2fff071d TG |
135 | memset(p->thread.ptrace_bps, 0, sizeof(p->thread.ptrace_bps)); |
136 | ||
137 | #ifdef CONFIG_X86_64 | |
005f141e CB |
138 | current_save_fsgs(); |
139 | p->thread.fsindex = current->thread.fsindex; | |
140 | p->thread.fsbase = current->thread.fsbase; | |
141 | p->thread.gsindex = current->thread.gsindex; | |
142 | p->thread.gsbase = current->thread.gsbase; | |
143 | ||
2fff071d TG |
144 | savesegment(es, p->thread.es); |
145 | savesegment(ds, p->thread.ds); | |
146 | #else | |
147 | p->thread.sp0 = (unsigned long) (childregs + 1); | |
148 | /* | |
149 | * Clear all status flags including IF and set fixed bit. 64bit | |
150 | * does not have this initialization as the frame does not contain | |
151 | * flags. The flags consistency (especially vs. AC) is there | |
152 | * ensured via objtool, which lacks 32bit support. | |
153 | */ | |
154 | frame->flags = X86_EFLAGS_FIXED; | |
155 | #endif | |
156 | ||
157 | /* Kernel thread ? */ | |
50b7b6f2 | 158 | if (unlikely(p->flags & PF_KTHREAD)) { |
9782a712 | 159 | p->thread.pkru = pkru_get_init_value(); |
2fff071d TG |
160 | memset(childregs, 0, sizeof(struct pt_regs)); |
161 | kthread_frame_init(frame, sp, arg); | |
162 | return 0; | |
163 | } | |
164 | ||
9782a712 DH |
165 | /* |
166 | * Clone current's PKRU value from hardware. tsk->thread.pkru | |
167 | * is only valid when scheduled out. | |
168 | */ | |
169 | p->thread.pkru = read_pkru(); | |
170 | ||
2fff071d TG |
171 | frame->bx = 0; |
172 | *childregs = *current_pt_regs(); | |
173 | childregs->ax = 0; | |
174 | if (sp) | |
175 | childregs->sp = sp; | |
176 | ||
177 | #ifdef CONFIG_X86_32 | |
178 | task_user_gs(p) = get_user_gs(current_pt_regs()); | |
179 | #endif | |
180 | ||
50b7b6f2 SM |
181 | if (unlikely(p->flags & PF_IO_WORKER)) { |
182 | /* | |
183 | * An IO thread is a user space thread, but it doesn't | |
184 | * return to ret_after_fork(). | |
185 | * | |
186 | * In order to indicate that to tools like gdb, | |
187 | * we reset the stack and instruction pointers. | |
188 | * | |
189 | * It does the same kernel frame setup to return to a kernel | |
190 | * function that a kernel thread does. | |
191 | */ | |
192 | childregs->sp = 0; | |
193 | childregs->ip = 0; | |
194 | kthread_frame_init(frame, sp, arg); | |
195 | return 0; | |
196 | } | |
197 | ||
2fff071d | 198 | /* Set a new TLS for the child thread? */ |
4804e382 | 199 | if (clone_flags & CLONE_SETTLS) |
2fff071d | 200 | ret = set_new_tls(p, tls); |
4804e382 TG |
201 | |
202 | if (!ret && unlikely(test_tsk_thread_flag(current, TIF_IO_BITMAP))) | |
203 | io_bitmap_share(p); | |
204 | ||
2fff071d TG |
205 | return ret; |
206 | } | |
207 | ||
33344368 AL |
208 | static void pkru_flush_thread(void) |
209 | { | |
210 | /* | |
211 | * If PKRU is enabled the default PKRU value has to be loaded into | |
212 | * the hardware right here (similar to context switch). | |
213 | */ | |
214 | pkru_write_default(); | |
215 | } | |
216 | ||
389d1fb1 JF |
217 | void flush_thread(void) |
218 | { | |
219 | struct task_struct *tsk = current; | |
220 | ||
24f1e32c | 221 | flush_ptrace_hw_breakpoint(tsk); |
389d1fb1 | 222 | memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array)); |
110d7f75 | 223 | |
e7ecad17 | 224 | fpu_flush_thread(); |
33344368 | 225 | pkru_flush_thread(); |
389d1fb1 JF |
226 | } |
227 | ||
389d1fb1 JF |
228 | void disable_TSC(void) |
229 | { | |
230 | preempt_disable(); | |
231 | if (!test_and_set_thread_flag(TIF_NOTSC)) | |
232 | /* | |
233 | * Must flip the CPU state synchronously with | |
234 | * TIF_NOTSC in the current running context. | |
235 | */ | |
5a920155 | 236 | cr4_set_bits(X86_CR4_TSD); |
389d1fb1 JF |
237 | preempt_enable(); |
238 | } | |
239 | ||
389d1fb1 JF |
240 | static void enable_TSC(void) |
241 | { | |
242 | preempt_disable(); | |
243 | if (test_and_clear_thread_flag(TIF_NOTSC)) | |
244 | /* | |
245 | * Must flip the CPU state synchronously with | |
246 | * TIF_NOTSC in the current running context. | |
247 | */ | |
5a920155 | 248 | cr4_clear_bits(X86_CR4_TSD); |
389d1fb1 JF |
249 | preempt_enable(); |
250 | } | |
251 | ||
252 | int get_tsc_mode(unsigned long adr) | |
253 | { | |
254 | unsigned int val; | |
255 | ||
256 | if (test_thread_flag(TIF_NOTSC)) | |
257 | val = PR_TSC_SIGSEGV; | |
258 | else | |
259 | val = PR_TSC_ENABLE; | |
260 | ||
261 | return put_user(val, (unsigned int __user *)adr); | |
262 | } | |
263 | ||
264 | int set_tsc_mode(unsigned int val) | |
265 | { | |
266 | if (val == PR_TSC_SIGSEGV) | |
267 | disable_TSC(); | |
268 | else if (val == PR_TSC_ENABLE) | |
269 | enable_TSC(); | |
270 | else | |
271 | return -EINVAL; | |
272 | ||
273 | return 0; | |
274 | } | |
275 | ||
e9ea1e7f KH |
276 | DEFINE_PER_CPU(u64, msr_misc_features_shadow); |
277 | ||
278 | static void set_cpuid_faulting(bool on) | |
279 | { | |
280 | u64 msrval; | |
281 | ||
282 | msrval = this_cpu_read(msr_misc_features_shadow); | |
283 | msrval &= ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT; | |
284 | msrval |= (on << MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT); | |
285 | this_cpu_write(msr_misc_features_shadow, msrval); | |
286 | wrmsrl(MSR_MISC_FEATURES_ENABLES, msrval); | |
287 | } | |
288 | ||
289 | static void disable_cpuid(void) | |
290 | { | |
291 | preempt_disable(); | |
292 | if (!test_and_set_thread_flag(TIF_NOCPUID)) { | |
293 | /* | |
294 | * Must flip the CPU state synchronously with | |
295 | * TIF_NOCPUID in the current running context. | |
296 | */ | |
297 | set_cpuid_faulting(true); | |
298 | } | |
299 | preempt_enable(); | |
300 | } | |
301 | ||
302 | static void enable_cpuid(void) | |
303 | { | |
304 | preempt_disable(); | |
305 | if (test_and_clear_thread_flag(TIF_NOCPUID)) { | |
306 | /* | |
307 | * Must flip the CPU state synchronously with | |
308 | * TIF_NOCPUID in the current running context. | |
309 | */ | |
310 | set_cpuid_faulting(false); | |
311 | } | |
312 | preempt_enable(); | |
313 | } | |
314 | ||
315 | static int get_cpuid_mode(void) | |
316 | { | |
317 | return !test_thread_flag(TIF_NOCPUID); | |
318 | } | |
319 | ||
320 | static int set_cpuid_mode(struct task_struct *task, unsigned long cpuid_enabled) | |
321 | { | |
67e87d43 | 322 | if (!boot_cpu_has(X86_FEATURE_CPUID_FAULT)) |
e9ea1e7f KH |
323 | return -ENODEV; |
324 | ||
325 | if (cpuid_enabled) | |
326 | enable_cpuid(); | |
327 | else | |
328 | disable_cpuid(); | |
329 | ||
330 | return 0; | |
331 | } | |
332 | ||
333 | /* | |
334 | * Called immediately after a successful exec. | |
335 | */ | |
336 | void arch_setup_new_exec(void) | |
337 | { | |
338 | /* If cpuid was previously disabled for this task, re-enable it. */ | |
339 | if (test_thread_flag(TIF_NOCPUID)) | |
340 | enable_cpuid(); | |
71368af9 WL |
341 | |
342 | /* | |
343 | * Don't inherit TIF_SSBD across exec boundary when | |
344 | * PR_SPEC_DISABLE_NOEXEC is used. | |
345 | */ | |
346 | if (test_thread_flag(TIF_SSBD) && | |
347 | task_spec_ssb_noexec(current)) { | |
348 | clear_thread_flag(TIF_SSBD); | |
349 | task_clear_spec_ssb_disable(current); | |
350 | task_clear_spec_ssb_noexec(current); | |
351 | speculation_ctrl_update(task_thread_info(current)->flags); | |
352 | } | |
e9ea1e7f KH |
353 | } |
354 | ||
111e7b15 | 355 | #ifdef CONFIG_X86_IOPL_IOPERM |
22fe5b04 TG |
356 | static inline void switch_to_bitmap(unsigned long tifp) |
357 | { | |
358 | /* | |
359 | * Invalidate I/O bitmap if the previous task used it. This prevents | |
360 | * any possible leakage of an active I/O bitmap. | |
361 | * | |
362 | * If the next task has an I/O bitmap it will handle it on exit to | |
363 | * user mode. | |
364 | */ | |
365 | if (tifp & _TIF_IO_BITMAP) | |
cadfad87 | 366 | tss_invalidate_io_bitmap(); |
22fe5b04 TG |
367 | } |
368 | ||
369 | static void tss_copy_io_bitmap(struct tss_struct *tss, struct io_bitmap *iobm) | |
060aa16f TG |
370 | { |
371 | /* | |
372 | * Copy at least the byte range of the incoming tasks bitmap which | |
373 | * covers the permitted I/O ports. | |
374 | * | |
375 | * If the previous task which used an I/O bitmap had more bits | |
376 | * permitted, then the copy needs to cover those as well so they | |
377 | * get turned off. | |
378 | */ | |
379 | memcpy(tss->io_bitmap.bitmap, iobm->bitmap, | |
380 | max(tss->io_bitmap.prev_max, iobm->max)); | |
381 | ||
382 | /* | |
383 | * Store the new max and the sequence number of this bitmap | |
384 | * and a pointer to the bitmap itself. | |
385 | */ | |
386 | tss->io_bitmap.prev_max = iobm->max; | |
387 | tss->io_bitmap.prev_sequence = iobm->sequence; | |
388 | } | |
389 | ||
22fe5b04 TG |
390 | /** |
391 | * tss_update_io_bitmap - Update I/O bitmap before exiting to usermode | |
392 | */ | |
99bcd4a6 | 393 | void native_tss_update_io_bitmap(void) |
af8b3cd3 | 394 | { |
ff16701a | 395 | struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw); |
7b0b8cfd | 396 | struct thread_struct *t = ¤t->thread; |
c8137ace | 397 | u16 *base = &tss->x86_tss.io_bitmap_base; |
ff16701a | 398 | |
7b0b8cfd | 399 | if (!test_thread_flag(TIF_IO_BITMAP)) { |
cadfad87 | 400 | native_tss_invalidate_io_bitmap(); |
7b0b8cfd BP |
401 | return; |
402 | } | |
403 | ||
404 | if (IS_ENABLED(CONFIG_X86_IOPL_IOPERM) && t->iopl_emul == 3) { | |
405 | *base = IO_BITMAP_OFFSET_VALID_ALL; | |
406 | } else { | |
407 | struct io_bitmap *iobm = t->io_bitmap; | |
408 | ||
af8b3cd3 | 409 | /* |
7b0b8cfd BP |
410 | * Only copy bitmap data when the sequence number differs. The |
411 | * update time is accounted to the incoming task. | |
af8b3cd3 | 412 | */ |
7b0b8cfd BP |
413 | if (tss->io_bitmap.prev_sequence != iobm->sequence) |
414 | tss_copy_io_bitmap(tss, iobm); | |
415 | ||
416 | /* Enable the bitmap */ | |
417 | *base = IO_BITMAP_OFFSET_VALID_MAP; | |
af8b3cd3 | 418 | } |
7b0b8cfd BP |
419 | |
420 | /* | |
421 | * Make sure that the TSS limit is covering the IO bitmap. It might have | |
422 | * been cut down by a VMEXIT to 0x67 which would cause a subsequent I/O | |
423 | * access from user space to trigger a #GP because tbe bitmap is outside | |
424 | * the TSS limit. | |
425 | */ | |
426 | refresh_tss_limit(); | |
af8b3cd3 | 427 | } |
111e7b15 TG |
428 | #else /* CONFIG_X86_IOPL_IOPERM */ |
429 | static inline void switch_to_bitmap(unsigned long tifp) { } | |
430 | #endif | |
af8b3cd3 | 431 | |
1f50ddb4 TG |
432 | #ifdef CONFIG_SMP |
433 | ||
434 | struct ssb_state { | |
435 | struct ssb_state *shared_state; | |
436 | raw_spinlock_t lock; | |
437 | unsigned int disable_state; | |
438 | unsigned long local_state; | |
439 | }; | |
440 | ||
441 | #define LSTATE_SSB 0 | |
442 | ||
443 | static DEFINE_PER_CPU(struct ssb_state, ssb_state); | |
444 | ||
445 | void speculative_store_bypass_ht_init(void) | |
885f82bf | 446 | { |
1f50ddb4 TG |
447 | struct ssb_state *st = this_cpu_ptr(&ssb_state); |
448 | unsigned int this_cpu = smp_processor_id(); | |
449 | unsigned int cpu; | |
450 | ||
451 | st->local_state = 0; | |
452 | ||
453 | /* | |
454 | * Shared state setup happens once on the first bringup | |
455 | * of the CPU. It's not destroyed on CPU hotunplug. | |
456 | */ | |
457 | if (st->shared_state) | |
458 | return; | |
459 | ||
460 | raw_spin_lock_init(&st->lock); | |
461 | ||
462 | /* | |
463 | * Go over HT siblings and check whether one of them has set up the | |
464 | * shared state pointer already. | |
465 | */ | |
466 | for_each_cpu(cpu, topology_sibling_cpumask(this_cpu)) { | |
467 | if (cpu == this_cpu) | |
468 | continue; | |
469 | ||
470 | if (!per_cpu(ssb_state, cpu).shared_state) | |
471 | continue; | |
472 | ||
473 | /* Link it to the state of the sibling: */ | |
474 | st->shared_state = per_cpu(ssb_state, cpu).shared_state; | |
475 | return; | |
476 | } | |
477 | ||
478 | /* | |
479 | * First HT sibling to come up on the core. Link shared state of | |
480 | * the first HT sibling to itself. The siblings on the same core | |
481 | * which come up later will see the shared state pointer and link | |
d9f6e12f | 482 | * themselves to the state of this CPU. |
1f50ddb4 TG |
483 | */ |
484 | st->shared_state = st; | |
485 | } | |
885f82bf | 486 | |
1f50ddb4 TG |
487 | /* |
488 | * Logic is: First HT sibling enables SSBD for both siblings in the core | |
489 | * and last sibling to disable it, disables it for the whole core. This how | |
490 | * MSR_SPEC_CTRL works in "hardware": | |
491 | * | |
492 | * CORE_SPEC_CTRL = THREAD0_SPEC_CTRL | THREAD1_SPEC_CTRL | |
493 | */ | |
494 | static __always_inline void amd_set_core_ssb_state(unsigned long tifn) | |
495 | { | |
496 | struct ssb_state *st = this_cpu_ptr(&ssb_state); | |
497 | u64 msr = x86_amd_ls_cfg_base; | |
498 | ||
499 | if (!static_cpu_has(X86_FEATURE_ZEN)) { | |
500 | msr |= ssbd_tif_to_amd_ls_cfg(tifn); | |
885f82bf | 501 | wrmsrl(MSR_AMD64_LS_CFG, msr); |
1f50ddb4 TG |
502 | return; |
503 | } | |
504 | ||
505 | if (tifn & _TIF_SSBD) { | |
506 | /* | |
507 | * Since this can race with prctl(), block reentry on the | |
508 | * same CPU. | |
509 | */ | |
510 | if (__test_and_set_bit(LSTATE_SSB, &st->local_state)) | |
511 | return; | |
512 | ||
513 | msr |= x86_amd_ls_cfg_ssbd_mask; | |
514 | ||
515 | raw_spin_lock(&st->shared_state->lock); | |
516 | /* First sibling enables SSBD: */ | |
517 | if (!st->shared_state->disable_state) | |
518 | wrmsrl(MSR_AMD64_LS_CFG, msr); | |
519 | st->shared_state->disable_state++; | |
520 | raw_spin_unlock(&st->shared_state->lock); | |
885f82bf | 521 | } else { |
1f50ddb4 TG |
522 | if (!__test_and_clear_bit(LSTATE_SSB, &st->local_state)) |
523 | return; | |
524 | ||
525 | raw_spin_lock(&st->shared_state->lock); | |
526 | st->shared_state->disable_state--; | |
527 | if (!st->shared_state->disable_state) | |
528 | wrmsrl(MSR_AMD64_LS_CFG, msr); | |
529 | raw_spin_unlock(&st->shared_state->lock); | |
885f82bf TG |
530 | } |
531 | } | |
1f50ddb4 TG |
532 | #else |
533 | static __always_inline void amd_set_core_ssb_state(unsigned long tifn) | |
534 | { | |
535 | u64 msr = x86_amd_ls_cfg_base | ssbd_tif_to_amd_ls_cfg(tifn); | |
536 | ||
537 | wrmsrl(MSR_AMD64_LS_CFG, msr); | |
538 | } | |
539 | #endif | |
540 | ||
11fb0683 TL |
541 | static __always_inline void amd_set_ssb_virt_state(unsigned long tifn) |
542 | { | |
543 | /* | |
544 | * SSBD has the same definition in SPEC_CTRL and VIRT_SPEC_CTRL, | |
545 | * so ssbd_tif_to_spec_ctrl() just works. | |
546 | */ | |
547 | wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, ssbd_tif_to_spec_ctrl(tifn)); | |
548 | } | |
549 | ||
01daf568 TC |
550 | /* |
551 | * Update the MSRs managing speculation control, during context switch. | |
552 | * | |
553 | * tifp: Previous task's thread flags | |
554 | * tifn: Next task's thread flags | |
555 | */ | |
556 | static __always_inline void __speculation_ctrl_update(unsigned long tifp, | |
557 | unsigned long tifn) | |
1f50ddb4 | 558 | { |
5bfbe3ad | 559 | unsigned long tif_diff = tifp ^ tifn; |
01daf568 TC |
560 | u64 msr = x86_spec_ctrl_base; |
561 | bool updmsr = false; | |
562 | ||
2f5fb193 TG |
563 | lockdep_assert_irqs_disabled(); |
564 | ||
dbbe2ad0 AS |
565 | /* Handle change of TIF_SSBD depending on the mitigation method. */ |
566 | if (static_cpu_has(X86_FEATURE_VIRT_SSBD)) { | |
567 | if (tif_diff & _TIF_SSBD) | |
01daf568 | 568 | amd_set_ssb_virt_state(tifn); |
dbbe2ad0 AS |
569 | } else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD)) { |
570 | if (tif_diff & _TIF_SSBD) | |
01daf568 | 571 | amd_set_core_ssb_state(tifn); |
dbbe2ad0 AS |
572 | } else if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) || |
573 | static_cpu_has(X86_FEATURE_AMD_SSBD)) { | |
574 | updmsr |= !!(tif_diff & _TIF_SSBD); | |
575 | msr |= ssbd_tif_to_spec_ctrl(tifn); | |
01daf568 | 576 | } |
1f50ddb4 | 577 | |
dbbe2ad0 | 578 | /* Only evaluate TIF_SPEC_IB if conditional STIBP is enabled. */ |
5bfbe3ad TC |
579 | if (IS_ENABLED(CONFIG_SMP) && |
580 | static_branch_unlikely(&switch_to_cond_stibp)) { | |
581 | updmsr |= !!(tif_diff & _TIF_SPEC_IB); | |
582 | msr |= stibp_tif_to_spec_ctrl(tifn); | |
583 | } | |
584 | ||
01daf568 TC |
585 | if (updmsr) |
586 | wrmsrl(MSR_IA32_SPEC_CTRL, msr); | |
1f50ddb4 TG |
587 | } |
588 | ||
6d991ba5 | 589 | static unsigned long speculation_ctrl_update_tif(struct task_struct *tsk) |
1f50ddb4 | 590 | { |
6d991ba5 TG |
591 | if (test_and_clear_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE)) { |
592 | if (task_spec_ssb_disable(tsk)) | |
593 | set_tsk_thread_flag(tsk, TIF_SSBD); | |
594 | else | |
595 | clear_tsk_thread_flag(tsk, TIF_SSBD); | |
9137bb27 TG |
596 | |
597 | if (task_spec_ib_disable(tsk)) | |
598 | set_tsk_thread_flag(tsk, TIF_SPEC_IB); | |
599 | else | |
600 | clear_tsk_thread_flag(tsk, TIF_SPEC_IB); | |
6d991ba5 TG |
601 | } |
602 | /* Return the updated threadinfo flags*/ | |
603 | return task_thread_info(tsk)->flags; | |
1f50ddb4 | 604 | } |
885f82bf | 605 | |
26c4d75b | 606 | void speculation_ctrl_update(unsigned long tif) |
885f82bf | 607 | { |
2f5fb193 TG |
608 | unsigned long flags; |
609 | ||
01daf568 | 610 | /* Forced update. Make sure all relevant TIF flags are different */ |
2f5fb193 | 611 | local_irq_save(flags); |
01daf568 | 612 | __speculation_ctrl_update(~tif, tif); |
2f5fb193 | 613 | local_irq_restore(flags); |
885f82bf TG |
614 | } |
615 | ||
6d991ba5 TG |
616 | /* Called from seccomp/prctl update */ |
617 | void speculation_ctrl_update_current(void) | |
618 | { | |
619 | preempt_disable(); | |
620 | speculation_ctrl_update(speculation_ctrl_update_tif(current)); | |
621 | preempt_enable(); | |
622 | } | |
623 | ||
d8f0b353 TG |
624 | static inline void cr4_toggle_bits_irqsoff(unsigned long mask) |
625 | { | |
626 | unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4); | |
627 | ||
628 | newval = cr4 ^ mask; | |
629 | if (newval != cr4) { | |
630 | this_cpu_write(cpu_tlbstate.cr4, newval); | |
631 | __write_cr4(newval); | |
632 | } | |
633 | } | |
634 | ||
ff16701a | 635 | void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p) |
389d1fb1 | 636 | { |
af8b3cd3 | 637 | unsigned long tifp, tifn; |
389d1fb1 | 638 | |
af8b3cd3 KH |
639 | tifn = READ_ONCE(task_thread_info(next_p)->flags); |
640 | tifp = READ_ONCE(task_thread_info(prev_p)->flags); | |
22fe5b04 TG |
641 | |
642 | switch_to_bitmap(tifp); | |
af8b3cd3 KH |
643 | |
644 | propagate_user_return_notify(prev_p, next_p); | |
645 | ||
b9894a2f KH |
646 | if ((tifp & _TIF_BLOCKSTEP || tifn & _TIF_BLOCKSTEP) && |
647 | arch_has_block_step()) { | |
648 | unsigned long debugctl, msk; | |
ea8e61b7 | 649 | |
b9894a2f | 650 | rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); |
ea8e61b7 | 651 | debugctl &= ~DEBUGCTLMSR_BTF; |
b9894a2f KH |
652 | msk = tifn & _TIF_BLOCKSTEP; |
653 | debugctl |= (msk >> TIF_BLOCKSTEP) << DEBUGCTLMSR_BTF_SHIFT; | |
654 | wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); | |
ea8e61b7 | 655 | } |
389d1fb1 | 656 | |
5a920155 | 657 | if ((tifp ^ tifn) & _TIF_NOTSC) |
9d0b6232 | 658 | cr4_toggle_bits_irqsoff(X86_CR4_TSD); |
e9ea1e7f KH |
659 | |
660 | if ((tifp ^ tifn) & _TIF_NOCPUID) | |
661 | set_cpuid_faulting(!!(tifn & _TIF_NOCPUID)); | |
885f82bf | 662 | |
6d991ba5 TG |
663 | if (likely(!((tifp | tifn) & _TIF_SPEC_FORCE_UPDATE))) { |
664 | __speculation_ctrl_update(tifp, tifn); | |
665 | } else { | |
666 | speculation_ctrl_update_tif(prev_p); | |
667 | tifn = speculation_ctrl_update_tif(next_p); | |
668 | ||
669 | /* Enforce MSR update to ensure consistent state */ | |
670 | __speculation_ctrl_update(~tifn, tifn); | |
671 | } | |
6650cdd9 PZI |
672 | |
673 | if ((tifp ^ tifn) & _TIF_SLD) | |
674 | switch_to_sld(tifn); | |
389d1fb1 JF |
675 | } |
676 | ||
00dba564 TG |
677 | /* |
678 | * Idle related variables and functions | |
679 | */ | |
d1896049 | 680 | unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE; |
00dba564 TG |
681 | EXPORT_SYMBOL(boot_option_idle_override); |
682 | ||
a476bda3 | 683 | static void (*x86_idle)(void); |
00dba564 | 684 | |
90e24014 RW |
685 | #ifndef CONFIG_SMP |
686 | static inline void play_dead(void) | |
687 | { | |
688 | BUG(); | |
689 | } | |
690 | #endif | |
691 | ||
7d1a9417 TG |
692 | void arch_cpu_idle_enter(void) |
693 | { | |
6a369583 | 694 | tsc_verify_tsc_adjust(false); |
7d1a9417 | 695 | local_touch_nmi(); |
7d1a9417 | 696 | } |
90e24014 | 697 | |
7d1a9417 TG |
698 | void arch_cpu_idle_dead(void) |
699 | { | |
700 | play_dead(); | |
701 | } | |
90e24014 | 702 | |
7d1a9417 TG |
703 | /* |
704 | * Called from the generic idle code. | |
705 | */ | |
706 | void arch_cpu_idle(void) | |
707 | { | |
16f8b05a | 708 | x86_idle(); |
90e24014 RW |
709 | } |
710 | ||
00dba564 | 711 | /* |
7d1a9417 | 712 | * We use this if we don't have any better idle routine.. |
00dba564 | 713 | */ |
6727ad9e | 714 | void __cpuidle default_idle(void) |
00dba564 | 715 | { |
58c644ba | 716 | raw_safe_halt(); |
00dba564 | 717 | } |
fa86ee90 | 718 | #if defined(CONFIG_APM_MODULE) || defined(CONFIG_HALTPOLL_CPUIDLE_MODULE) |
00dba564 TG |
719 | EXPORT_SYMBOL(default_idle); |
720 | #endif | |
721 | ||
6a377ddc LB |
722 | #ifdef CONFIG_XEN |
723 | bool xen_set_default_idle(void) | |
e5fd47bf | 724 | { |
a476bda3 | 725 | bool ret = !!x86_idle; |
e5fd47bf | 726 | |
a476bda3 | 727 | x86_idle = default_idle; |
e5fd47bf KRW |
728 | |
729 | return ret; | |
730 | } | |
6a377ddc | 731 | #endif |
bba4ed01 | 732 | |
d3ec5cae IV |
733 | void stop_this_cpu(void *dummy) |
734 | { | |
735 | local_irq_disable(); | |
736 | /* | |
737 | * Remove this CPU: | |
738 | */ | |
4f062896 | 739 | set_cpu_online(smp_processor_id(), false); |
d3ec5cae | 740 | disable_local_APIC(); |
8838eb6c | 741 | mcheck_cpu_clear(this_cpu_ptr(&cpu_info)); |
d3ec5cae | 742 | |
f23d74f6 TL |
743 | /* |
744 | * Use wbinvd on processors that support SME. This provides support | |
745 | * for performing a successful kexec when going from SME inactive | |
746 | * to SME active (or vice-versa). The cache must be cleared so that | |
747 | * if there are entries with the same physical address, both with and | |
748 | * without the encryption bit, they don't race each other when flushed | |
749 | * and potentially end up with the wrong entry being committed to | |
750 | * memory. | |
751 | */ | |
752 | if (boot_cpu_has(X86_FEATURE_SME)) | |
753 | native_wbinvd(); | |
bba4ed01 TL |
754 | for (;;) { |
755 | /* | |
f23d74f6 TL |
756 | * Use native_halt() so that memory contents don't change |
757 | * (stack usage and variables) after possibly issuing the | |
758 | * native_wbinvd() above. | |
bba4ed01 | 759 | */ |
f23d74f6 | 760 | native_halt(); |
bba4ed01 | 761 | } |
7f424a8b PZ |
762 | } |
763 | ||
aa276e1c | 764 | /* |
07c94a38 BP |
765 | * AMD Erratum 400 aware idle routine. We handle it the same way as C3 power |
766 | * states (local apic timer and TSC stop). | |
58c644ba PZ |
767 | * |
768 | * XXX this function is completely buggered vs RCU and tracing. | |
aa276e1c | 769 | */ |
02c68a02 | 770 | static void amd_e400_idle(void) |
aa276e1c | 771 | { |
07c94a38 BP |
772 | /* |
773 | * We cannot use static_cpu_has_bug() here because X86_BUG_AMD_APIC_C1E | |
774 | * gets set after static_cpu_has() places have been converted via | |
775 | * alternatives. | |
776 | */ | |
777 | if (!boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) { | |
778 | default_idle(); | |
779 | return; | |
aa276e1c TG |
780 | } |
781 | ||
07c94a38 | 782 | tick_broadcast_enter(); |
aa276e1c | 783 | |
07c94a38 | 784 | default_idle(); |
0beefa20 | 785 | |
07c94a38 BP |
786 | /* |
787 | * The switch back from broadcast mode needs to be called with | |
788 | * interrupts disabled. | |
789 | */ | |
58c644ba | 790 | raw_local_irq_disable(); |
07c94a38 | 791 | tick_broadcast_exit(); |
58c644ba | 792 | raw_local_irq_enable(); |
aa276e1c TG |
793 | } |
794 | ||
b253149b LB |
795 | /* |
796 | * Intel Core2 and older machines prefer MWAIT over HALT for C1. | |
797 | * We can't rely on cpuidle installing MWAIT, because it will not load | |
798 | * on systems that support only C1 -- so the boot default must be MWAIT. | |
799 | * | |
800 | * Some AMD machines are the opposite, they depend on using HALT. | |
801 | * | |
802 | * So for default C1, which is used during boot until cpuidle loads, | |
803 | * use MWAIT-C1 on Intel HW that has it, else use HALT. | |
804 | */ | |
805 | static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c) | |
806 | { | |
807 | if (c->x86_vendor != X86_VENDOR_INTEL) | |
808 | return 0; | |
809 | ||
67e87d43 | 810 | if (!cpu_has(c, X86_FEATURE_MWAIT) || boot_cpu_has_bug(X86_BUG_MONITOR)) |
b253149b LB |
811 | return 0; |
812 | ||
813 | return 1; | |
814 | } | |
815 | ||
816 | /* | |
0fb0328d HR |
817 | * MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT |
818 | * with interrupts enabled and no flags, which is backwards compatible with the | |
819 | * original MWAIT implementation. | |
b253149b | 820 | */ |
6727ad9e | 821 | static __cpuidle void mwait_idle(void) |
b253149b | 822 | { |
f8e617f4 MG |
823 | if (!current_set_polling_and_test()) { |
824 | if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) { | |
ca59809f | 825 | mb(); /* quirk */ |
b253149b | 826 | clflush((void *)¤t_thread_info()->flags); |
ca59809f | 827 | mb(); /* quirk */ |
f8e617f4 | 828 | } |
b253149b LB |
829 | |
830 | __monitor((void *)¤t_thread_info()->flags, 0, 0); | |
b253149b LB |
831 | if (!need_resched()) |
832 | __sti_mwait(0, 0); | |
833 | else | |
58c644ba | 834 | raw_local_irq_enable(); |
f8e617f4 | 835 | } else { |
58c644ba | 836 | raw_local_irq_enable(); |
f8e617f4 MG |
837 | } |
838 | __current_clr_polling(); | |
b253149b LB |
839 | } |
840 | ||
148f9bb8 | 841 | void select_idle_routine(const struct cpuinfo_x86 *c) |
7f424a8b | 842 | { |
3e5095d1 | 843 | #ifdef CONFIG_SMP |
7d1a9417 | 844 | if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1) |
c767a54b | 845 | pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n"); |
7f424a8b | 846 | #endif |
7d1a9417 | 847 | if (x86_idle || boot_option_idle_override == IDLE_POLL) |
6ddd2a27 TG |
848 | return; |
849 | ||
3344ed30 | 850 | if (boot_cpu_has_bug(X86_BUG_AMD_E400)) { |
c767a54b | 851 | pr_info("using AMD E400 aware idle routine\n"); |
a476bda3 | 852 | x86_idle = amd_e400_idle; |
b253149b LB |
853 | } else if (prefer_mwait_c1_over_halt(c)) { |
854 | pr_info("using mwait in idle threads\n"); | |
855 | x86_idle = mwait_idle; | |
6ddd2a27 | 856 | } else |
a476bda3 | 857 | x86_idle = default_idle; |
7f424a8b PZ |
858 | } |
859 | ||
07c94a38 | 860 | void amd_e400_c1e_apic_setup(void) |
30e1e6d1 | 861 | { |
07c94a38 BP |
862 | if (boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) { |
863 | pr_info("Switch to broadcast mode on CPU%d\n", smp_processor_id()); | |
864 | local_irq_disable(); | |
865 | tick_broadcast_force(); | |
866 | local_irq_enable(); | |
867 | } | |
30e1e6d1 RR |
868 | } |
869 | ||
e7ff3a47 TG |
870 | void __init arch_post_acpi_subsys_init(void) |
871 | { | |
872 | u32 lo, hi; | |
873 | ||
874 | if (!boot_cpu_has_bug(X86_BUG_AMD_E400)) | |
875 | return; | |
876 | ||
877 | /* | |
878 | * AMD E400 detection needs to happen after ACPI has been enabled. If | |
879 | * the machine is affected K8_INTP_C1E_ACTIVE_MASK bits are set in | |
880 | * MSR_K8_INT_PENDING_MSG. | |
881 | */ | |
882 | rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi); | |
883 | if (!(lo & K8_INTP_C1E_ACTIVE_MASK)) | |
884 | return; | |
885 | ||
886 | boot_cpu_set_bug(X86_BUG_AMD_APIC_C1E); | |
887 | ||
888 | if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) | |
889 | mark_tsc_unstable("TSC halt in AMD C1E"); | |
890 | pr_info("System has AMD C1E enabled\n"); | |
891 | } | |
892 | ||
7f424a8b PZ |
893 | static int __init idle_setup(char *str) |
894 | { | |
ab6bc3e3 CG |
895 | if (!str) |
896 | return -EINVAL; | |
897 | ||
7f424a8b | 898 | if (!strcmp(str, "poll")) { |
c767a54b | 899 | pr_info("using polling idle threads\n"); |
d1896049 | 900 | boot_option_idle_override = IDLE_POLL; |
7d1a9417 | 901 | cpu_idle_poll_ctrl(true); |
d1896049 | 902 | } else if (!strcmp(str, "halt")) { |
c1e3b377 ZY |
903 | /* |
904 | * When the boot option of idle=halt is added, halt is | |
905 | * forced to be used for CPU idle. In such case CPU C2/C3 | |
906 | * won't be used again. | |
907 | * To continue to load the CPU idle driver, don't touch | |
908 | * the boot_option_idle_override. | |
909 | */ | |
a476bda3 | 910 | x86_idle = default_idle; |
d1896049 | 911 | boot_option_idle_override = IDLE_HALT; |
da5e09a1 ZY |
912 | } else if (!strcmp(str, "nomwait")) { |
913 | /* | |
914 | * If the boot option of "idle=nomwait" is added, | |
915 | * it means that mwait will be disabled for CPU C2/C3 | |
916 | * states. In such case it won't touch the variable | |
917 | * of boot_option_idle_override. | |
918 | */ | |
d1896049 | 919 | boot_option_idle_override = IDLE_NOMWAIT; |
c1e3b377 | 920 | } else |
7f424a8b PZ |
921 | return -1; |
922 | ||
7f424a8b PZ |
923 | return 0; |
924 | } | |
925 | early_param("idle", idle_setup); | |
926 | ||
9d62dcdf AW |
927 | unsigned long arch_align_stack(unsigned long sp) |
928 | { | |
929 | if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) | |
930 | sp -= get_random_int() % 8192; | |
931 | return sp & ~0xf; | |
932 | } | |
933 | ||
934 | unsigned long arch_randomize_brk(struct mm_struct *mm) | |
935 | { | |
9c6f0902 | 936 | return randomize_page(mm->brk, 0x02000000); |
9d62dcdf AW |
937 | } |
938 | ||
7ba78053 TG |
939 | /* |
940 | * Called from fs/proc with a reference on @p to find the function | |
941 | * which called into schedule(). This needs to be done carefully | |
942 | * because the task might wake up and we might look at a stack | |
943 | * changing under us. | |
944 | */ | |
945 | unsigned long get_wchan(struct task_struct *p) | |
946 | { | |
bc9bbb81 | 947 | unsigned long entry = 0; |
7ba78053 | 948 | |
b03fbd4f | 949 | if (p == current || task_is_running(p)) |
7ba78053 TG |
950 | return 0; |
951 | ||
bc9bbb81 QZ |
952 | stack_trace_save_tsk(p, &entry, 1, 0); |
953 | return entry; | |
7ba78053 | 954 | } |
b0b9b014 KH |
955 | |
956 | long do_arch_prctl_common(struct task_struct *task, int option, | |
957 | unsigned long cpuid_enabled) | |
958 | { | |
e9ea1e7f KH |
959 | switch (option) { |
960 | case ARCH_GET_CPUID: | |
961 | return get_cpuid_mode(); | |
962 | case ARCH_SET_CPUID: | |
963 | return set_cpuid_mode(task, cpuid_enabled); | |
964 | } | |
965 | ||
b0b9b014 KH |
966 | return -EINVAL; |
967 | } |