Commit | Line | Data |
---|---|---|
c767a54b JP |
1 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
2 | ||
61c4628b SS |
3 | #include <linux/errno.h> |
4 | #include <linux/kernel.h> | |
5 | #include <linux/mm.h> | |
6 | #include <linux/smp.h> | |
389d1fb1 | 7 | #include <linux/prctl.h> |
61c4628b SS |
8 | #include <linux/slab.h> |
9 | #include <linux/sched.h> | |
7f424a8b PZ |
10 | #include <linux/module.h> |
11 | #include <linux/pm.h> | |
aa276e1c | 12 | #include <linux/clockchips.h> |
9d62dcdf | 13 | #include <linux/random.h> |
7c68af6e | 14 | #include <linux/user-return-notifier.h> |
814e2c84 AI |
15 | #include <linux/dmi.h> |
16 | #include <linux/utsname.h> | |
90e24014 RW |
17 | #include <linux/stackprotector.h> |
18 | #include <linux/tick.h> | |
19 | #include <linux/cpuidle.h> | |
61613521 | 20 | #include <trace/events/power.h> |
24f1e32c | 21 | #include <linux/hw_breakpoint.h> |
93789b32 | 22 | #include <asm/cpu.h> |
d3ec5cae | 23 | #include <asm/apic.h> |
2c1b284e | 24 | #include <asm/syscalls.h> |
389d1fb1 JF |
25 | #include <asm/idle.h> |
26 | #include <asm/uaccess.h> | |
27 | #include <asm/i387.h> | |
1361b83a | 28 | #include <asm/fpu-internal.h> |
66cb5917 | 29 | #include <asm/debugreg.h> |
90e24014 RW |
30 | #include <asm/nmi.h> |
31 | ||
45046892 TG |
32 | /* |
33 | * per-CPU TSS segments. Threads are completely 'soft' on Linux, | |
34 | * no more per-task TSS's. The TSS size is kept cacheline-aligned | |
35 | * so they are allowed to end up in the .data..cacheline_aligned | |
36 | * section. Since TSS's are completely CPU-local, we want them | |
37 | * on exact cacheline boundaries, to eliminate cacheline ping-pong. | |
38 | */ | |
39 | DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss) = INIT_TSS; | |
40 | ||
90e24014 RW |
41 | #ifdef CONFIG_X86_64 |
42 | static DEFINE_PER_CPU(unsigned char, is_idle); | |
43 | static ATOMIC_NOTIFIER_HEAD(idle_notifier); | |
44 | ||
45 | void idle_notifier_register(struct notifier_block *n) | |
46 | { | |
47 | atomic_notifier_chain_register(&idle_notifier, n); | |
48 | } | |
49 | EXPORT_SYMBOL_GPL(idle_notifier_register); | |
50 | ||
51 | void idle_notifier_unregister(struct notifier_block *n) | |
52 | { | |
53 | atomic_notifier_chain_unregister(&idle_notifier, n); | |
54 | } | |
55 | EXPORT_SYMBOL_GPL(idle_notifier_unregister); | |
56 | #endif | |
c1e3b377 | 57 | |
aa283f49 | 58 | struct kmem_cache *task_xstate_cachep; |
5ee481da | 59 | EXPORT_SYMBOL_GPL(task_xstate_cachep); |
61c4628b | 60 | |
55ccf3fe SS |
61 | /* |
62 | * this gets called so that we can store lazy state into memory and copy the | |
63 | * current task into the new thread. | |
64 | */ | |
61c4628b SS |
65 | int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) |
66 | { | |
86603283 AK |
67 | int ret; |
68 | ||
61c4628b | 69 | *dst = *src; |
86603283 AK |
70 | if (fpu_allocated(&src->thread.fpu)) { |
71 | memset(&dst->thread.fpu, 0, sizeof(dst->thread.fpu)); | |
72 | ret = fpu_alloc(&dst->thread.fpu); | |
73 | if (ret) | |
74 | return ret; | |
304bceda | 75 | fpu_copy(dst, src); |
aa283f49 | 76 | } |
61c4628b SS |
77 | return 0; |
78 | } | |
79 | ||
aa283f49 | 80 | void free_thread_xstate(struct task_struct *tsk) |
61c4628b | 81 | { |
86603283 | 82 | fpu_free(&tsk->thread.fpu); |
aa283f49 SS |
83 | } |
84 | ||
38e7c572 | 85 | void arch_release_task_struct(struct task_struct *tsk) |
aa283f49 | 86 | { |
38e7c572 | 87 | free_thread_xstate(tsk); |
61c4628b SS |
88 | } |
89 | ||
90 | void arch_task_cache_init(void) | |
91 | { | |
92 | task_xstate_cachep = | |
93 | kmem_cache_create("task_xstate", xstate_size, | |
94 | __alignof__(union thread_xstate), | |
2dff4405 | 95 | SLAB_PANIC | SLAB_NOTRACK, NULL); |
61c4628b | 96 | } |
7f424a8b | 97 | |
389d1fb1 JF |
98 | /* |
99 | * Free current thread data structures etc.. | |
100 | */ | |
101 | void exit_thread(void) | |
102 | { | |
103 | struct task_struct *me = current; | |
104 | struct thread_struct *t = &me->thread; | |
250981e6 | 105 | unsigned long *bp = t->io_bitmap_ptr; |
389d1fb1 | 106 | |
250981e6 | 107 | if (bp) { |
389d1fb1 JF |
108 | struct tss_struct *tss = &per_cpu(init_tss, get_cpu()); |
109 | ||
389d1fb1 JF |
110 | t->io_bitmap_ptr = NULL; |
111 | clear_thread_flag(TIF_IO_BITMAP); | |
112 | /* | |
113 | * Careful, clear this in the TSS too: | |
114 | */ | |
115 | memset(tss->io_bitmap, 0xff, t->io_bitmap_max); | |
116 | t->io_bitmap_max = 0; | |
117 | put_cpu(); | |
250981e6 | 118 | kfree(bp); |
389d1fb1 | 119 | } |
1dcc8d7b SS |
120 | |
121 | drop_fpu(me); | |
389d1fb1 JF |
122 | } |
123 | ||
814e2c84 AI |
124 | void show_regs_common(void) |
125 | { | |
84e383b3 | 126 | const char *vendor, *product, *board; |
814e2c84 | 127 | |
84e383b3 NC |
128 | vendor = dmi_get_system_info(DMI_SYS_VENDOR); |
129 | if (!vendor) | |
130 | vendor = ""; | |
a1884b8e AI |
131 | product = dmi_get_system_info(DMI_PRODUCT_NAME); |
132 | if (!product) | |
133 | product = ""; | |
814e2c84 | 134 | |
84e383b3 NC |
135 | /* Board Name is optional */ |
136 | board = dmi_get_system_info(DMI_BOARD_NAME); | |
137 | ||
c767a54b JP |
138 | printk(KERN_DEFAULT "Pid: %d, comm: %.20s %s %s %.*s %s %s%s%s\n", |
139 | current->pid, current->comm, print_tainted(), | |
140 | init_utsname()->release, | |
141 | (int)strcspn(init_utsname()->version, " "), | |
142 | init_utsname()->version, | |
143 | vendor, product, | |
144 | board ? "/" : "", | |
145 | board ? board : ""); | |
814e2c84 AI |
146 | } |
147 | ||
389d1fb1 JF |
148 | void flush_thread(void) |
149 | { | |
150 | struct task_struct *tsk = current; | |
151 | ||
24f1e32c | 152 | flush_ptrace_hw_breakpoint(tsk); |
389d1fb1 | 153 | memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array)); |
304bceda SS |
154 | drop_init_fpu(tsk); |
155 | /* | |
156 | * Free the FPU state for non xsave platforms. They get reallocated | |
157 | * lazily at the first use. | |
158 | */ | |
5d2bd700 | 159 | if (!use_eager_fpu()) |
304bceda | 160 | free_thread_xstate(tsk); |
389d1fb1 JF |
161 | } |
162 | ||
163 | static void hard_disable_TSC(void) | |
164 | { | |
165 | write_cr4(read_cr4() | X86_CR4_TSD); | |
166 | } | |
167 | ||
168 | void disable_TSC(void) | |
169 | { | |
170 | preempt_disable(); | |
171 | if (!test_and_set_thread_flag(TIF_NOTSC)) | |
172 | /* | |
173 | * Must flip the CPU state synchronously with | |
174 | * TIF_NOTSC in the current running context. | |
175 | */ | |
176 | hard_disable_TSC(); | |
177 | preempt_enable(); | |
178 | } | |
179 | ||
180 | static void hard_enable_TSC(void) | |
181 | { | |
182 | write_cr4(read_cr4() & ~X86_CR4_TSD); | |
183 | } | |
184 | ||
185 | static void enable_TSC(void) | |
186 | { | |
187 | preempt_disable(); | |
188 | if (test_and_clear_thread_flag(TIF_NOTSC)) | |
189 | /* | |
190 | * Must flip the CPU state synchronously with | |
191 | * TIF_NOTSC in the current running context. | |
192 | */ | |
193 | hard_enable_TSC(); | |
194 | preempt_enable(); | |
195 | } | |
196 | ||
197 | int get_tsc_mode(unsigned long adr) | |
198 | { | |
199 | unsigned int val; | |
200 | ||
201 | if (test_thread_flag(TIF_NOTSC)) | |
202 | val = PR_TSC_SIGSEGV; | |
203 | else | |
204 | val = PR_TSC_ENABLE; | |
205 | ||
206 | return put_user(val, (unsigned int __user *)adr); | |
207 | } | |
208 | ||
209 | int set_tsc_mode(unsigned int val) | |
210 | { | |
211 | if (val == PR_TSC_SIGSEGV) | |
212 | disable_TSC(); | |
213 | else if (val == PR_TSC_ENABLE) | |
214 | enable_TSC(); | |
215 | else | |
216 | return -EINVAL; | |
217 | ||
218 | return 0; | |
219 | } | |
220 | ||
221 | void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p, | |
222 | struct tss_struct *tss) | |
223 | { | |
224 | struct thread_struct *prev, *next; | |
225 | ||
226 | prev = &prev_p->thread; | |
227 | next = &next_p->thread; | |
228 | ||
ea8e61b7 PZ |
229 | if (test_tsk_thread_flag(prev_p, TIF_BLOCKSTEP) ^ |
230 | test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) { | |
231 | unsigned long debugctl = get_debugctlmsr(); | |
232 | ||
233 | debugctl &= ~DEBUGCTLMSR_BTF; | |
234 | if (test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) | |
235 | debugctl |= DEBUGCTLMSR_BTF; | |
236 | ||
237 | update_debugctlmsr(debugctl); | |
238 | } | |
389d1fb1 | 239 | |
389d1fb1 JF |
240 | if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^ |
241 | test_tsk_thread_flag(next_p, TIF_NOTSC)) { | |
242 | /* prev and next are different */ | |
243 | if (test_tsk_thread_flag(next_p, TIF_NOTSC)) | |
244 | hard_disable_TSC(); | |
245 | else | |
246 | hard_enable_TSC(); | |
247 | } | |
248 | ||
249 | if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) { | |
250 | /* | |
251 | * Copy the relevant range of the IO bitmap. | |
252 | * Normally this is 128 bytes or less: | |
253 | */ | |
254 | memcpy(tss->io_bitmap, next->io_bitmap_ptr, | |
255 | max(prev->io_bitmap_max, next->io_bitmap_max)); | |
256 | } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) { | |
257 | /* | |
258 | * Clear any possible leftover bits: | |
259 | */ | |
260 | memset(tss->io_bitmap, 0xff, prev->io_bitmap_max); | |
261 | } | |
7c68af6e | 262 | propagate_user_return_notify(prev_p, next_p); |
389d1fb1 JF |
263 | } |
264 | ||
00dba564 TG |
265 | /* |
266 | * Idle related variables and functions | |
267 | */ | |
d1896049 | 268 | unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE; |
00dba564 TG |
269 | EXPORT_SYMBOL(boot_option_idle_override); |
270 | ||
a476bda3 | 271 | static void (*x86_idle)(void); |
00dba564 | 272 | |
90e24014 RW |
273 | #ifndef CONFIG_SMP |
274 | static inline void play_dead(void) | |
275 | { | |
276 | BUG(); | |
277 | } | |
278 | #endif | |
279 | ||
280 | #ifdef CONFIG_X86_64 | |
281 | void enter_idle(void) | |
282 | { | |
c6ae41e7 | 283 | this_cpu_write(is_idle, 1); |
90e24014 RW |
284 | atomic_notifier_call_chain(&idle_notifier, IDLE_START, NULL); |
285 | } | |
286 | ||
287 | static void __exit_idle(void) | |
288 | { | |
289 | if (x86_test_and_clear_bit_percpu(0, is_idle) == 0) | |
290 | return; | |
291 | atomic_notifier_call_chain(&idle_notifier, IDLE_END, NULL); | |
292 | } | |
293 | ||
294 | /* Called from interrupts to signify idle end */ | |
295 | void exit_idle(void) | |
296 | { | |
297 | /* idle loop has pid 0 */ | |
298 | if (current->pid) | |
299 | return; | |
300 | __exit_idle(); | |
301 | } | |
302 | #endif | |
303 | ||
304 | /* | |
305 | * The idle thread. There's no useful work to be | |
306 | * done, so just try to conserve power and have a | |
307 | * low exit latency (ie sit in a loop waiting for | |
308 | * somebody to say that they'd like to reschedule) | |
309 | */ | |
310 | void cpu_idle(void) | |
311 | { | |
312 | /* | |
313 | * If we're the non-boot CPU, nothing set the stack canary up | |
314 | * for us. CPU0 already has it initialized but no harm in | |
315 | * doing it again. This is a good place for updating it, as | |
316 | * we wont ever return from this function (so the invalid | |
317 | * canaries already on the stack wont ever trigger). | |
318 | */ | |
319 | boot_init_stack_canary(); | |
320 | current_thread_info()->status |= TS_POLLING; | |
321 | ||
322 | while (1) { | |
323 | tick_nohz_idle_enter(); | |
324 | ||
325 | while (!need_resched()) { | |
326 | rmb(); | |
327 | ||
328 | if (cpu_is_offline(smp_processor_id())) | |
329 | play_dead(); | |
330 | ||
331 | /* | |
332 | * Idle routines should keep interrupts disabled | |
333 | * from here on, until they go to idle. | |
334 | * Otherwise, idle callbacks can misfire. | |
335 | */ | |
336 | local_touch_nmi(); | |
337 | local_irq_disable(); | |
338 | ||
339 | enter_idle(); | |
340 | ||
341 | /* Don't trace irqs off for idle */ | |
342 | stop_critical_timings(); | |
343 | ||
344 | /* enter_idle() needs rcu for notifiers */ | |
345 | rcu_idle_enter(); | |
346 | ||
347 | if (cpuidle_idle_call()) | |
a476bda3 | 348 | x86_idle(); |
90e24014 RW |
349 | |
350 | rcu_idle_exit(); | |
351 | start_critical_timings(); | |
352 | ||
353 | /* In many cases the interrupt that ended idle | |
354 | has already called exit_idle. But some idle | |
355 | loops can be woken up without interrupt. */ | |
356 | __exit_idle(); | |
357 | } | |
358 | ||
359 | tick_nohz_idle_exit(); | |
360 | preempt_enable_no_resched(); | |
361 | schedule(); | |
362 | preempt_disable(); | |
363 | } | |
364 | } | |
365 | ||
00dba564 TG |
366 | /* |
367 | * We use this if we don't have any better | |
368 | * idle routine.. | |
369 | */ | |
370 | void default_idle(void) | |
371 | { | |
4d0e42cc DL |
372 | trace_power_start_rcuidle(POWER_CSTATE, 1, smp_processor_id()); |
373 | trace_cpu_idle_rcuidle(1, smp_processor_id()); | |
374 | current_thread_info()->status &= ~TS_POLLING; | |
375 | /* | |
376 | * TS_POLLING-cleared state must be visible before we | |
377 | * test NEED_RESCHED: | |
378 | */ | |
379 | smp_mb(); | |
00dba564 | 380 | |
4d0e42cc DL |
381 | if (!need_resched()) |
382 | safe_halt(); /* enables interrupts racelessly */ | |
383 | else | |
00dba564 | 384 | local_irq_enable(); |
4d0e42cc DL |
385 | current_thread_info()->status |= TS_POLLING; |
386 | trace_power_end_rcuidle(smp_processor_id()); | |
387 | trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id()); | |
00dba564 | 388 | } |
60b8b1de | 389 | #ifdef CONFIG_APM_MODULE |
00dba564 TG |
390 | EXPORT_SYMBOL(default_idle); |
391 | #endif | |
392 | ||
e5fd47bf KRW |
393 | bool set_pm_idle_to_default(void) |
394 | { | |
a476bda3 | 395 | bool ret = !!x86_idle; |
e5fd47bf | 396 | |
a476bda3 | 397 | x86_idle = default_idle; |
e5fd47bf KRW |
398 | |
399 | return ret; | |
400 | } | |
d3ec5cae IV |
401 | void stop_this_cpu(void *dummy) |
402 | { | |
403 | local_irq_disable(); | |
404 | /* | |
405 | * Remove this CPU: | |
406 | */ | |
4f062896 | 407 | set_cpu_online(smp_processor_id(), false); |
d3ec5cae IV |
408 | disable_local_APIC(); |
409 | ||
410 | for (;;) { | |
411 | if (hlt_works(smp_processor_id())) | |
412 | halt(); | |
413 | } | |
414 | } | |
415 | ||
7f424a8b PZ |
416 | /* Default MONITOR/MWAIT with no hints, used for default C1 state */ |
417 | static void mwait_idle(void) | |
418 | { | |
419 | if (!need_resched()) { | |
48454650 SR |
420 | trace_power_start_rcuidle(POWER_CSTATE, 1, smp_processor_id()); |
421 | trace_cpu_idle_rcuidle(1, smp_processor_id()); | |
349c004e | 422 | if (this_cpu_has(X86_FEATURE_CLFLUSH_MONITOR)) |
e736ad54 PV |
423 | clflush((void *)¤t_thread_info()->flags); |
424 | ||
7f424a8b PZ |
425 | __monitor((void *)¤t_thread_info()->flags, 0, 0); |
426 | smp_mb(); | |
427 | if (!need_resched()) | |
428 | __sti_mwait(0, 0); | |
429 | else | |
430 | local_irq_enable(); | |
48454650 SR |
431 | trace_power_end_rcuidle(smp_processor_id()); |
432 | trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id()); | |
7f424a8b PZ |
433 | } else |
434 | local_irq_enable(); | |
435 | } | |
436 | ||
7f424a8b PZ |
437 | /* |
438 | * On SMP it's slightly faster (but much more power-consuming!) | |
439 | * to poll the ->work.need_resched flag instead of waiting for the | |
440 | * cross-CPU IPI to arrive. Use this option with caution. | |
441 | */ | |
442 | static void poll_idle(void) | |
443 | { | |
48454650 SR |
444 | trace_power_start_rcuidle(POWER_CSTATE, 0, smp_processor_id()); |
445 | trace_cpu_idle_rcuidle(0, smp_processor_id()); | |
7f424a8b | 446 | local_irq_enable(); |
2c7e9fd4 JK |
447 | while (!need_resched()) |
448 | cpu_relax(); | |
48454650 SR |
449 | trace_power_end_rcuidle(smp_processor_id()); |
450 | trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id()); | |
7f424a8b PZ |
451 | } |
452 | ||
e9623b35 TG |
453 | /* |
454 | * mwait selection logic: | |
455 | * | |
456 | * It depends on the CPU. For AMD CPUs that support MWAIT this is | |
457 | * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings | |
458 | * then depend on a clock divisor and current Pstate of the core. If | |
459 | * all cores of a processor are in halt state (C1) the processor can | |
460 | * enter the C1E (C1 enhanced) state. If mwait is used this will never | |
461 | * happen. | |
462 | * | |
463 | * idle=mwait overrides this decision and forces the usage of mwait. | |
464 | */ | |
09fd4b4e TG |
465 | |
466 | #define MWAIT_INFO 0x05 | |
467 | #define MWAIT_ECX_EXTENDED_INFO 0x01 | |
468 | #define MWAIT_EDX_C1 0xf0 | |
469 | ||
1c9d16e3 | 470 | int mwait_usable(const struct cpuinfo_x86 *c) |
e9623b35 | 471 | { |
09fd4b4e TG |
472 | u32 eax, ebx, ecx, edx; |
473 | ||
19209bbb | 474 | /* Use mwait if idle=mwait boot option is given */ |
d1896049 | 475 | if (boot_option_idle_override == IDLE_FORCE_MWAIT) |
e9623b35 TG |
476 | return 1; |
477 | ||
19209bbb SB |
478 | /* |
479 | * Any idle= boot option other than idle=mwait means that we must not | |
480 | * use mwait. Eg: idle=halt or idle=poll or idle=nomwait | |
481 | */ | |
482 | if (boot_option_idle_override != IDLE_NO_OVERRIDE) | |
483 | return 0; | |
484 | ||
09fd4b4e TG |
485 | if (c->cpuid_level < MWAIT_INFO) |
486 | return 0; | |
487 | ||
488 | cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx); | |
489 | /* Check, whether EDX has extended info about MWAIT */ | |
490 | if (!(ecx & MWAIT_ECX_EXTENDED_INFO)) | |
491 | return 1; | |
492 | ||
493 | /* | |
494 | * edx enumeratios MONITOR/MWAIT extensions. Check, whether | |
495 | * C1 supports MWAIT | |
496 | */ | |
497 | return (edx & MWAIT_EDX_C1); | |
e9623b35 TG |
498 | } |
499 | ||
02c68a02 LB |
500 | bool amd_e400_c1e_detected; |
501 | EXPORT_SYMBOL(amd_e400_c1e_detected); | |
aa276e1c | 502 | |
02c68a02 | 503 | static cpumask_var_t amd_e400_c1e_mask; |
4faac97d | 504 | |
02c68a02 | 505 | void amd_e400_remove_cpu(int cpu) |
4faac97d | 506 | { |
02c68a02 LB |
507 | if (amd_e400_c1e_mask != NULL) |
508 | cpumask_clear_cpu(cpu, amd_e400_c1e_mask); | |
4faac97d TG |
509 | } |
510 | ||
aa276e1c | 511 | /* |
02c68a02 | 512 | * AMD Erratum 400 aware idle routine. We check for C1E active in the interrupt |
aa276e1c TG |
513 | * pending message MSR. If we detect C1E, then we handle it the same |
514 | * way as C3 power states (local apic timer and TSC stop) | |
515 | */ | |
02c68a02 | 516 | static void amd_e400_idle(void) |
aa276e1c | 517 | { |
aa276e1c TG |
518 | if (need_resched()) |
519 | return; | |
520 | ||
02c68a02 | 521 | if (!amd_e400_c1e_detected) { |
aa276e1c TG |
522 | u32 lo, hi; |
523 | ||
524 | rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi); | |
e8c534ec | 525 | |
aa276e1c | 526 | if (lo & K8_INTP_C1E_ACTIVE_MASK) { |
02c68a02 | 527 | amd_e400_c1e_detected = true; |
40fb1715 | 528 | if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) |
09bfeea1 | 529 | mark_tsc_unstable("TSC halt in AMD C1E"); |
c767a54b | 530 | pr_info("System has AMD C1E enabled\n"); |
aa276e1c TG |
531 | } |
532 | } | |
533 | ||
02c68a02 | 534 | if (amd_e400_c1e_detected) { |
aa276e1c TG |
535 | int cpu = smp_processor_id(); |
536 | ||
02c68a02 LB |
537 | if (!cpumask_test_cpu(cpu, amd_e400_c1e_mask)) { |
538 | cpumask_set_cpu(cpu, amd_e400_c1e_mask); | |
0beefa20 | 539 | /* |
f833bab8 | 540 | * Force broadcast so ACPI can not interfere. |
0beefa20 | 541 | */ |
aa276e1c TG |
542 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE, |
543 | &cpu); | |
c767a54b | 544 | pr_info("Switch to broadcast mode on CPU%d\n", cpu); |
aa276e1c TG |
545 | } |
546 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu); | |
0beefa20 | 547 | |
aa276e1c | 548 | default_idle(); |
0beefa20 TG |
549 | |
550 | /* | |
551 | * The switch back from broadcast mode needs to be | |
552 | * called with interrupts disabled. | |
553 | */ | |
554 | local_irq_disable(); | |
555 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu); | |
556 | local_irq_enable(); | |
aa276e1c TG |
557 | } else |
558 | default_idle(); | |
559 | } | |
560 | ||
7f424a8b PZ |
561 | void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c) |
562 | { | |
3e5095d1 | 563 | #ifdef CONFIG_SMP |
a476bda3 | 564 | if (x86_idle == poll_idle && smp_num_siblings > 1) |
c767a54b | 565 | pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n"); |
7f424a8b | 566 | #endif |
a476bda3 | 567 | if (x86_idle) |
6ddd2a27 TG |
568 | return; |
569 | ||
e9623b35 | 570 | if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) { |
7f424a8b | 571 | /* |
7f424a8b PZ |
572 | * One CPU supports mwait => All CPUs supports mwait |
573 | */ | |
c767a54b | 574 | pr_info("using mwait in idle threads\n"); |
a476bda3 | 575 | x86_idle = mwait_idle; |
9d8888c2 HR |
576 | } else if (cpu_has_amd_erratum(amd_erratum_400)) { |
577 | /* E400: APIC timer interrupt does not wake up CPU from C1e */ | |
c767a54b | 578 | pr_info("using AMD E400 aware idle routine\n"); |
a476bda3 | 579 | x86_idle = amd_e400_idle; |
6ddd2a27 | 580 | } else |
a476bda3 | 581 | x86_idle = default_idle; |
7f424a8b PZ |
582 | } |
583 | ||
02c68a02 | 584 | void __init init_amd_e400_c1e_mask(void) |
30e1e6d1 | 585 | { |
02c68a02 | 586 | /* If we're using amd_e400_idle, we need to allocate amd_e400_c1e_mask. */ |
a476bda3 | 587 | if (x86_idle == amd_e400_idle) |
02c68a02 | 588 | zalloc_cpumask_var(&amd_e400_c1e_mask, GFP_KERNEL); |
30e1e6d1 RR |
589 | } |
590 | ||
7f424a8b PZ |
591 | static int __init idle_setup(char *str) |
592 | { | |
ab6bc3e3 CG |
593 | if (!str) |
594 | return -EINVAL; | |
595 | ||
7f424a8b | 596 | if (!strcmp(str, "poll")) { |
c767a54b | 597 | pr_info("using polling idle threads\n"); |
a476bda3 | 598 | x86_idle = poll_idle; |
d1896049 TR |
599 | boot_option_idle_override = IDLE_POLL; |
600 | } else if (!strcmp(str, "mwait")) { | |
601 | boot_option_idle_override = IDLE_FORCE_MWAIT; | |
af0d6a0a | 602 | WARN_ONCE(1, "\"idle=mwait\" will be removed in 2012\n"); |
d1896049 | 603 | } else if (!strcmp(str, "halt")) { |
c1e3b377 ZY |
604 | /* |
605 | * When the boot option of idle=halt is added, halt is | |
606 | * forced to be used for CPU idle. In such case CPU C2/C3 | |
607 | * won't be used again. | |
608 | * To continue to load the CPU idle driver, don't touch | |
609 | * the boot_option_idle_override. | |
610 | */ | |
a476bda3 | 611 | x86_idle = default_idle; |
d1896049 | 612 | boot_option_idle_override = IDLE_HALT; |
da5e09a1 ZY |
613 | } else if (!strcmp(str, "nomwait")) { |
614 | /* | |
615 | * If the boot option of "idle=nomwait" is added, | |
616 | * it means that mwait will be disabled for CPU C2/C3 | |
617 | * states. In such case it won't touch the variable | |
618 | * of boot_option_idle_override. | |
619 | */ | |
d1896049 | 620 | boot_option_idle_override = IDLE_NOMWAIT; |
c1e3b377 | 621 | } else |
7f424a8b PZ |
622 | return -1; |
623 | ||
7f424a8b PZ |
624 | return 0; |
625 | } | |
626 | early_param("idle", idle_setup); | |
627 | ||
9d62dcdf AW |
628 | unsigned long arch_align_stack(unsigned long sp) |
629 | { | |
630 | if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) | |
631 | sp -= get_random_int() % 8192; | |
632 | return sp & ~0xf; | |
633 | } | |
634 | ||
635 | unsigned long arch_randomize_brk(struct mm_struct *mm) | |
636 | { | |
637 | unsigned long range_end = mm->brk + 0x02000000; | |
638 | return randomize_range(mm->brk, range_end, 0) ? : mm->brk; | |
639 | } | |
640 |