Commit | Line | Data |
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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
c767a54b JP |
2 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
3 | ||
61c4628b SS |
4 | #include <linux/errno.h> |
5 | #include <linux/kernel.h> | |
6 | #include <linux/mm.h> | |
7 | #include <linux/smp.h> | |
389d1fb1 | 8 | #include <linux/prctl.h> |
61c4628b SS |
9 | #include <linux/slab.h> |
10 | #include <linux/sched.h> | |
4c822698 | 11 | #include <linux/sched/idle.h> |
b17b0153 | 12 | #include <linux/sched/debug.h> |
29930025 | 13 | #include <linux/sched/task.h> |
68db0cf1 | 14 | #include <linux/sched/task_stack.h> |
186f4360 PG |
15 | #include <linux/init.h> |
16 | #include <linux/export.h> | |
7f424a8b | 17 | #include <linux/pm.h> |
162a688e | 18 | #include <linux/tick.h> |
9d62dcdf | 19 | #include <linux/random.h> |
7c68af6e | 20 | #include <linux/user-return-notifier.h> |
814e2c84 AI |
21 | #include <linux/dmi.h> |
22 | #include <linux/utsname.h> | |
90e24014 | 23 | #include <linux/stackprotector.h> |
90e24014 | 24 | #include <linux/cpuidle.h> |
89f579ce YW |
25 | #include <linux/acpi.h> |
26 | #include <linux/elf-randomize.h> | |
61613521 | 27 | #include <trace/events/power.h> |
24f1e32c | 28 | #include <linux/hw_breakpoint.h> |
93789b32 | 29 | #include <asm/cpu.h> |
d3ec5cae | 30 | #include <asm/apic.h> |
2c1b284e | 31 | #include <asm/syscalls.h> |
7c0f6ba6 | 32 | #include <linux/uaccess.h> |
b253149b | 33 | #include <asm/mwait.h> |
78f7f1e5 | 34 | #include <asm/fpu/internal.h> |
66cb5917 | 35 | #include <asm/debugreg.h> |
90e24014 | 36 | #include <asm/nmi.h> |
375074cc | 37 | #include <asm/tlbflush.h> |
8838eb6c | 38 | #include <asm/mce.h> |
9fda6a06 | 39 | #include <asm/vm86.h> |
7b32aead | 40 | #include <asm/switch_to.h> |
b7ffc44d | 41 | #include <asm/desc.h> |
e9ea1e7f | 42 | #include <asm/prctl.h> |
885f82bf | 43 | #include <asm/spec-ctrl.h> |
577d5cd7 | 44 | #include <asm/io_bitmap.h> |
89f579ce | 45 | #include <asm/proto.h> |
90e24014 | 46 | |
ff16701a TG |
47 | #include "process.h" |
48 | ||
45046892 TG |
49 | /* |
50 | * per-CPU TSS segments. Threads are completely 'soft' on Linux, | |
51 | * no more per-task TSS's. The TSS size is kept cacheline-aligned | |
52 | * so they are allowed to end up in the .data..cacheline_aligned | |
53 | * section. Since TSS's are completely CPU-local, we want them | |
54 | * on exact cacheline boundaries, to eliminate cacheline ping-pong. | |
55 | */ | |
2fd9c41a | 56 | __visible DEFINE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw) = { |
d0a0de21 | 57 | .x86_tss = { |
20bb8344 AL |
58 | /* |
59 | * .sp0 is only used when entering ring 0 from a lower | |
60 | * privilege level. Since the init task never runs anything | |
61 | * but ring 0 code, there is no need for a valid value here. | |
62 | * Poison it. | |
63 | */ | |
64 | .sp0 = (1UL << (BITS_PER_LONG-1)) + 1, | |
9aaefe7b | 65 | |
9aaefe7b AL |
66 | /* |
67 | * .sp1 is cpu_current_top_of_stack. The init task never | |
68 | * runs user code, but cpu_current_top_of_stack should still | |
69 | * be well defined before the first context switch. | |
70 | */ | |
71 | .sp1 = TOP_OF_INIT_STACK, | |
9aaefe7b | 72 | |
d0a0de21 AL |
73 | #ifdef CONFIG_X86_32 |
74 | .ss0 = __KERNEL_DS, | |
75 | .ss1 = __KERNEL_CS, | |
d0a0de21 | 76 | #endif |
ecc7e37d | 77 | .io_bitmap_base = IO_BITMAP_OFFSET_INVALID, |
d0a0de21 | 78 | }, |
d0a0de21 | 79 | }; |
c482feef | 80 | EXPORT_PER_CPU_SYMBOL(cpu_tss_rw); |
45046892 | 81 | |
b7ceaec1 AL |
82 | DEFINE_PER_CPU(bool, __tss_limit_invalid); |
83 | EXPORT_PER_CPU_SYMBOL_GPL(__tss_limit_invalid); | |
b7ffc44d | 84 | |
55ccf3fe SS |
85 | /* |
86 | * this gets called so that we can store lazy state into memory and copy the | |
87 | * current task into the new thread. | |
88 | */ | |
61c4628b SS |
89 | int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) |
90 | { | |
5aaeb5c0 | 91 | memcpy(dst, src, arch_task_struct_size); |
2459ee86 AL |
92 | #ifdef CONFIG_VM86 |
93 | dst->thread.vm86 = NULL; | |
94 | #endif | |
f1853505 | 95 | |
5f409e20 | 96 | return fpu__copy(dst, src); |
61c4628b | 97 | } |
7f424a8b | 98 | |
389d1fb1 JF |
99 | /* |
100 | * Free current thread data structures etc.. | |
101 | */ | |
e6464694 | 102 | void exit_thread(struct task_struct *tsk) |
389d1fb1 | 103 | { |
e6464694 | 104 | struct thread_struct *t = &tsk->thread; |
ca6787ba | 105 | struct fpu *fpu = &t->fpu; |
ea5f1cd7 TG |
106 | |
107 | if (test_thread_flag(TIF_IO_BITMAP)) | |
108 | io_bitmap_exit(); | |
1dcc8d7b | 109 | |
9fda6a06 BG |
110 | free_vm86(t); |
111 | ||
50338615 | 112 | fpu__drop(fpu); |
389d1fb1 JF |
113 | } |
114 | ||
2fff071d TG |
115 | static int set_new_tls(struct task_struct *p, unsigned long tls) |
116 | { | |
117 | struct user_desc __user *utls = (struct user_desc __user *)tls; | |
118 | ||
119 | if (in_ia32_syscall()) | |
120 | return do_set_thread_area(p, -1, utls, 0); | |
121 | else | |
122 | return do_set_thread_area_64(p, ARCH_SET_FS, tls); | |
123 | } | |
124 | ||
2fff071d TG |
125 | int copy_thread_tls(unsigned long clone_flags, unsigned long sp, |
126 | unsigned long arg, struct task_struct *p, unsigned long tls) | |
127 | { | |
128 | struct inactive_task_frame *frame; | |
129 | struct fork_frame *fork_frame; | |
130 | struct pt_regs *childregs; | |
4804e382 | 131 | int ret = 0; |
2fff071d TG |
132 | |
133 | childregs = task_pt_regs(p); | |
134 | fork_frame = container_of(childregs, struct fork_frame, regs); | |
135 | frame = &fork_frame->frame; | |
136 | ||
137 | frame->bp = 0; | |
138 | frame->ret_addr = (unsigned long) ret_from_fork; | |
139 | p->thread.sp = (unsigned long) fork_frame; | |
577d5cd7 | 140 | p->thread.io_bitmap = NULL; |
2fff071d TG |
141 | memset(p->thread.ptrace_bps, 0, sizeof(p->thread.ptrace_bps)); |
142 | ||
143 | #ifdef CONFIG_X86_64 | |
144 | savesegment(gs, p->thread.gsindex); | |
145 | p->thread.gsbase = p->thread.gsindex ? 0 : current->thread.gsbase; | |
146 | savesegment(fs, p->thread.fsindex); | |
147 | p->thread.fsbase = p->thread.fsindex ? 0 : current->thread.fsbase; | |
148 | savesegment(es, p->thread.es); | |
149 | savesegment(ds, p->thread.ds); | |
150 | #else | |
151 | p->thread.sp0 = (unsigned long) (childregs + 1); | |
152 | /* | |
153 | * Clear all status flags including IF and set fixed bit. 64bit | |
154 | * does not have this initialization as the frame does not contain | |
155 | * flags. The flags consistency (especially vs. AC) is there | |
156 | * ensured via objtool, which lacks 32bit support. | |
157 | */ | |
158 | frame->flags = X86_EFLAGS_FIXED; | |
159 | #endif | |
160 | ||
161 | /* Kernel thread ? */ | |
162 | if (unlikely(p->flags & PF_KTHREAD)) { | |
163 | memset(childregs, 0, sizeof(struct pt_regs)); | |
164 | kthread_frame_init(frame, sp, arg); | |
165 | return 0; | |
166 | } | |
167 | ||
168 | frame->bx = 0; | |
169 | *childregs = *current_pt_regs(); | |
170 | childregs->ax = 0; | |
171 | if (sp) | |
172 | childregs->sp = sp; | |
173 | ||
174 | #ifdef CONFIG_X86_32 | |
175 | task_user_gs(p) = get_user_gs(current_pt_regs()); | |
176 | #endif | |
177 | ||
2fff071d | 178 | /* Set a new TLS for the child thread? */ |
4804e382 | 179 | if (clone_flags & CLONE_SETTLS) |
2fff071d | 180 | ret = set_new_tls(p, tls); |
4804e382 TG |
181 | |
182 | if (!ret && unlikely(test_tsk_thread_flag(current, TIF_IO_BITMAP))) | |
183 | io_bitmap_share(p); | |
184 | ||
2fff071d TG |
185 | return ret; |
186 | } | |
187 | ||
389d1fb1 JF |
188 | void flush_thread(void) |
189 | { | |
190 | struct task_struct *tsk = current; | |
191 | ||
24f1e32c | 192 | flush_ptrace_hw_breakpoint(tsk); |
389d1fb1 | 193 | memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array)); |
110d7f75 | 194 | |
04c8e01d | 195 | fpu__clear(&tsk->thread.fpu); |
389d1fb1 JF |
196 | } |
197 | ||
389d1fb1 JF |
198 | void disable_TSC(void) |
199 | { | |
200 | preempt_disable(); | |
201 | if (!test_and_set_thread_flag(TIF_NOTSC)) | |
202 | /* | |
203 | * Must flip the CPU state synchronously with | |
204 | * TIF_NOTSC in the current running context. | |
205 | */ | |
5a920155 | 206 | cr4_set_bits(X86_CR4_TSD); |
389d1fb1 JF |
207 | preempt_enable(); |
208 | } | |
209 | ||
389d1fb1 JF |
210 | static void enable_TSC(void) |
211 | { | |
212 | preempt_disable(); | |
213 | if (test_and_clear_thread_flag(TIF_NOTSC)) | |
214 | /* | |
215 | * Must flip the CPU state synchronously with | |
216 | * TIF_NOTSC in the current running context. | |
217 | */ | |
5a920155 | 218 | cr4_clear_bits(X86_CR4_TSD); |
389d1fb1 JF |
219 | preempt_enable(); |
220 | } | |
221 | ||
222 | int get_tsc_mode(unsigned long adr) | |
223 | { | |
224 | unsigned int val; | |
225 | ||
226 | if (test_thread_flag(TIF_NOTSC)) | |
227 | val = PR_TSC_SIGSEGV; | |
228 | else | |
229 | val = PR_TSC_ENABLE; | |
230 | ||
231 | return put_user(val, (unsigned int __user *)adr); | |
232 | } | |
233 | ||
234 | int set_tsc_mode(unsigned int val) | |
235 | { | |
236 | if (val == PR_TSC_SIGSEGV) | |
237 | disable_TSC(); | |
238 | else if (val == PR_TSC_ENABLE) | |
239 | enable_TSC(); | |
240 | else | |
241 | return -EINVAL; | |
242 | ||
243 | return 0; | |
244 | } | |
245 | ||
e9ea1e7f KH |
246 | DEFINE_PER_CPU(u64, msr_misc_features_shadow); |
247 | ||
248 | static void set_cpuid_faulting(bool on) | |
249 | { | |
250 | u64 msrval; | |
251 | ||
252 | msrval = this_cpu_read(msr_misc_features_shadow); | |
253 | msrval &= ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT; | |
254 | msrval |= (on << MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT); | |
255 | this_cpu_write(msr_misc_features_shadow, msrval); | |
256 | wrmsrl(MSR_MISC_FEATURES_ENABLES, msrval); | |
257 | } | |
258 | ||
259 | static void disable_cpuid(void) | |
260 | { | |
261 | preempt_disable(); | |
262 | if (!test_and_set_thread_flag(TIF_NOCPUID)) { | |
263 | /* | |
264 | * Must flip the CPU state synchronously with | |
265 | * TIF_NOCPUID in the current running context. | |
266 | */ | |
267 | set_cpuid_faulting(true); | |
268 | } | |
269 | preempt_enable(); | |
270 | } | |
271 | ||
272 | static void enable_cpuid(void) | |
273 | { | |
274 | preempt_disable(); | |
275 | if (test_and_clear_thread_flag(TIF_NOCPUID)) { | |
276 | /* | |
277 | * Must flip the CPU state synchronously with | |
278 | * TIF_NOCPUID in the current running context. | |
279 | */ | |
280 | set_cpuid_faulting(false); | |
281 | } | |
282 | preempt_enable(); | |
283 | } | |
284 | ||
285 | static int get_cpuid_mode(void) | |
286 | { | |
287 | return !test_thread_flag(TIF_NOCPUID); | |
288 | } | |
289 | ||
290 | static int set_cpuid_mode(struct task_struct *task, unsigned long cpuid_enabled) | |
291 | { | |
67e87d43 | 292 | if (!boot_cpu_has(X86_FEATURE_CPUID_FAULT)) |
e9ea1e7f KH |
293 | return -ENODEV; |
294 | ||
295 | if (cpuid_enabled) | |
296 | enable_cpuid(); | |
297 | else | |
298 | disable_cpuid(); | |
299 | ||
300 | return 0; | |
301 | } | |
302 | ||
303 | /* | |
304 | * Called immediately after a successful exec. | |
305 | */ | |
306 | void arch_setup_new_exec(void) | |
307 | { | |
308 | /* If cpuid was previously disabled for this task, re-enable it. */ | |
309 | if (test_thread_flag(TIF_NOCPUID)) | |
310 | enable_cpuid(); | |
71368af9 WL |
311 | |
312 | /* | |
313 | * Don't inherit TIF_SSBD across exec boundary when | |
314 | * PR_SPEC_DISABLE_NOEXEC is used. | |
315 | */ | |
316 | if (test_thread_flag(TIF_SSBD) && | |
317 | task_spec_ssb_noexec(current)) { | |
318 | clear_thread_flag(TIF_SSBD); | |
319 | task_clear_spec_ssb_disable(current); | |
320 | task_clear_spec_ssb_noexec(current); | |
321 | speculation_ctrl_update(task_thread_info(current)->flags); | |
322 | } | |
e9ea1e7f KH |
323 | } |
324 | ||
22fe5b04 TG |
325 | static inline void tss_invalidate_io_bitmap(struct tss_struct *tss) |
326 | { | |
327 | /* | |
328 | * Invalidate the I/O bitmap by moving io_bitmap_base outside the | |
329 | * TSS limit so any subsequent I/O access from user space will | |
330 | * trigger a #GP. | |
331 | * | |
332 | * This is correct even when VMEXIT rewrites the TSS limit | |
333 | * to 0x67 as the only requirement is that the base points | |
334 | * outside the limit. | |
335 | */ | |
336 | tss->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET_INVALID; | |
337 | } | |
338 | ||
339 | static inline void switch_to_bitmap(unsigned long tifp) | |
340 | { | |
341 | /* | |
342 | * Invalidate I/O bitmap if the previous task used it. This prevents | |
343 | * any possible leakage of an active I/O bitmap. | |
344 | * | |
345 | * If the next task has an I/O bitmap it will handle it on exit to | |
346 | * user mode. | |
347 | */ | |
348 | if (tifp & _TIF_IO_BITMAP) | |
349 | tss_invalidate_io_bitmap(this_cpu_ptr(&cpu_tss_rw)); | |
350 | } | |
351 | ||
352 | static void tss_copy_io_bitmap(struct tss_struct *tss, struct io_bitmap *iobm) | |
060aa16f TG |
353 | { |
354 | /* | |
355 | * Copy at least the byte range of the incoming tasks bitmap which | |
356 | * covers the permitted I/O ports. | |
357 | * | |
358 | * If the previous task which used an I/O bitmap had more bits | |
359 | * permitted, then the copy needs to cover those as well so they | |
360 | * get turned off. | |
361 | */ | |
362 | memcpy(tss->io_bitmap.bitmap, iobm->bitmap, | |
363 | max(tss->io_bitmap.prev_max, iobm->max)); | |
364 | ||
365 | /* | |
366 | * Store the new max and the sequence number of this bitmap | |
367 | * and a pointer to the bitmap itself. | |
368 | */ | |
369 | tss->io_bitmap.prev_max = iobm->max; | |
370 | tss->io_bitmap.prev_sequence = iobm->sequence; | |
371 | } | |
372 | ||
22fe5b04 TG |
373 | /** |
374 | * tss_update_io_bitmap - Update I/O bitmap before exiting to usermode | |
375 | */ | |
376 | void tss_update_io_bitmap(void) | |
af8b3cd3 | 377 | { |
ff16701a | 378 | struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw); |
c8137ace | 379 | u16 *base = &tss->x86_tss.io_bitmap_base; |
ff16701a | 380 | |
22fe5b04 | 381 | if (test_thread_flag(TIF_IO_BITMAP)) { |
c8137ace TG |
382 | struct thread_struct *t = ¤t->thread; |
383 | ||
384 | if (IS_ENABLED(CONFIG_X86_IOPL_EMULATION) && | |
385 | t->iopl_emul == 3) { | |
386 | *base = IO_BITMAP_OFFSET_VALID_ALL; | |
387 | } else { | |
388 | struct io_bitmap *iobm = t->io_bitmap; | |
389 | /* | |
390 | * Only copy bitmap data when the sequence number | |
391 | * differs. The update time is accounted to the | |
392 | * incoming task. | |
393 | */ | |
394 | if (tss->io_bitmap.prev_sequence != iobm->sequence) | |
395 | tss_copy_io_bitmap(tss, iobm); | |
396 | ||
397 | /* Enable the bitmap */ | |
398 | *base = IO_BITMAP_OFFSET_VALID_MAP; | |
399 | } | |
af8b3cd3 | 400 | /* |
ecc7e37d TG |
401 | * Make sure that the TSS limit is covering the io bitmap. |
402 | * It might have been cut down by a VMEXIT to 0x67 which | |
403 | * would cause a subsequent I/O access from user space to | |
404 | * trigger a #GP because tbe bitmap is outside the TSS | |
405 | * limit. | |
af8b3cd3 KH |
406 | */ |
407 | refresh_tss_limit(); | |
22fe5b04 TG |
408 | } else { |
409 | tss_invalidate_io_bitmap(tss); | |
af8b3cd3 KH |
410 | } |
411 | } | |
412 | ||
1f50ddb4 TG |
413 | #ifdef CONFIG_SMP |
414 | ||
415 | struct ssb_state { | |
416 | struct ssb_state *shared_state; | |
417 | raw_spinlock_t lock; | |
418 | unsigned int disable_state; | |
419 | unsigned long local_state; | |
420 | }; | |
421 | ||
422 | #define LSTATE_SSB 0 | |
423 | ||
424 | static DEFINE_PER_CPU(struct ssb_state, ssb_state); | |
425 | ||
426 | void speculative_store_bypass_ht_init(void) | |
885f82bf | 427 | { |
1f50ddb4 TG |
428 | struct ssb_state *st = this_cpu_ptr(&ssb_state); |
429 | unsigned int this_cpu = smp_processor_id(); | |
430 | unsigned int cpu; | |
431 | ||
432 | st->local_state = 0; | |
433 | ||
434 | /* | |
435 | * Shared state setup happens once on the first bringup | |
436 | * of the CPU. It's not destroyed on CPU hotunplug. | |
437 | */ | |
438 | if (st->shared_state) | |
439 | return; | |
440 | ||
441 | raw_spin_lock_init(&st->lock); | |
442 | ||
443 | /* | |
444 | * Go over HT siblings and check whether one of them has set up the | |
445 | * shared state pointer already. | |
446 | */ | |
447 | for_each_cpu(cpu, topology_sibling_cpumask(this_cpu)) { | |
448 | if (cpu == this_cpu) | |
449 | continue; | |
450 | ||
451 | if (!per_cpu(ssb_state, cpu).shared_state) | |
452 | continue; | |
453 | ||
454 | /* Link it to the state of the sibling: */ | |
455 | st->shared_state = per_cpu(ssb_state, cpu).shared_state; | |
456 | return; | |
457 | } | |
458 | ||
459 | /* | |
460 | * First HT sibling to come up on the core. Link shared state of | |
461 | * the first HT sibling to itself. The siblings on the same core | |
462 | * which come up later will see the shared state pointer and link | |
463 | * themself to the state of this CPU. | |
464 | */ | |
465 | st->shared_state = st; | |
466 | } | |
885f82bf | 467 | |
1f50ddb4 TG |
468 | /* |
469 | * Logic is: First HT sibling enables SSBD for both siblings in the core | |
470 | * and last sibling to disable it, disables it for the whole core. This how | |
471 | * MSR_SPEC_CTRL works in "hardware": | |
472 | * | |
473 | * CORE_SPEC_CTRL = THREAD0_SPEC_CTRL | THREAD1_SPEC_CTRL | |
474 | */ | |
475 | static __always_inline void amd_set_core_ssb_state(unsigned long tifn) | |
476 | { | |
477 | struct ssb_state *st = this_cpu_ptr(&ssb_state); | |
478 | u64 msr = x86_amd_ls_cfg_base; | |
479 | ||
480 | if (!static_cpu_has(X86_FEATURE_ZEN)) { | |
481 | msr |= ssbd_tif_to_amd_ls_cfg(tifn); | |
885f82bf | 482 | wrmsrl(MSR_AMD64_LS_CFG, msr); |
1f50ddb4 TG |
483 | return; |
484 | } | |
485 | ||
486 | if (tifn & _TIF_SSBD) { | |
487 | /* | |
488 | * Since this can race with prctl(), block reentry on the | |
489 | * same CPU. | |
490 | */ | |
491 | if (__test_and_set_bit(LSTATE_SSB, &st->local_state)) | |
492 | return; | |
493 | ||
494 | msr |= x86_amd_ls_cfg_ssbd_mask; | |
495 | ||
496 | raw_spin_lock(&st->shared_state->lock); | |
497 | /* First sibling enables SSBD: */ | |
498 | if (!st->shared_state->disable_state) | |
499 | wrmsrl(MSR_AMD64_LS_CFG, msr); | |
500 | st->shared_state->disable_state++; | |
501 | raw_spin_unlock(&st->shared_state->lock); | |
885f82bf | 502 | } else { |
1f50ddb4 TG |
503 | if (!__test_and_clear_bit(LSTATE_SSB, &st->local_state)) |
504 | return; | |
505 | ||
506 | raw_spin_lock(&st->shared_state->lock); | |
507 | st->shared_state->disable_state--; | |
508 | if (!st->shared_state->disable_state) | |
509 | wrmsrl(MSR_AMD64_LS_CFG, msr); | |
510 | raw_spin_unlock(&st->shared_state->lock); | |
885f82bf TG |
511 | } |
512 | } | |
1f50ddb4 TG |
513 | #else |
514 | static __always_inline void amd_set_core_ssb_state(unsigned long tifn) | |
515 | { | |
516 | u64 msr = x86_amd_ls_cfg_base | ssbd_tif_to_amd_ls_cfg(tifn); | |
517 | ||
518 | wrmsrl(MSR_AMD64_LS_CFG, msr); | |
519 | } | |
520 | #endif | |
521 | ||
11fb0683 TL |
522 | static __always_inline void amd_set_ssb_virt_state(unsigned long tifn) |
523 | { | |
524 | /* | |
525 | * SSBD has the same definition in SPEC_CTRL and VIRT_SPEC_CTRL, | |
526 | * so ssbd_tif_to_spec_ctrl() just works. | |
527 | */ | |
528 | wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, ssbd_tif_to_spec_ctrl(tifn)); | |
529 | } | |
530 | ||
01daf568 TC |
531 | /* |
532 | * Update the MSRs managing speculation control, during context switch. | |
533 | * | |
534 | * tifp: Previous task's thread flags | |
535 | * tifn: Next task's thread flags | |
536 | */ | |
537 | static __always_inline void __speculation_ctrl_update(unsigned long tifp, | |
538 | unsigned long tifn) | |
1f50ddb4 | 539 | { |
5bfbe3ad | 540 | unsigned long tif_diff = tifp ^ tifn; |
01daf568 TC |
541 | u64 msr = x86_spec_ctrl_base; |
542 | bool updmsr = false; | |
543 | ||
2f5fb193 TG |
544 | lockdep_assert_irqs_disabled(); |
545 | ||
5bfbe3ad TC |
546 | /* |
547 | * If TIF_SSBD is different, select the proper mitigation | |
548 | * method. Note that if SSBD mitigation is disabled or permanentely | |
549 | * enabled this branch can't be taken because nothing can set | |
550 | * TIF_SSBD. | |
551 | */ | |
552 | if (tif_diff & _TIF_SSBD) { | |
01daf568 TC |
553 | if (static_cpu_has(X86_FEATURE_VIRT_SSBD)) { |
554 | amd_set_ssb_virt_state(tifn); | |
555 | } else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD)) { | |
556 | amd_set_core_ssb_state(tifn); | |
557 | } else if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) || | |
558 | static_cpu_has(X86_FEATURE_AMD_SSBD)) { | |
559 | msr |= ssbd_tif_to_spec_ctrl(tifn); | |
560 | updmsr = true; | |
561 | } | |
562 | } | |
1f50ddb4 | 563 | |
5bfbe3ad TC |
564 | /* |
565 | * Only evaluate TIF_SPEC_IB if conditional STIBP is enabled, | |
566 | * otherwise avoid the MSR write. | |
567 | */ | |
568 | if (IS_ENABLED(CONFIG_SMP) && | |
569 | static_branch_unlikely(&switch_to_cond_stibp)) { | |
570 | updmsr |= !!(tif_diff & _TIF_SPEC_IB); | |
571 | msr |= stibp_tif_to_spec_ctrl(tifn); | |
572 | } | |
573 | ||
01daf568 TC |
574 | if (updmsr) |
575 | wrmsrl(MSR_IA32_SPEC_CTRL, msr); | |
1f50ddb4 TG |
576 | } |
577 | ||
6d991ba5 | 578 | static unsigned long speculation_ctrl_update_tif(struct task_struct *tsk) |
1f50ddb4 | 579 | { |
6d991ba5 TG |
580 | if (test_and_clear_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE)) { |
581 | if (task_spec_ssb_disable(tsk)) | |
582 | set_tsk_thread_flag(tsk, TIF_SSBD); | |
583 | else | |
584 | clear_tsk_thread_flag(tsk, TIF_SSBD); | |
9137bb27 TG |
585 | |
586 | if (task_spec_ib_disable(tsk)) | |
587 | set_tsk_thread_flag(tsk, TIF_SPEC_IB); | |
588 | else | |
589 | clear_tsk_thread_flag(tsk, TIF_SPEC_IB); | |
6d991ba5 TG |
590 | } |
591 | /* Return the updated threadinfo flags*/ | |
592 | return task_thread_info(tsk)->flags; | |
1f50ddb4 | 593 | } |
885f82bf | 594 | |
26c4d75b | 595 | void speculation_ctrl_update(unsigned long tif) |
885f82bf | 596 | { |
2f5fb193 TG |
597 | unsigned long flags; |
598 | ||
01daf568 | 599 | /* Forced update. Make sure all relevant TIF flags are different */ |
2f5fb193 | 600 | local_irq_save(flags); |
01daf568 | 601 | __speculation_ctrl_update(~tif, tif); |
2f5fb193 | 602 | local_irq_restore(flags); |
885f82bf TG |
603 | } |
604 | ||
6d991ba5 TG |
605 | /* Called from seccomp/prctl update */ |
606 | void speculation_ctrl_update_current(void) | |
607 | { | |
608 | preempt_disable(); | |
609 | speculation_ctrl_update(speculation_ctrl_update_tif(current)); | |
610 | preempt_enable(); | |
611 | } | |
612 | ||
ff16701a | 613 | void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p) |
389d1fb1 JF |
614 | { |
615 | struct thread_struct *prev, *next; | |
af8b3cd3 | 616 | unsigned long tifp, tifn; |
389d1fb1 JF |
617 | |
618 | prev = &prev_p->thread; | |
619 | next = &next_p->thread; | |
620 | ||
af8b3cd3 KH |
621 | tifn = READ_ONCE(task_thread_info(next_p)->flags); |
622 | tifp = READ_ONCE(task_thread_info(prev_p)->flags); | |
22fe5b04 TG |
623 | |
624 | switch_to_bitmap(tifp); | |
af8b3cd3 KH |
625 | |
626 | propagate_user_return_notify(prev_p, next_p); | |
627 | ||
b9894a2f KH |
628 | if ((tifp & _TIF_BLOCKSTEP || tifn & _TIF_BLOCKSTEP) && |
629 | arch_has_block_step()) { | |
630 | unsigned long debugctl, msk; | |
ea8e61b7 | 631 | |
b9894a2f | 632 | rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); |
ea8e61b7 | 633 | debugctl &= ~DEBUGCTLMSR_BTF; |
b9894a2f KH |
634 | msk = tifn & _TIF_BLOCKSTEP; |
635 | debugctl |= (msk >> TIF_BLOCKSTEP) << DEBUGCTLMSR_BTF_SHIFT; | |
636 | wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); | |
ea8e61b7 | 637 | } |
389d1fb1 | 638 | |
5a920155 | 639 | if ((tifp ^ tifn) & _TIF_NOTSC) |
9d0b6232 | 640 | cr4_toggle_bits_irqsoff(X86_CR4_TSD); |
e9ea1e7f KH |
641 | |
642 | if ((tifp ^ tifn) & _TIF_NOCPUID) | |
643 | set_cpuid_faulting(!!(tifn & _TIF_NOCPUID)); | |
885f82bf | 644 | |
6d991ba5 TG |
645 | if (likely(!((tifp | tifn) & _TIF_SPEC_FORCE_UPDATE))) { |
646 | __speculation_ctrl_update(tifp, tifn); | |
647 | } else { | |
648 | speculation_ctrl_update_tif(prev_p); | |
649 | tifn = speculation_ctrl_update_tif(next_p); | |
650 | ||
651 | /* Enforce MSR update to ensure consistent state */ | |
652 | __speculation_ctrl_update(~tifn, tifn); | |
653 | } | |
389d1fb1 JF |
654 | } |
655 | ||
00dba564 TG |
656 | /* |
657 | * Idle related variables and functions | |
658 | */ | |
d1896049 | 659 | unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE; |
00dba564 TG |
660 | EXPORT_SYMBOL(boot_option_idle_override); |
661 | ||
a476bda3 | 662 | static void (*x86_idle)(void); |
00dba564 | 663 | |
90e24014 RW |
664 | #ifndef CONFIG_SMP |
665 | static inline void play_dead(void) | |
666 | { | |
667 | BUG(); | |
668 | } | |
669 | #endif | |
670 | ||
7d1a9417 TG |
671 | void arch_cpu_idle_enter(void) |
672 | { | |
6a369583 | 673 | tsc_verify_tsc_adjust(false); |
7d1a9417 | 674 | local_touch_nmi(); |
7d1a9417 | 675 | } |
90e24014 | 676 | |
7d1a9417 TG |
677 | void arch_cpu_idle_dead(void) |
678 | { | |
679 | play_dead(); | |
680 | } | |
90e24014 | 681 | |
7d1a9417 TG |
682 | /* |
683 | * Called from the generic idle code. | |
684 | */ | |
685 | void arch_cpu_idle(void) | |
686 | { | |
16f8b05a | 687 | x86_idle(); |
90e24014 RW |
688 | } |
689 | ||
00dba564 | 690 | /* |
7d1a9417 | 691 | * We use this if we don't have any better idle routine.. |
00dba564 | 692 | */ |
6727ad9e | 693 | void __cpuidle default_idle(void) |
00dba564 | 694 | { |
4d0e42cc | 695 | trace_cpu_idle_rcuidle(1, smp_processor_id()); |
7d1a9417 | 696 | safe_halt(); |
4d0e42cc | 697 | trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id()); |
00dba564 | 698 | } |
fa86ee90 | 699 | #if defined(CONFIG_APM_MODULE) || defined(CONFIG_HALTPOLL_CPUIDLE_MODULE) |
00dba564 TG |
700 | EXPORT_SYMBOL(default_idle); |
701 | #endif | |
702 | ||
6a377ddc LB |
703 | #ifdef CONFIG_XEN |
704 | bool xen_set_default_idle(void) | |
e5fd47bf | 705 | { |
a476bda3 | 706 | bool ret = !!x86_idle; |
e5fd47bf | 707 | |
a476bda3 | 708 | x86_idle = default_idle; |
e5fd47bf KRW |
709 | |
710 | return ret; | |
711 | } | |
6a377ddc | 712 | #endif |
bba4ed01 | 713 | |
d3ec5cae IV |
714 | void stop_this_cpu(void *dummy) |
715 | { | |
716 | local_irq_disable(); | |
717 | /* | |
718 | * Remove this CPU: | |
719 | */ | |
4f062896 | 720 | set_cpu_online(smp_processor_id(), false); |
d3ec5cae | 721 | disable_local_APIC(); |
8838eb6c | 722 | mcheck_cpu_clear(this_cpu_ptr(&cpu_info)); |
d3ec5cae | 723 | |
f23d74f6 TL |
724 | /* |
725 | * Use wbinvd on processors that support SME. This provides support | |
726 | * for performing a successful kexec when going from SME inactive | |
727 | * to SME active (or vice-versa). The cache must be cleared so that | |
728 | * if there are entries with the same physical address, both with and | |
729 | * without the encryption bit, they don't race each other when flushed | |
730 | * and potentially end up with the wrong entry being committed to | |
731 | * memory. | |
732 | */ | |
733 | if (boot_cpu_has(X86_FEATURE_SME)) | |
734 | native_wbinvd(); | |
bba4ed01 TL |
735 | for (;;) { |
736 | /* | |
f23d74f6 TL |
737 | * Use native_halt() so that memory contents don't change |
738 | * (stack usage and variables) after possibly issuing the | |
739 | * native_wbinvd() above. | |
bba4ed01 | 740 | */ |
f23d74f6 | 741 | native_halt(); |
bba4ed01 | 742 | } |
7f424a8b PZ |
743 | } |
744 | ||
aa276e1c | 745 | /* |
07c94a38 BP |
746 | * AMD Erratum 400 aware idle routine. We handle it the same way as C3 power |
747 | * states (local apic timer and TSC stop). | |
aa276e1c | 748 | */ |
02c68a02 | 749 | static void amd_e400_idle(void) |
aa276e1c | 750 | { |
07c94a38 BP |
751 | /* |
752 | * We cannot use static_cpu_has_bug() here because X86_BUG_AMD_APIC_C1E | |
753 | * gets set after static_cpu_has() places have been converted via | |
754 | * alternatives. | |
755 | */ | |
756 | if (!boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) { | |
757 | default_idle(); | |
758 | return; | |
aa276e1c TG |
759 | } |
760 | ||
07c94a38 | 761 | tick_broadcast_enter(); |
aa276e1c | 762 | |
07c94a38 | 763 | default_idle(); |
0beefa20 | 764 | |
07c94a38 BP |
765 | /* |
766 | * The switch back from broadcast mode needs to be called with | |
767 | * interrupts disabled. | |
768 | */ | |
769 | local_irq_disable(); | |
770 | tick_broadcast_exit(); | |
771 | local_irq_enable(); | |
aa276e1c TG |
772 | } |
773 | ||
b253149b LB |
774 | /* |
775 | * Intel Core2 and older machines prefer MWAIT over HALT for C1. | |
776 | * We can't rely on cpuidle installing MWAIT, because it will not load | |
777 | * on systems that support only C1 -- so the boot default must be MWAIT. | |
778 | * | |
779 | * Some AMD machines are the opposite, they depend on using HALT. | |
780 | * | |
781 | * So for default C1, which is used during boot until cpuidle loads, | |
782 | * use MWAIT-C1 on Intel HW that has it, else use HALT. | |
783 | */ | |
784 | static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c) | |
785 | { | |
786 | if (c->x86_vendor != X86_VENDOR_INTEL) | |
787 | return 0; | |
788 | ||
67e87d43 | 789 | if (!cpu_has(c, X86_FEATURE_MWAIT) || boot_cpu_has_bug(X86_BUG_MONITOR)) |
b253149b LB |
790 | return 0; |
791 | ||
792 | return 1; | |
793 | } | |
794 | ||
795 | /* | |
0fb0328d HR |
796 | * MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT |
797 | * with interrupts enabled and no flags, which is backwards compatible with the | |
798 | * original MWAIT implementation. | |
b253149b | 799 | */ |
6727ad9e | 800 | static __cpuidle void mwait_idle(void) |
b253149b | 801 | { |
f8e617f4 | 802 | if (!current_set_polling_and_test()) { |
e43d0189 | 803 | trace_cpu_idle_rcuidle(1, smp_processor_id()); |
f8e617f4 | 804 | if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) { |
ca59809f | 805 | mb(); /* quirk */ |
b253149b | 806 | clflush((void *)¤t_thread_info()->flags); |
ca59809f | 807 | mb(); /* quirk */ |
f8e617f4 | 808 | } |
b253149b LB |
809 | |
810 | __monitor((void *)¤t_thread_info()->flags, 0, 0); | |
b253149b LB |
811 | if (!need_resched()) |
812 | __sti_mwait(0, 0); | |
813 | else | |
814 | local_irq_enable(); | |
e43d0189 | 815 | trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id()); |
f8e617f4 | 816 | } else { |
b253149b | 817 | local_irq_enable(); |
f8e617f4 MG |
818 | } |
819 | __current_clr_polling(); | |
b253149b LB |
820 | } |
821 | ||
148f9bb8 | 822 | void select_idle_routine(const struct cpuinfo_x86 *c) |
7f424a8b | 823 | { |
3e5095d1 | 824 | #ifdef CONFIG_SMP |
7d1a9417 | 825 | if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1) |
c767a54b | 826 | pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n"); |
7f424a8b | 827 | #endif |
7d1a9417 | 828 | if (x86_idle || boot_option_idle_override == IDLE_POLL) |
6ddd2a27 TG |
829 | return; |
830 | ||
3344ed30 | 831 | if (boot_cpu_has_bug(X86_BUG_AMD_E400)) { |
c767a54b | 832 | pr_info("using AMD E400 aware idle routine\n"); |
a476bda3 | 833 | x86_idle = amd_e400_idle; |
b253149b LB |
834 | } else if (prefer_mwait_c1_over_halt(c)) { |
835 | pr_info("using mwait in idle threads\n"); | |
836 | x86_idle = mwait_idle; | |
6ddd2a27 | 837 | } else |
a476bda3 | 838 | x86_idle = default_idle; |
7f424a8b PZ |
839 | } |
840 | ||
07c94a38 | 841 | void amd_e400_c1e_apic_setup(void) |
30e1e6d1 | 842 | { |
07c94a38 BP |
843 | if (boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) { |
844 | pr_info("Switch to broadcast mode on CPU%d\n", smp_processor_id()); | |
845 | local_irq_disable(); | |
846 | tick_broadcast_force(); | |
847 | local_irq_enable(); | |
848 | } | |
30e1e6d1 RR |
849 | } |
850 | ||
e7ff3a47 TG |
851 | void __init arch_post_acpi_subsys_init(void) |
852 | { | |
853 | u32 lo, hi; | |
854 | ||
855 | if (!boot_cpu_has_bug(X86_BUG_AMD_E400)) | |
856 | return; | |
857 | ||
858 | /* | |
859 | * AMD E400 detection needs to happen after ACPI has been enabled. If | |
860 | * the machine is affected K8_INTP_C1E_ACTIVE_MASK bits are set in | |
861 | * MSR_K8_INT_PENDING_MSG. | |
862 | */ | |
863 | rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi); | |
864 | if (!(lo & K8_INTP_C1E_ACTIVE_MASK)) | |
865 | return; | |
866 | ||
867 | boot_cpu_set_bug(X86_BUG_AMD_APIC_C1E); | |
868 | ||
869 | if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) | |
870 | mark_tsc_unstable("TSC halt in AMD C1E"); | |
871 | pr_info("System has AMD C1E enabled\n"); | |
872 | } | |
873 | ||
7f424a8b PZ |
874 | static int __init idle_setup(char *str) |
875 | { | |
ab6bc3e3 CG |
876 | if (!str) |
877 | return -EINVAL; | |
878 | ||
7f424a8b | 879 | if (!strcmp(str, "poll")) { |
c767a54b | 880 | pr_info("using polling idle threads\n"); |
d1896049 | 881 | boot_option_idle_override = IDLE_POLL; |
7d1a9417 | 882 | cpu_idle_poll_ctrl(true); |
d1896049 | 883 | } else if (!strcmp(str, "halt")) { |
c1e3b377 ZY |
884 | /* |
885 | * When the boot option of idle=halt is added, halt is | |
886 | * forced to be used for CPU idle. In such case CPU C2/C3 | |
887 | * won't be used again. | |
888 | * To continue to load the CPU idle driver, don't touch | |
889 | * the boot_option_idle_override. | |
890 | */ | |
a476bda3 | 891 | x86_idle = default_idle; |
d1896049 | 892 | boot_option_idle_override = IDLE_HALT; |
da5e09a1 ZY |
893 | } else if (!strcmp(str, "nomwait")) { |
894 | /* | |
895 | * If the boot option of "idle=nomwait" is added, | |
896 | * it means that mwait will be disabled for CPU C2/C3 | |
897 | * states. In such case it won't touch the variable | |
898 | * of boot_option_idle_override. | |
899 | */ | |
d1896049 | 900 | boot_option_idle_override = IDLE_NOMWAIT; |
c1e3b377 | 901 | } else |
7f424a8b PZ |
902 | return -1; |
903 | ||
7f424a8b PZ |
904 | return 0; |
905 | } | |
906 | early_param("idle", idle_setup); | |
907 | ||
9d62dcdf AW |
908 | unsigned long arch_align_stack(unsigned long sp) |
909 | { | |
910 | if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) | |
911 | sp -= get_random_int() % 8192; | |
912 | return sp & ~0xf; | |
913 | } | |
914 | ||
915 | unsigned long arch_randomize_brk(struct mm_struct *mm) | |
916 | { | |
9c6f0902 | 917 | return randomize_page(mm->brk, 0x02000000); |
9d62dcdf AW |
918 | } |
919 | ||
7ba78053 TG |
920 | /* |
921 | * Called from fs/proc with a reference on @p to find the function | |
922 | * which called into schedule(). This needs to be done carefully | |
923 | * because the task might wake up and we might look at a stack | |
924 | * changing under us. | |
925 | */ | |
926 | unsigned long get_wchan(struct task_struct *p) | |
927 | { | |
74327a3e | 928 | unsigned long start, bottom, top, sp, fp, ip, ret = 0; |
7ba78053 TG |
929 | int count = 0; |
930 | ||
6e662ae7 | 931 | if (p == current || p->state == TASK_RUNNING) |
7ba78053 TG |
932 | return 0; |
933 | ||
74327a3e AL |
934 | if (!try_get_task_stack(p)) |
935 | return 0; | |
936 | ||
7ba78053 TG |
937 | start = (unsigned long)task_stack_page(p); |
938 | if (!start) | |
74327a3e | 939 | goto out; |
7ba78053 TG |
940 | |
941 | /* | |
942 | * Layout of the stack page: | |
943 | * | |
944 | * ----------- topmax = start + THREAD_SIZE - sizeof(unsigned long) | |
945 | * PADDING | |
946 | * ----------- top = topmax - TOP_OF_KERNEL_STACK_PADDING | |
947 | * stack | |
15f4eae7 | 948 | * ----------- bottom = start |
7ba78053 TG |
949 | * |
950 | * The tasks stack pointer points at the location where the | |
951 | * framepointer is stored. The data on the stack is: | |
952 | * ... IP FP ... IP FP | |
953 | * | |
954 | * We need to read FP and IP, so we need to adjust the upper | |
955 | * bound by another unsigned long. | |
956 | */ | |
957 | top = start + THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; | |
958 | top -= 2 * sizeof(unsigned long); | |
15f4eae7 | 959 | bottom = start; |
7ba78053 TG |
960 | |
961 | sp = READ_ONCE(p->thread.sp); | |
962 | if (sp < bottom || sp > top) | |
74327a3e | 963 | goto out; |
7ba78053 | 964 | |
7b32aead | 965 | fp = READ_ONCE_NOCHECK(((struct inactive_task_frame *)sp)->bp); |
7ba78053 TG |
966 | do { |
967 | if (fp < bottom || fp > top) | |
74327a3e | 968 | goto out; |
f7d27c35 | 969 | ip = READ_ONCE_NOCHECK(*(unsigned long *)(fp + sizeof(unsigned long))); |
74327a3e AL |
970 | if (!in_sched_functions(ip)) { |
971 | ret = ip; | |
972 | goto out; | |
973 | } | |
f7d27c35 | 974 | fp = READ_ONCE_NOCHECK(*(unsigned long *)fp); |
7ba78053 | 975 | } while (count++ < 16 && p->state != TASK_RUNNING); |
74327a3e AL |
976 | |
977 | out: | |
978 | put_task_stack(p); | |
979 | return ret; | |
7ba78053 | 980 | } |
b0b9b014 KH |
981 | |
982 | long do_arch_prctl_common(struct task_struct *task, int option, | |
983 | unsigned long cpuid_enabled) | |
984 | { | |
e9ea1e7f KH |
985 | switch (option) { |
986 | case ARCH_GET_CPUID: | |
987 | return get_cpuid_mode(); | |
988 | case ARCH_SET_CPUID: | |
989 | return set_cpuid_mode(task, cpuid_enabled); | |
990 | } | |
991 | ||
b0b9b014 KH |
992 | return -EINVAL; |
993 | } |