Commit | Line | Data |
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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
c767a54b JP |
2 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
3 | ||
61c4628b SS |
4 | #include <linux/errno.h> |
5 | #include <linux/kernel.h> | |
6 | #include <linux/mm.h> | |
7 | #include <linux/smp.h> | |
389d1fb1 | 8 | #include <linux/prctl.h> |
61c4628b SS |
9 | #include <linux/slab.h> |
10 | #include <linux/sched.h> | |
4c822698 | 11 | #include <linux/sched/idle.h> |
b17b0153 | 12 | #include <linux/sched/debug.h> |
29930025 | 13 | #include <linux/sched/task.h> |
68db0cf1 | 14 | #include <linux/sched/task_stack.h> |
186f4360 PG |
15 | #include <linux/init.h> |
16 | #include <linux/export.h> | |
7f424a8b | 17 | #include <linux/pm.h> |
162a688e | 18 | #include <linux/tick.h> |
9d62dcdf | 19 | #include <linux/random.h> |
7c68af6e | 20 | #include <linux/user-return-notifier.h> |
814e2c84 AI |
21 | #include <linux/dmi.h> |
22 | #include <linux/utsname.h> | |
90e24014 | 23 | #include <linux/stackprotector.h> |
90e24014 | 24 | #include <linux/cpuidle.h> |
89f579ce YW |
25 | #include <linux/acpi.h> |
26 | #include <linux/elf-randomize.h> | |
61613521 | 27 | #include <trace/events/power.h> |
24f1e32c | 28 | #include <linux/hw_breakpoint.h> |
93789b32 | 29 | #include <asm/cpu.h> |
d3ec5cae | 30 | #include <asm/apic.h> |
7c0f6ba6 | 31 | #include <linux/uaccess.h> |
b253149b | 32 | #include <asm/mwait.h> |
db8268df | 33 | #include <asm/fpu/api.h> |
63e81807 | 34 | #include <asm/fpu/sched.h> |
500afbf6 | 35 | #include <asm/fpu/xstate.h> |
66cb5917 | 36 | #include <asm/debugreg.h> |
90e24014 | 37 | #include <asm/nmi.h> |
375074cc | 38 | #include <asm/tlbflush.h> |
8838eb6c | 39 | #include <asm/mce.h> |
9fda6a06 | 40 | #include <asm/vm86.h> |
7b32aead | 41 | #include <asm/switch_to.h> |
b7ffc44d | 42 | #include <asm/desc.h> |
e9ea1e7f | 43 | #include <asm/prctl.h> |
885f82bf | 44 | #include <asm/spec-ctrl.h> |
577d5cd7 | 45 | #include <asm/io_bitmap.h> |
89f579ce | 46 | #include <asm/proto.h> |
6f9885a3 | 47 | #include <asm/frame.h> |
5d1ceb39 | 48 | #include <asm/unwind.h> |
bfe6ed0c | 49 | #include <asm/tdx.h> |
90e24014 | 50 | |
ff16701a TG |
51 | #include "process.h" |
52 | ||
45046892 TG |
53 | /* |
54 | * per-CPU TSS segments. Threads are completely 'soft' on Linux, | |
55 | * no more per-task TSS's. The TSS size is kept cacheline-aligned | |
56 | * so they are allowed to end up in the .data..cacheline_aligned | |
57 | * section. Since TSS's are completely CPU-local, we want them | |
58 | * on exact cacheline boundaries, to eliminate cacheline ping-pong. | |
59 | */ | |
2fd9c41a | 60 | __visible DEFINE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw) = { |
d0a0de21 | 61 | .x86_tss = { |
20bb8344 AL |
62 | /* |
63 | * .sp0 is only used when entering ring 0 from a lower | |
64 | * privilege level. Since the init task never runs anything | |
65 | * but ring 0 code, there is no need for a valid value here. | |
66 | * Poison it. | |
67 | */ | |
68 | .sp0 = (1UL << (BITS_PER_LONG-1)) + 1, | |
9aaefe7b | 69 | |
1591584e | 70 | #ifdef CONFIG_X86_32 |
9aaefe7b | 71 | .sp1 = TOP_OF_INIT_STACK, |
9aaefe7b | 72 | |
d0a0de21 AL |
73 | .ss0 = __KERNEL_DS, |
74 | .ss1 = __KERNEL_CS, | |
d0a0de21 | 75 | #endif |
ecc7e37d | 76 | .io_bitmap_base = IO_BITMAP_OFFSET_INVALID, |
d0a0de21 | 77 | }, |
d0a0de21 | 78 | }; |
c482feef | 79 | EXPORT_PER_CPU_SYMBOL(cpu_tss_rw); |
45046892 | 80 | |
b7ceaec1 AL |
81 | DEFINE_PER_CPU(bool, __tss_limit_invalid); |
82 | EXPORT_PER_CPU_SYMBOL_GPL(__tss_limit_invalid); | |
b7ffc44d | 83 | |
55ccf3fe SS |
84 | /* |
85 | * this gets called so that we can store lazy state into memory and copy the | |
86 | * current task into the new thread. | |
87 | */ | |
61c4628b SS |
88 | int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) |
89 | { | |
5aaeb5c0 | 90 | memcpy(dst, src, arch_task_struct_size); |
2459ee86 AL |
91 | #ifdef CONFIG_VM86 |
92 | dst->thread.vm86 = NULL; | |
93 | #endif | |
f0cbc8b3 TG |
94 | /* Drop the copied pointer to current's fpstate */ |
95 | dst->thread.fpu.fpstate = NULL; | |
500afbf6 | 96 | |
2d16a187 | 97 | return 0; |
61c4628b | 98 | } |
7f424a8b | 99 | |
500afbf6 CB |
100 | #ifdef CONFIG_X86_64 |
101 | void arch_release_task_struct(struct task_struct *tsk) | |
102 | { | |
103 | if (fpu_state_size_dynamic()) | |
104 | fpstate_free(&tsk->thread.fpu); | |
61c4628b | 105 | } |
500afbf6 | 106 | #endif |
7f424a8b | 107 | |
389d1fb1 | 108 | /* |
4bfe6cce | 109 | * Free thread data structures etc.. |
389d1fb1 | 110 | */ |
e6464694 | 111 | void exit_thread(struct task_struct *tsk) |
389d1fb1 | 112 | { |
e6464694 | 113 | struct thread_struct *t = &tsk->thread; |
ca6787ba | 114 | struct fpu *fpu = &t->fpu; |
ea5f1cd7 TG |
115 | |
116 | if (test_thread_flag(TIF_IO_BITMAP)) | |
4bfe6cce | 117 | io_bitmap_exit(tsk); |
1dcc8d7b | 118 | |
9fda6a06 BG |
119 | free_vm86(t); |
120 | ||
50338615 | 121 | fpu__drop(fpu); |
389d1fb1 JF |
122 | } |
123 | ||
2fff071d TG |
124 | static int set_new_tls(struct task_struct *p, unsigned long tls) |
125 | { | |
126 | struct user_desc __user *utls = (struct user_desc __user *)tls; | |
127 | ||
128 | if (in_ia32_syscall()) | |
129 | return do_set_thread_area(p, -1, utls, 0); | |
130 | else | |
131 | return do_set_thread_area_64(p, ARCH_SET_FS, tls); | |
132 | } | |
133 | ||
c5febea0 | 134 | int copy_thread(struct task_struct *p, const struct kernel_clone_args *args) |
2fff071d | 135 | { |
c5febea0 EB |
136 | unsigned long clone_flags = args->flags; |
137 | unsigned long sp = args->stack; | |
c5febea0 | 138 | unsigned long tls = args->tls; |
2fff071d TG |
139 | struct inactive_task_frame *frame; |
140 | struct fork_frame *fork_frame; | |
141 | struct pt_regs *childregs; | |
4804e382 | 142 | int ret = 0; |
2fff071d TG |
143 | |
144 | childregs = task_pt_regs(p); | |
145 | fork_frame = container_of(childregs, struct fork_frame, regs); | |
146 | frame = &fork_frame->frame; | |
147 | ||
6f9885a3 | 148 | frame->bp = encode_frame_pointer(childregs); |
2fff071d TG |
149 | frame->ret_addr = (unsigned long) ret_from_fork; |
150 | p->thread.sp = (unsigned long) fork_frame; | |
577d5cd7 | 151 | p->thread.io_bitmap = NULL; |
b968e84b | 152 | p->thread.iopl_warn = 0; |
2fff071d TG |
153 | memset(p->thread.ptrace_bps, 0, sizeof(p->thread.ptrace_bps)); |
154 | ||
155 | #ifdef CONFIG_X86_64 | |
005f141e CB |
156 | current_save_fsgs(); |
157 | p->thread.fsindex = current->thread.fsindex; | |
158 | p->thread.fsbase = current->thread.fsbase; | |
159 | p->thread.gsindex = current->thread.gsindex; | |
160 | p->thread.gsbase = current->thread.gsbase; | |
161 | ||
2fff071d TG |
162 | savesegment(es, p->thread.es); |
163 | savesegment(ds, p->thread.ds); | |
164 | #else | |
165 | p->thread.sp0 = (unsigned long) (childregs + 1); | |
3a24a608 | 166 | savesegment(gs, p->thread.gs); |
2fff071d TG |
167 | /* |
168 | * Clear all status flags including IF and set fixed bit. 64bit | |
169 | * does not have this initialization as the frame does not contain | |
170 | * flags. The flags consistency (especially vs. AC) is there | |
171 | * ensured via objtool, which lacks 32bit support. | |
172 | */ | |
173 | frame->flags = X86_EFLAGS_FIXED; | |
174 | #endif | |
175 | ||
5bd2e97c | 176 | fpu_clone(p, clone_flags, args->fn); |
2d16a187 | 177 | |
2fff071d | 178 | /* Kernel thread ? */ |
50b7b6f2 | 179 | if (unlikely(p->flags & PF_KTHREAD)) { |
9782a712 | 180 | p->thread.pkru = pkru_get_init_value(); |
2fff071d | 181 | memset(childregs, 0, sizeof(struct pt_regs)); |
5bd2e97c | 182 | kthread_frame_init(frame, args->fn, args->fn_arg); |
2fff071d TG |
183 | return 0; |
184 | } | |
185 | ||
9782a712 DH |
186 | /* |
187 | * Clone current's PKRU value from hardware. tsk->thread.pkru | |
188 | * is only valid when scheduled out. | |
189 | */ | |
190 | p->thread.pkru = read_pkru(); | |
191 | ||
2fff071d TG |
192 | frame->bx = 0; |
193 | *childregs = *current_pt_regs(); | |
194 | childregs->ax = 0; | |
195 | if (sp) | |
196 | childregs->sp = sp; | |
197 | ||
5bd2e97c | 198 | if (unlikely(args->fn)) { |
50b7b6f2 | 199 | /* |
5bd2e97c EB |
200 | * A user space thread, but it doesn't return to |
201 | * ret_after_fork(). | |
50b7b6f2 SM |
202 | * |
203 | * In order to indicate that to tools like gdb, | |
204 | * we reset the stack and instruction pointers. | |
205 | * | |
206 | * It does the same kernel frame setup to return to a kernel | |
207 | * function that a kernel thread does. | |
208 | */ | |
209 | childregs->sp = 0; | |
210 | childregs->ip = 0; | |
5bd2e97c | 211 | kthread_frame_init(frame, args->fn, args->fn_arg); |
50b7b6f2 SM |
212 | return 0; |
213 | } | |
214 | ||
2fff071d | 215 | /* Set a new TLS for the child thread? */ |
4804e382 | 216 | if (clone_flags & CLONE_SETTLS) |
2fff071d | 217 | ret = set_new_tls(p, tls); |
4804e382 TG |
218 | |
219 | if (!ret && unlikely(test_tsk_thread_flag(current, TIF_IO_BITMAP))) | |
220 | io_bitmap_share(p); | |
221 | ||
2fff071d TG |
222 | return ret; |
223 | } | |
224 | ||
33344368 AL |
225 | static void pkru_flush_thread(void) |
226 | { | |
227 | /* | |
228 | * If PKRU is enabled the default PKRU value has to be loaded into | |
229 | * the hardware right here (similar to context switch). | |
230 | */ | |
231 | pkru_write_default(); | |
232 | } | |
233 | ||
389d1fb1 JF |
234 | void flush_thread(void) |
235 | { | |
236 | struct task_struct *tsk = current; | |
237 | ||
24f1e32c | 238 | flush_ptrace_hw_breakpoint(tsk); |
389d1fb1 | 239 | memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array)); |
110d7f75 | 240 | |
e7ecad17 | 241 | fpu_flush_thread(); |
33344368 | 242 | pkru_flush_thread(); |
389d1fb1 JF |
243 | } |
244 | ||
389d1fb1 JF |
245 | void disable_TSC(void) |
246 | { | |
247 | preempt_disable(); | |
248 | if (!test_and_set_thread_flag(TIF_NOTSC)) | |
249 | /* | |
250 | * Must flip the CPU state synchronously with | |
251 | * TIF_NOTSC in the current running context. | |
252 | */ | |
5a920155 | 253 | cr4_set_bits(X86_CR4_TSD); |
389d1fb1 JF |
254 | preempt_enable(); |
255 | } | |
256 | ||
389d1fb1 JF |
257 | static void enable_TSC(void) |
258 | { | |
259 | preempt_disable(); | |
260 | if (test_and_clear_thread_flag(TIF_NOTSC)) | |
261 | /* | |
262 | * Must flip the CPU state synchronously with | |
263 | * TIF_NOTSC in the current running context. | |
264 | */ | |
5a920155 | 265 | cr4_clear_bits(X86_CR4_TSD); |
389d1fb1 JF |
266 | preempt_enable(); |
267 | } | |
268 | ||
269 | int get_tsc_mode(unsigned long adr) | |
270 | { | |
271 | unsigned int val; | |
272 | ||
273 | if (test_thread_flag(TIF_NOTSC)) | |
274 | val = PR_TSC_SIGSEGV; | |
275 | else | |
276 | val = PR_TSC_ENABLE; | |
277 | ||
278 | return put_user(val, (unsigned int __user *)adr); | |
279 | } | |
280 | ||
281 | int set_tsc_mode(unsigned int val) | |
282 | { | |
283 | if (val == PR_TSC_SIGSEGV) | |
284 | disable_TSC(); | |
285 | else if (val == PR_TSC_ENABLE) | |
286 | enable_TSC(); | |
287 | else | |
288 | return -EINVAL; | |
289 | ||
290 | return 0; | |
291 | } | |
292 | ||
e9ea1e7f KH |
293 | DEFINE_PER_CPU(u64, msr_misc_features_shadow); |
294 | ||
295 | static void set_cpuid_faulting(bool on) | |
296 | { | |
297 | u64 msrval; | |
298 | ||
299 | msrval = this_cpu_read(msr_misc_features_shadow); | |
300 | msrval &= ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT; | |
301 | msrval |= (on << MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT); | |
302 | this_cpu_write(msr_misc_features_shadow, msrval); | |
303 | wrmsrl(MSR_MISC_FEATURES_ENABLES, msrval); | |
304 | } | |
305 | ||
306 | static void disable_cpuid(void) | |
307 | { | |
308 | preempt_disable(); | |
309 | if (!test_and_set_thread_flag(TIF_NOCPUID)) { | |
310 | /* | |
311 | * Must flip the CPU state synchronously with | |
312 | * TIF_NOCPUID in the current running context. | |
313 | */ | |
314 | set_cpuid_faulting(true); | |
315 | } | |
316 | preempt_enable(); | |
317 | } | |
318 | ||
319 | static void enable_cpuid(void) | |
320 | { | |
321 | preempt_disable(); | |
322 | if (test_and_clear_thread_flag(TIF_NOCPUID)) { | |
323 | /* | |
324 | * Must flip the CPU state synchronously with | |
325 | * TIF_NOCPUID in the current running context. | |
326 | */ | |
327 | set_cpuid_faulting(false); | |
328 | } | |
329 | preempt_enable(); | |
330 | } | |
331 | ||
332 | static int get_cpuid_mode(void) | |
333 | { | |
334 | return !test_thread_flag(TIF_NOCPUID); | |
335 | } | |
336 | ||
f5c0b4f3 | 337 | static int set_cpuid_mode(unsigned long cpuid_enabled) |
e9ea1e7f | 338 | { |
67e87d43 | 339 | if (!boot_cpu_has(X86_FEATURE_CPUID_FAULT)) |
e9ea1e7f KH |
340 | return -ENODEV; |
341 | ||
342 | if (cpuid_enabled) | |
343 | enable_cpuid(); | |
344 | else | |
345 | disable_cpuid(); | |
346 | ||
347 | return 0; | |
348 | } | |
349 | ||
350 | /* | |
351 | * Called immediately after a successful exec. | |
352 | */ | |
353 | void arch_setup_new_exec(void) | |
354 | { | |
355 | /* If cpuid was previously disabled for this task, re-enable it. */ | |
356 | if (test_thread_flag(TIF_NOCPUID)) | |
357 | enable_cpuid(); | |
71368af9 WL |
358 | |
359 | /* | |
360 | * Don't inherit TIF_SSBD across exec boundary when | |
361 | * PR_SPEC_DISABLE_NOEXEC is used. | |
362 | */ | |
363 | if (test_thread_flag(TIF_SSBD) && | |
364 | task_spec_ssb_noexec(current)) { | |
365 | clear_thread_flag(TIF_SSBD); | |
366 | task_clear_spec_ssb_disable(current); | |
367 | task_clear_spec_ssb_noexec(current); | |
dca99fb6 | 368 | speculation_ctrl_update(read_thread_flags()); |
71368af9 | 369 | } |
e9ea1e7f KH |
370 | } |
371 | ||
111e7b15 | 372 | #ifdef CONFIG_X86_IOPL_IOPERM |
22fe5b04 TG |
373 | static inline void switch_to_bitmap(unsigned long tifp) |
374 | { | |
375 | /* | |
376 | * Invalidate I/O bitmap if the previous task used it. This prevents | |
377 | * any possible leakage of an active I/O bitmap. | |
378 | * | |
379 | * If the next task has an I/O bitmap it will handle it on exit to | |
380 | * user mode. | |
381 | */ | |
382 | if (tifp & _TIF_IO_BITMAP) | |
cadfad87 | 383 | tss_invalidate_io_bitmap(); |
22fe5b04 TG |
384 | } |
385 | ||
386 | static void tss_copy_io_bitmap(struct tss_struct *tss, struct io_bitmap *iobm) | |
060aa16f TG |
387 | { |
388 | /* | |
389 | * Copy at least the byte range of the incoming tasks bitmap which | |
390 | * covers the permitted I/O ports. | |
391 | * | |
392 | * If the previous task which used an I/O bitmap had more bits | |
393 | * permitted, then the copy needs to cover those as well so they | |
394 | * get turned off. | |
395 | */ | |
396 | memcpy(tss->io_bitmap.bitmap, iobm->bitmap, | |
397 | max(tss->io_bitmap.prev_max, iobm->max)); | |
398 | ||
399 | /* | |
400 | * Store the new max and the sequence number of this bitmap | |
401 | * and a pointer to the bitmap itself. | |
402 | */ | |
403 | tss->io_bitmap.prev_max = iobm->max; | |
404 | tss->io_bitmap.prev_sequence = iobm->sequence; | |
405 | } | |
406 | ||
22fe5b04 | 407 | /** |
dbb5ab6d | 408 | * native_tss_update_io_bitmap - Update I/O bitmap before exiting to user mode |
22fe5b04 | 409 | */ |
99bcd4a6 | 410 | void native_tss_update_io_bitmap(void) |
af8b3cd3 | 411 | { |
ff16701a | 412 | struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw); |
7b0b8cfd | 413 | struct thread_struct *t = ¤t->thread; |
c8137ace | 414 | u16 *base = &tss->x86_tss.io_bitmap_base; |
ff16701a | 415 | |
7b0b8cfd | 416 | if (!test_thread_flag(TIF_IO_BITMAP)) { |
cadfad87 | 417 | native_tss_invalidate_io_bitmap(); |
7b0b8cfd BP |
418 | return; |
419 | } | |
420 | ||
421 | if (IS_ENABLED(CONFIG_X86_IOPL_IOPERM) && t->iopl_emul == 3) { | |
422 | *base = IO_BITMAP_OFFSET_VALID_ALL; | |
423 | } else { | |
424 | struct io_bitmap *iobm = t->io_bitmap; | |
425 | ||
af8b3cd3 | 426 | /* |
7b0b8cfd BP |
427 | * Only copy bitmap data when the sequence number differs. The |
428 | * update time is accounted to the incoming task. | |
af8b3cd3 | 429 | */ |
7b0b8cfd BP |
430 | if (tss->io_bitmap.prev_sequence != iobm->sequence) |
431 | tss_copy_io_bitmap(tss, iobm); | |
432 | ||
433 | /* Enable the bitmap */ | |
434 | *base = IO_BITMAP_OFFSET_VALID_MAP; | |
af8b3cd3 | 435 | } |
7b0b8cfd BP |
436 | |
437 | /* | |
438 | * Make sure that the TSS limit is covering the IO bitmap. It might have | |
439 | * been cut down by a VMEXIT to 0x67 which would cause a subsequent I/O | |
440 | * access from user space to trigger a #GP because tbe bitmap is outside | |
441 | * the TSS limit. | |
442 | */ | |
443 | refresh_tss_limit(); | |
af8b3cd3 | 444 | } |
111e7b15 TG |
445 | #else /* CONFIG_X86_IOPL_IOPERM */ |
446 | static inline void switch_to_bitmap(unsigned long tifp) { } | |
447 | #endif | |
af8b3cd3 | 448 | |
1f50ddb4 TG |
449 | #ifdef CONFIG_SMP |
450 | ||
451 | struct ssb_state { | |
452 | struct ssb_state *shared_state; | |
453 | raw_spinlock_t lock; | |
454 | unsigned int disable_state; | |
455 | unsigned long local_state; | |
456 | }; | |
457 | ||
458 | #define LSTATE_SSB 0 | |
459 | ||
460 | static DEFINE_PER_CPU(struct ssb_state, ssb_state); | |
461 | ||
462 | void speculative_store_bypass_ht_init(void) | |
885f82bf | 463 | { |
1f50ddb4 TG |
464 | struct ssb_state *st = this_cpu_ptr(&ssb_state); |
465 | unsigned int this_cpu = smp_processor_id(); | |
466 | unsigned int cpu; | |
467 | ||
468 | st->local_state = 0; | |
469 | ||
470 | /* | |
471 | * Shared state setup happens once on the first bringup | |
472 | * of the CPU. It's not destroyed on CPU hotunplug. | |
473 | */ | |
474 | if (st->shared_state) | |
475 | return; | |
476 | ||
477 | raw_spin_lock_init(&st->lock); | |
478 | ||
479 | /* | |
480 | * Go over HT siblings and check whether one of them has set up the | |
481 | * shared state pointer already. | |
482 | */ | |
483 | for_each_cpu(cpu, topology_sibling_cpumask(this_cpu)) { | |
484 | if (cpu == this_cpu) | |
485 | continue; | |
486 | ||
487 | if (!per_cpu(ssb_state, cpu).shared_state) | |
488 | continue; | |
489 | ||
490 | /* Link it to the state of the sibling: */ | |
491 | st->shared_state = per_cpu(ssb_state, cpu).shared_state; | |
492 | return; | |
493 | } | |
494 | ||
495 | /* | |
496 | * First HT sibling to come up on the core. Link shared state of | |
497 | * the first HT sibling to itself. The siblings on the same core | |
498 | * which come up later will see the shared state pointer and link | |
d9f6e12f | 499 | * themselves to the state of this CPU. |
1f50ddb4 TG |
500 | */ |
501 | st->shared_state = st; | |
502 | } | |
885f82bf | 503 | |
1f50ddb4 TG |
504 | /* |
505 | * Logic is: First HT sibling enables SSBD for both siblings in the core | |
506 | * and last sibling to disable it, disables it for the whole core. This how | |
507 | * MSR_SPEC_CTRL works in "hardware": | |
508 | * | |
509 | * CORE_SPEC_CTRL = THREAD0_SPEC_CTRL | THREAD1_SPEC_CTRL | |
510 | */ | |
511 | static __always_inline void amd_set_core_ssb_state(unsigned long tifn) | |
512 | { | |
513 | struct ssb_state *st = this_cpu_ptr(&ssb_state); | |
514 | u64 msr = x86_amd_ls_cfg_base; | |
515 | ||
516 | if (!static_cpu_has(X86_FEATURE_ZEN)) { | |
517 | msr |= ssbd_tif_to_amd_ls_cfg(tifn); | |
885f82bf | 518 | wrmsrl(MSR_AMD64_LS_CFG, msr); |
1f50ddb4 TG |
519 | return; |
520 | } | |
521 | ||
522 | if (tifn & _TIF_SSBD) { | |
523 | /* | |
524 | * Since this can race with prctl(), block reentry on the | |
525 | * same CPU. | |
526 | */ | |
527 | if (__test_and_set_bit(LSTATE_SSB, &st->local_state)) | |
528 | return; | |
529 | ||
530 | msr |= x86_amd_ls_cfg_ssbd_mask; | |
531 | ||
532 | raw_spin_lock(&st->shared_state->lock); | |
533 | /* First sibling enables SSBD: */ | |
534 | if (!st->shared_state->disable_state) | |
535 | wrmsrl(MSR_AMD64_LS_CFG, msr); | |
536 | st->shared_state->disable_state++; | |
537 | raw_spin_unlock(&st->shared_state->lock); | |
885f82bf | 538 | } else { |
1f50ddb4 TG |
539 | if (!__test_and_clear_bit(LSTATE_SSB, &st->local_state)) |
540 | return; | |
541 | ||
542 | raw_spin_lock(&st->shared_state->lock); | |
543 | st->shared_state->disable_state--; | |
544 | if (!st->shared_state->disable_state) | |
545 | wrmsrl(MSR_AMD64_LS_CFG, msr); | |
546 | raw_spin_unlock(&st->shared_state->lock); | |
885f82bf TG |
547 | } |
548 | } | |
1f50ddb4 TG |
549 | #else |
550 | static __always_inline void amd_set_core_ssb_state(unsigned long tifn) | |
551 | { | |
552 | u64 msr = x86_amd_ls_cfg_base | ssbd_tif_to_amd_ls_cfg(tifn); | |
553 | ||
554 | wrmsrl(MSR_AMD64_LS_CFG, msr); | |
555 | } | |
556 | #endif | |
557 | ||
11fb0683 TL |
558 | static __always_inline void amd_set_ssb_virt_state(unsigned long tifn) |
559 | { | |
560 | /* | |
561 | * SSBD has the same definition in SPEC_CTRL and VIRT_SPEC_CTRL, | |
562 | * so ssbd_tif_to_spec_ctrl() just works. | |
563 | */ | |
564 | wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, ssbd_tif_to_spec_ctrl(tifn)); | |
565 | } | |
566 | ||
01daf568 TC |
567 | /* |
568 | * Update the MSRs managing speculation control, during context switch. | |
569 | * | |
570 | * tifp: Previous task's thread flags | |
571 | * tifn: Next task's thread flags | |
572 | */ | |
573 | static __always_inline void __speculation_ctrl_update(unsigned long tifp, | |
574 | unsigned long tifn) | |
1f50ddb4 | 575 | { |
5bfbe3ad | 576 | unsigned long tif_diff = tifp ^ tifn; |
01daf568 TC |
577 | u64 msr = x86_spec_ctrl_base; |
578 | bool updmsr = false; | |
579 | ||
2f5fb193 TG |
580 | lockdep_assert_irqs_disabled(); |
581 | ||
dbbe2ad0 AS |
582 | /* Handle change of TIF_SSBD depending on the mitigation method. */ |
583 | if (static_cpu_has(X86_FEATURE_VIRT_SSBD)) { | |
584 | if (tif_diff & _TIF_SSBD) | |
01daf568 | 585 | amd_set_ssb_virt_state(tifn); |
dbbe2ad0 AS |
586 | } else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD)) { |
587 | if (tif_diff & _TIF_SSBD) | |
01daf568 | 588 | amd_set_core_ssb_state(tifn); |
dbbe2ad0 AS |
589 | } else if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) || |
590 | static_cpu_has(X86_FEATURE_AMD_SSBD)) { | |
591 | updmsr |= !!(tif_diff & _TIF_SSBD); | |
592 | msr |= ssbd_tif_to_spec_ctrl(tifn); | |
01daf568 | 593 | } |
1f50ddb4 | 594 | |
dbbe2ad0 | 595 | /* Only evaluate TIF_SPEC_IB if conditional STIBP is enabled. */ |
5bfbe3ad TC |
596 | if (IS_ENABLED(CONFIG_SMP) && |
597 | static_branch_unlikely(&switch_to_cond_stibp)) { | |
598 | updmsr |= !!(tif_diff & _TIF_SPEC_IB); | |
599 | msr |= stibp_tif_to_spec_ctrl(tifn); | |
600 | } | |
601 | ||
01daf568 | 602 | if (updmsr) |
c779bc1a | 603 | write_spec_ctrl_current(msr, false); |
1f50ddb4 TG |
604 | } |
605 | ||
6d991ba5 | 606 | static unsigned long speculation_ctrl_update_tif(struct task_struct *tsk) |
1f50ddb4 | 607 | { |
6d991ba5 TG |
608 | if (test_and_clear_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE)) { |
609 | if (task_spec_ssb_disable(tsk)) | |
610 | set_tsk_thread_flag(tsk, TIF_SSBD); | |
611 | else | |
612 | clear_tsk_thread_flag(tsk, TIF_SSBD); | |
9137bb27 TG |
613 | |
614 | if (task_spec_ib_disable(tsk)) | |
615 | set_tsk_thread_flag(tsk, TIF_SPEC_IB); | |
616 | else | |
617 | clear_tsk_thread_flag(tsk, TIF_SPEC_IB); | |
6d991ba5 TG |
618 | } |
619 | /* Return the updated threadinfo flags*/ | |
dca99fb6 | 620 | return read_task_thread_flags(tsk); |
1f50ddb4 | 621 | } |
885f82bf | 622 | |
26c4d75b | 623 | void speculation_ctrl_update(unsigned long tif) |
885f82bf | 624 | { |
2f5fb193 TG |
625 | unsigned long flags; |
626 | ||
01daf568 | 627 | /* Forced update. Make sure all relevant TIF flags are different */ |
2f5fb193 | 628 | local_irq_save(flags); |
01daf568 | 629 | __speculation_ctrl_update(~tif, tif); |
2f5fb193 | 630 | local_irq_restore(flags); |
885f82bf TG |
631 | } |
632 | ||
6d991ba5 TG |
633 | /* Called from seccomp/prctl update */ |
634 | void speculation_ctrl_update_current(void) | |
635 | { | |
636 | preempt_disable(); | |
637 | speculation_ctrl_update(speculation_ctrl_update_tif(current)); | |
638 | preempt_enable(); | |
639 | } | |
640 | ||
d8f0b353 TG |
641 | static inline void cr4_toggle_bits_irqsoff(unsigned long mask) |
642 | { | |
643 | unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4); | |
644 | ||
645 | newval = cr4 ^ mask; | |
646 | if (newval != cr4) { | |
647 | this_cpu_write(cpu_tlbstate.cr4, newval); | |
648 | __write_cr4(newval); | |
649 | } | |
650 | } | |
651 | ||
ff16701a | 652 | void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p) |
389d1fb1 | 653 | { |
af8b3cd3 | 654 | unsigned long tifp, tifn; |
389d1fb1 | 655 | |
dca99fb6 MR |
656 | tifn = read_task_thread_flags(next_p); |
657 | tifp = read_task_thread_flags(prev_p); | |
22fe5b04 TG |
658 | |
659 | switch_to_bitmap(tifp); | |
af8b3cd3 KH |
660 | |
661 | propagate_user_return_notify(prev_p, next_p); | |
662 | ||
b9894a2f KH |
663 | if ((tifp & _TIF_BLOCKSTEP || tifn & _TIF_BLOCKSTEP) && |
664 | arch_has_block_step()) { | |
665 | unsigned long debugctl, msk; | |
ea8e61b7 | 666 | |
b9894a2f | 667 | rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); |
ea8e61b7 | 668 | debugctl &= ~DEBUGCTLMSR_BTF; |
b9894a2f KH |
669 | msk = tifn & _TIF_BLOCKSTEP; |
670 | debugctl |= (msk >> TIF_BLOCKSTEP) << DEBUGCTLMSR_BTF_SHIFT; | |
671 | wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); | |
ea8e61b7 | 672 | } |
389d1fb1 | 673 | |
5a920155 | 674 | if ((tifp ^ tifn) & _TIF_NOTSC) |
9d0b6232 | 675 | cr4_toggle_bits_irqsoff(X86_CR4_TSD); |
e9ea1e7f KH |
676 | |
677 | if ((tifp ^ tifn) & _TIF_NOCPUID) | |
678 | set_cpuid_faulting(!!(tifn & _TIF_NOCPUID)); | |
885f82bf | 679 | |
6d991ba5 TG |
680 | if (likely(!((tifp | tifn) & _TIF_SPEC_FORCE_UPDATE))) { |
681 | __speculation_ctrl_update(tifp, tifn); | |
682 | } else { | |
683 | speculation_ctrl_update_tif(prev_p); | |
684 | tifn = speculation_ctrl_update_tif(next_p); | |
685 | ||
686 | /* Enforce MSR update to ensure consistent state */ | |
687 | __speculation_ctrl_update(~tifn, tifn); | |
688 | } | |
389d1fb1 JF |
689 | } |
690 | ||
00dba564 TG |
691 | /* |
692 | * Idle related variables and functions | |
693 | */ | |
d1896049 | 694 | unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE; |
00dba564 TG |
695 | EXPORT_SYMBOL(boot_option_idle_override); |
696 | ||
a476bda3 | 697 | static void (*x86_idle)(void); |
00dba564 | 698 | |
90e24014 RW |
699 | #ifndef CONFIG_SMP |
700 | static inline void play_dead(void) | |
701 | { | |
702 | BUG(); | |
703 | } | |
704 | #endif | |
705 | ||
7d1a9417 TG |
706 | void arch_cpu_idle_enter(void) |
707 | { | |
6a369583 | 708 | tsc_verify_tsc_adjust(false); |
7d1a9417 | 709 | local_touch_nmi(); |
7d1a9417 | 710 | } |
90e24014 | 711 | |
7d1a9417 TG |
712 | void arch_cpu_idle_dead(void) |
713 | { | |
714 | play_dead(); | |
715 | } | |
90e24014 | 716 | |
7d1a9417 TG |
717 | /* |
718 | * Called from the generic idle code. | |
719 | */ | |
720 | void arch_cpu_idle(void) | |
721 | { | |
16f8b05a | 722 | x86_idle(); |
90e24014 RW |
723 | } |
724 | ||
00dba564 | 725 | /* |
7d1a9417 | 726 | * We use this if we don't have any better idle routine.. |
00dba564 | 727 | */ |
6727ad9e | 728 | void __cpuidle default_idle(void) |
00dba564 | 729 | { |
58c644ba | 730 | raw_safe_halt(); |
00dba564 | 731 | } |
fa86ee90 | 732 | #if defined(CONFIG_APM_MODULE) || defined(CONFIG_HALTPOLL_CPUIDLE_MODULE) |
00dba564 TG |
733 | EXPORT_SYMBOL(default_idle); |
734 | #endif | |
735 | ||
6a377ddc LB |
736 | #ifdef CONFIG_XEN |
737 | bool xen_set_default_idle(void) | |
e5fd47bf | 738 | { |
a476bda3 | 739 | bool ret = !!x86_idle; |
e5fd47bf | 740 | |
a476bda3 | 741 | x86_idle = default_idle; |
e5fd47bf KRW |
742 | |
743 | return ret; | |
744 | } | |
6a377ddc | 745 | #endif |
bba4ed01 | 746 | |
f9cdf7ca | 747 | void __noreturn stop_this_cpu(void *dummy) |
d3ec5cae IV |
748 | { |
749 | local_irq_disable(); | |
750 | /* | |
751 | * Remove this CPU: | |
752 | */ | |
4f062896 | 753 | set_cpu_online(smp_processor_id(), false); |
d3ec5cae | 754 | disable_local_APIC(); |
8838eb6c | 755 | mcheck_cpu_clear(this_cpu_ptr(&cpu_info)); |
d3ec5cae | 756 | |
f23d74f6 TL |
757 | /* |
758 | * Use wbinvd on processors that support SME. This provides support | |
759 | * for performing a successful kexec when going from SME inactive | |
760 | * to SME active (or vice-versa). The cache must be cleared so that | |
761 | * if there are entries with the same physical address, both with and | |
762 | * without the encryption bit, they don't race each other when flushed | |
763 | * and potentially end up with the wrong entry being committed to | |
764 | * memory. | |
08f253ec ML |
765 | * |
766 | * Test the CPUID bit directly because the machine might've cleared | |
767 | * X86_FEATURE_SME due to cmdline options. | |
f23d74f6 | 768 | */ |
08f253ec | 769 | if (cpuid_eax(0x8000001f) & BIT(0)) |
f23d74f6 | 770 | native_wbinvd(); |
bba4ed01 TL |
771 | for (;;) { |
772 | /* | |
f23d74f6 TL |
773 | * Use native_halt() so that memory contents don't change |
774 | * (stack usage and variables) after possibly issuing the | |
775 | * native_wbinvd() above. | |
bba4ed01 | 776 | */ |
f23d74f6 | 777 | native_halt(); |
bba4ed01 | 778 | } |
7f424a8b PZ |
779 | } |
780 | ||
aa276e1c | 781 | /* |
07c94a38 BP |
782 | * AMD Erratum 400 aware idle routine. We handle it the same way as C3 power |
783 | * states (local apic timer and TSC stop). | |
58c644ba PZ |
784 | * |
785 | * XXX this function is completely buggered vs RCU and tracing. | |
aa276e1c | 786 | */ |
02c68a02 | 787 | static void amd_e400_idle(void) |
aa276e1c | 788 | { |
07c94a38 BP |
789 | /* |
790 | * We cannot use static_cpu_has_bug() here because X86_BUG_AMD_APIC_C1E | |
791 | * gets set after static_cpu_has() places have been converted via | |
792 | * alternatives. | |
793 | */ | |
794 | if (!boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) { | |
795 | default_idle(); | |
796 | return; | |
aa276e1c TG |
797 | } |
798 | ||
07c94a38 | 799 | tick_broadcast_enter(); |
aa276e1c | 800 | |
07c94a38 | 801 | default_idle(); |
0beefa20 | 802 | |
07c94a38 BP |
803 | /* |
804 | * The switch back from broadcast mode needs to be called with | |
805 | * interrupts disabled. | |
806 | */ | |
58c644ba | 807 | raw_local_irq_disable(); |
07c94a38 | 808 | tick_broadcast_exit(); |
58c644ba | 809 | raw_local_irq_enable(); |
aa276e1c TG |
810 | } |
811 | ||
b253149b | 812 | /* |
aebef63c WK |
813 | * Prefer MWAIT over HALT if MWAIT is supported, MWAIT_CPUID leaf |
814 | * exists and whenever MONITOR/MWAIT extensions are present there is at | |
815 | * least one C1 substate. | |
b253149b | 816 | * |
aebef63c WK |
817 | * Do not prefer MWAIT if MONITOR instruction has a bug or idle=nomwait |
818 | * is passed to kernel commandline parameter. | |
b253149b LB |
819 | */ |
820 | static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c) | |
821 | { | |
aebef63c WK |
822 | u32 eax, ebx, ecx, edx; |
823 | ||
8bcedb4c WK |
824 | /* User has disallowed the use of MWAIT. Fallback to HALT */ |
825 | if (boot_option_idle_override == IDLE_NOMWAIT) | |
b253149b LB |
826 | return 0; |
827 | ||
aebef63c WK |
828 | /* MWAIT is not supported on this platform. Fallback to HALT */ |
829 | if (!cpu_has(c, X86_FEATURE_MWAIT)) | |
b253149b LB |
830 | return 0; |
831 | ||
aebef63c WK |
832 | /* Monitor has a bug. Fallback to HALT */ |
833 | if (boot_cpu_has_bug(X86_BUG_MONITOR)) | |
b253149b LB |
834 | return 0; |
835 | ||
aebef63c WK |
836 | cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &edx); |
837 | ||
838 | /* | |
839 | * If MWAIT extensions are not available, it is safe to use MWAIT | |
840 | * with EAX=0, ECX=0. | |
841 | */ | |
842 | if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) | |
843 | return 1; | |
844 | ||
845 | /* | |
846 | * If MWAIT extensions are available, there should be at least one | |
847 | * MWAIT C1 substate present. | |
848 | */ | |
849 | return (edx & MWAIT_C1_SUBSTATE_MASK); | |
b253149b LB |
850 | } |
851 | ||
852 | /* | |
0fb0328d HR |
853 | * MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT |
854 | * with interrupts enabled and no flags, which is backwards compatible with the | |
855 | * original MWAIT implementation. | |
b253149b | 856 | */ |
6727ad9e | 857 | static __cpuidle void mwait_idle(void) |
b253149b | 858 | { |
f8e617f4 MG |
859 | if (!current_set_polling_and_test()) { |
860 | if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) { | |
ca59809f | 861 | mb(); /* quirk */ |
b253149b | 862 | clflush((void *)¤t_thread_info()->flags); |
ca59809f | 863 | mb(); /* quirk */ |
f8e617f4 | 864 | } |
b253149b LB |
865 | |
866 | __monitor((void *)¤t_thread_info()->flags, 0, 0); | |
b253149b LB |
867 | if (!need_resched()) |
868 | __sti_mwait(0, 0); | |
869 | else | |
58c644ba | 870 | raw_local_irq_enable(); |
f8e617f4 | 871 | } else { |
58c644ba | 872 | raw_local_irq_enable(); |
f8e617f4 MG |
873 | } |
874 | __current_clr_polling(); | |
b253149b LB |
875 | } |
876 | ||
148f9bb8 | 877 | void select_idle_routine(const struct cpuinfo_x86 *c) |
7f424a8b | 878 | { |
3e5095d1 | 879 | #ifdef CONFIG_SMP |
7d1a9417 | 880 | if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1) |
c767a54b | 881 | pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n"); |
7f424a8b | 882 | #endif |
7d1a9417 | 883 | if (x86_idle || boot_option_idle_override == IDLE_POLL) |
6ddd2a27 TG |
884 | return; |
885 | ||
3344ed30 | 886 | if (boot_cpu_has_bug(X86_BUG_AMD_E400)) { |
c767a54b | 887 | pr_info("using AMD E400 aware idle routine\n"); |
a476bda3 | 888 | x86_idle = amd_e400_idle; |
b253149b LB |
889 | } else if (prefer_mwait_c1_over_halt(c)) { |
890 | pr_info("using mwait in idle threads\n"); | |
891 | x86_idle = mwait_idle; | |
bfe6ed0c KS |
892 | } else if (cpu_feature_enabled(X86_FEATURE_TDX_GUEST)) { |
893 | pr_info("using TDX aware idle routine\n"); | |
894 | x86_idle = tdx_safe_halt; | |
6ddd2a27 | 895 | } else |
a476bda3 | 896 | x86_idle = default_idle; |
7f424a8b PZ |
897 | } |
898 | ||
07c94a38 | 899 | void amd_e400_c1e_apic_setup(void) |
30e1e6d1 | 900 | { |
07c94a38 BP |
901 | if (boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) { |
902 | pr_info("Switch to broadcast mode on CPU%d\n", smp_processor_id()); | |
903 | local_irq_disable(); | |
904 | tick_broadcast_force(); | |
905 | local_irq_enable(); | |
906 | } | |
30e1e6d1 RR |
907 | } |
908 | ||
e7ff3a47 TG |
909 | void __init arch_post_acpi_subsys_init(void) |
910 | { | |
911 | u32 lo, hi; | |
912 | ||
913 | if (!boot_cpu_has_bug(X86_BUG_AMD_E400)) | |
914 | return; | |
915 | ||
916 | /* | |
917 | * AMD E400 detection needs to happen after ACPI has been enabled. If | |
918 | * the machine is affected K8_INTP_C1E_ACTIVE_MASK bits are set in | |
919 | * MSR_K8_INT_PENDING_MSG. | |
920 | */ | |
921 | rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi); | |
922 | if (!(lo & K8_INTP_C1E_ACTIVE_MASK)) | |
923 | return; | |
924 | ||
925 | boot_cpu_set_bug(X86_BUG_AMD_APIC_C1E); | |
926 | ||
927 | if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) | |
928 | mark_tsc_unstable("TSC halt in AMD C1E"); | |
929 | pr_info("System has AMD C1E enabled\n"); | |
930 | } | |
931 | ||
7f424a8b PZ |
932 | static int __init idle_setup(char *str) |
933 | { | |
ab6bc3e3 CG |
934 | if (!str) |
935 | return -EINVAL; | |
936 | ||
7f424a8b | 937 | if (!strcmp(str, "poll")) { |
c767a54b | 938 | pr_info("using polling idle threads\n"); |
d1896049 | 939 | boot_option_idle_override = IDLE_POLL; |
7d1a9417 | 940 | cpu_idle_poll_ctrl(true); |
d1896049 | 941 | } else if (!strcmp(str, "halt")) { |
c1e3b377 ZY |
942 | /* |
943 | * When the boot option of idle=halt is added, halt is | |
944 | * forced to be used for CPU idle. In such case CPU C2/C3 | |
945 | * won't be used again. | |
946 | * To continue to load the CPU idle driver, don't touch | |
947 | * the boot_option_idle_override. | |
948 | */ | |
a476bda3 | 949 | x86_idle = default_idle; |
d1896049 | 950 | boot_option_idle_override = IDLE_HALT; |
da5e09a1 ZY |
951 | } else if (!strcmp(str, "nomwait")) { |
952 | /* | |
953 | * If the boot option of "idle=nomwait" is added, | |
8bcedb4c WK |
954 | * it means that mwait will be disabled for CPU C1/C2/C3 |
955 | * states. | |
da5e09a1 | 956 | */ |
d1896049 | 957 | boot_option_idle_override = IDLE_NOMWAIT; |
c1e3b377 | 958 | } else |
7f424a8b PZ |
959 | return -1; |
960 | ||
7f424a8b PZ |
961 | return 0; |
962 | } | |
963 | early_param("idle", idle_setup); | |
964 | ||
9d62dcdf AW |
965 | unsigned long arch_align_stack(unsigned long sp) |
966 | { | |
967 | if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) | |
81895a65 | 968 | sp -= prandom_u32_max(8192); |
9d62dcdf AW |
969 | return sp & ~0xf; |
970 | } | |
971 | ||
972 | unsigned long arch_randomize_brk(struct mm_struct *mm) | |
973 | { | |
9c6f0902 | 974 | return randomize_page(mm->brk, 0x02000000); |
9d62dcdf AW |
975 | } |
976 | ||
7ba78053 TG |
977 | /* |
978 | * Called from fs/proc with a reference on @p to find the function | |
979 | * which called into schedule(). This needs to be done carefully | |
980 | * because the task might wake up and we might look at a stack | |
981 | * changing under us. | |
982 | */ | |
42a20f86 | 983 | unsigned long __get_wchan(struct task_struct *p) |
7ba78053 | 984 | { |
5d1ceb39 PZ |
985 | struct unwind_state state; |
986 | unsigned long addr = 0; | |
7ba78053 | 987 | |
0dc636b3 PZ |
988 | if (!try_get_task_stack(p)) |
989 | return 0; | |
990 | ||
5d1ceb39 PZ |
991 | for (unwind_start(&state, p, NULL, NULL); !unwind_done(&state); |
992 | unwind_next_frame(&state)) { | |
993 | addr = unwind_get_return_address(&state); | |
994 | if (!addr) | |
995 | break; | |
996 | if (in_sched_functions(addr)) | |
997 | continue; | |
998 | break; | |
999 | } | |
1000 | ||
0dc636b3 PZ |
1001 | put_task_stack(p); |
1002 | ||
5d1ceb39 | 1003 | return addr; |
7ba78053 | 1004 | } |
b0b9b014 | 1005 | |
f5c0b4f3 | 1006 | long do_arch_prctl_common(int option, unsigned long arg2) |
b0b9b014 | 1007 | { |
e9ea1e7f KH |
1008 | switch (option) { |
1009 | case ARCH_GET_CPUID: | |
1010 | return get_cpuid_mode(); | |
1011 | case ARCH_SET_CPUID: | |
f5c0b4f3 | 1012 | return set_cpuid_mode(arg2); |
db8268df CB |
1013 | case ARCH_GET_XCOMP_SUPP: |
1014 | case ARCH_GET_XCOMP_PERM: | |
1015 | case ARCH_REQ_XCOMP_PERM: | |
980fe2fd TG |
1016 | case ARCH_GET_XCOMP_GUEST_PERM: |
1017 | case ARCH_REQ_XCOMP_GUEST_PERM: | |
f5c0b4f3 | 1018 | return fpu_xstate_prctl(option, arg2); |
e9ea1e7f KH |
1019 | } |
1020 | ||
b0b9b014 KH |
1021 | return -EINVAL; |
1022 | } |