Commit | Line | Data |
---|---|---|
c767a54b JP |
1 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
2 | ||
61c4628b SS |
3 | #include <linux/errno.h> |
4 | #include <linux/kernel.h> | |
5 | #include <linux/mm.h> | |
6 | #include <linux/smp.h> | |
389d1fb1 | 7 | #include <linux/prctl.h> |
61c4628b SS |
8 | #include <linux/slab.h> |
9 | #include <linux/sched.h> | |
7f424a8b PZ |
10 | #include <linux/module.h> |
11 | #include <linux/pm.h> | |
aa276e1c | 12 | #include <linux/clockchips.h> |
9d62dcdf | 13 | #include <linux/random.h> |
7c68af6e | 14 | #include <linux/user-return-notifier.h> |
814e2c84 AI |
15 | #include <linux/dmi.h> |
16 | #include <linux/utsname.h> | |
90e24014 RW |
17 | #include <linux/stackprotector.h> |
18 | #include <linux/tick.h> | |
19 | #include <linux/cpuidle.h> | |
61613521 | 20 | #include <trace/events/power.h> |
24f1e32c | 21 | #include <linux/hw_breakpoint.h> |
93789b32 | 22 | #include <asm/cpu.h> |
d3ec5cae | 23 | #include <asm/apic.h> |
2c1b284e | 24 | #include <asm/syscalls.h> |
389d1fb1 JF |
25 | #include <asm/idle.h> |
26 | #include <asm/uaccess.h> | |
27 | #include <asm/i387.h> | |
1361b83a | 28 | #include <asm/fpu-internal.h> |
66cb5917 | 29 | #include <asm/debugreg.h> |
90e24014 | 30 | #include <asm/nmi.h> |
375074cc | 31 | #include <asm/tlbflush.h> |
90e24014 | 32 | |
45046892 TG |
33 | /* |
34 | * per-CPU TSS segments. Threads are completely 'soft' on Linux, | |
35 | * no more per-task TSS's. The TSS size is kept cacheline-aligned | |
36 | * so they are allowed to end up in the .data..cacheline_aligned | |
37 | * section. Since TSS's are completely CPU-local, we want them | |
38 | * on exact cacheline boundaries, to eliminate cacheline ping-pong. | |
39 | */ | |
277d5b40 | 40 | __visible DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss) = INIT_TSS; |
45046892 | 41 | |
90e24014 RW |
42 | #ifdef CONFIG_X86_64 |
43 | static DEFINE_PER_CPU(unsigned char, is_idle); | |
44 | static ATOMIC_NOTIFIER_HEAD(idle_notifier); | |
45 | ||
46 | void idle_notifier_register(struct notifier_block *n) | |
47 | { | |
48 | atomic_notifier_chain_register(&idle_notifier, n); | |
49 | } | |
50 | EXPORT_SYMBOL_GPL(idle_notifier_register); | |
51 | ||
52 | void idle_notifier_unregister(struct notifier_block *n) | |
53 | { | |
54 | atomic_notifier_chain_unregister(&idle_notifier, n); | |
55 | } | |
56 | EXPORT_SYMBOL_GPL(idle_notifier_unregister); | |
57 | #endif | |
c1e3b377 | 58 | |
aa283f49 | 59 | struct kmem_cache *task_xstate_cachep; |
5ee481da | 60 | EXPORT_SYMBOL_GPL(task_xstate_cachep); |
61c4628b | 61 | |
55ccf3fe SS |
62 | /* |
63 | * this gets called so that we can store lazy state into memory and copy the | |
64 | * current task into the new thread. | |
65 | */ | |
61c4628b SS |
66 | int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) |
67 | { | |
68 | *dst = *src; | |
f1853505 | 69 | |
dc56c0f9 | 70 | dst->thread.fpu_counter = 0; |
5e23fee2 | 71 | dst->thread.fpu.has_fpu = 0; |
5e23fee2 | 72 | dst->thread.fpu.state = NULL; |
6a5fe895 | 73 | task_disable_lazy_fpu_restore(dst); |
f1853505 ON |
74 | if (tsk_used_math(src)) { |
75 | int err = fpu_alloc(&dst->thread.fpu); | |
76 | if (err) | |
77 | return err; | |
304bceda | 78 | fpu_copy(dst, src); |
aa283f49 | 79 | } |
61c4628b SS |
80 | return 0; |
81 | } | |
82 | ||
aa283f49 | 83 | void free_thread_xstate(struct task_struct *tsk) |
61c4628b | 84 | { |
86603283 | 85 | fpu_free(&tsk->thread.fpu); |
aa283f49 SS |
86 | } |
87 | ||
38e7c572 | 88 | void arch_release_task_struct(struct task_struct *tsk) |
aa283f49 | 89 | { |
38e7c572 | 90 | free_thread_xstate(tsk); |
61c4628b SS |
91 | } |
92 | ||
93 | void arch_task_cache_init(void) | |
94 | { | |
95 | task_xstate_cachep = | |
96 | kmem_cache_create("task_xstate", xstate_size, | |
97 | __alignof__(union thread_xstate), | |
2dff4405 | 98 | SLAB_PANIC | SLAB_NOTRACK, NULL); |
7496d645 | 99 | setup_xstate_comp(); |
61c4628b | 100 | } |
7f424a8b | 101 | |
389d1fb1 JF |
102 | /* |
103 | * Free current thread data structures etc.. | |
104 | */ | |
105 | void exit_thread(void) | |
106 | { | |
107 | struct task_struct *me = current; | |
108 | struct thread_struct *t = &me->thread; | |
250981e6 | 109 | unsigned long *bp = t->io_bitmap_ptr; |
389d1fb1 | 110 | |
250981e6 | 111 | if (bp) { |
389d1fb1 JF |
112 | struct tss_struct *tss = &per_cpu(init_tss, get_cpu()); |
113 | ||
389d1fb1 JF |
114 | t->io_bitmap_ptr = NULL; |
115 | clear_thread_flag(TIF_IO_BITMAP); | |
116 | /* | |
117 | * Careful, clear this in the TSS too: | |
118 | */ | |
119 | memset(tss->io_bitmap, 0xff, t->io_bitmap_max); | |
120 | t->io_bitmap_max = 0; | |
121 | put_cpu(); | |
250981e6 | 122 | kfree(bp); |
389d1fb1 | 123 | } |
1dcc8d7b SS |
124 | |
125 | drop_fpu(me); | |
389d1fb1 JF |
126 | } |
127 | ||
128 | void flush_thread(void) | |
129 | { | |
130 | struct task_struct *tsk = current; | |
131 | ||
24f1e32c | 132 | flush_ptrace_hw_breakpoint(tsk); |
389d1fb1 | 133 | memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array)); |
110d7f75 | 134 | |
304bceda SS |
135 | drop_init_fpu(tsk); |
136 | /* | |
137 | * Free the FPU state for non xsave platforms. They get reallocated | |
138 | * lazily at the first use. | |
139 | */ | |
5d2bd700 | 140 | if (!use_eager_fpu()) |
304bceda | 141 | free_thread_xstate(tsk); |
110d7f75 ON |
142 | else if (!used_math()) { |
143 | /* kthread execs. TODO: cleanup this horror. */ | |
144 | if (WARN_ON(init_fpu(current))) | |
145 | force_sig(SIGKILL, current); | |
9cb6ce82 ON |
146 | user_fpu_begin(); |
147 | restore_init_xstate(); | |
110d7f75 | 148 | } |
389d1fb1 JF |
149 | } |
150 | ||
151 | static void hard_disable_TSC(void) | |
152 | { | |
375074cc | 153 | cr4_set_bits(X86_CR4_TSD); |
389d1fb1 JF |
154 | } |
155 | ||
156 | void disable_TSC(void) | |
157 | { | |
158 | preempt_disable(); | |
159 | if (!test_and_set_thread_flag(TIF_NOTSC)) | |
160 | /* | |
161 | * Must flip the CPU state synchronously with | |
162 | * TIF_NOTSC in the current running context. | |
163 | */ | |
164 | hard_disable_TSC(); | |
165 | preempt_enable(); | |
166 | } | |
167 | ||
168 | static void hard_enable_TSC(void) | |
169 | { | |
375074cc | 170 | cr4_clear_bits(X86_CR4_TSD); |
389d1fb1 JF |
171 | } |
172 | ||
173 | static void enable_TSC(void) | |
174 | { | |
175 | preempt_disable(); | |
176 | if (test_and_clear_thread_flag(TIF_NOTSC)) | |
177 | /* | |
178 | * Must flip the CPU state synchronously with | |
179 | * TIF_NOTSC in the current running context. | |
180 | */ | |
181 | hard_enable_TSC(); | |
182 | preempt_enable(); | |
183 | } | |
184 | ||
185 | int get_tsc_mode(unsigned long adr) | |
186 | { | |
187 | unsigned int val; | |
188 | ||
189 | if (test_thread_flag(TIF_NOTSC)) | |
190 | val = PR_TSC_SIGSEGV; | |
191 | else | |
192 | val = PR_TSC_ENABLE; | |
193 | ||
194 | return put_user(val, (unsigned int __user *)adr); | |
195 | } | |
196 | ||
197 | int set_tsc_mode(unsigned int val) | |
198 | { | |
199 | if (val == PR_TSC_SIGSEGV) | |
200 | disable_TSC(); | |
201 | else if (val == PR_TSC_ENABLE) | |
202 | enable_TSC(); | |
203 | else | |
204 | return -EINVAL; | |
205 | ||
206 | return 0; | |
207 | } | |
208 | ||
209 | void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p, | |
210 | struct tss_struct *tss) | |
211 | { | |
212 | struct thread_struct *prev, *next; | |
213 | ||
214 | prev = &prev_p->thread; | |
215 | next = &next_p->thread; | |
216 | ||
ea8e61b7 PZ |
217 | if (test_tsk_thread_flag(prev_p, TIF_BLOCKSTEP) ^ |
218 | test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) { | |
219 | unsigned long debugctl = get_debugctlmsr(); | |
220 | ||
221 | debugctl &= ~DEBUGCTLMSR_BTF; | |
222 | if (test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) | |
223 | debugctl |= DEBUGCTLMSR_BTF; | |
224 | ||
225 | update_debugctlmsr(debugctl); | |
226 | } | |
389d1fb1 | 227 | |
389d1fb1 JF |
228 | if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^ |
229 | test_tsk_thread_flag(next_p, TIF_NOTSC)) { | |
230 | /* prev and next are different */ | |
231 | if (test_tsk_thread_flag(next_p, TIF_NOTSC)) | |
232 | hard_disable_TSC(); | |
233 | else | |
234 | hard_enable_TSC(); | |
235 | } | |
236 | ||
237 | if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) { | |
238 | /* | |
239 | * Copy the relevant range of the IO bitmap. | |
240 | * Normally this is 128 bytes or less: | |
241 | */ | |
242 | memcpy(tss->io_bitmap, next->io_bitmap_ptr, | |
243 | max(prev->io_bitmap_max, next->io_bitmap_max)); | |
244 | } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) { | |
245 | /* | |
246 | * Clear any possible leftover bits: | |
247 | */ | |
248 | memset(tss->io_bitmap, 0xff, prev->io_bitmap_max); | |
249 | } | |
7c68af6e | 250 | propagate_user_return_notify(prev_p, next_p); |
389d1fb1 JF |
251 | } |
252 | ||
00dba564 TG |
253 | /* |
254 | * Idle related variables and functions | |
255 | */ | |
d1896049 | 256 | unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE; |
00dba564 TG |
257 | EXPORT_SYMBOL(boot_option_idle_override); |
258 | ||
a476bda3 | 259 | static void (*x86_idle)(void); |
00dba564 | 260 | |
90e24014 RW |
261 | #ifndef CONFIG_SMP |
262 | static inline void play_dead(void) | |
263 | { | |
264 | BUG(); | |
265 | } | |
266 | #endif | |
267 | ||
268 | #ifdef CONFIG_X86_64 | |
269 | void enter_idle(void) | |
270 | { | |
c6ae41e7 | 271 | this_cpu_write(is_idle, 1); |
90e24014 RW |
272 | atomic_notifier_call_chain(&idle_notifier, IDLE_START, NULL); |
273 | } | |
274 | ||
275 | static void __exit_idle(void) | |
276 | { | |
277 | if (x86_test_and_clear_bit_percpu(0, is_idle) == 0) | |
278 | return; | |
279 | atomic_notifier_call_chain(&idle_notifier, IDLE_END, NULL); | |
280 | } | |
281 | ||
282 | /* Called from interrupts to signify idle end */ | |
283 | void exit_idle(void) | |
284 | { | |
285 | /* idle loop has pid 0 */ | |
286 | if (current->pid) | |
287 | return; | |
288 | __exit_idle(); | |
289 | } | |
290 | #endif | |
291 | ||
7d1a9417 TG |
292 | void arch_cpu_idle_enter(void) |
293 | { | |
294 | local_touch_nmi(); | |
295 | enter_idle(); | |
296 | } | |
90e24014 | 297 | |
7d1a9417 TG |
298 | void arch_cpu_idle_exit(void) |
299 | { | |
300 | __exit_idle(); | |
301 | } | |
90e24014 | 302 | |
7d1a9417 TG |
303 | void arch_cpu_idle_dead(void) |
304 | { | |
305 | play_dead(); | |
306 | } | |
90e24014 | 307 | |
7d1a9417 TG |
308 | /* |
309 | * Called from the generic idle code. | |
310 | */ | |
311 | void arch_cpu_idle(void) | |
312 | { | |
16f8b05a | 313 | x86_idle(); |
90e24014 RW |
314 | } |
315 | ||
00dba564 | 316 | /* |
7d1a9417 | 317 | * We use this if we don't have any better idle routine.. |
00dba564 TG |
318 | */ |
319 | void default_idle(void) | |
320 | { | |
4d0e42cc | 321 | trace_cpu_idle_rcuidle(1, smp_processor_id()); |
7d1a9417 | 322 | safe_halt(); |
4d0e42cc | 323 | trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id()); |
00dba564 | 324 | } |
60b8b1de | 325 | #ifdef CONFIG_APM_MODULE |
00dba564 TG |
326 | EXPORT_SYMBOL(default_idle); |
327 | #endif | |
328 | ||
6a377ddc LB |
329 | #ifdef CONFIG_XEN |
330 | bool xen_set_default_idle(void) | |
e5fd47bf | 331 | { |
a476bda3 | 332 | bool ret = !!x86_idle; |
e5fd47bf | 333 | |
a476bda3 | 334 | x86_idle = default_idle; |
e5fd47bf KRW |
335 | |
336 | return ret; | |
337 | } | |
6a377ddc | 338 | #endif |
d3ec5cae IV |
339 | void stop_this_cpu(void *dummy) |
340 | { | |
341 | local_irq_disable(); | |
342 | /* | |
343 | * Remove this CPU: | |
344 | */ | |
4f062896 | 345 | set_cpu_online(smp_processor_id(), false); |
d3ec5cae IV |
346 | disable_local_APIC(); |
347 | ||
27be4570 LB |
348 | for (;;) |
349 | halt(); | |
7f424a8b PZ |
350 | } |
351 | ||
02c68a02 LB |
352 | bool amd_e400_c1e_detected; |
353 | EXPORT_SYMBOL(amd_e400_c1e_detected); | |
aa276e1c | 354 | |
02c68a02 | 355 | static cpumask_var_t amd_e400_c1e_mask; |
4faac97d | 356 | |
02c68a02 | 357 | void amd_e400_remove_cpu(int cpu) |
4faac97d | 358 | { |
02c68a02 LB |
359 | if (amd_e400_c1e_mask != NULL) |
360 | cpumask_clear_cpu(cpu, amd_e400_c1e_mask); | |
4faac97d TG |
361 | } |
362 | ||
aa276e1c | 363 | /* |
02c68a02 | 364 | * AMD Erratum 400 aware idle routine. We check for C1E active in the interrupt |
aa276e1c TG |
365 | * pending message MSR. If we detect C1E, then we handle it the same |
366 | * way as C3 power states (local apic timer and TSC stop) | |
367 | */ | |
02c68a02 | 368 | static void amd_e400_idle(void) |
aa276e1c | 369 | { |
02c68a02 | 370 | if (!amd_e400_c1e_detected) { |
aa276e1c TG |
371 | u32 lo, hi; |
372 | ||
373 | rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi); | |
e8c534ec | 374 | |
aa276e1c | 375 | if (lo & K8_INTP_C1E_ACTIVE_MASK) { |
02c68a02 | 376 | amd_e400_c1e_detected = true; |
40fb1715 | 377 | if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) |
09bfeea1 | 378 | mark_tsc_unstable("TSC halt in AMD C1E"); |
c767a54b | 379 | pr_info("System has AMD C1E enabled\n"); |
aa276e1c TG |
380 | } |
381 | } | |
382 | ||
02c68a02 | 383 | if (amd_e400_c1e_detected) { |
aa276e1c TG |
384 | int cpu = smp_processor_id(); |
385 | ||
02c68a02 LB |
386 | if (!cpumask_test_cpu(cpu, amd_e400_c1e_mask)) { |
387 | cpumask_set_cpu(cpu, amd_e400_c1e_mask); | |
0beefa20 | 388 | /* |
f833bab8 | 389 | * Force broadcast so ACPI can not interfere. |
0beefa20 | 390 | */ |
aa276e1c TG |
391 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE, |
392 | &cpu); | |
c767a54b | 393 | pr_info("Switch to broadcast mode on CPU%d\n", cpu); |
aa276e1c TG |
394 | } |
395 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu); | |
0beefa20 | 396 | |
aa276e1c | 397 | default_idle(); |
0beefa20 TG |
398 | |
399 | /* | |
400 | * The switch back from broadcast mode needs to be | |
401 | * called with interrupts disabled. | |
402 | */ | |
ea811747 PZ |
403 | local_irq_disable(); |
404 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu); | |
405 | local_irq_enable(); | |
aa276e1c TG |
406 | } else |
407 | default_idle(); | |
408 | } | |
409 | ||
148f9bb8 | 410 | void select_idle_routine(const struct cpuinfo_x86 *c) |
7f424a8b | 411 | { |
3e5095d1 | 412 | #ifdef CONFIG_SMP |
7d1a9417 | 413 | if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1) |
c767a54b | 414 | pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n"); |
7f424a8b | 415 | #endif |
7d1a9417 | 416 | if (x86_idle || boot_option_idle_override == IDLE_POLL) |
6ddd2a27 TG |
417 | return; |
418 | ||
7d7dc116 | 419 | if (cpu_has_bug(c, X86_BUG_AMD_APIC_C1E)) { |
9d8888c2 | 420 | /* E400: APIC timer interrupt does not wake up CPU from C1e */ |
c767a54b | 421 | pr_info("using AMD E400 aware idle routine\n"); |
a476bda3 | 422 | x86_idle = amd_e400_idle; |
6ddd2a27 | 423 | } else |
a476bda3 | 424 | x86_idle = default_idle; |
7f424a8b PZ |
425 | } |
426 | ||
02c68a02 | 427 | void __init init_amd_e400_c1e_mask(void) |
30e1e6d1 | 428 | { |
02c68a02 | 429 | /* If we're using amd_e400_idle, we need to allocate amd_e400_c1e_mask. */ |
a476bda3 | 430 | if (x86_idle == amd_e400_idle) |
02c68a02 | 431 | zalloc_cpumask_var(&amd_e400_c1e_mask, GFP_KERNEL); |
30e1e6d1 RR |
432 | } |
433 | ||
7f424a8b PZ |
434 | static int __init idle_setup(char *str) |
435 | { | |
ab6bc3e3 CG |
436 | if (!str) |
437 | return -EINVAL; | |
438 | ||
7f424a8b | 439 | if (!strcmp(str, "poll")) { |
c767a54b | 440 | pr_info("using polling idle threads\n"); |
d1896049 | 441 | boot_option_idle_override = IDLE_POLL; |
7d1a9417 | 442 | cpu_idle_poll_ctrl(true); |
d1896049 | 443 | } else if (!strcmp(str, "halt")) { |
c1e3b377 ZY |
444 | /* |
445 | * When the boot option of idle=halt is added, halt is | |
446 | * forced to be used for CPU idle. In such case CPU C2/C3 | |
447 | * won't be used again. | |
448 | * To continue to load the CPU idle driver, don't touch | |
449 | * the boot_option_idle_override. | |
450 | */ | |
a476bda3 | 451 | x86_idle = default_idle; |
d1896049 | 452 | boot_option_idle_override = IDLE_HALT; |
da5e09a1 ZY |
453 | } else if (!strcmp(str, "nomwait")) { |
454 | /* | |
455 | * If the boot option of "idle=nomwait" is added, | |
456 | * it means that mwait will be disabled for CPU C2/C3 | |
457 | * states. In such case it won't touch the variable | |
458 | * of boot_option_idle_override. | |
459 | */ | |
d1896049 | 460 | boot_option_idle_override = IDLE_NOMWAIT; |
c1e3b377 | 461 | } else |
7f424a8b PZ |
462 | return -1; |
463 | ||
7f424a8b PZ |
464 | return 0; |
465 | } | |
466 | early_param("idle", idle_setup); | |
467 | ||
9d62dcdf AW |
468 | unsigned long arch_align_stack(unsigned long sp) |
469 | { | |
470 | if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) | |
471 | sp -= get_random_int() % 8192; | |
472 | return sp & ~0xf; | |
473 | } | |
474 | ||
475 | unsigned long arch_randomize_brk(struct mm_struct *mm) | |
476 | { | |
477 | unsigned long range_end = mm->brk + 0x02000000; | |
478 | return randomize_range(mm->brk, range_end, 0) ? : mm->brk; | |
479 | } | |
480 |