Commit | Line | Data |
---|---|---|
c767a54b JP |
1 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
2 | ||
61c4628b SS |
3 | #include <linux/errno.h> |
4 | #include <linux/kernel.h> | |
5 | #include <linux/mm.h> | |
6 | #include <linux/smp.h> | |
389d1fb1 | 7 | #include <linux/prctl.h> |
61c4628b SS |
8 | #include <linux/slab.h> |
9 | #include <linux/sched.h> | |
4c822698 | 10 | #include <linux/sched/idle.h> |
b17b0153 | 11 | #include <linux/sched/debug.h> |
29930025 | 12 | #include <linux/sched/task.h> |
68db0cf1 | 13 | #include <linux/sched/task_stack.h> |
186f4360 PG |
14 | #include <linux/init.h> |
15 | #include <linux/export.h> | |
7f424a8b | 16 | #include <linux/pm.h> |
162a688e | 17 | #include <linux/tick.h> |
9d62dcdf | 18 | #include <linux/random.h> |
7c68af6e | 19 | #include <linux/user-return-notifier.h> |
814e2c84 AI |
20 | #include <linux/dmi.h> |
21 | #include <linux/utsname.h> | |
90e24014 RW |
22 | #include <linux/stackprotector.h> |
23 | #include <linux/tick.h> | |
24 | #include <linux/cpuidle.h> | |
61613521 | 25 | #include <trace/events/power.h> |
24f1e32c | 26 | #include <linux/hw_breakpoint.h> |
93789b32 | 27 | #include <asm/cpu.h> |
d3ec5cae | 28 | #include <asm/apic.h> |
2c1b284e | 29 | #include <asm/syscalls.h> |
7c0f6ba6 | 30 | #include <linux/uaccess.h> |
b253149b | 31 | #include <asm/mwait.h> |
78f7f1e5 | 32 | #include <asm/fpu/internal.h> |
66cb5917 | 33 | #include <asm/debugreg.h> |
90e24014 | 34 | #include <asm/nmi.h> |
375074cc | 35 | #include <asm/tlbflush.h> |
8838eb6c | 36 | #include <asm/mce.h> |
9fda6a06 | 37 | #include <asm/vm86.h> |
7b32aead | 38 | #include <asm/switch_to.h> |
b7ffc44d | 39 | #include <asm/desc.h> |
90e24014 | 40 | |
45046892 TG |
41 | /* |
42 | * per-CPU TSS segments. Threads are completely 'soft' on Linux, | |
43 | * no more per-task TSS's. The TSS size is kept cacheline-aligned | |
44 | * so they are allowed to end up in the .data..cacheline_aligned | |
45 | * section. Since TSS's are completely CPU-local, we want them | |
46 | * on exact cacheline boundaries, to eliminate cacheline ping-pong. | |
47 | */ | |
d0a0de21 AL |
48 | __visible DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss) = { |
49 | .x86_tss = { | |
d9e05cc5 | 50 | .sp0 = TOP_OF_INIT_STACK, |
d0a0de21 AL |
51 | #ifdef CONFIG_X86_32 |
52 | .ss0 = __KERNEL_DS, | |
53 | .ss1 = __KERNEL_CS, | |
54 | .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, | |
55 | #endif | |
56 | }, | |
57 | #ifdef CONFIG_X86_32 | |
58 | /* | |
59 | * Note that the .io_bitmap member must be extra-big. This is because | |
60 | * the CPU will access an additional byte beyond the end of the IO | |
61 | * permission bitmap. The extra byte must be all 1 bits, and must | |
62 | * be within the limit. | |
63 | */ | |
64 | .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, | |
65 | #endif | |
2a41aa4f AL |
66 | #ifdef CONFIG_X86_32 |
67 | .SYSENTER_stack_canary = STACK_END_MAGIC, | |
68 | #endif | |
d0a0de21 | 69 | }; |
de71ad2c | 70 | EXPORT_PER_CPU_SYMBOL(cpu_tss); |
45046892 | 71 | |
b7ceaec1 AL |
72 | DEFINE_PER_CPU(bool, __tss_limit_invalid); |
73 | EXPORT_PER_CPU_SYMBOL_GPL(__tss_limit_invalid); | |
b7ffc44d | 74 | |
55ccf3fe SS |
75 | /* |
76 | * this gets called so that we can store lazy state into memory and copy the | |
77 | * current task into the new thread. | |
78 | */ | |
61c4628b SS |
79 | int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) |
80 | { | |
5aaeb5c0 | 81 | memcpy(dst, src, arch_task_struct_size); |
2459ee86 AL |
82 | #ifdef CONFIG_VM86 |
83 | dst->thread.vm86 = NULL; | |
84 | #endif | |
f1853505 | 85 | |
c69e098b | 86 | return fpu__copy(&dst->thread.fpu, &src->thread.fpu); |
61c4628b | 87 | } |
7f424a8b | 88 | |
389d1fb1 JF |
89 | /* |
90 | * Free current thread data structures etc.. | |
91 | */ | |
e6464694 | 92 | void exit_thread(struct task_struct *tsk) |
389d1fb1 | 93 | { |
e6464694 | 94 | struct thread_struct *t = &tsk->thread; |
250981e6 | 95 | unsigned long *bp = t->io_bitmap_ptr; |
ca6787ba | 96 | struct fpu *fpu = &t->fpu; |
389d1fb1 | 97 | |
250981e6 | 98 | if (bp) { |
24933b82 | 99 | struct tss_struct *tss = &per_cpu(cpu_tss, get_cpu()); |
389d1fb1 | 100 | |
389d1fb1 JF |
101 | t->io_bitmap_ptr = NULL; |
102 | clear_thread_flag(TIF_IO_BITMAP); | |
103 | /* | |
104 | * Careful, clear this in the TSS too: | |
105 | */ | |
106 | memset(tss->io_bitmap, 0xff, t->io_bitmap_max); | |
107 | t->io_bitmap_max = 0; | |
108 | put_cpu(); | |
250981e6 | 109 | kfree(bp); |
389d1fb1 | 110 | } |
1dcc8d7b | 111 | |
9fda6a06 BG |
112 | free_vm86(t); |
113 | ||
50338615 | 114 | fpu__drop(fpu); |
389d1fb1 JF |
115 | } |
116 | ||
117 | void flush_thread(void) | |
118 | { | |
119 | struct task_struct *tsk = current; | |
120 | ||
24f1e32c | 121 | flush_ptrace_hw_breakpoint(tsk); |
389d1fb1 | 122 | memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array)); |
110d7f75 | 123 | |
04c8e01d | 124 | fpu__clear(&tsk->thread.fpu); |
389d1fb1 JF |
125 | } |
126 | ||
389d1fb1 JF |
127 | void disable_TSC(void) |
128 | { | |
129 | preempt_disable(); | |
130 | if (!test_and_set_thread_flag(TIF_NOTSC)) | |
131 | /* | |
132 | * Must flip the CPU state synchronously with | |
133 | * TIF_NOTSC in the current running context. | |
134 | */ | |
5a920155 | 135 | cr4_set_bits(X86_CR4_TSD); |
389d1fb1 JF |
136 | preempt_enable(); |
137 | } | |
138 | ||
389d1fb1 JF |
139 | static void enable_TSC(void) |
140 | { | |
141 | preempt_disable(); | |
142 | if (test_and_clear_thread_flag(TIF_NOTSC)) | |
143 | /* | |
144 | * Must flip the CPU state synchronously with | |
145 | * TIF_NOTSC in the current running context. | |
146 | */ | |
5a920155 | 147 | cr4_clear_bits(X86_CR4_TSD); |
389d1fb1 JF |
148 | preempt_enable(); |
149 | } | |
150 | ||
151 | int get_tsc_mode(unsigned long adr) | |
152 | { | |
153 | unsigned int val; | |
154 | ||
155 | if (test_thread_flag(TIF_NOTSC)) | |
156 | val = PR_TSC_SIGSEGV; | |
157 | else | |
158 | val = PR_TSC_ENABLE; | |
159 | ||
160 | return put_user(val, (unsigned int __user *)adr); | |
161 | } | |
162 | ||
163 | int set_tsc_mode(unsigned int val) | |
164 | { | |
165 | if (val == PR_TSC_SIGSEGV) | |
166 | disable_TSC(); | |
167 | else if (val == PR_TSC_ENABLE) | |
168 | enable_TSC(); | |
169 | else | |
170 | return -EINVAL; | |
171 | ||
172 | return 0; | |
173 | } | |
174 | ||
af8b3cd3 KH |
175 | static inline void switch_to_bitmap(struct tss_struct *tss, |
176 | struct thread_struct *prev, | |
177 | struct thread_struct *next, | |
178 | unsigned long tifp, unsigned long tifn) | |
179 | { | |
180 | if (tifn & _TIF_IO_BITMAP) { | |
181 | /* | |
182 | * Copy the relevant range of the IO bitmap. | |
183 | * Normally this is 128 bytes or less: | |
184 | */ | |
185 | memcpy(tss->io_bitmap, next->io_bitmap_ptr, | |
186 | max(prev->io_bitmap_max, next->io_bitmap_max)); | |
187 | /* | |
188 | * Make sure that the TSS limit is correct for the CPU | |
189 | * to notice the IO bitmap. | |
190 | */ | |
191 | refresh_tss_limit(); | |
192 | } else if (tifp & _TIF_IO_BITMAP) { | |
193 | /* | |
194 | * Clear any possible leftover bits: | |
195 | */ | |
196 | memset(tss->io_bitmap, 0xff, prev->io_bitmap_max); | |
197 | } | |
198 | } | |
199 | ||
389d1fb1 JF |
200 | void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p, |
201 | struct tss_struct *tss) | |
202 | { | |
203 | struct thread_struct *prev, *next; | |
af8b3cd3 | 204 | unsigned long tifp, tifn; |
389d1fb1 JF |
205 | |
206 | prev = &prev_p->thread; | |
207 | next = &next_p->thread; | |
208 | ||
af8b3cd3 KH |
209 | tifn = READ_ONCE(task_thread_info(next_p)->flags); |
210 | tifp = READ_ONCE(task_thread_info(prev_p)->flags); | |
211 | switch_to_bitmap(tss, prev, next, tifp, tifn); | |
212 | ||
213 | propagate_user_return_notify(prev_p, next_p); | |
214 | ||
b9894a2f KH |
215 | if ((tifp & _TIF_BLOCKSTEP || tifn & _TIF_BLOCKSTEP) && |
216 | arch_has_block_step()) { | |
217 | unsigned long debugctl, msk; | |
ea8e61b7 | 218 | |
b9894a2f | 219 | rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); |
ea8e61b7 | 220 | debugctl &= ~DEBUGCTLMSR_BTF; |
b9894a2f KH |
221 | msk = tifn & _TIF_BLOCKSTEP; |
222 | debugctl |= (msk >> TIF_BLOCKSTEP) << DEBUGCTLMSR_BTF_SHIFT; | |
223 | wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); | |
ea8e61b7 | 224 | } |
389d1fb1 | 225 | |
5a920155 TG |
226 | if ((tifp ^ tifn) & _TIF_NOTSC) |
227 | cr4_toggle_bits(X86_CR4_TSD); | |
389d1fb1 JF |
228 | } |
229 | ||
00dba564 TG |
230 | /* |
231 | * Idle related variables and functions | |
232 | */ | |
d1896049 | 233 | unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE; |
00dba564 TG |
234 | EXPORT_SYMBOL(boot_option_idle_override); |
235 | ||
a476bda3 | 236 | static void (*x86_idle)(void); |
00dba564 | 237 | |
90e24014 RW |
238 | #ifndef CONFIG_SMP |
239 | static inline void play_dead(void) | |
240 | { | |
241 | BUG(); | |
242 | } | |
243 | #endif | |
244 | ||
7d1a9417 TG |
245 | void arch_cpu_idle_enter(void) |
246 | { | |
6a369583 | 247 | tsc_verify_tsc_adjust(false); |
7d1a9417 | 248 | local_touch_nmi(); |
7d1a9417 | 249 | } |
90e24014 | 250 | |
7d1a9417 TG |
251 | void arch_cpu_idle_dead(void) |
252 | { | |
253 | play_dead(); | |
254 | } | |
90e24014 | 255 | |
7d1a9417 TG |
256 | /* |
257 | * Called from the generic idle code. | |
258 | */ | |
259 | void arch_cpu_idle(void) | |
260 | { | |
16f8b05a | 261 | x86_idle(); |
90e24014 RW |
262 | } |
263 | ||
00dba564 | 264 | /* |
7d1a9417 | 265 | * We use this if we don't have any better idle routine.. |
00dba564 | 266 | */ |
6727ad9e | 267 | void __cpuidle default_idle(void) |
00dba564 | 268 | { |
4d0e42cc | 269 | trace_cpu_idle_rcuidle(1, smp_processor_id()); |
7d1a9417 | 270 | safe_halt(); |
4d0e42cc | 271 | trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id()); |
00dba564 | 272 | } |
60b8b1de | 273 | #ifdef CONFIG_APM_MODULE |
00dba564 TG |
274 | EXPORT_SYMBOL(default_idle); |
275 | #endif | |
276 | ||
6a377ddc LB |
277 | #ifdef CONFIG_XEN |
278 | bool xen_set_default_idle(void) | |
e5fd47bf | 279 | { |
a476bda3 | 280 | bool ret = !!x86_idle; |
e5fd47bf | 281 | |
a476bda3 | 282 | x86_idle = default_idle; |
e5fd47bf KRW |
283 | |
284 | return ret; | |
285 | } | |
6a377ddc | 286 | #endif |
d3ec5cae IV |
287 | void stop_this_cpu(void *dummy) |
288 | { | |
289 | local_irq_disable(); | |
290 | /* | |
291 | * Remove this CPU: | |
292 | */ | |
4f062896 | 293 | set_cpu_online(smp_processor_id(), false); |
d3ec5cae | 294 | disable_local_APIC(); |
8838eb6c | 295 | mcheck_cpu_clear(this_cpu_ptr(&cpu_info)); |
d3ec5cae | 296 | |
27be4570 LB |
297 | for (;;) |
298 | halt(); | |
7f424a8b PZ |
299 | } |
300 | ||
aa276e1c | 301 | /* |
07c94a38 BP |
302 | * AMD Erratum 400 aware idle routine. We handle it the same way as C3 power |
303 | * states (local apic timer and TSC stop). | |
aa276e1c | 304 | */ |
02c68a02 | 305 | static void amd_e400_idle(void) |
aa276e1c | 306 | { |
07c94a38 BP |
307 | /* |
308 | * We cannot use static_cpu_has_bug() here because X86_BUG_AMD_APIC_C1E | |
309 | * gets set after static_cpu_has() places have been converted via | |
310 | * alternatives. | |
311 | */ | |
312 | if (!boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) { | |
313 | default_idle(); | |
314 | return; | |
aa276e1c TG |
315 | } |
316 | ||
07c94a38 | 317 | tick_broadcast_enter(); |
aa276e1c | 318 | |
07c94a38 | 319 | default_idle(); |
0beefa20 | 320 | |
07c94a38 BP |
321 | /* |
322 | * The switch back from broadcast mode needs to be called with | |
323 | * interrupts disabled. | |
324 | */ | |
325 | local_irq_disable(); | |
326 | tick_broadcast_exit(); | |
327 | local_irq_enable(); | |
aa276e1c TG |
328 | } |
329 | ||
b253149b LB |
330 | /* |
331 | * Intel Core2 and older machines prefer MWAIT over HALT for C1. | |
332 | * We can't rely on cpuidle installing MWAIT, because it will not load | |
333 | * on systems that support only C1 -- so the boot default must be MWAIT. | |
334 | * | |
335 | * Some AMD machines are the opposite, they depend on using HALT. | |
336 | * | |
337 | * So for default C1, which is used during boot until cpuidle loads, | |
338 | * use MWAIT-C1 on Intel HW that has it, else use HALT. | |
339 | */ | |
340 | static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c) | |
341 | { | |
342 | if (c->x86_vendor != X86_VENDOR_INTEL) | |
343 | return 0; | |
344 | ||
08e237fa | 345 | if (!cpu_has(c, X86_FEATURE_MWAIT) || static_cpu_has_bug(X86_BUG_MONITOR)) |
b253149b LB |
346 | return 0; |
347 | ||
348 | return 1; | |
349 | } | |
350 | ||
351 | /* | |
0fb0328d HR |
352 | * MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT |
353 | * with interrupts enabled and no flags, which is backwards compatible with the | |
354 | * original MWAIT implementation. | |
b253149b | 355 | */ |
6727ad9e | 356 | static __cpuidle void mwait_idle(void) |
b253149b | 357 | { |
f8e617f4 | 358 | if (!current_set_polling_and_test()) { |
e43d0189 | 359 | trace_cpu_idle_rcuidle(1, smp_processor_id()); |
f8e617f4 | 360 | if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) { |
ca59809f | 361 | mb(); /* quirk */ |
b253149b | 362 | clflush((void *)¤t_thread_info()->flags); |
ca59809f | 363 | mb(); /* quirk */ |
f8e617f4 | 364 | } |
b253149b LB |
365 | |
366 | __monitor((void *)¤t_thread_info()->flags, 0, 0); | |
b253149b LB |
367 | if (!need_resched()) |
368 | __sti_mwait(0, 0); | |
369 | else | |
370 | local_irq_enable(); | |
e43d0189 | 371 | trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id()); |
f8e617f4 | 372 | } else { |
b253149b | 373 | local_irq_enable(); |
f8e617f4 MG |
374 | } |
375 | __current_clr_polling(); | |
b253149b LB |
376 | } |
377 | ||
148f9bb8 | 378 | void select_idle_routine(const struct cpuinfo_x86 *c) |
7f424a8b | 379 | { |
3e5095d1 | 380 | #ifdef CONFIG_SMP |
7d1a9417 | 381 | if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1) |
c767a54b | 382 | pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n"); |
7f424a8b | 383 | #endif |
7d1a9417 | 384 | if (x86_idle || boot_option_idle_override == IDLE_POLL) |
6ddd2a27 TG |
385 | return; |
386 | ||
3344ed30 | 387 | if (boot_cpu_has_bug(X86_BUG_AMD_E400)) { |
c767a54b | 388 | pr_info("using AMD E400 aware idle routine\n"); |
a476bda3 | 389 | x86_idle = amd_e400_idle; |
b253149b LB |
390 | } else if (prefer_mwait_c1_over_halt(c)) { |
391 | pr_info("using mwait in idle threads\n"); | |
392 | x86_idle = mwait_idle; | |
6ddd2a27 | 393 | } else |
a476bda3 | 394 | x86_idle = default_idle; |
7f424a8b PZ |
395 | } |
396 | ||
07c94a38 | 397 | void amd_e400_c1e_apic_setup(void) |
30e1e6d1 | 398 | { |
07c94a38 BP |
399 | if (boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) { |
400 | pr_info("Switch to broadcast mode on CPU%d\n", smp_processor_id()); | |
401 | local_irq_disable(); | |
402 | tick_broadcast_force(); | |
403 | local_irq_enable(); | |
404 | } | |
30e1e6d1 RR |
405 | } |
406 | ||
e7ff3a47 TG |
407 | void __init arch_post_acpi_subsys_init(void) |
408 | { | |
409 | u32 lo, hi; | |
410 | ||
411 | if (!boot_cpu_has_bug(X86_BUG_AMD_E400)) | |
412 | return; | |
413 | ||
414 | /* | |
415 | * AMD E400 detection needs to happen after ACPI has been enabled. If | |
416 | * the machine is affected K8_INTP_C1E_ACTIVE_MASK bits are set in | |
417 | * MSR_K8_INT_PENDING_MSG. | |
418 | */ | |
419 | rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi); | |
420 | if (!(lo & K8_INTP_C1E_ACTIVE_MASK)) | |
421 | return; | |
422 | ||
423 | boot_cpu_set_bug(X86_BUG_AMD_APIC_C1E); | |
424 | ||
425 | if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) | |
426 | mark_tsc_unstable("TSC halt in AMD C1E"); | |
427 | pr_info("System has AMD C1E enabled\n"); | |
428 | } | |
429 | ||
7f424a8b PZ |
430 | static int __init idle_setup(char *str) |
431 | { | |
ab6bc3e3 CG |
432 | if (!str) |
433 | return -EINVAL; | |
434 | ||
7f424a8b | 435 | if (!strcmp(str, "poll")) { |
c767a54b | 436 | pr_info("using polling idle threads\n"); |
d1896049 | 437 | boot_option_idle_override = IDLE_POLL; |
7d1a9417 | 438 | cpu_idle_poll_ctrl(true); |
d1896049 | 439 | } else if (!strcmp(str, "halt")) { |
c1e3b377 ZY |
440 | /* |
441 | * When the boot option of idle=halt is added, halt is | |
442 | * forced to be used for CPU idle. In such case CPU C2/C3 | |
443 | * won't be used again. | |
444 | * To continue to load the CPU idle driver, don't touch | |
445 | * the boot_option_idle_override. | |
446 | */ | |
a476bda3 | 447 | x86_idle = default_idle; |
d1896049 | 448 | boot_option_idle_override = IDLE_HALT; |
da5e09a1 ZY |
449 | } else if (!strcmp(str, "nomwait")) { |
450 | /* | |
451 | * If the boot option of "idle=nomwait" is added, | |
452 | * it means that mwait will be disabled for CPU C2/C3 | |
453 | * states. In such case it won't touch the variable | |
454 | * of boot_option_idle_override. | |
455 | */ | |
d1896049 | 456 | boot_option_idle_override = IDLE_NOMWAIT; |
c1e3b377 | 457 | } else |
7f424a8b PZ |
458 | return -1; |
459 | ||
7f424a8b PZ |
460 | return 0; |
461 | } | |
462 | early_param("idle", idle_setup); | |
463 | ||
9d62dcdf AW |
464 | unsigned long arch_align_stack(unsigned long sp) |
465 | { | |
466 | if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) | |
467 | sp -= get_random_int() % 8192; | |
468 | return sp & ~0xf; | |
469 | } | |
470 | ||
471 | unsigned long arch_randomize_brk(struct mm_struct *mm) | |
472 | { | |
9c6f0902 | 473 | return randomize_page(mm->brk, 0x02000000); |
9d62dcdf AW |
474 | } |
475 | ||
ffcb043b BG |
476 | /* |
477 | * Return saved PC of a blocked thread. | |
478 | * What is this good for? it will be always the scheduler or ret_from_fork. | |
479 | */ | |
480 | unsigned long thread_saved_pc(struct task_struct *tsk) | |
481 | { | |
482 | struct inactive_task_frame *frame = | |
483 | (struct inactive_task_frame *) READ_ONCE(tsk->thread.sp); | |
484 | return READ_ONCE_NOCHECK(frame->ret_addr); | |
485 | } | |
486 | ||
7ba78053 TG |
487 | /* |
488 | * Called from fs/proc with a reference on @p to find the function | |
489 | * which called into schedule(). This needs to be done carefully | |
490 | * because the task might wake up and we might look at a stack | |
491 | * changing under us. | |
492 | */ | |
493 | unsigned long get_wchan(struct task_struct *p) | |
494 | { | |
74327a3e | 495 | unsigned long start, bottom, top, sp, fp, ip, ret = 0; |
7ba78053 TG |
496 | int count = 0; |
497 | ||
498 | if (!p || p == current || p->state == TASK_RUNNING) | |
499 | return 0; | |
500 | ||
74327a3e AL |
501 | if (!try_get_task_stack(p)) |
502 | return 0; | |
503 | ||
7ba78053 TG |
504 | start = (unsigned long)task_stack_page(p); |
505 | if (!start) | |
74327a3e | 506 | goto out; |
7ba78053 TG |
507 | |
508 | /* | |
509 | * Layout of the stack page: | |
510 | * | |
511 | * ----------- topmax = start + THREAD_SIZE - sizeof(unsigned long) | |
512 | * PADDING | |
513 | * ----------- top = topmax - TOP_OF_KERNEL_STACK_PADDING | |
514 | * stack | |
15f4eae7 | 515 | * ----------- bottom = start |
7ba78053 TG |
516 | * |
517 | * The tasks stack pointer points at the location where the | |
518 | * framepointer is stored. The data on the stack is: | |
519 | * ... IP FP ... IP FP | |
520 | * | |
521 | * We need to read FP and IP, so we need to adjust the upper | |
522 | * bound by another unsigned long. | |
523 | */ | |
524 | top = start + THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; | |
525 | top -= 2 * sizeof(unsigned long); | |
15f4eae7 | 526 | bottom = start; |
7ba78053 TG |
527 | |
528 | sp = READ_ONCE(p->thread.sp); | |
529 | if (sp < bottom || sp > top) | |
74327a3e | 530 | goto out; |
7ba78053 | 531 | |
7b32aead | 532 | fp = READ_ONCE_NOCHECK(((struct inactive_task_frame *)sp)->bp); |
7ba78053 TG |
533 | do { |
534 | if (fp < bottom || fp > top) | |
74327a3e | 535 | goto out; |
f7d27c35 | 536 | ip = READ_ONCE_NOCHECK(*(unsigned long *)(fp + sizeof(unsigned long))); |
74327a3e AL |
537 | if (!in_sched_functions(ip)) { |
538 | ret = ip; | |
539 | goto out; | |
540 | } | |
f7d27c35 | 541 | fp = READ_ONCE_NOCHECK(*(unsigned long *)fp); |
7ba78053 | 542 | } while (count++ < 16 && p->state != TASK_RUNNING); |
74327a3e AL |
543 | |
544 | out: | |
545 | put_task_stack(p); | |
546 | return ret; | |
7ba78053 | 547 | } |
b0b9b014 KH |
548 | |
549 | long do_arch_prctl_common(struct task_struct *task, int option, | |
550 | unsigned long cpuid_enabled) | |
551 | { | |
552 | return -EINVAL; | |
553 | } |